Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Jani Nikula <jani.nikula@linux.intel.com>
To: Anshuman Gupta <anshuman.gupta@intel.com>,
	intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: rodrigo.vivi@intel.com
Subject: Re: [Intel-gfx] [PATCH v2 9/9] drm/i915/rpm: d3cold Policy
Date: Thu, 16 Jun 2022 17:28:22 +0300	[thread overview]
Message-ID: <871qvowum1.fsf@intel.com> (raw)
In-Reply-To: <20220616120106.24353-10-anshuman.gupta@intel.com>

On Thu, 16 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> Add d3cold_sr_lmem_threshold modparam to choose between
> d3cold-off zero watt and d3cold-VRAM Self Refresh.
> i915 requires to evict the lmem objects to smem in order to
> support d3cold-Off.
>
> If gfx root port is not capable of sending PME from d3cold
> then i915 don't need to program d3cold-off/d3cold-vram_sr
> sequence.
>
> FIXME: Eviction of lmem objects in case of D3Cold off is wip.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_driver.c | 27 ++++++++++++++++++++++++---
>  drivers/gpu/drm/i915/i915_params.c |  4 ++++
>  drivers/gpu/drm/i915/i915_params.h |  3 ++-
>  3 files changed, 30 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index fcff5f3fe05e..aef4b17efdbe 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -1560,15 +1560,36 @@ static int i915_pm_restore(struct device *kdev)
>  static int intel_runtime_idle(struct device *kdev)
>  {
>  	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> +	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> +	u64 lmem_total = to_gt(dev_priv)->lmem->total;
> +	u64 lmem_avail = to_gt(dev_priv)->lmem->avail;
> +	u64 lmem_used = lmem_total - lmem_avail;
> +	struct pci_dev *root_pdev;
>  	int ret = 1;
>  
> -	if (!HAS_LMEM_SR(dev_priv)) {
> -		/*TODO: Prepare for D3Cold-Off */
> +	root_pdev = pcie_find_root_port(pdev);
> +	if (!root_pdev)
> +		goto out;
> +
> +	if (!pci_pme_capable(root_pdev, PCI_D3cold))
>  		goto out;
> -	}
>  
>  	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>  
> +	if (lmem_used < dev_priv->params.d3cold_sr_lmem_threshold  * 1024 * 1024) {
> +		drm_dbg(&dev_priv->drm, "Prepare for D3Cold off\n");
> +		pci_d3cold_enable(root_pdev);
> +		/* FIXME: Eviction of lmem objects and guc reset is wip */
> +		intel_pm_vram_sr(dev_priv, false);
> +		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> +		goto out;
> +	} else if (!HAS_LMEM_SR(dev_priv)) {
> +		/* Disable D3Cold to reduce the eviction latency */
> +		pci_d3cold_disable(root_pdev);
> +		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> +		goto out;
> +	}

This is *way* too low level code for such high level function. This
needs to be abstracted better.

> +
>  	ret = intel_pm_vram_sr(dev_priv, true);
>  	if (!ret)
>  		drm_dbg(&dev_priv->drm, "VRAM Self Refresh enabled\n");
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 701fbc98afa0..6c6b3c372d4d 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -197,6 +197,10 @@ i915_param_named(enable_gvt, bool, 0400,
>  	"Enable support for Intel GVT-g graphics virtualization host support(default:false)");
>  #endif
>  
> +i915_param_named_unsafe(d3cold_sr_lmem_threshold, int, 0400,
> +	"Enable Vidoe RAM Self refresh when size of lmem is greater to this threshold. "
> +	"It helps to optimize the suspend/resume latecy. (default: 300mb)");
> +
>  #if CONFIG_DRM_I915_REQUEST_TIMEOUT
>  i915_param_named_unsafe(request_timeout_ms, uint, 0600,
>  			"Default request/fence/batch buffer expiration timeout.");
> diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
> index b5e7ea45d191..28f20ebaf41f 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -83,7 +83,8 @@ struct drm_printer;
>  	param(bool, verbose_state_checks, true, 0) \
>  	param(bool, nuclear_pageflip, false, 0400) \
>  	param(bool, enable_dp_mst, true, 0600) \
> -	param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0)
> +	param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0) \
> +	param(int, d3cold_sr_lmem_threshold, 300, 0600) \

What's the point of the parameter?

Also, please read the comment /* leave bools at the end to not create
holes */ above.


BR,
Jani.


>  
>  #define MEMBER(T, member, ...) T member;
>  struct i915_params {

-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2022-06-16 14:28 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-16 12:00 [Intel-gfx] [PATCH v2 0/9] DG2 VRAM_SR Support Anshuman Gupta
2022-06-16 12:00 ` [Intel-gfx] [PATCH v2 1/9] drm/i915/dgfx: OpRegion VRAM Self Refresh Support Anshuman Gupta
2022-06-16 12:56   ` Jani Nikula
2022-06-17  9:46     ` Gupta, Anshuman
2022-06-16 12:00 ` [Intel-gfx] [PATCH v2 2/9] drm/i915/dg1: OpRegion PCON DG1 MBD config support Anshuman Gupta
2022-06-16 13:00   ` Jani Nikula
2022-06-16 12:01 ` [Intel-gfx] [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform Anshuman Gupta
2022-06-16 12:13   ` Tvrtko Ursulin
2022-06-16 14:15     ` Jani Nikula
2022-06-16 14:38       ` Tvrtko Ursulin
2022-06-16 14:47         ` Jani Nikula
2022-06-17  0:12   ` Matt Roper
2022-06-17  6:10     ` Gupta, Anshuman
2022-06-16 12:01 ` [Intel-gfx] [PATCH v2 4/9] drm/i915/dg2: DG2 MBD config Anshuman Gupta
2022-06-16 12:01 ` [Intel-gfx] [PATCH v2 5/9] drm/i915/dgfx: Add has_lmem_sr Anshuman Gupta
2022-06-16 12:01 ` [Intel-gfx] [PATCH v2 6/9] drm/i915/dgfx: Setup VRAM SR with D3COLD Anshuman Gupta
2022-06-16 12:46   ` Jani Nikula
2022-06-16 12:01 ` [Intel-gfx] [PATCH v2 7/9] drm/i915/rpm: Enable D3Cold VRAM SR Support Anshuman Gupta
2022-06-16 14:32   ` Jani Nikula
2022-06-17  9:36     ` Gupta, Anshuman
2022-06-16 12:01 ` [Intel-gfx] [PATCH v2 8/9] drm/i915/xehpsdv: Store lmem region in gt Anshuman Gupta
2022-06-16 14:30   ` Jani Nikula
2022-06-17 13:45   ` Andi Shyti
2022-06-16 12:01 ` [Intel-gfx] [PATCH v2 9/9] drm/i915/rpm: d3cold Policy Anshuman Gupta
2022-06-16 14:28   ` Jani Nikula [this message]
2022-06-21  6:14     ` Gupta, Anshuman
2022-06-16 16:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DG2 VRAM_SR Support (rev3) Patchwork
2022-06-16 17:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-06-16 23:30 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=871qvowum1.fsf@intel.com \
    --to=jani.nikula@linux.intel.com \
    --cc=anshuman.gupta@intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=rodrigo.vivi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox