From: Jani Nikula <jani.nikula@linux.intel.com>
To: dhinakaran.pandiyan@intel.com, mika.kahola@intel.com
Cc: imre.deak@linux.intel.com, intel-gfx@lists.freedesktop.org,
Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH] drm/i915: Wait for vblank after register read
Date: Tue, 24 Apr 2018 10:41:04 +0300 [thread overview]
Message-ID: <871sf5dpbj.fsf@intel.com> (raw)
In-Reply-To: <1524511299.24522.21.camel@dk-H97M-D3H>
On Mon, 23 Apr 2018, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> On Fri, 2018-04-20 at 14:15 +0300, Mika Kahola wrote:
>> On Fri, 2018-04-20 at 11:22 +0300, Jani Nikula wrote:
>> > On Fri, 20 Apr 2018, Mika Kahola <mika.kahola@intel.com> wrote:
>> > >
>> > > On Thu, 2018-04-19 at 17:09 +0300, Jani Nikula wrote:
>> > > >
>> > > > On Wed, 18 Apr 2018, Mika Kahola <mika.kahola@intel.com> wrote:
>> > > > >
>> > > > >
>> > > > > When reading out CRC's we wait for a vblank on
>> > > > > intel_dp_sink_crc_start()
>> > > > > function. When we start reading out CRC's in
>> > > > > intel_dp_sink_crc()
>> > > > > loop we
>> > > > > first wait for a vblank yielding that all in all we end up
>> > > > > waiting
>> > > > > two
>> > > > > vblanks on the first iteration round. Therefore, let's move the
>> > > > > intel_wait_for_vblank() as the last routine that we do in an
>> > > > > iteration loop
>> > > > > in intel_dp_sink_crc().
>> > > > >
>> > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103166
>> > > > Umm, do the CI failures in the bug really use sink crc, or are
>> > > > they
>> > > > rather about pipe crc?
>> > > >
>> > > The bug is more on pipe crc. This just caught my attention while I
>> > > was
>> > > looking into these bugs.
>> > I think the practice we've adopted is,
>> >
>> > Bugzilla: <bug that this patch should fix>
>> >
>> > References: <bug or something else that this patch is related to>
>> Got it :) I try to remember this notation.
>>
>> >
>> > >
>> > > Was there a reason why we need to wait two vblanks here before
>> > > running
>> > > the loop?
>> > I can't remember by heart. I'm not sure if it would make more sense
>> > to
>> > remove the vblank wait from intel_dp_sink_crc_start() instead. Even
>> > with
>> > your patch, there'll still be an extra vblank wait, you just move it
>> > to
>> > a different place.
>> We could remove vblank wait form intel_dp_sink_crc_start(). Maybe that
>> would be more logical place for the removal. As CI runs pointed out
>> this patch didn't fix the actual bug so should I drop this change or
>> should we still try optimize the code a bit?
>>
>
> I looked at this code in more detail, there is a big problem here.
>
> The implementation generously uses vblank waits that end up triggering
> PSR exits. This in turn means we never read crc's when PSR is active. I
> am not surprised anymore the tests were not reliable. We should nuke
> this whole thing or use delays in place of vblank waits. This patch is
> not what we need.
The other day I was looking at some aux code, and bpsec says PSR should
be disabled before doing aux transactions. So I also don't understand
how this is supposed to work. (+Imre, what was the conclusion on our aux
code dealing with PSR being enabled?)
BR,
Jani.
>
> There is also the assumption of starting and stopping crc calculation.
> Careful reading of the spec shows they are not required for crc
> calculation for PSR idle frames. We need to put more thought into fixing
> this.
>
>
> -DK
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
prev parent reply other threads:[~2018-04-24 7:38 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-18 7:56 [PATCH] drm/i915: Wait for vblank after register read Mika Kahola
2018-04-18 14:32 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-04-18 18:00 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-04-19 6:11 ` [PATCH] " Lofstedt, Marta
2018-04-19 7:03 ` Mika Kahola
2018-04-20 18:15 ` Rodrigo Vivi
2018-04-20 20:56 ` Dhinakaran Pandiyan
2018-04-24 8:14 ` Mika Kahola
2018-04-19 14:09 ` Jani Nikula
2018-04-20 6:42 ` Mika Kahola
2018-04-20 8:22 ` Jani Nikula
2018-04-20 11:15 ` Mika Kahola
2018-04-23 19:21 ` Dhinakaran Pandiyan
2018-04-23 19:34 ` Rodrigo Vivi
2018-04-23 20:24 ` Dhinakaran Pandiyan
2018-04-23 20:17 ` Rodrigo Vivi
2018-04-24 7:41 ` Jani Nikula [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=871sf5dpbj.fsf@intel.com \
--to=jani.nikula@linux.intel.com \
--cc=dhinakaran.pandiyan@intel.com \
--cc=imre.deak@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=mika.kahola@intel.com \
--cc=rodrigo.vivi@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox