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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>, intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 50/53] drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable
Date: Fri, 02 Jul 2021 11:19:59 +0300	[thread overview]
Message-ID: <8735sxqg9c.fsf@intel.com> (raw)
In-Reply-To: <20210701202427.1547543-51-matthew.d.roper@intel.com>

On Thu, 01 Jul 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> DSC can be supported per DP connector. This patch creates
> a per connector debugfs node to expose the Input and
> Compressed BPP.
>
> The same node can be used from userspace to force
> DSC to a certain BPP.
>
> force_dsc_bpp is written through this debugfs
> node to force DSC BPP to all accepted values

I think this patch needs rework, and it's independent of the rest of the
series. Please just drop this one and the next.

BR,
Jani.

>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Patnana Venkata Sai <venkata.sai.patnana@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  .../drm/i915/display/intel_display_debugfs.c  | 103 +++++++++++++++++-
>  .../drm/i915/display/intel_display_types.h    |   1 +
>  2 files changed, 103 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index af9e58619667..1805d70ea817 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2389,6 +2389,100 @@ static const struct file_operations i915_dsc_fec_support_fops = {
>  	.write = i915_dsc_fec_support_write
>  };
>  
> +static int i915_dsc_bpp_support_show(struct seq_file *m, void *data)
> +{
> +	struct drm_connector *connector = m->private;
> +	struct drm_device *dev = connector->dev;
> +	struct drm_crtc *crtc;
> +	struct intel_dp *intel_dp;
> +	struct drm_modeset_acquire_ctx ctx;
> +	struct intel_crtc_state *crtc_state = NULL;
> +	int ret = 0;
> +	bool try_again = false;
> +
> +	drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
> +
> +	do {
> +		try_again = false;
> +		ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
> +				       &ctx);
> +		if (ret) {
> +			ret = -EINTR;
> +			break;
> +		}
> +		crtc = connector->state->crtc;
> +		if (connector->status != connector_status_connected || !crtc) {
> +			ret = -ENODEV;
> +			break;
> +		}
> +		ret = drm_modeset_lock(&crtc->mutex, &ctx);
> +		if (ret == -EDEADLK) {
> +			ret = drm_modeset_backoff(&ctx);
> +			if (!ret) {
> +				try_again = true;
> +				continue;
> +			}
> +			break;
> +		} else if (ret) {
> +			break;
> +		}
> +		intel_dp = intel_attached_dp(to_intel_connector(connector));
> +		crtc_state = to_intel_crtc_state(crtc->state);
> +		seq_printf(m, "Input_BPP: %d\n", crtc_state->pipe_bpp);
> +		seq_printf(m, "Compressed_BPP: %d\n",
> +				crtc_state->dsc.compressed_bpp);
> +	} while (try_again);
> +
> +	drm_modeset_drop_locks(&ctx);
> +	drm_modeset_acquire_fini(&ctx);
> +
> +	return ret;
> +}
> +
> +static ssize_t i915_dsc_bpp_support_write(struct file *file,
> +						const char __user *ubuf,
> +						size_t len, loff_t *offp)
> +{
> +	int dsc_bpp = 0;
> +	int ret;
> +	struct drm_connector *connector =
> +		((struct seq_file *)file->private_data)->private;
> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> +	if (len == 0)
> +		return 0;
> +
> +	drm_dbg(&i915->drm,
> +		"Copied %zu bytes from user to force BPP\n", len);
> +
> +	ret = kstrtoint_from_user(ubuf, len, 0, &dsc_bpp);
> +
> +	intel_dp->force_dsc_bpp = dsc_bpp;
> +	if (ret < 0)
> +		return ret;
> +
> +	*offp += len;
> +	return len;
> +}
> +
> +static int i915_dsc_bpp_support_open(struct inode *inode,
> +					   struct file *file)
> +{
> +	return single_open(file, i915_dsc_bpp_support_show,
> +			   inode->i_private);
> +}
> +
> +static const struct file_operations i915_dsc_bpp_support_fops = {
> +	.owner = THIS_MODULE,
> +	.open = i915_dsc_bpp_support_open,
> +	.read = seq_read,
> +	.llseek = seq_lseek,
> +	.release = single_release,
> +	.write = i915_dsc_bpp_support_write
> +};
> +
>  /**
>   * intel_connector_debugfs_add - add i915 specific connector debugfs files
>   * @connector: pointer to a registered drm_connector
> @@ -2427,9 +2521,16 @@ int intel_connector_debugfs_add(struct drm_connector *connector)
>  				    connector, &i915_hdcp_sink_capability_fops);
>  	}
>  
> -	if ((DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) && ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && !to_intel_connector(connector)->mst_port) || connector->connector_type == DRM_MODE_CONNECTOR_eDP))
> +	if ((DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) &&
> +	    ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort &&
> +	      !to_intel_connector(connector)->mst_port) ||
> +	     connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
>  		debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root,
>  				    connector, &i915_dsc_fec_support_fops);
> +		debugfs_create_file("i915_dsc_bpp_support", 0444,
> +				    root, connector,
> +				    &i915_dsc_bpp_support_fops);
> +	}
>  
>  	/* Legacy panels doesn't lpsp on any platform */
>  	if ((DISPLAY_VER(dev_priv) >= 9 || IS_HASWELL(dev_priv) ||
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 29ae1d9b5abc..00320d89d266 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1627,6 +1627,7 @@ struct intel_dp {
>  
>  	/* Display stream compression testing */
>  	bool force_dsc_en;
> +	int force_dsc_bpp;
>  
>  	bool hobl_failed;
>  	bool hobl_active;

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2021-07-02  8:20 UTC|newest]

Thread overview: 91+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-01 20:23 [Intel-gfx] [PATCH 00/53] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 01/53] drm/i915: Add "release id" version Matt Roper
2021-07-02 12:33   ` Tvrtko Ursulin
2021-07-05 11:52     ` Jani Nikula
2021-07-06 21:09       ` Lucas De Marchi
2021-07-07  8:34         ` Jani Nikula
2021-07-07 15:40           ` Lucas De Marchi
2021-07-06 20:57     ` Lucas De Marchi
2021-07-01 20:23 ` [Intel-gfx] [PATCH 02/53] drm/i915: Add XE_HP initial definitions Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 03/53] drm/i915: Fork DG1 interrupt handler Matt Roper
2021-07-02  9:21   ` Daniel Vetter
2021-07-06 22:48     ` Lucas De Marchi
2021-07-07  7:39       ` Daniel Vetter
2021-07-07 15:53         ` Lucas De Marchi
2021-07-01 20:23 ` [Intel-gfx] [PATCH 04/53] drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Matt Roper
2021-07-01 22:06   ` Lucas De Marchi
2021-07-01 20:23 ` [Intel-gfx] [PATCH 05/53] drm/i915/gen12: Use fuse info to enable SFC Matt Roper
2021-07-01 22:19   ` Lucas De Marchi
2021-07-02 12:08   ` Tvrtko Ursulin
2021-07-01 20:23 ` [Intel-gfx] [PATCH 06/53] drm/i915/selftests: Allow for larger engine counts Matt Roper
2021-07-01 22:33   ` Lucas De Marchi
2021-07-01 20:23 ` [Intel-gfx] [PATCH 07/53] drm/i915/xehp: Extra media engines - Part 1 (engine definitions) Matt Roper
2021-07-02 12:22   ` Tvrtko Ursulin
2021-07-07 22:17     ` [Intel-gfx] [PATCH v2] " Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 08/53] drm/i915/xehp: Extra media engines - Part 2 (interrupts) Matt Roper
2021-07-02 12:42   ` Tvrtko Ursulin
2021-07-06 21:15     ` Lucas De Marchi
2021-07-07  7:46       ` Tvrtko Ursulin
2021-07-01 20:23 ` [Intel-gfx] [PATCH 09/53] drm/i915/xehp: Extra media engines - Part 3 (reset) Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 10/53] drm/i915/xehp: Xe_HP forcewake support Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 11/53] drm/i915/xehp: Define multicast register ranges Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 12/53] drm/i915/xehp: Handle new device context ID format Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 13/53] drm/i915/xehp: New engine context offsets Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 14/53] drm/i915/xehp: handle new steering options Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 15/53] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 16/53] drm/i915/xehpsdv: add initial XeHP SDV definitions Matt Roper
2021-07-01 21:41   ` Rodrigo Vivi
2021-07-02  7:57   ` Jani Nikula
2021-07-07 22:20     ` [Intel-gfx] [PATCH v2] " Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 17/53] drm/i915/xehp: Changes to ss/eu definitions Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 18/53] drm/i915/xehpsdv: Add maximum sseu limits Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 19/53] drm/i915/xehpsdv: Add compute DSS type Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 20/53] drm/i915/xehpsdv: Define steering tables Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 21/53] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 22/53] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 23/53] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper
2021-07-01 21:41   ` Rodrigo Vivi
2021-07-01 20:23 ` [Intel-gfx] [PATCH 24/53] drm/i915/dg2: add DG2 platform info Matt Roper
2021-07-01 20:23 ` [Intel-gfx] [PATCH 25/53] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 26/53] drm/i915/dg2: Add forcewake table Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 27/53] drm/i915/dg2: Update LNCF steering ranges Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 28/53] drm/i915/dg2: Add SQIDI steering Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 29/53] drm/i915/dg2: Add new LRI reg offsets Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 30/53] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 31/53] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper
2021-07-02  8:57   ` Lionel Landwerlin
2021-07-01 20:24 ` [Intel-gfx] [PATCH 32/53] drm/i915/dg2: Define MOCS table for DG2 Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 33/53] drm/i915/dg2: Add fake PCH Matt Roper
2021-07-06 21:47   ` Lucas De Marchi
2021-07-01 20:24 ` [Intel-gfx] [PATCH 34/53] drm/i915/dg2: Add cdclk table and reference clock Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 35/53] drm/i915/dg2: Skip shared DPLL handling Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 36/53] drm/i915/dg2: Don't wait for AUX power well enable ACKs Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 37/53] drm/i915/dg2: Setup display outputs Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 38/53] drm/i915/dg2: Add dbuf programming Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 39/53] drm/i915/dg2: Don't program BW_BUDDY registers Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 40/53] drm/i915/dg2: Don't read DRAM info Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 41/53] drm/i915/dg2: DG2 has fixed memory bandwidth Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 42/53] drm/i915/dg2: Add MPLLB programming for SNPS PHY Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 43/53] drm/i915/dg2: Add MPLLB programming for HDMI Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 44/53] drm/i915/dg2: Add vswing programming for SNPS phys Matt Roper
2021-07-02  8:14   ` Jani Nikula
2021-07-01 20:24 ` [Intel-gfx] [PATCH 45/53] drm/i915/dg2: Update modeset sequences Matt Roper
2021-07-02  8:16   ` Jani Nikula
2021-07-07 22:22     ` [Intel-gfx] [PATCH v2] " Matt Roper
2021-07-09 18:25       ` Lucas De Marchi
2021-07-01 20:24 ` [Intel-gfx] [PATCH 46/53] drm/i915/dg2: Classify DG2 PHY types Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 47/53] drm/i915/dg2: Wait for SNPS PHY calibration during display init Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 48/53] drm/i915/dg2: Update lane disable power state during PSR Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 49/53] drm/i915/dg2: Add DG2 to the PSR2 defeature list Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 50/53] drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable Matt Roper
2021-07-02  8:19   ` Jani Nikula [this message]
2021-08-23  5:42     ` Kulkarni, Vandita
2021-07-01 20:24 ` [Intel-gfx] [PATCH 51/53] drm/i915/display/dsc: Set BPP in the kernel Matt Roper
2021-07-01 20:24 ` [Intel-gfx] [PATCH 52/53] drm/i915/dg2: Update to bigjoiner path Matt Roper
2021-07-09  0:11   ` Navare, Manasi
2021-07-01 20:24 ` [Intel-gfx] [PATCH 53/53] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper
2021-07-02  1:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms Patchwork
2021-07-02  1:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-02  2:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-02  8:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-07-07 22:48 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Begin enabling Xe_HP SDV and DG2 platforms (rev4) Patchwork

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