From: Jani Nikula <jani.nikula@linux.intel.com>
To: Suraj Kandpal <suraj.kandpal@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v6 6/9] drm/i915/vdsc: Check slice design requirement
Date: Wed, 11 Jan 2023 15:41:56 +0200 [thread overview]
Message-ID: <874jsxi3x7.fsf@intel.com> (raw)
In-Reply-To: <20230111053837.1608588-7-suraj.kandpal@intel.com>
On Wed, 11 Jan 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Add function to check if slice design requirements are being
> met as defined in the below link section Slice Design Requirement
>
> https://gfxspecs.intel.com/Predator/Home/Index/49259
>
Just add this:
Bspec: 49259
and no URLs.
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 52a82d8b289e..0a683d6dff33 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -447,6 +447,29 @@ calculate_rc_params(struct rc_parameters *rc,
> }
> }
>
> +static int intel_dsc_check_slice_design_req(struct intel_crtc_state *pipe_config,
> + struct drm_dsc_config *vdsc_cfg)
Bikeshedding, I think "check" is generally a poor verb in a function
name.
intel_dsc_slice_dimensions_valid() or something like that?
> +{
> + if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
> + pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
> + if (vdsc_cfg->slice_height > 4095)
> + return -EINVAL;
> + if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000)
> + return -EINVAL;
> + } else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
> + if (!(vdsc_cfg->slice_width % 2))
> + return -EINVAL;
> + if (!(vdsc_cfg->slice_height % 2))
> + return -EINVAL;
> + if (vdsc_cfg->slice_height > 4094)
> + return -EINVAL;
> + if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000)
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> {
> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> @@ -455,11 +478,20 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
> const struct rc_parameters *rc_params;
> struct rc_parameters *rc = NULL;
> + int err;
> u8 i = 0;
>
> vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
> pipe_config->dsc.slice_count);
> +
> + err = intel_dsc_check_slice_design_req(pipe_config, vdsc_cfg);
> +
> + if (err) {
> + drm_dbg_kms(&dev_priv->drm, "Slice design requirements not met\n");
> + return err;
> + }
> +
> /*
> * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
> * else 1
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2023-01-11 13:42 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-11 5:38 [Intel-gfx] [PATCH v6 0/9] Enable YCbCr420 for VDSC Suraj Kandpal
2023-01-11 5:38 ` [Intel-gfx] [PATCH v6 1/9] drm/dp_helper: Add helper to check if the sink supports given format with DSC Suraj Kandpal
2023-01-11 5:38 ` [Intel-gfx] [PATCH v6 2/9] drm/i915/dp: Check if DSC supports the given output_format Suraj Kandpal
2023-01-11 5:38 ` [Intel-gfx] [PATCH v6 3/9] drm/i915: Adding the new registers for DSC Suraj Kandpal
2023-01-13 5:34 ` Kulkarni, Vandita
2023-01-11 5:38 ` [Intel-gfx] [PATCH v6 4/9] drm/i915: Enable YCbCr420 for VDSC Suraj Kandpal
2023-01-13 5:28 ` Kulkarni, Vandita
2023-01-11 5:38 ` [Intel-gfx] [PATCH v6 5/9] drm/i915: Fill in native_420 field Suraj Kandpal
2023-01-11 13:32 ` Jani Nikula
2023-01-11 5:38 ` [Intel-gfx] [PATCH v6 6/9] drm/i915/vdsc: Check slice design requirement Suraj Kandpal
2023-01-11 13:41 ` Jani Nikula [this message]
2023-01-11 14:29 ` Kandpal, Suraj
2023-01-11 14:41 ` Jani Nikula
2023-01-11 5:38 ` [Intel-gfx] [PATCH v6 7/9] drm/i915/dsc: Add debugfs entry to validate DSC YCbCr420 Suraj Kandpal
2023-01-11 5:38 ` [Intel-gfx] [PATCH v6 8/9] drm/i915/dsc: Allow DSC only with YCbCr420 format when forced from debugfs Suraj Kandpal
2023-01-11 13:54 ` Jani Nikula
2023-02-07 7:41 ` Swati Sharma
2023-01-11 5:38 ` [Intel-gfx] [PATCH v6 9/9] drm/i915: Code styling fixes Suraj Kandpal
2023-01-11 6:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC Patchwork
2023-01-11 12:10 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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