Re: [Intel-gfx] [PATCH] drm/i915/mtl: Add support for 32 bit OAG formats in MTL

["Dixit, Ashutosh" <ashutosh.dixit@intel.com>]

On Mon, 28 Nov 2022 17:21:46 -0800, Umesh Nerlige Ramappa wrote:
>
> +/*
> + * Ref: 14010536224:
> + * 0x20cc is repurposed on MTL, so use a separate array for MTL.

Wondering if it was WAIT_FOR_RC6_EXIT (seen in gen12_oa_mux_regs) which
moved elsewhere and if that needs to be added to the array below too?

> + */
> +static const struct i915_range mtl_oa_mux_regs[] = {
> +	{ .start = 0x0d00, .end = 0x0d04 },	/* RPM_CONFIG[0-1] */
> +	{ .start = 0x0d0c, .end = 0x0d2c },	/* NOA_CONFIG[0-8] */
> +	{ .start = 0x9840, .end = 0x9840 },	/* GDT_CHICKEN_BITS */
> +	{ .start = 0x9884, .end = 0x9888 },	/* NOA_WRITE */
> +};
> +
>  static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
>  {
>	return reg_in_range_table(addr, gen7_oa_b_counters);
> @@ -4349,7 +4372,10 @@ static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
>
>  static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
>  {
> -	return reg_in_range_table(addr, gen12_oa_mux_regs);
> +	if (IS_METEORLAKE(perf->i915))
> +		return reg_in_range_table(addr, mtl_oa_mux_regs);
> +	else
> +		return reg_in_range_table(addr, gen12_oa_mux_regs);

But otherwise this is:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

If you decide to split the patches, please add my R-b on all the split patches.