From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>,
stable@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/slpc: Let's fix the PCODE min freq table setup for SLPC
Date: Tue, 30 Aug 2022 17:45:36 -0700 [thread overview]
Message-ID: <874jxtz1e7.wl-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <20220830191620.45119-1-rodrigo.vivi@intel.com>
On Tue, 30 Aug 2022 12:16:20 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> @@ -65,13 +63,8 @@ static bool get_ia_constants(struct intel_llc *llc,
> /* convert DDR frequency from units of 266.6MHz to bandwidth */
> consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3);
>
> - consts->min_gpu_freq = rps->min_freq;
> - consts->max_gpu_freq = rps->max_freq;
> - if (GRAPHICS_VER(i915) >= 9) {
> - /* Convert GT frequency to 50 HZ units */
> - consts->min_gpu_freq /= GEN9_FREQ_SCALER;
> - consts->max_gpu_freq /= GEN9_FREQ_SCALER;
> - }
> + consts->min_gpu_freq = intel_rps_get_min_raw_freq(rps);
> + consts->max_gpu_freq = intel_rps_get_max_raw_freq(rps);
>
> return true;
> }
> @@ -130,6 +123,12 @@ static void gen6_update_ring_freq(struct intel_llc *llc)
> if (!get_ia_constants(llc, &consts))
> return;
>
> + /*
> + * Although this is unlikely on any platform during initialization,
> + * let's ensure we don't get accidentally into infinite loop
> + */
> + if (consts.max_gpu_freq <= consts.min_gpu_freq)
> + return;
As I said this is not correct and is not needed. If 'consts.max_gpu_freq ==
consts.min_gpu_freq' we would *want* to program PCODE. If
'consts.max_gpu_freq < consts.min_gpu_freq' the loop will automatically
skip (and also it is not an infinite loop).
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index de794f5f8594..26af974292c7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2156,6 +2156,24 @@ u32 intel_rps_get_max_frequency(struct intel_rps *rps)
> return intel_gpu_freq(rps, rps->max_freq_softlimit);
> }
>
> +u32 intel_rps_get_max_raw_freq(struct intel_rps *rps)
What does "raw" mean? Or are we introducing a new concept here then we need
to explain the new concept? I was previously told there is a concept of "hw
units" of freq and intel_gpu_freq will convert from "hw units" to MHz.
Also, Is the return value in units of 50 MHz in all cases (we know it is
for SLPC and Gen 9+)? In that case we should name such a function to
something like intel_rps_get_max_freq_in_50mhz_units?
> +{
> + struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> + u32 freq;
> +
> + if (rps_uses_slpc(rps)) {
> + return DIV_ROUND_CLOSEST(slpc->rp0_freq,
> + GT_FREQUENCY_MULTIPLIER);
> + } else {
> + freq = rps->max_freq;
> + if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) {
> + /* Convert GT frequency to 50 HZ units */
50 MHz and not 50 Hz. Also the comment should be moved to above
rps_uses_slpc() line if returned freq is always in units of 50 MHz.
> + freq /= GEN9_FREQ_SCALER;
> + }
> + return freq;
> + }
> +}
Also is this function equivalent to this:
u32 intel_rps_get_max_freq_in_50mhz_units(struct intel_rps *rps)
{
struct intel_guc_slpc *slpc = rps_to_slpc(rps);
u32 freq;
/* freq in MHz */
freq = rps_uses_slpc(rps) ? slpc->rp0_freq : intel_gpu_freq(rps->max_freq);
return DIV_ROUND_CLOSEST(freq, GT_FREQUENCY_MULTIPLIER);
}
Sorry I don't have a lot of history in how these frequencies are scaled
specially for old platforms like CHV/VLV/Gen6+. But afaiu intel_gpu_freq()
will convert the freq to MHz for all platforms.
And then does get_ia_constants() accept freq in 50 MHz units for all
platforms?
If we are not sure about this, we can go with your version which is closer
to the original version in get_ia_constants() and so "safer" I guess.
Thanks.
--
Ashutosh
next prev parent reply other threads:[~2022-08-31 0:45 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-25 22:23 [Intel-gfx] [PATCH] drm/i915/slpc: Set rps' min and max frequencies even with SLPC Rodrigo Vivi
2022-08-25 22:42 ` Rodrigo Vivi
2022-08-25 23:00 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
2022-08-25 23:59 ` [Intel-gfx] [PATCH] " Dixit, Ashutosh
2022-08-26 9:28 ` Vivi, Rodrigo
2022-08-26 10:13 ` [Intel-gfx] [PATCH] drm/i915/slpc: Fix PCODE IA Freq requests when using SLPC Rodrigo Vivi
2022-08-26 13:13 ` Dixit, Ashutosh
2022-08-26 17:44 ` Rodrigo Vivi
2022-08-26 20:03 ` Dixit, Ashutosh
2022-08-30 15:42 ` Dixit, Ashutosh
2022-08-30 19:16 ` [Intel-gfx] [PATCH] drm/i915/slpc: Let's fix the PCODE min freq table setup for SLPC Rodrigo Vivi
2022-08-31 0:45 ` Dixit, Ashutosh [this message]
2022-08-31 19:35 ` Vivi, Rodrigo
2022-08-31 21:45 ` Rodrigo Vivi
2022-08-31 22:17 ` Dixit, Ashutosh
2022-09-01 16:53 ` Rodrigo Vivi
2022-08-26 0:53 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/slpc: Set rps' min and max frequencies even with SLPC. (rev2) Patchwork
2022-08-26 11:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/slpc: Set rps' min and max frequencies even with SLPC. (rev4) Patchwork
2022-08-26 18:43 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/slpc: Set rps' min and max frequencies even with SLPC. (rev5) Patchwork
2022-08-30 12:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/slpc: Set rps' min and max frequencies even with SLPC. (rev4) Patchwork
2022-08-30 19:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/slpc: Set rps' min and max frequencies even with SLPC. (rev6) Patchwork
2022-08-31 15:31 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-08-31 22:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/slpc: Set rps' min and max frequencies even with SLPC. (rev7) Patchwork
2022-09-01 17:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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