From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 08/14] drm/i915: Check for IVB instead of gen7 when we think about IVB CPU eDP
Date: Tue, 20 Mar 2018 09:11:30 +0200 [thread overview]
Message-ID: <874llbz0f1.fsf@intel.com> (raw)
In-Reply-To: <20180302095512.19329-9-ville.syrjala@linux.intel.com>
On Fri, 02 Mar 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Almost all of the GEN7 checks in the DP code are actually looking for
> IVB. HSW doesn't even take these codepaths, and VLV is excluded on
> account of not having port A. So let's change the checks to IS_IVB to
> make the code less confusing.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 642ae298df07..2a82eccffe54 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1970,7 +1970,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
>
> /* Split out the IBX/CPU vs CPT settings */
>
> - if (IS_GEN7(dev_priv) && port == PORT_A) {
> + if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> intel_dp->DP |= DP_SYNC_HS_HIGH;
> if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> @@ -2650,7 +2650,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
> if (!(tmp & DP_PORT_EN))
> goto out;
>
> - if (IS_GEN7(dev_priv) && port == PORT_A) {
> + if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> *pipe = PORT_TO_PIPE_CPT(tmp);
> } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
> enum pipe p;
> @@ -2887,7 +2887,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> }
> I915_WRITE(DP_TP_CTL(port), temp);
>
> - } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
> + } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
> (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
> *DP &= ~DP_LINK_TRAIN_MASK_CPT;
>
> @@ -3213,7 +3213,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> return intel_ddi_dp_voltage_max(encoder);
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> - else if (IS_GEN7(dev_priv) && port == PORT_A)
> + else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> @@ -3242,7 +3242,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> default:
> return DP_TRAIN_PRE_EMPH_LEVEL_0;
> }
> - } else if (IS_GEN7(dev_priv) && port == PORT_A) {
> + } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> return DP_TRAIN_PRE_EMPH_LEVEL_2;
> @@ -3551,7 +3551,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> signal_levels = chv_signal_levels(intel_dp);
> } else if (IS_VALLEYVIEW(dev_priv)) {
> signal_levels = vlv_signal_levels(intel_dp);
> - } else if (IS_GEN7(dev_priv) && port == PORT_A) {
> + } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> signal_levels = gen7_edp_signal_levels(train_set);
I guess a follow-up could rename the gen7_ function to ivb_ too.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
> } else if (IS_GEN6(dev_priv) && port == PORT_A) {
> @@ -3641,7 +3641,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
>
> DRM_DEBUG_KMS("\n");
>
> - if ((IS_GEN7(dev_priv) && port == PORT_A) ||
> + if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
> (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
> DP &= ~DP_LINK_TRAIN_MASK_CPT;
> DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
--
Jani Nikula, Intel Open Source Technology Center
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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next prev parent reply other threads:[~2018-03-20 7:11 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-02 9:54 [PATCH 00/14] drm/i915: Clean up the port pipe select bits Ville Syrjala
2018-03-02 9:54 ` [PATCH 01/14] drm/i915: Clean up ADPA " Ville Syrjala
2018-03-20 6:27 ` Jani Nikula
2018-03-02 9:55 ` [PATCH 02/14] drm/i915: Clean up LVDS " Ville Syrjala
2018-03-20 6:39 ` Jani Nikula
2018-03-02 9:55 ` [PATCH 03/14] drm/i915: Clean up SDVO " Ville Syrjala
2018-03-20 6:50 ` Jani Nikula
2018-03-02 9:55 ` [PATCH 04/14] drm/i915: Clean up TV " Ville Syrjala
2018-03-20 6:55 ` Jani Nikula
2018-03-02 9:55 ` [PATCH 05/14] drm/i915: Clean up DVO " Ville Syrjala
2018-03-20 7:00 ` Jani Nikula
2018-03-02 9:55 ` [PATCH 06/14] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too Ville Syrjala
2018-03-02 9:55 ` [PATCH 07/14] drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+ Ville Syrjala
2018-03-02 9:55 ` [PATCH 08/14] drm/i915: Check for IVB instead of gen7 when we think about IVB CPU eDP Ville Syrjala
2018-03-20 7:11 ` Jani Nikula [this message]
2018-03-02 9:55 ` [PATCH 09/14] drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi code Ville Syrjala
2018-03-20 7:19 ` Jani Nikula
2018-03-02 9:55 ` [PATCH 10/14] drm/i915: Parametrize TRANS_DP_PORT_SEL Ville Syrjala
2018-03-20 8:36 ` Jani Nikula
2018-03-02 9:55 ` [PATCH 11/14] drm/i915: Nuke intel_trans_dp_port_sel() Ville Syrjala
2018-03-02 9:55 ` [PATCH 12/14] drm/i915: Clean up DP pipe select bits Ville Syrjala
2018-03-02 18:08 ` [PATCH v2 " Ville Syrjala
2018-03-02 9:55 ` [PATCH 13/14] drm/i915: Allow eDP on port C in theory Ville Syrjala
2018-03-02 9:55 ` [PATCH 14/14] drm/i915: Implement the missing bits of assert_panel_unlocked() Ville Syrjala
2018-03-02 11:02 ` ✗ Fi.CI.BAT: failure for drm/i915: Clean up the port pipe select bits Patchwork
2018-03-02 13:09 ` Patchwork
2018-03-02 18:40 ` ✗ Fi.CI.BAT: failure for drm/i915: Clean up the port pipe select bits (rev2) Patchwork
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