[PATCH v2 00/16] drm/i915/dp: 128b/132b uncompressed SST

[PATCH v2 00/16] drm/i915/dp: 128b/132b uncompressed SST

[Jani Nikula]

This is v2 of [1], enabling uncompressed 128b/132b UHBR SST.

The first one was accidentally "RFC v0", and there have been a few
iterations sent to CI trybot since, with various version numbers, so I
expect everyone to get royally confused about the versioning
here. Sorry.

Anyway, unlike with [1], we get a picture on screen with this, so it
must be perfect. Please review. :)


BR,
Jani.


[1] https://lore.kernel.org/r/cover.1734085515.git.jani.nikula@intel.com

Jani Nikula (16):
  drm/mst: remove mgr parameter and debug logging from
    drm_dp_get_vc_payload_bw()
  drm/i915/mst: drop connector parameter from intel_dp_mst_bw_overhead()
  drm/i915/mst: drop connector parameter from intel_dp_mst_compute_m_n()
  drm/i915/mst: change return value of
    mst_stream_find_vcpi_slots_for_bpp()
  drm/i915/mst: remove crtc_state->pbn
  drm/i915/mst: split out a helper for figuring out the TU
  drm/i915/mst: adapt intel_dp_mtp_tu_compute_config() for 128b/132b SST
  drm/i915/ddi: enable 128b/132b TRANS_DDI_FUNC_CTL mode for UHBR SST
  drm/i915/ddi: 128b/132b SST also needs DP_TP_CTL_MODE_MST
  drm/i915/ddi: write payload for 128b/132b SST
  drm/i915/ddi: initialize 128b/132b SST DP2 VFREQ registers
  drm/i915/ddi: enable ACT handling for 128b/132b SST
  drm/i915/ddi: start distinguishing 128b/132b SST and MST at state
    readout
  drm/i915/ddi: handle 128b/132b SST in intel_ddi_read_func_ctl()
  drm/i915/ddi: disable trancoder port select for 128b/132b SST
  drm/i915/dp: compute config for 128b/132b SST w/o DSC

 drivers/gpu/drm/display/drm_dp_mst_topology.c |  10 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  97 +++++++-
 .../drm/i915/display/intel_display_types.h    |   2 -
 drivers/gpu/drm/i915/display/intel_dp.c       |  34 ++-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 218 +++++++++---------
 drivers/gpu/drm/i915/display/intel_dp_mst.h   |   7 +
 drivers/gpu/drm/nouveau/dispnv50/disp.c       |   3 +-
 .../gpu/drm/tests/drm_dp_mst_helper_test.c    |   4 +-
 include/drm/display/drm_dp_mst_helper.h       |   3 +-
 9 files changed, 235 insertions(+), 143 deletions(-)

-- 
2.39.5

[PATCH v2 01/16] drm/mst: remove mgr parameter and debug logging from drm_dp_get_vc_payload_bw()

[Jani Nikula]

The struct drm_dp_mst_topology_mgr *mgr parameter is only used for debug
logging in case the passed in link rate or lane count are zero. There's
no further error checking as such, and the function returns 0.

There should be no case where the parameters are zero. The returned
value is generally used as a divisor, and if we were hitting this, we'd
be seeing division by zero.

Just remove the debug logging altogether, along with the mgr parameter,
so that the function can be used in non-MST contexts without the
topology manager.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Lyude Paul <lyude@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/display/drm_dp_mst_topology.c  | 10 ++--------
 drivers/gpu/drm/i915/display/intel_dp_mst.c    |  3 +--
 drivers/gpu/drm/nouveau/dispnv50/disp.c        |  3 +--
 drivers/gpu/drm/tests/drm_dp_mst_helper_test.c |  4 +---
 include/drm/display/drm_dp_mst_helper.h        |  3 +--
 5 files changed, 6 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index f8cd094efa3c..06c91c5b7f7c 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -3572,8 +3572,7 @@ static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr,
 }
 
 /**
- * drm_dp_get_vc_payload_bw - get the VC payload BW for an MST link
- * @mgr: The &drm_dp_mst_topology_mgr to use
+ * drm_dp_get_vc_payload_bw - get the VC payload BW for an MTP link
  * @link_rate: link rate in 10kbits/s units
  * @link_lane_count: lane count
  *
@@ -3584,17 +3583,12 @@ static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr,
  *
  * Returns the BW / timeslot value in 20.12 fixed point format.
  */
-fixed20_12 drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
-				    int link_rate, int link_lane_count)
+fixed20_12 drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count)
 {
 	int ch_coding_efficiency =
 		drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(link_rate));
 	fixed20_12 ret;
 
-	if (link_rate == 0 || link_lane_count == 0)
-		drm_dbg_kms(mgr->dev, "invalid link rate/lane count: (%d / %d)\n",
-			    link_rate, link_lane_count);
-
 	/* See DP v2.0 2.6.4.2, 2.7.6.3 VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
 	ret.full = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_rate * link_lane_count,
 						  ch_coding_efficiency),
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 708fe93d8b06..163a009e51b8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -244,8 +244,7 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
 		crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
 	}
 
-	mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
-						      crtc_state->port_clock,
+	mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock,
 						      crtc_state->lane_count);
 
 	max_dpt_bpp = intel_dp_mst_max_dpt_bpp(crtc_state, dsc);
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 8097249612bc..62d72b7a8d04 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -992,8 +992,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
 	if (!mst_state->pbn_div.full) {
 		struct nouveau_encoder *outp = mstc->mstm->outp;
 
-		mst_state->pbn_div = drm_dp_get_vc_payload_bw(&mstm->mgr,
-							      outp->dp.link_bw, outp->dp.link_nr);
+		mst_state->pbn_div = drm_dp_get_vc_payload_bw(outp->dp.link_bw, outp->dp.link_nr);
 	}
 
 	slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn);
diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
index 89cd9e4f4d32..ad29593d28cf 100644
--- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
+++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
@@ -199,10 +199,8 @@ static const struct drm_dp_mst_calc_pbn_div_test drm_dp_mst_calc_pbn_div_dp1_4_c
 static void drm_test_dp_mst_calc_pbn_div(struct kunit *test)
 {
 	const struct drm_dp_mst_calc_pbn_div_test *params = test->param_value;
-	/* mgr->dev is only needed by drm_dbg_kms(), but it's not called for the test cases. */
-	struct drm_dp_mst_topology_mgr *mgr = test->priv;
 
-	KUNIT_EXPECT_EQ(test, drm_dp_get_vc_payload_bw(mgr, params->link_rate, params->lane_count).full,
+	KUNIT_EXPECT_EQ(test, drm_dp_get_vc_payload_bw(params->link_rate, params->lane_count).full,
 			params->expected.full);
 }
 
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index a80ba457a858..e39de161c938 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -867,8 +867,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector,
 				 struct drm_dp_mst_topology_mgr *mgr,
 				 struct drm_dp_mst_port *port);
 
-fixed20_12 drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
-				    int link_rate, int link_lane_count);
+fixed20_12 drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count);
 
 int drm_dp_calc_pbn_mode(int clock, int bpp);
 
-- 
2.39.5

Re: [PATCH v2 01/16] drm/mst: remove mgr parameter and debug logging from drm_dp_get_vc_payload_bw()

[Imre Deak]

On Thu, Dec 19, 2024 at 11:33:50PM +0200, Jani Nikula wrote:
> The struct drm_dp_mst_topology_mgr *mgr parameter is only used for debug
> logging in case the passed in link rate or lane count are zero. There's
> no further error checking as such, and the function returns 0.
> 
> There should be no case where the parameters are zero. The returned
> value is generally used as a divisor, and if we were hitting this, we'd
> be seeing division by zero.
> 
> Just remove the debug logging altogether, along with the mgr parameter,
> so that the function can be used in non-MST contexts without the
> topology manager.
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Lyude Paul <lyude@redhat.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> [...]
> diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> index 89cd9e4f4d32..ad29593d28cf 100644
> --- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> +++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> @@ -199,10 +199,8 @@ static const struct drm_dp_mst_calc_pbn_div_test drm_dp_mst_calc_pbn_div_dp1_4_c
>  static void drm_test_dp_mst_calc_pbn_div(struct kunit *test)
>  {
>  	const struct drm_dp_mst_calc_pbn_div_test *params = test->param_value;
> -	/* mgr->dev is only needed by drm_dbg_kms(), but it's not called for the test cases. */
> -	struct drm_dp_mst_topology_mgr *mgr = test->priv;
>  
> -	KUNIT_EXPECT_EQ(test, drm_dp_get_vc_payload_bw(mgr, params->link_rate, params->lane_count).full,
> +	KUNIT_EXPECT_EQ(test, drm_dp_get_vc_payload_bw(params->link_rate, params->lane_count).full,
>  			params->expected.full);
>  }

Allocating the topology manager and setting kunit::priv isn't needed
then either, so that along with drm_dp_mst_helper_tests_init() should be
also removed. With that:

Reviewed-by: Imre Deak <imre.deak@intel.com>

[PATCH] drm/mst: remove mgr parameter and debug logging from drm_dp_get_vc_payload_bw()

[Jani Nikula]

The struct drm_dp_mst_topology_mgr *mgr parameter is only used for debug
logging in case the passed in link rate or lane count are zero. There's
no further error checking as such, and the function returns 0.

There should be no case where the parameters are zero. The returned
value is generally used as a divisor, and if we were hitting this, we'd
be seeing division by zero.

Just remove the debug logging altogether, along with the mgr parameter,
so that the function can be used in non-MST contexts without the
topology manager.

v2: Also remove drm_dp_mst_helper_tests_init as unnecessary (Imre)

Cc: Imre Deak <imre.deak@intel.com>
Cc: Lyude Paul <lyude@redhat.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/display/drm_dp_mst_topology.c  | 10 ++--------
 drivers/gpu/drm/i915/display/intel_dp_mst.c    |  3 +--
 drivers/gpu/drm/nouveau/dispnv50/disp.c        |  3 +--
 drivers/gpu/drm/tests/drm_dp_mst_helper_test.c | 17 +----------------
 include/drm/display/drm_dp_mst_helper.h        |  3 +--
 5 files changed, 6 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index f8cd094efa3c..06c91c5b7f7c 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -3572,8 +3572,7 @@ static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr,
 }
 
 /**
- * drm_dp_get_vc_payload_bw - get the VC payload BW for an MST link
- * @mgr: The &drm_dp_mst_topology_mgr to use
+ * drm_dp_get_vc_payload_bw - get the VC payload BW for an MTP link
  * @link_rate: link rate in 10kbits/s units
  * @link_lane_count: lane count
  *
@@ -3584,17 +3583,12 @@ static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr,
  *
  * Returns the BW / timeslot value in 20.12 fixed point format.
  */
-fixed20_12 drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
-				    int link_rate, int link_lane_count)
+fixed20_12 drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count)
 {
 	int ch_coding_efficiency =
 		drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(link_rate));
 	fixed20_12 ret;
 
-	if (link_rate == 0 || link_lane_count == 0)
-		drm_dbg_kms(mgr->dev, "invalid link rate/lane count: (%d / %d)\n",
-			    link_rate, link_lane_count);
-
 	/* See DP v2.0 2.6.4.2, 2.7.6.3 VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
 	ret.full = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_rate * link_lane_count,
 						  ch_coding_efficiency),
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index fffd199999e0..ca091ed291d5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -244,8 +244,7 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
 		crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
 	}
 
-	mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
-						      crtc_state->port_clock,
+	mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock,
 						      crtc_state->lane_count);
 
 	max_dpt_bpp = intel_dp_mst_max_dpt_bpp(crtc_state, dsc);
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 8097249612bc..62d72b7a8d04 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -992,8 +992,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
 	if (!mst_state->pbn_div.full) {
 		struct nouveau_encoder *outp = mstc->mstm->outp;
 
-		mst_state->pbn_div = drm_dp_get_vc_payload_bw(&mstm->mgr,
-							      outp->dp.link_bw, outp->dp.link_nr);
+		mst_state->pbn_div = drm_dp_get_vc_payload_bw(outp->dp.link_bw, outp->dp.link_nr);
 	}
 
 	slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn);
diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
index 89cd9e4f4d32..9e0e2fb65944 100644
--- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
+++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
@@ -199,10 +199,8 @@ static const struct drm_dp_mst_calc_pbn_div_test drm_dp_mst_calc_pbn_div_dp1_4_c
 static void drm_test_dp_mst_calc_pbn_div(struct kunit *test)
 {
 	const struct drm_dp_mst_calc_pbn_div_test *params = test->param_value;
-	/* mgr->dev is only needed by drm_dbg_kms(), but it's not called for the test cases. */
-	struct drm_dp_mst_topology_mgr *mgr = test->priv;
 
-	KUNIT_EXPECT_EQ(test, drm_dp_get_vc_payload_bw(mgr, params->link_rate, params->lane_count).full,
+	KUNIT_EXPECT_EQ(test, drm_dp_get_vc_payload_bw(params->link_rate, params->lane_count).full,
 			params->expected.full);
 }
 
@@ -568,21 +566,8 @@ static struct kunit_case drm_dp_mst_helper_tests[] = {
 	{ }
 };
 
-static int drm_dp_mst_helper_tests_init(struct kunit *test)
-{
-	struct drm_dp_mst_topology_mgr *mgr;
-
-	mgr = kunit_kzalloc(test, sizeof(*mgr), GFP_KERNEL);
-	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, mgr);
-
-	test->priv = mgr;
-
-	return 0;
-}
-
 static struct kunit_suite drm_dp_mst_helper_test_suite = {
 	.name = "drm_dp_mst_helper",
-	.init = drm_dp_mst_helper_tests_init,
 	.test_cases = drm_dp_mst_helper_tests,
 };
 
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index a80ba457a858..e39de161c938 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -867,8 +867,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector,
 				 struct drm_dp_mst_topology_mgr *mgr,
 				 struct drm_dp_mst_port *port);
 
-fixed20_12 drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
-				    int link_rate, int link_lane_count);
+fixed20_12 drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count);
 
 int drm_dp_calc_pbn_mode(int clock, int bpp);
 
-- 
2.39.5

Re: [PATCH] drm/mst: remove mgr parameter and debug logging from drm_dp_get_vc_payload_bw()

[Jani Nikula]

On Thu, 02 Jan 2025, Jani Nikula <jani.nikula@intel.com> wrote:
> The struct drm_dp_mst_topology_mgr *mgr parameter is only used for debug
> logging in case the passed in link rate or lane count are zero. There's
> no further error checking as such, and the function returns 0.
>
> There should be no case where the parameters are zero. The returned
> value is generally used as a divisor, and if we were hitting this, we'd
> be seeing division by zero.
>
> Just remove the debug logging altogether, along with the mgr parameter,
> so that the function can be used in non-MST contexts without the
> topology manager.
>
> v2: Also remove drm_dp_mst_helper_tests_init as unnecessary (Imre)
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Lyude Paul <lyude@redhat.com>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Maarten, Maxime, Thomas, ack for merging this via drm-intel along with
the rest of the series?

BR,
Jani.


> ---
>  drivers/gpu/drm/display/drm_dp_mst_topology.c  | 10 ++--------
>  drivers/gpu/drm/i915/display/intel_dp_mst.c    |  3 +--
>  drivers/gpu/drm/nouveau/dispnv50/disp.c        |  3 +--
>  drivers/gpu/drm/tests/drm_dp_mst_helper_test.c | 17 +----------------
>  include/drm/display/drm_dp_mst_helper.h        |  3 +--
>  5 files changed, 6 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index f8cd094efa3c..06c91c5b7f7c 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -3572,8 +3572,7 @@ static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr,
>  }
>  
>  /**
> - * drm_dp_get_vc_payload_bw - get the VC payload BW for an MST link
> - * @mgr: The &drm_dp_mst_topology_mgr to use
> + * drm_dp_get_vc_payload_bw - get the VC payload BW for an MTP link
>   * @link_rate: link rate in 10kbits/s units
>   * @link_lane_count: lane count
>   *
> @@ -3584,17 +3583,12 @@ static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr,
>   *
>   * Returns the BW / timeslot value in 20.12 fixed point format.
>   */
> -fixed20_12 drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
> -				    int link_rate, int link_lane_count)
> +fixed20_12 drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count)
>  {
>  	int ch_coding_efficiency =
>  		drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(link_rate));
>  	fixed20_12 ret;
>  
> -	if (link_rate == 0 || link_lane_count == 0)
> -		drm_dbg_kms(mgr->dev, "invalid link rate/lane count: (%d / %d)\n",
> -			    link_rate, link_lane_count);
> -
>  	/* See DP v2.0 2.6.4.2, 2.7.6.3 VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
>  	ret.full = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_rate * link_lane_count,
>  						  ch_coding_efficiency),
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index fffd199999e0..ca091ed291d5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -244,8 +244,7 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
>  		crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
>  	}
>  
> -	mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
> -						      crtc_state->port_clock,
> +	mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock,
>  						      crtc_state->lane_count);
>  
>  	max_dpt_bpp = intel_dp_mst_max_dpt_bpp(crtc_state, dsc);
> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> index 8097249612bc..62d72b7a8d04 100644
> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> @@ -992,8 +992,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
>  	if (!mst_state->pbn_div.full) {
>  		struct nouveau_encoder *outp = mstc->mstm->outp;
>  
> -		mst_state->pbn_div = drm_dp_get_vc_payload_bw(&mstm->mgr,
> -							      outp->dp.link_bw, outp->dp.link_nr);
> +		mst_state->pbn_div = drm_dp_get_vc_payload_bw(outp->dp.link_bw, outp->dp.link_nr);
>  	}
>  
>  	slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn);
> diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> index 89cd9e4f4d32..9e0e2fb65944 100644
> --- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> +++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> @@ -199,10 +199,8 @@ static const struct drm_dp_mst_calc_pbn_div_test drm_dp_mst_calc_pbn_div_dp1_4_c
>  static void drm_test_dp_mst_calc_pbn_div(struct kunit *test)
>  {
>  	const struct drm_dp_mst_calc_pbn_div_test *params = test->param_value;
> -	/* mgr->dev is only needed by drm_dbg_kms(), but it's not called for the test cases. */
> -	struct drm_dp_mst_topology_mgr *mgr = test->priv;
>  
> -	KUNIT_EXPECT_EQ(test, drm_dp_get_vc_payload_bw(mgr, params->link_rate, params->lane_count).full,
> +	KUNIT_EXPECT_EQ(test, drm_dp_get_vc_payload_bw(params->link_rate, params->lane_count).full,
>  			params->expected.full);
>  }
>  
> @@ -568,21 +566,8 @@ static struct kunit_case drm_dp_mst_helper_tests[] = {
>  	{ }
>  };
>  
> -static int drm_dp_mst_helper_tests_init(struct kunit *test)
> -{
> -	struct drm_dp_mst_topology_mgr *mgr;
> -
> -	mgr = kunit_kzalloc(test, sizeof(*mgr), GFP_KERNEL);
> -	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, mgr);
> -
> -	test->priv = mgr;
> -
> -	return 0;
> -}
> -
>  static struct kunit_suite drm_dp_mst_helper_test_suite = {
>  	.name = "drm_dp_mst_helper",
> -	.init = drm_dp_mst_helper_tests_init,
>  	.test_cases = drm_dp_mst_helper_tests,
>  };
>  
> diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
> index a80ba457a858..e39de161c938 100644
> --- a/include/drm/display/drm_dp_mst_helper.h
> +++ b/include/drm/display/drm_dp_mst_helper.h
> @@ -867,8 +867,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector,
>  				 struct drm_dp_mst_topology_mgr *mgr,
>  				 struct drm_dp_mst_port *port);
>  
> -fixed20_12 drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
> -				    int link_rate, int link_lane_count);
> +fixed20_12 drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count);
>  
>  int drm_dp_calc_pbn_mode(int clock, int bpp);

-- 
Jani Nikula, Intel

[PATCH v2 02/16] drm/i915/mst: drop connector parameter from intel_dp_mst_bw_overhead()

[Jani Nikula]

intel_dp_mst_bw_overhead() doesn't need the connector. Remove the
parameter.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 163a009e51b8..50426ba5bdeb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -139,7 +139,6 @@ static int intel_dp_mst_max_dpt_bpp(const struct intel_crtc_state *crtc_state,
 }
 
 static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
-				    const struct intel_connector *connector,
 				    bool ssc, int dsc_slice_count, int bpp_x16)
 {
 	const struct drm_display_mode *adjusted_mode =
@@ -278,9 +277,9 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
 		link_bpp_x16 = fxp_q4_from_int(dsc ? bpp :
 					       intel_dp_output_bpp(crtc_state->output_format, bpp));
 
-		local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
+		local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
 							     false, dsc_slice_count, link_bpp_x16);
-		remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
+		remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
 							      true, dsc_slice_count, link_bpp_x16);
 
 		intel_dp_mst_compute_m_n(crtc_state, connector,
-- 
2.39.5

Re: [PATCH v2 02/16] drm/i915/mst: drop connector parameter from intel_dp_mst_bw_overhead()

[Imre Deak]

On Thu, Dec 19, 2024 at 11:33:51PM +0200, Jani Nikula wrote:
> intel_dp_mst_bw_overhead() doesn't need the connector. Remove the
> parameter.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 163a009e51b8..50426ba5bdeb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -139,7 +139,6 @@ static int intel_dp_mst_max_dpt_bpp(const struct intel_crtc_state *crtc_state,
>  }
>  
>  static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
> -				    const struct intel_connector *connector,
>  				    bool ssc, int dsc_slice_count, int bpp_x16)
>  {
>  	const struct drm_display_mode *adjusted_mode =
> @@ -278,9 +277,9 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
>  		link_bpp_x16 = fxp_q4_from_int(dsc ? bpp :
>  					       intel_dp_output_bpp(crtc_state->output_format, bpp));
>  
> -		local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
> +		local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
>  							     false, dsc_slice_count, link_bpp_x16);
> -		remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
> +		remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
>  							      true, dsc_slice_count, link_bpp_x16);
>  
>  		intel_dp_mst_compute_m_n(crtc_state, connector,
> -- 
> 2.39.5
> 

[PATCH v2 03/16] drm/i915/mst: drop connector parameter from intel_dp_mst_compute_m_n()

[Jani Nikula]

intel_dp_mst_compute_m_n() doesn't need the connector. Remove the
parameter.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 50426ba5bdeb..f52f9c968adb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -167,7 +167,6 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
 }
 
 static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
-				     const struct intel_connector *connector,
 				     int overhead,
 				     int bpp_x16,
 				     struct intel_link_m_n *m_n)
@@ -282,7 +281,7 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
 		remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
 							      true, dsc_slice_count, link_bpp_x16);
 
-		intel_dp_mst_compute_m_n(crtc_state, connector,
+		intel_dp_mst_compute_m_n(crtc_state,
 					 local_bw_overhead,
 					 link_bpp_x16,
 					 &crtc_state->dp_m_n);
-- 
2.39.5

Re: [PATCH v2 03/16] drm/i915/mst: drop connector parameter from intel_dp_mst_compute_m_n()

[Imre Deak]

On Thu, Dec 19, 2024 at 11:33:52PM +0200, Jani Nikula wrote:
> intel_dp_mst_compute_m_n() doesn't need the connector. Remove the
> parameter.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 50426ba5bdeb..f52f9c968adb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -167,7 +167,6 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
>  }
>  
>  static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
> -				     const struct intel_connector *connector,
>  				     int overhead,
>  				     int bpp_x16,
>  				     struct intel_link_m_n *m_n)
> @@ -282,7 +281,7 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
>  		remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
>  							      true, dsc_slice_count, link_bpp_x16);
>  
> -		intel_dp_mst_compute_m_n(crtc_state, connector,
> +		intel_dp_mst_compute_m_n(crtc_state,
>  					 local_bw_overhead,
>  					 link_bpp_x16,
>  					 &crtc_state->dp_m_n);
> -- 
> 2.39.5
> 

[PATCH v2 04/16] drm/i915/mst: change return value of mst_stream_find_vcpi_slots_for_bpp()

[Jani Nikula]

The callers of mst_stream_find_vcpi_slots_for_bpp() don't need the
returned slots for anything. On the contrary, they need to jump through
hoops to just distinguish between success and failure. Just return 0
instead of slots from mst_stream_find_vcpi_slots_for_bpp() for success,
and simplify the callers.

There's a pointless ret local variable that we can drop in the process.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 52 +++++++--------------
 1 file changed, 18 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index f52f9c968adb..f7b91cf32b5b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -226,7 +226,6 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
 	int bpp, slots = -EINVAL;
 	int dsc_slice_count = 0;
 	int max_dpt_bpp;
-	int ret = 0;
 
 	mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
 	if (IS_ERR(mst_state))
@@ -340,23 +339,21 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
 		}
 	}
 
-	/* We failed to find a proper bpp/timeslots, return error */
-	if (ret)
-		slots = ret;
-
 	if (slots < 0) {
 		drm_dbg_kms(display->drm, "failed finding vcpi slots:%d\n",
 			    slots);
-	} else {
-		if (!dsc)
-			crtc_state->pipe_bpp = bpp;
-		else
-			crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(bpp);
-		drm_dbg_kms(display->drm, "Got %d slots for pipe bpp %d dsc %d\n",
-			    slots, bpp, dsc);
+		return slots;
 	}
 
-	return slots;
+	if (!dsc)
+		crtc_state->pipe_bpp = bpp;
+	else
+		crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(bpp);
+
+	drm_dbg_kms(display->drm, "Got %d slots for pipe bpp %d dsc %d\n",
+		    slots, bpp, dsc);
+
+	return 0;
 }
 
 static int mst_stream_compute_link_config(struct intel_dp *intel_dp,
@@ -364,22 +361,15 @@ static int mst_stream_compute_link_config(struct intel_dp *intel_dp,
 					  struct drm_connector_state *conn_state,
 					  struct link_config_limits *limits)
 {
-	int slots = -EINVAL;
-
 	/*
 	 * FIXME: allocate the BW according to link_bpp, which in the case of
 	 * YUV420 is only half of the pipe bpp value.
 	 */
-	slots = mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state,
-						   fxp_q4_to_int(limits->link.max_bpp_x16),
-						   fxp_q4_to_int(limits->link.min_bpp_x16),
-						   limits,
-						   conn_state, 2 * 3, false);
-
-	if (slots < 0)
-		return slots;
-
-	return 0;
+	return mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state,
+						  fxp_q4_to_int(limits->link.max_bpp_x16),
+						  fxp_q4_to_int(limits->link.min_bpp_x16),
+						  limits,
+						  conn_state, 2 * 3, false);
 }
 
 static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp,
@@ -389,7 +379,6 @@ static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp,
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_connector *connector = to_intel_connector(conn_state->connector);
-	int slots = -EINVAL;
 	int i, num_bpc;
 	u8 dsc_bpc[3] = {};
 	int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
@@ -451,14 +440,9 @@ static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp,
 	min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(display, min_compressed_bpp,
 							    crtc_state->pipe_bpp);
 
-	slots = mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state, max_compressed_bpp,
-						   min_compressed_bpp, limits,
-						   conn_state, 1, true);
-
-	if (slots < 0)
-		return slots;
-
-	return 0;
+	return mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state, max_compressed_bpp,
+						  min_compressed_bpp, limits,
+						  conn_state, 1, true);
 }
 
 static int mst_stream_update_slots(struct intel_dp *intel_dp,
-- 
2.39.5

Re: [PATCH v2 04/16] drm/i915/mst: change return value of mst_stream_find_vcpi_slots_for_bpp()

[Imre Deak]

On Thu, Dec 19, 2024 at 11:33:53PM +0200, Jani Nikula wrote:
> The callers of mst_stream_find_vcpi_slots_for_bpp() don't need the
> returned slots for anything. On the contrary, they need to jump through
> hoops to just distinguish between success and failure. Just return 0
> instead of slots from mst_stream_find_vcpi_slots_for_bpp() for success,
> and simplify the callers.
> 
> There's a pointless ret local variable that we can drop in the process.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 52 +++++++--------------
>  1 file changed, 18 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index f52f9c968adb..f7b91cf32b5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -226,7 +226,6 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
>  	int bpp, slots = -EINVAL;
>  	int dsc_slice_count = 0;
>  	int max_dpt_bpp;
> -	int ret = 0;
>  
>  	mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
>  	if (IS_ERR(mst_state))
> @@ -340,23 +339,21 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
>  		}
>  	}
>  
> -	/* We failed to find a proper bpp/timeslots, return error */
> -	if (ret)
> -		slots = ret;
> -
>  	if (slots < 0) {
>  		drm_dbg_kms(display->drm, "failed finding vcpi slots:%d\n",
>  			    slots);
> -	} else {
> -		if (!dsc)
> -			crtc_state->pipe_bpp = bpp;
> -		else
> -			crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(bpp);
> -		drm_dbg_kms(display->drm, "Got %d slots for pipe bpp %d dsc %d\n",
> -			    slots, bpp, dsc);
> +		return slots;
>  	}
>  
> -	return slots;
> +	if (!dsc)
> +		crtc_state->pipe_bpp = bpp;
> +	else
> +		crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(bpp);
> +
> +	drm_dbg_kms(display->drm, "Got %d slots for pipe bpp %d dsc %d\n",
> +		    slots, bpp, dsc);
> +
> +	return 0;
>  }
>  
>  static int mst_stream_compute_link_config(struct intel_dp *intel_dp,
> @@ -364,22 +361,15 @@ static int mst_stream_compute_link_config(struct intel_dp *intel_dp,
>  					  struct drm_connector_state *conn_state,
>  					  struct link_config_limits *limits)
>  {
> -	int slots = -EINVAL;
> -
>  	/*
>  	 * FIXME: allocate the BW according to link_bpp, which in the case of
>  	 * YUV420 is only half of the pipe bpp value.
>  	 */
> -	slots = mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state,
> -						   fxp_q4_to_int(limits->link.max_bpp_x16),
> -						   fxp_q4_to_int(limits->link.min_bpp_x16),
> -						   limits,
> -						   conn_state, 2 * 3, false);
> -
> -	if (slots < 0)
> -		return slots;
> -
> -	return 0;
> +	return mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state,
> +						  fxp_q4_to_int(limits->link.max_bpp_x16),
> +						  fxp_q4_to_int(limits->link.min_bpp_x16),
> +						  limits,
> +						  conn_state, 2 * 3, false);
>  }
>  
>  static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp,
> @@ -389,7 +379,6 @@ static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp,
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	struct intel_connector *connector = to_intel_connector(conn_state->connector);
> -	int slots = -EINVAL;
>  	int i, num_bpc;
>  	u8 dsc_bpc[3] = {};
>  	int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
> @@ -451,14 +440,9 @@ static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp,
>  	min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(display, min_compressed_bpp,
>  							    crtc_state->pipe_bpp);
>  
> -	slots = mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state, max_compressed_bpp,
> -						   min_compressed_bpp, limits,
> -						   conn_state, 1, true);
> -
> -	if (slots < 0)
> -		return slots;
> -
> -	return 0;
> +	return mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state, max_compressed_bpp,
> +						  min_compressed_bpp, limits,
> +						  conn_state, 1, true);
>  }
>  
>  static int mst_stream_update_slots(struct intel_dp *intel_dp,
> -- 
> 2.39.5
> 

[PATCH v2 05/16] drm/i915/mst: remove crtc_state->pbn

[Jani Nikula]

The crtc_state->pbn member is only used as a temporary variable within
mst_stream_find_vcpi_slots_for_bpp(). Remove it as unnecessary.

Suggested-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 2 --
 drivers/gpu/drm/i915/display/intel_dp_mst.c        | 3 +--
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index eb9dd1125a4a..16e2bbde76eb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1160,8 +1160,6 @@ struct intel_crtc_state {
 
 	bool double_wide;
 
-	int pbn;
-
 	struct intel_crtc_scaler_state scaler_state;
 
 	/* w/a for waiting 2 vblanks during crtc enable */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index f7b91cf32b5b..51f0248084b6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -321,14 +321,13 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
 		 * first branch device's link also applies here.
 		 */
 		pbn.full = remote_tu * mst_state->pbn_div.full;
-		crtc_state->pbn = dfixed_trunc(pbn);
 
 		drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
 		crtc_state->dp_m_n.tu = remote_tu;
 
 		slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
 						      connector->port,
-						      crtc_state->pbn);
+						      dfixed_trunc(pbn));
 		if (slots == -EDEADLK)
 			return slots;
 
-- 
2.39.5

Re: [PATCH v2 05/16] drm/i915/mst: remove crtc_state->pbn

[Imre Deak]

On Thu, Dec 19, 2024 at 11:33:54PM +0200, Jani Nikula wrote:
> The crtc_state->pbn member is only used as a temporary variable within
> mst_stream_find_vcpi_slots_for_bpp(). Remove it as unnecessary.
> 
> Suggested-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h | 2 --
>  drivers/gpu/drm/i915/display/intel_dp_mst.c        | 3 +--
>  2 files changed, 1 insertion(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index eb9dd1125a4a..16e2bbde76eb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1160,8 +1160,6 @@ struct intel_crtc_state {
>  
>  	bool double_wide;
>  
> -	int pbn;
> -
>  	struct intel_crtc_scaler_state scaler_state;
>  
>  	/* w/a for waiting 2 vblanks during crtc enable */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index f7b91cf32b5b..51f0248084b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -321,14 +321,13 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
>  		 * first branch device's link also applies here.
>  		 */
>  		pbn.full = remote_tu * mst_state->pbn_div.full;
> -		crtc_state->pbn = dfixed_trunc(pbn);
>  
>  		drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
>  		crtc_state->dp_m_n.tu = remote_tu;
>  
>  		slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
>  						      connector->port,
> -						      crtc_state->pbn);
> +						      dfixed_trunc(pbn));
>  		if (slots == -EDEADLK)
>  			return slots;
>  
> -- 
> 2.39.5
> 

[PATCH v2 06/16] drm/i915/mst: split out a helper for figuring out the TU

[Jani Nikula]

Extract intel_dp_mtp_tu_compute_config() for figuring out the TU. Move
the link configuration and mst state access to the callers. This will be
easier to adapt to 128b/132b SST.

v2: Don't add SST stuff here yet

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 53 ++++++++++++++-------
 drivers/gpu/drm/i915/display/intel_dp_mst.h |  7 +++
 2 files changed, 42 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 51f0248084b6..d08824d2fefe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -209,31 +209,23 @@ static int intel_dp_mst_dsc_get_slice_count(const struct intel_connector *connec
 					    num_joined_pipes);
 }
 
-static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
-					      struct intel_crtc_state *crtc_state,
-					      int max_bpp, int min_bpp,
-					      struct link_config_limits *limits,
-					      struct drm_connector_state *conn_state,
-					      int step, bool dsc)
+int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
+				   struct intel_crtc_state *crtc_state,
+				   int max_bpp, int min_bpp,
+				   struct drm_connector_state *conn_state,
+				   int step, bool dsc)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct drm_atomic_state *state = crtc_state->uapi.state;
-	struct drm_dp_mst_topology_state *mst_state;
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
+	fixed20_12 pbn_div;
 	int bpp, slots = -EINVAL;
 	int dsc_slice_count = 0;
 	int max_dpt_bpp;
 
-	mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
-	if (IS_ERR(mst_state))
-		return PTR_ERR(mst_state);
-
-	crtc_state->lane_count = limits->max_lane_count;
-	crtc_state->port_clock = limits->max_rate;
-
 	if (dsc) {
 		if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
 			return -EINVAL;
@@ -241,8 +233,8 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
 		crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
 	}
 
-	mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock,
-						      crtc_state->lane_count);
+	pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock,
+					   crtc_state->lane_count);
 
 	max_dpt_bpp = intel_dp_mst_max_dpt_bpp(crtc_state, dsc);
 	if (max_bpp > max_dpt_bpp) {
@@ -302,7 +294,7 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
 		pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
 							      link_bpp_x16,
 							      remote_bw_overhead));
-		remote_tu = DIV_ROUND_UP(pbn.full, mst_state->pbn_div.full);
+		remote_tu = DIV_ROUND_UP(pbn.full, pbn_div.full);
 
 		/*
 		 * Aligning the TUs ensures that symbols consisting of multiple
@@ -320,7 +312,7 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
 		 * allocated for the whole path and the TUs allocated for the
 		 * first branch device's link also applies here.
 		 */
-		pbn.full = remote_tu * mst_state->pbn_div.full;
+		pbn.full = remote_tu * pbn_div.full;
 
 		drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
 		crtc_state->dp_m_n.tu = remote_tu;
@@ -355,6 +347,31 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
 	return 0;
 }
 
+static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
+					      struct intel_crtc_state *crtc_state,
+					      int max_bpp, int min_bpp,
+					      struct link_config_limits *limits,
+					      struct drm_connector_state *conn_state,
+					      int step, bool dsc)
+{
+	struct drm_atomic_state *state = crtc_state->uapi.state;
+	struct drm_dp_mst_topology_state *mst_state;
+
+	mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
+	if (IS_ERR(mst_state))
+		return PTR_ERR(mst_state);
+
+	crtc_state->lane_count = limits->max_lane_count;
+	crtc_state->port_clock = limits->max_rate;
+
+	mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock,
+						      crtc_state->lane_count);
+
+	return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state,
+					      max_bpp, min_bpp,
+					      conn_state, step, dsc);
+}
+
 static int mst_stream_compute_link_config(struct intel_dp *intel_dp,
 					  struct intel_crtc_state *crtc_state,
 					  struct drm_connector_state *conn_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
index 8343804ce3f8..c6bdc1d190a4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
@@ -8,6 +8,7 @@
 
 #include <linux/types.h>
 
+struct drm_connector_state;
 struct intel_atomic_state;
 struct intel_crtc;
 struct intel_crtc_state;
@@ -30,4 +31,10 @@ bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
 void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp);
 bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp);
 
+int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
+				   struct intel_crtc_state *crtc_state,
+				   int max_bpp, int min_bpp,
+				   struct drm_connector_state *conn_state,
+				   int step, bool dsc);
+
 #endif /* __INTEL_DP_MST_H__ */
-- 
2.39.5

Re: [PATCH v2 06/16] drm/i915/mst: split out a helper for figuring out the TU

[Imre Deak]

On Thu, Dec 19, 2024 at 11:33:55PM +0200, Jani Nikula wrote:
> Extract intel_dp_mtp_tu_compute_config() for figuring out the TU. Move
> the link configuration and mst state access to the callers. This will be
> easier to adapt to 128b/132b SST.
> 
> v2: Don't add SST stuff here yet
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 53 ++++++++++++++-------
>  drivers/gpu/drm/i915/display/intel_dp_mst.h |  7 +++
>  2 files changed, 42 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 51f0248084b6..d08824d2fefe 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -209,31 +209,23 @@ static int intel_dp_mst_dsc_get_slice_count(const struct intel_connector *connec
>  					    num_joined_pipes);
>  }
>  
> -static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
> -					      struct intel_crtc_state *crtc_state,
> -					      int max_bpp, int min_bpp,
> -					      struct link_config_limits *limits,
> -					      struct drm_connector_state *conn_state,
> -					      int step, bool dsc)
> +int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
> +				   struct intel_crtc_state *crtc_state,
> +				   int max_bpp, int min_bpp,
> +				   struct drm_connector_state *conn_state,
> +				   int step, bool dsc)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	struct drm_atomic_state *state = crtc_state->uapi.state;
> -	struct drm_dp_mst_topology_state *mst_state;
>  	struct intel_connector *connector =
>  		to_intel_connector(conn_state->connector);
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
> +	fixed20_12 pbn_div;
>  	int bpp, slots = -EINVAL;
>  	int dsc_slice_count = 0;
>  	int max_dpt_bpp;
>  
> -	mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
> -	if (IS_ERR(mst_state))
> -		return PTR_ERR(mst_state);
> -
> -	crtc_state->lane_count = limits->max_lane_count;
> -	crtc_state->port_clock = limits->max_rate;
> -
>  	if (dsc) {
>  		if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
>  			return -EINVAL;
> @@ -241,8 +233,8 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
>  		crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
>  	}
>  
> -	mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock,
> -						      crtc_state->lane_count);
> +	pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock,
> +					   crtc_state->lane_count);

Nit: looking this up from drm_dp_mst_topology_state (once SST and MST is
separated done only in the MST case) instead of recalculating the same
would be better. Either way:

Reviewed-by: Imre Deak <imre.deak@intel.com>

>  
>  	max_dpt_bpp = intel_dp_mst_max_dpt_bpp(crtc_state, dsc);
>  	if (max_bpp > max_dpt_bpp) {
> @@ -302,7 +294,7 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
>  		pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
>  							      link_bpp_x16,
>  							      remote_bw_overhead));
> -		remote_tu = DIV_ROUND_UP(pbn.full, mst_state->pbn_div.full);
> +		remote_tu = DIV_ROUND_UP(pbn.full, pbn_div.full);
>  
>  		/*
>  		 * Aligning the TUs ensures that symbols consisting of multiple
> @@ -320,7 +312,7 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
>  		 * allocated for the whole path and the TUs allocated for the
>  		 * first branch device's link also applies here.
>  		 */
> -		pbn.full = remote_tu * mst_state->pbn_div.full;
> +		pbn.full = remote_tu * pbn_div.full;
>  
>  		drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
>  		crtc_state->dp_m_n.tu = remote_tu;
> @@ -355,6 +347,31 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
>  	return 0;
>  }
>  
> +static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
> +					      struct intel_crtc_state *crtc_state,
> +					      int max_bpp, int min_bpp,
> +					      struct link_config_limits *limits,
> +					      struct drm_connector_state *conn_state,
> +					      int step, bool dsc)
> +{
> +	struct drm_atomic_state *state = crtc_state->uapi.state;
> +	struct drm_dp_mst_topology_state *mst_state;
> +
> +	mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
> +	if (IS_ERR(mst_state))
> +		return PTR_ERR(mst_state);
> +
> +	crtc_state->lane_count = limits->max_lane_count;
> +	crtc_state->port_clock = limits->max_rate;
> +
> +	mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock,
> +						      crtc_state->lane_count);
> +
> +	return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state,
> +					      max_bpp, min_bpp,
> +					      conn_state, step, dsc);
> +}
> +
>  static int mst_stream_compute_link_config(struct intel_dp *intel_dp,
>  					  struct intel_crtc_state *crtc_state,
>  					  struct drm_connector_state *conn_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
> index 8343804ce3f8..c6bdc1d190a4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
> @@ -8,6 +8,7 @@
>  
>  #include <linux/types.h>
>  
> +struct drm_connector_state;
>  struct intel_atomic_state;
>  struct intel_crtc;
>  struct intel_crtc_state;
> @@ -30,4 +31,10 @@ bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
>  void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp);
>  bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp);
>  
> +int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
> +				   struct intel_crtc_state *crtc_state,
> +				   int max_bpp, int min_bpp,
> +				   struct drm_connector_state *conn_state,
> +				   int step, bool dsc);
> +
>  #endif /* __INTEL_DP_MST_H__ */
> -- 
> 2.39.5
> 

Re: [PATCH v2 06/16] drm/i915/mst: split out a helper for figuring out the TU

[Jani Nikula]

On Tue, 31 Dec 2024, Imre Deak <imre.deak@intel.com> wrote:
> On Thu, Dec 19, 2024 at 11:33:55PM +0200, Jani Nikula wrote:
>> Extract intel_dp_mtp_tu_compute_config() for figuring out the TU. Move
>> the link configuration and mst state access to the callers. This will be
>> easier to adapt to 128b/132b SST.
>> 
>> v2: Don't add SST stuff here yet
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 53 ++++++++++++++-------
>>  drivers/gpu/drm/i915/display/intel_dp_mst.h |  7 +++
>>  2 files changed, 42 insertions(+), 18 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> index 51f0248084b6..d08824d2fefe 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> @@ -209,31 +209,23 @@ static int intel_dp_mst_dsc_get_slice_count(const struct intel_connector *connec
>>  					    num_joined_pipes);
>>  }
>>  
>> -static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
>> -					      struct intel_crtc_state *crtc_state,
>> -					      int max_bpp, int min_bpp,
>> -					      struct link_config_limits *limits,
>> -					      struct drm_connector_state *conn_state,
>> -					      int step, bool dsc)
>> +int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
>> +				   struct intel_crtc_state *crtc_state,
>> +				   int max_bpp, int min_bpp,
>> +				   struct drm_connector_state *conn_state,
>> +				   int step, bool dsc)
>>  {
>>  	struct intel_display *display = to_intel_display(intel_dp);
>>  	struct drm_atomic_state *state = crtc_state->uapi.state;
>> -	struct drm_dp_mst_topology_state *mst_state;
>>  	struct intel_connector *connector =
>>  		to_intel_connector(conn_state->connector);
>>  	const struct drm_display_mode *adjusted_mode =
>>  		&crtc_state->hw.adjusted_mode;
>> +	fixed20_12 pbn_div;
>>  	int bpp, slots = -EINVAL;
>>  	int dsc_slice_count = 0;
>>  	int max_dpt_bpp;
>>  
>> -	mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
>> -	if (IS_ERR(mst_state))
>> -		return PTR_ERR(mst_state);
>> -
>> -	crtc_state->lane_count = limits->max_lane_count;
>> -	crtc_state->port_clock = limits->max_rate;
>> -
>>  	if (dsc) {
>>  		if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
>>  			return -EINVAL;
>> @@ -241,8 +233,8 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
>>  		crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
>>  	}
>>  
>> -	mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock,
>> -						      crtc_state->lane_count);
>> +	pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock,
>> +					   crtc_state->lane_count);
>
> Nit: looking this up from drm_dp_mst_topology_state (once SST and MST is
> separated done only in the MST case) instead of recalculating the same
> would be better. Either way:

I don't disagree, but I couldn't figure out a neat way to deduplicate
that just yet. This seemed simpler. I think I'll leave that for future
improvement.

> Reviewed-by: Imre Deak <imre.deak@intel.com>

Thanks,
Jani.

>
>>  
>>  	max_dpt_bpp = intel_dp_mst_max_dpt_bpp(crtc_state, dsc);
>>  	if (max_bpp > max_dpt_bpp) {
>> @@ -302,7 +294,7 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
>>  		pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
>>  							      link_bpp_x16,
>>  							      remote_bw_overhead));
>> -		remote_tu = DIV_ROUND_UP(pbn.full, mst_state->pbn_div.full);
>> +		remote_tu = DIV_ROUND_UP(pbn.full, pbn_div.full);
>>  
>>  		/*
>>  		 * Aligning the TUs ensures that symbols consisting of multiple
>> @@ -320,7 +312,7 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
>>  		 * allocated for the whole path and the TUs allocated for the
>>  		 * first branch device's link also applies here.
>>  		 */
>> -		pbn.full = remote_tu * mst_state->pbn_div.full;
>> +		pbn.full = remote_tu * pbn_div.full;
>>  
>>  		drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
>>  		crtc_state->dp_m_n.tu = remote_tu;
>> @@ -355,6 +347,31 @@ static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
>>  	return 0;
>>  }
>>  
>> +static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp,
>> +					      struct intel_crtc_state *crtc_state,
>> +					      int max_bpp, int min_bpp,
>> +					      struct link_config_limits *limits,
>> +					      struct drm_connector_state *conn_state,
>> +					      int step, bool dsc)
>> +{
>> +	struct drm_atomic_state *state = crtc_state->uapi.state;
>> +	struct drm_dp_mst_topology_state *mst_state;
>> +
>> +	mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
>> +	if (IS_ERR(mst_state))
>> +		return PTR_ERR(mst_state);
>> +
>> +	crtc_state->lane_count = limits->max_lane_count;
>> +	crtc_state->port_clock = limits->max_rate;
>> +
>> +	mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock,
>> +						      crtc_state->lane_count);
>> +
>> +	return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state,
>> +					      max_bpp, min_bpp,
>> +					      conn_state, step, dsc);
>> +}
>> +
>>  static int mst_stream_compute_link_config(struct intel_dp *intel_dp,
>>  					  struct intel_crtc_state *crtc_state,
>>  					  struct drm_connector_state *conn_state,
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
>> index 8343804ce3f8..c6bdc1d190a4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
>> @@ -8,6 +8,7 @@
>>  
>>  #include <linux/types.h>
>>  
>> +struct drm_connector_state;
>>  struct intel_atomic_state;
>>  struct intel_crtc;
>>  struct intel_crtc_state;
>> @@ -30,4 +31,10 @@ bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
>>  void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp);
>>  bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp);
>>  
>> +int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
>> +				   struct intel_crtc_state *crtc_state,
>> +				   int max_bpp, int min_bpp,
>> +				   struct drm_connector_state *conn_state,
>> +				   int step, bool dsc);
>> +
>>  #endif /* __INTEL_DP_MST_H__ */
>> -- 
>> 2.39.5
>> 

-- 
Jani Nikula, Intel

[PATCH v2 07/16] drm/i915/mst: adapt intel_dp_mtp_tu_compute_config() for 128b/132b SST

[Jani Nikula]

Handle 128b/132b SST in intel_dp_mtp_tu_compute_config(). The remote
bandwidth overhead and time slot allocation are only relevant for MST;
SST only needs the local bandwidth and a check that 64 slots isn't
exceeded.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 109 +++++++++++---------
 1 file changed, 61 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index d08824d2fefe..3fbf9163272b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -257,10 +257,7 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
 
 	for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
 		int local_bw_overhead;
-		int remote_bw_overhead;
 		int link_bpp_x16;
-		int remote_tu;
-		fixed20_12 pbn;
 
 		drm_dbg_kms(display->drm, "Trying bpp %d\n", bpp);
 
@@ -269,57 +266,73 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
 
 		local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
 							     false, dsc_slice_count, link_bpp_x16);
-		remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
-							      true, dsc_slice_count, link_bpp_x16);
-
 		intel_dp_mst_compute_m_n(crtc_state,
 					 local_bw_overhead,
 					 link_bpp_x16,
 					 &crtc_state->dp_m_n);
 
-		/*
-		 * The TU size programmed to the HW determines which slots in
-		 * an MTP frame are used for this stream, which needs to match
-		 * the payload size programmed to the first downstream branch
-		 * device's payload table.
-		 *
-		 * Note that atm the payload's PBN value DRM core sends via
-		 * the ALLOCATE_PAYLOAD side-band message matches the payload
-		 * size (which it calculates from the PBN value) it programs
-		 * to the first branch device's payload table. The allocation
-		 * in the payload table could be reduced though (to
-		 * crtc_state->dp_m_n.tu), provided that the driver doesn't
-		 * enable SSC on the corresponding link.
-		 */
-		pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
-							      link_bpp_x16,
-							      remote_bw_overhead));
-		remote_tu = DIV_ROUND_UP(pbn.full, pbn_div.full);
-
-		/*
-		 * Aligning the TUs ensures that symbols consisting of multiple
-		 * (4) symbol cycles don't get split between two consecutive
-		 * MTPs, as required by Bspec.
-		 * TODO: remove the alignment restriction for 128b/132b links
-		 * on some platforms, where Bspec allows this.
-		 */
-		remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);
-
-		/*
-		 * Also align PBNs accordingly, since MST core will derive its
-		 * own copy of TU from the PBN in drm_dp_atomic_find_time_slots().
-		 * The above comment about the difference between the PBN
-		 * allocated for the whole path and the TUs allocated for the
-		 * first branch device's link also applies here.
-		 */
-		pbn.full = remote_tu * pbn_div.full;
-
-		drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
-		crtc_state->dp_m_n.tu = remote_tu;
+		if (intel_dp->is_mst) {
+			int remote_bw_overhead;
+			int remote_tu;
+			fixed20_12 pbn;
+
+			remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
+								      true, dsc_slice_count, link_bpp_x16);
+
+			/*
+			 * The TU size programmed to the HW determines which slots in
+			 * an MTP frame are used for this stream, which needs to match
+			 * the payload size programmed to the first downstream branch
+			 * device's payload table.
+			 *
+			 * Note that atm the payload's PBN value DRM core sends via
+			 * the ALLOCATE_PAYLOAD side-band message matches the payload
+			 * size (which it calculates from the PBN value) it programs
+			 * to the first branch device's payload table. The allocation
+			 * in the payload table could be reduced though (to
+			 * crtc_state->dp_m_n.tu), provided that the driver doesn't
+			 * enable SSC on the corresponding link.
+			 */
+			pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
+								      link_bpp_x16,
+								      remote_bw_overhead));
+			remote_tu = DIV_ROUND_UP(pbn.full, pbn_div.full);
+
+			/*
+			 * Aligning the TUs ensures that symbols consisting of multiple
+			 * (4) symbol cycles don't get split between two consecutive
+			 * MTPs, as required by Bspec.
+			 * TODO: remove the alignment restriction for 128b/132b links
+			 * on some platforms, where Bspec allows this.
+			 */
+			remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);
+
+			/*
+			 * Also align PBNs accordingly, since MST core will derive its
+			 * own copy of TU from the PBN in drm_dp_atomic_find_time_slots().
+			 * The above comment about the difference between the PBN
+			 * allocated for the whole path and the TUs allocated for the
+			 * first branch device's link also applies here.
+			 */
+			pbn.full = remote_tu * pbn_div.full;
+
+			drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
+			crtc_state->dp_m_n.tu = remote_tu;
+
+			slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
+							      connector->port,
+							      dfixed_trunc(pbn));
+		} else {
+			/* Same as above for remote_tu */
+			crtc_state->dp_m_n.tu = ALIGN(crtc_state->dp_m_n.tu,
+						      4 / crtc_state->lane_count);
+
+			if (crtc_state->dp_m_n.tu <= 64)
+				slots = crtc_state->dp_m_n.tu;
+			else
+				slots = -EINVAL;
+		}
 
-		slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
-						      connector->port,
-						      dfixed_trunc(pbn));
 		if (slots == -EDEADLK)
 			return slots;
 
-- 
2.39.5

Re: [PATCH v2 07/16] drm/i915/mst: adapt intel_dp_mtp_tu_compute_config() for 128b/132b SST

[Imre Deak]

On Thu, Dec 19, 2024 at 11:33:56PM +0200, Jani Nikula wrote:
> Handle 128b/132b SST in intel_dp_mtp_tu_compute_config(). The remote
> bandwidth overhead and time slot allocation are only relevant for MST;
> SST only needs the local bandwidth and a check that 64 slots isn't
> exceeded.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 109 +++++++++++---------
>  1 file changed, 61 insertions(+), 48 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index d08824d2fefe..3fbf9163272b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -257,10 +257,7 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
>  
>  	for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
>  		int local_bw_overhead;
> -		int remote_bw_overhead;
>  		int link_bpp_x16;
> -		int remote_tu;
> -		fixed20_12 pbn;
>  
>  		drm_dbg_kms(display->drm, "Trying bpp %d\n", bpp);
>  
> @@ -269,57 +266,73 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
>  
>  		local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
>  							     false, dsc_slice_count, link_bpp_x16);
> -		remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
> -							      true, dsc_slice_count, link_bpp_x16);
> -
>  		intel_dp_mst_compute_m_n(crtc_state,
>  					 local_bw_overhead,
>  					 link_bpp_x16,
>  					 &crtc_state->dp_m_n);
>  
> -		/*
> -		 * The TU size programmed to the HW determines which slots in
> -		 * an MTP frame are used for this stream, which needs to match
> -		 * the payload size programmed to the first downstream branch
> -		 * device's payload table.
> -		 *
> -		 * Note that atm the payload's PBN value DRM core sends via
> -		 * the ALLOCATE_PAYLOAD side-band message matches the payload
> -		 * size (which it calculates from the PBN value) it programs
> -		 * to the first branch device's payload table. The allocation
> -		 * in the payload table could be reduced though (to
> -		 * crtc_state->dp_m_n.tu), provided that the driver doesn't
> -		 * enable SSC on the corresponding link.
> -		 */
> -		pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
> -							      link_bpp_x16,
> -							      remote_bw_overhead));
> -		remote_tu = DIV_ROUND_UP(pbn.full, pbn_div.full);
> -
> -		/*
> -		 * Aligning the TUs ensures that symbols consisting of multiple
> -		 * (4) symbol cycles don't get split between two consecutive
> -		 * MTPs, as required by Bspec.
> -		 * TODO: remove the alignment restriction for 128b/132b links
> -		 * on some platforms, where Bspec allows this.
> -		 */
> -		remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);
> -
> -		/*
> -		 * Also align PBNs accordingly, since MST core will derive its
> -		 * own copy of TU from the PBN in drm_dp_atomic_find_time_slots().
> -		 * The above comment about the difference between the PBN
> -		 * allocated for the whole path and the TUs allocated for the
> -		 * first branch device's link also applies here.
> -		 */
> -		pbn.full = remote_tu * pbn_div.full;
> -
> -		drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
> -		crtc_state->dp_m_n.tu = remote_tu;
> +		if (intel_dp->is_mst) {
> +			int remote_bw_overhead;
> +			int remote_tu;
> +			fixed20_12 pbn;

Nit: pbn_div is only used for MST, so would (calculate/look it up from
mst_state) here. Also this MST block could be in a separate function,
perhaps for symmetry with the SST part in a function too, but this could
be a follow-up as well. Either way:

Reviewed-by: Imre Deak <imre.deak@intel.com>

> +
> +			remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
> +								      true, dsc_slice_count, link_bpp_x16);
> +
> +			/*
> +			 * The TU size programmed to the HW determines which slots in
> +			 * an MTP frame are used for this stream, which needs to match
> +			 * the payload size programmed to the first downstream branch
> +			 * device's payload table.
> +			 *
> +			 * Note that atm the payload's PBN value DRM core sends via
> +			 * the ALLOCATE_PAYLOAD side-band message matches the payload
> +			 * size (which it calculates from the PBN value) it programs
> +			 * to the first branch device's payload table. The allocation
> +			 * in the payload table could be reduced though (to
> +			 * crtc_state->dp_m_n.tu), provided that the driver doesn't
> +			 * enable SSC on the corresponding link.
> +			 */
> +			pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
> +								      link_bpp_x16,
> +								      remote_bw_overhead));
> +			remote_tu = DIV_ROUND_UP(pbn.full, pbn_div.full);
> +
> +			/*
> +			 * Aligning the TUs ensures that symbols consisting of multiple
> +			 * (4) symbol cycles don't get split between two consecutive
> +			 * MTPs, as required by Bspec.
> +			 * TODO: remove the alignment restriction for 128b/132b links
> +			 * on some platforms, where Bspec allows this.
> +			 */
> +			remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);
> +
> +			/*
> +			 * Also align PBNs accordingly, since MST core will derive its
> +			 * own copy of TU from the PBN in drm_dp_atomic_find_time_slots().
> +			 * The above comment about the difference between the PBN
> +			 * allocated for the whole path and the TUs allocated for the
> +			 * first branch device's link also applies here.
> +			 */
> +			pbn.full = remote_tu * pbn_div.full;
> +
> +			drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
> +			crtc_state->dp_m_n.tu = remote_tu;
> +
> +			slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
> +							      connector->port,
> +							      dfixed_trunc(pbn));
> +		} else {
> +			/* Same as above for remote_tu */
> +			crtc_state->dp_m_n.tu = ALIGN(crtc_state->dp_m_n.tu,
> +						      4 / crtc_state->lane_count);
> +
> +			if (crtc_state->dp_m_n.tu <= 64)
> +				slots = crtc_state->dp_m_n.tu;
> +			else
> +				slots = -EINVAL;
> +		}
>  
> -		slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
> -						      connector->port,
> -						      dfixed_trunc(pbn));
>  		if (slots == -EDEADLK)
>  			return slots;
>  
> -- 
> 2.39.5
> 

Re: [PATCH v2 07/16] drm/i915/mst: adapt intel_dp_mtp_tu_compute_config() for 128b/132b SST

[Jani Nikula]

On Tue, 31 Dec 2024, Imre Deak <imre.deak@intel.com> wrote:
> On Thu, Dec 19, 2024 at 11:33:56PM +0200, Jani Nikula wrote:
>> Handle 128b/132b SST in intel_dp_mtp_tu_compute_config(). The remote
>> bandwidth overhead and time slot allocation are only relevant for MST;
>> SST only needs the local bandwidth and a check that 64 slots isn't
>> exceeded.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 109 +++++++++++---------
>>  1 file changed, 61 insertions(+), 48 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> index d08824d2fefe..3fbf9163272b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> @@ -257,10 +257,7 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
>>  
>>  	for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
>>  		int local_bw_overhead;
>> -		int remote_bw_overhead;
>>  		int link_bpp_x16;
>> -		int remote_tu;
>> -		fixed20_12 pbn;
>>  
>>  		drm_dbg_kms(display->drm, "Trying bpp %d\n", bpp);
>>  
>> @@ -269,57 +266,73 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
>>  
>>  		local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
>>  							     false, dsc_slice_count, link_bpp_x16);
>> -		remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
>> -							      true, dsc_slice_count, link_bpp_x16);
>> -
>>  		intel_dp_mst_compute_m_n(crtc_state,
>>  					 local_bw_overhead,
>>  					 link_bpp_x16,
>>  					 &crtc_state->dp_m_n);
>>  
>> -		/*
>> -		 * The TU size programmed to the HW determines which slots in
>> -		 * an MTP frame are used for this stream, which needs to match
>> -		 * the payload size programmed to the first downstream branch
>> -		 * device's payload table.
>> -		 *
>> -		 * Note that atm the payload's PBN value DRM core sends via
>> -		 * the ALLOCATE_PAYLOAD side-band message matches the payload
>> -		 * size (which it calculates from the PBN value) it programs
>> -		 * to the first branch device's payload table. The allocation
>> -		 * in the payload table could be reduced though (to
>> -		 * crtc_state->dp_m_n.tu), provided that the driver doesn't
>> -		 * enable SSC on the corresponding link.
>> -		 */
>> -		pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
>> -							      link_bpp_x16,
>> -							      remote_bw_overhead));
>> -		remote_tu = DIV_ROUND_UP(pbn.full, pbn_div.full);
>> -
>> -		/*
>> -		 * Aligning the TUs ensures that symbols consisting of multiple
>> -		 * (4) symbol cycles don't get split between two consecutive
>> -		 * MTPs, as required by Bspec.
>> -		 * TODO: remove the alignment restriction for 128b/132b links
>> -		 * on some platforms, where Bspec allows this.
>> -		 */
>> -		remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);
>> -
>> -		/*
>> -		 * Also align PBNs accordingly, since MST core will derive its
>> -		 * own copy of TU from the PBN in drm_dp_atomic_find_time_slots().
>> -		 * The above comment about the difference between the PBN
>> -		 * allocated for the whole path and the TUs allocated for the
>> -		 * first branch device's link also applies here.
>> -		 */
>> -		pbn.full = remote_tu * pbn_div.full;
>> -
>> -		drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
>> -		crtc_state->dp_m_n.tu = remote_tu;
>> +		if (intel_dp->is_mst) {
>> +			int remote_bw_overhead;
>> +			int remote_tu;
>> +			fixed20_12 pbn;
>
> Nit: pbn_div is only used for MST, so would (calculate/look it up from
> mst_state) here. Also this MST block could be in a separate function,
> perhaps for symmetry with the SST part in a function too, but this could
> be a follow-up as well. Either way:

I guess I'm just not sure yet which direction this should be taken. It
would be easy enough to add the functions, but is that the right
division? How to handle pbn_div in that case? How is UHBR SST DSC going
to impact all this?

I know I'm kind of weaseling out of fixing this up front, but I also try
to avoid adding stuff that we may have to back out of later.

I think I'd let this be for now.

> Reviewed-by: Imre Deak <imre.deak@intel.com>

Thanks,
Jani.

>
>> +
>> +			remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
>> +								      true, dsc_slice_count, link_bpp_x16);
>> +
>> +			/*
>> +			 * The TU size programmed to the HW determines which slots in
>> +			 * an MTP frame are used for this stream, which needs to match
>> +			 * the payload size programmed to the first downstream branch
>> +			 * device's payload table.
>> +			 *
>> +			 * Note that atm the payload's PBN value DRM core sends via
>> +			 * the ALLOCATE_PAYLOAD side-band message matches the payload
>> +			 * size (which it calculates from the PBN value) it programs
>> +			 * to the first branch device's payload table. The allocation
>> +			 * in the payload table could be reduced though (to
>> +			 * crtc_state->dp_m_n.tu), provided that the driver doesn't
>> +			 * enable SSC on the corresponding link.
>> +			 */
>> +			pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
>> +								      link_bpp_x16,
>> +								      remote_bw_overhead));
>> +			remote_tu = DIV_ROUND_UP(pbn.full, pbn_div.full);
>> +
>> +			/*
>> +			 * Aligning the TUs ensures that symbols consisting of multiple
>> +			 * (4) symbol cycles don't get split between two consecutive
>> +			 * MTPs, as required by Bspec.
>> +			 * TODO: remove the alignment restriction for 128b/132b links
>> +			 * on some platforms, where Bspec allows this.
>> +			 */
>> +			remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);
>> +
>> +			/*
>> +			 * Also align PBNs accordingly, since MST core will derive its
>> +			 * own copy of TU from the PBN in drm_dp_atomic_find_time_slots().
>> +			 * The above comment about the difference between the PBN
>> +			 * allocated for the whole path and the TUs allocated for the
>> +			 * first branch device's link also applies here.
>> +			 */
>> +			pbn.full = remote_tu * pbn_div.full;
>> +
>> +			drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
>> +			crtc_state->dp_m_n.tu = remote_tu;
>> +
>> +			slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
>> +							      connector->port,
>> +							      dfixed_trunc(pbn));
>> +		} else {
>> +			/* Same as above for remote_tu */
>> +			crtc_state->dp_m_n.tu = ALIGN(crtc_state->dp_m_n.tu,
>> +						      4 / crtc_state->lane_count);
>> +
>> +			if (crtc_state->dp_m_n.tu <= 64)
>> +				slots = crtc_state->dp_m_n.tu;
>> +			else
>> +				slots = -EINVAL;
>> +		}
>>  
>> -		slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
>> -						      connector->port,
>> -						      dfixed_trunc(pbn));
>>  		if (slots == -EDEADLK)
>>  			return slots;
>>  
>> -- 
>> 2.39.5
>> 

-- 
Jani Nikula, Intel

Re: [PATCH v2 07/16] drm/i915/mst: adapt intel_dp_mtp_tu_compute_config() for 128b/132b SST

[Imre Deak]

On Thu, Jan 02, 2025 at 12:30:34PM +0200, Jani Nikula wrote:
> On Tue, 31 Dec 2024, Imre Deak <imre.deak@intel.com> wrote:
> > On Thu, Dec 19, 2024 at 11:33:56PM +0200, Jani Nikula wrote:
> >> Handle 128b/132b SST in intel_dp_mtp_tu_compute_config(). The remote
> >> bandwidth overhead and time slot allocation are only relevant for MST;
> >> SST only needs the local bandwidth and a check that 64 slots isn't
> >> exceeded.
> >> 
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 109 +++++++++++---------
> >>  1 file changed, 61 insertions(+), 48 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> >> index d08824d2fefe..3fbf9163272b 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> >> @@ -257,10 +257,7 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
> >>  
> >>  	for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
> >>  		int local_bw_overhead;
> >> -		int remote_bw_overhead;
> >>  		int link_bpp_x16;
> >> -		int remote_tu;
> >> -		fixed20_12 pbn;
> >>  
> >>  		drm_dbg_kms(display->drm, "Trying bpp %d\n", bpp);
> >>  
> >> @@ -269,57 +266,73 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
> >>  
> >>  		local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
> >>  							     false, dsc_slice_count, link_bpp_x16);
> >> -		remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
> >> -							      true, dsc_slice_count, link_bpp_x16);
> >> -
> >>  		intel_dp_mst_compute_m_n(crtc_state,
> >>  					 local_bw_overhead,
> >>  					 link_bpp_x16,
> >>  					 &crtc_state->dp_m_n);
> >>  
> >> -		/*
> >> -		 * The TU size programmed to the HW determines which slots in
> >> -		 * an MTP frame are used for this stream, which needs to match
> >> -		 * the payload size programmed to the first downstream branch
> >> -		 * device's payload table.
> >> -		 *
> >> -		 * Note that atm the payload's PBN value DRM core sends via
> >> -		 * the ALLOCATE_PAYLOAD side-band message matches the payload
> >> -		 * size (which it calculates from the PBN value) it programs
> >> -		 * to the first branch device's payload table. The allocation
> >> -		 * in the payload table could be reduced though (to
> >> -		 * crtc_state->dp_m_n.tu), provided that the driver doesn't
> >> -		 * enable SSC on the corresponding link.
> >> -		 */
> >> -		pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
> >> -							      link_bpp_x16,
> >> -							      remote_bw_overhead));
> >> -		remote_tu = DIV_ROUND_UP(pbn.full, pbn_div.full);
> >> -
> >> -		/*
> >> -		 * Aligning the TUs ensures that symbols consisting of multiple
> >> -		 * (4) symbol cycles don't get split between two consecutive
> >> -		 * MTPs, as required by Bspec.
> >> -		 * TODO: remove the alignment restriction for 128b/132b links
> >> -		 * on some platforms, where Bspec allows this.
> >> -		 */
> >> -		remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);
> >> -
> >> -		/*
> >> -		 * Also align PBNs accordingly, since MST core will derive its
> >> -		 * own copy of TU from the PBN in drm_dp_atomic_find_time_slots().
> >> -		 * The above comment about the difference between the PBN
> >> -		 * allocated for the whole path and the TUs allocated for the
> >> -		 * first branch device's link also applies here.
> >> -		 */
> >> -		pbn.full = remote_tu * pbn_div.full;
> >> -
> >> -		drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
> >> -		crtc_state->dp_m_n.tu = remote_tu;
> >> +		if (intel_dp->is_mst) {
> >> +			int remote_bw_overhead;
> >> +			int remote_tu;
> >> +			fixed20_12 pbn;
> >
> > Nit: pbn_div is only used for MST, so would (calculate/look it up from
> > mst_state) here. Also this MST block could be in a separate function,
> > perhaps for symmetry with the SST part in a function too, but this could
> > be a follow-up as well. Either way:
> 
> I guess I'm just not sure yet which direction this should be taken. It
> would be easy enough to add the functions, but is that the right
> division? How to handle pbn_div in that case?

It's only needed to calculate PBN, hence only for MST. So the MST helper
could just use

	drm_atomic_get_new_mst_topology_state()->pbn_div

> How is UHBR SST DSC going to impact all this?

Calculating PBN is only needed for MST, so it doesn't change the SST DSC
handling.

> I know I'm kind of weaseling out of fixing this up front, but I also try
> to avoid adding stuff that we may have to back out of later.
> 
> I think I'd let this be for now.

Ok.

> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> Thanks,
> Jani.
> 
> >
> >> +
> >> +			remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
> >> +								      true, dsc_slice_count, link_bpp_x16);
> >> +
> >> +			/*
> >> +			 * The TU size programmed to the HW determines which slots in
> >> +			 * an MTP frame are used for this stream, which needs to match
> >> +			 * the payload size programmed to the first downstream branch
> >> +			 * device's payload table.
> >> +			 *
> >> +			 * Note that atm the payload's PBN value DRM core sends via
> >> +			 * the ALLOCATE_PAYLOAD side-band message matches the payload
> >> +			 * size (which it calculates from the PBN value) it programs
> >> +			 * to the first branch device's payload table. The allocation
> >> +			 * in the payload table could be reduced though (to
> >> +			 * crtc_state->dp_m_n.tu), provided that the driver doesn't
> >> +			 * enable SSC on the corresponding link.
> >> +			 */
> >> +			pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
> >> +								      link_bpp_x16,
> >> +								      remote_bw_overhead));
> >> +			remote_tu = DIV_ROUND_UP(pbn.full, pbn_div.full);
> >> +
> >> +			/*
> >> +			 * Aligning the TUs ensures that symbols consisting of multiple
> >> +			 * (4) symbol cycles don't get split between two consecutive
> >> +			 * MTPs, as required by Bspec.
> >> +			 * TODO: remove the alignment restriction for 128b/132b links
> >> +			 * on some platforms, where Bspec allows this.
> >> +			 */
> >> +			remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);
> >> +
> >> +			/*
> >> +			 * Also align PBNs accordingly, since MST core will derive its
> >> +			 * own copy of TU from the PBN in drm_dp_atomic_find_time_slots().
> >> +			 * The above comment about the difference between the PBN
> >> +			 * allocated for the whole path and the TUs allocated for the
> >> +			 * first branch device's link also applies here.
> >> +			 */
> >> +			pbn.full = remote_tu * pbn_div.full;
> >> +
> >> +			drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
> >> +			crtc_state->dp_m_n.tu = remote_tu;
> >> +
> >> +			slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
> >> +							      connector->port,
> >> +							      dfixed_trunc(pbn));
> >> +		} else {
> >> +			/* Same as above for remote_tu */
> >> +			crtc_state->dp_m_n.tu = ALIGN(crtc_state->dp_m_n.tu,
> >> +						      4 / crtc_state->lane_count);
> >> +
> >> +			if (crtc_state->dp_m_n.tu <= 64)
> >> +				slots = crtc_state->dp_m_n.tu;
> >> +			else
> >> +				slots = -EINVAL;
> >> +		}
> >>  
> >> -		slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
> >> -						      connector->port,
> >> -						      dfixed_trunc(pbn));
> >>  		if (slots == -EDEADLK)
> >>  			return slots;
> >>  
> >> -- 
> >> 2.39.5
> >> 
> 
> -- 
> Jani Nikula, Intel

[PATCH v2 08/16] drm/i915/ddi: enable 128b/132b TRANS_DDI_FUNC_CTL mode for UHBR SST

[Jani Nikula]

128b/132b SST needs 128b/132b mode enabled in the TRANS_DDI_FUNC_CTL
register.

This is preparation for enabling 128b/132b SST. This path is not
reachable yet.

v2: Use the MST path instead of SST to also set transport select (Imre)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4f9c50996446..ce34a619d48a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -561,7 +561,8 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 		temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
 		temp |= (crtc_state->fdi_lanes - 1) << 1;
-	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
+	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
+		   intel_dp_is_uhbr(crtc_state)) {
 		if (intel_dp_is_uhbr(crtc_state))
 			temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
 		else
-- 
2.39.5

Re: [PATCH v2 08/16] drm/i915/ddi: enable 128b/132b TRANS_DDI_FUNC_CTL mode for UHBR SST

[Imre Deak]

On Thu, Dec 19, 2024 at 11:33:57PM +0200, Jani Nikula wrote:
> 128b/132b SST needs 128b/132b mode enabled in the TRANS_DDI_FUNC_CTL
> register.
> 
> This is preparation for enabling 128b/132b SST. This path is not
> reachable yet.
> 
> v2: Use the MST path instead of SST to also set transport select (Imre)
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4f9c50996446..ce34a619d48a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -561,7 +561,8 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
>  	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
>  		temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
>  		temp |= (crtc_state->fdi_lanes - 1) << 1;
> -	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
> +	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
> +		   intel_dp_is_uhbr(crtc_state)) {
>  		if (intel_dp_is_uhbr(crtc_state))
>  			temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
>  		else
> -- 
> 2.39.5
> 

[PATCH v2 09/16] drm/i915/ddi: 128b/132b SST also needs DP_TP_CTL_MODE_MST

[Jani Nikula]

It's not very clearly specified, and the hardware bit is ill-named, but
128b/132b SST also needs the MST mode set in the DP_TP_CTL register.

This is preparation for enabling 128b/132b SST. This path is not
reachable yet.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ce34a619d48a..6f813bf85b23 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3656,7 +3656,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 
 	/* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */
 	dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
+	    intel_dp_is_uhbr(crtc_state)) {
 		dp_tp_ctl |= DP_TP_CTL_MODE_MST;
 	} else {
 		dp_tp_ctl |= DP_TP_CTL_MODE_SST;
@@ -3716,7 +3717,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 	}
 
 	dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
+	    intel_dp_is_uhbr(crtc_state)) {
 		dp_tp_ctl |= DP_TP_CTL_MODE_MST;
 	} else {
 		dp_tp_ctl |= DP_TP_CTL_MODE_SST;
-- 
2.39.5

Re: [PATCH v2 09/16] drm/i915/ddi: 128b/132b SST also needs DP_TP_CTL_MODE_MST

[Imre Deak]

On Thu, Dec 19, 2024 at 11:33:58PM +0200, Jani Nikula wrote:
> It's not very clearly specified, and the hardware bit is ill-named, but
> 128b/132b SST also needs the MST mode set in the DP_TP_CTL register.
> 
> This is preparation for enabling 128b/132b SST. This path is not
> reachable yet.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index ce34a619d48a..6f813bf85b23 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3656,7 +3656,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
>  
>  	/* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */
>  	dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
> +	    intel_dp_is_uhbr(crtc_state)) {
>  		dp_tp_ctl |= DP_TP_CTL_MODE_MST;
>  	} else {
>  		dp_tp_ctl |= DP_TP_CTL_MODE_SST;
> @@ -3716,7 +3717,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
>  	}
>  
>  	dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
> +	    intel_dp_is_uhbr(crtc_state)) {
>  		dp_tp_ctl |= DP_TP_CTL_MODE_MST;
>  	} else {
>  		dp_tp_ctl |= DP_TP_CTL_MODE_SST;
> -- 
> 2.39.5
> 

[PATCH v2 10/16] drm/i915/ddi: write payload for 128b/132b SST

[Jani Nikula]

Write the payload allocation table for 128b/132b SST. Use VCPID 1 and
start from slot 0, with dp_m_n.tu slots.

This is preparation for enabling 128b/132b SST. This path is not
reachable yet. Indeed, we don't yet compute TU for 128b/132b SST.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6f813bf85b23..64528ff8856e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2669,6 +2669,12 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	/* 6.o Configure and enable FEC if needed */
 	intel_ddi_enable_fec(encoder, crtc_state);
 
+	/* 7.a 128b/132b SST. */
+	if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
+		/* VCPID 1, start slot 0 for 128b/132b, tu slots */
+		drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
+	}
+
 	if (!is_mst)
 		intel_dsc_dp_pps_write(encoder, crtc_state);
 }
@@ -2808,6 +2814,11 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	/* 7.l Configure and enable FEC if needed */
 	intel_ddi_enable_fec(encoder, crtc_state);
 
+	if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
+		/* VCPID 1, start slot 0 for 128b/132b, tu slots */
+		drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
+	}
+
 	if (!is_mst)
 		intel_dsc_dp_pps_write(encoder, crtc_state);
 }
-- 
2.39.5

Re: [PATCH v2 10/16] drm/i915/ddi: write payload for 128b/132b SST

[Imre Deak]

On Thu, Dec 19, 2024 at 11:33:59PM +0200, Jani Nikula wrote:
> Write the payload allocation table for 128b/132b SST. Use VCPID 1 and
> start from slot 0, with dp_m_n.tu slots.
> 
> This is preparation for enabling 128b/132b SST. This path is not
> reachable yet. Indeed, we don't yet compute TU for 128b/132b SST.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 6f813bf85b23..64528ff8856e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2669,6 +2669,12 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  	/* 6.o Configure and enable FEC if needed */
>  	intel_ddi_enable_fec(encoder, crtc_state);
>  
> +	/* 7.a 128b/132b SST. */
> +	if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
> +		/* VCPID 1, start slot 0 for 128b/132b, tu slots */
> +		drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);

I would handle the error by sending a modeset retry uevent. Either way:

Reviewed-by: Imre Deak <imre.deak@intel.com>

> +	}
> +
>  	if (!is_mst)
>  		intel_dsc_dp_pps_write(encoder, crtc_state);
>  }
> @@ -2808,6 +2814,11 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  	/* 7.l Configure and enable FEC if needed */
>  	intel_ddi_enable_fec(encoder, crtc_state);
>  
> +	if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
> +		/* VCPID 1, start slot 0 for 128b/132b, tu slots */
> +		drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
> +	}
> +
>  	if (!is_mst)
>  		intel_dsc_dp_pps_write(encoder, crtc_state);
>  }
> -- 
> 2.39.5
> 

Re: [PATCH v2 10/16] drm/i915/ddi: write payload for 128b/132b SST

[Jani Nikula]

On Tue, 31 Dec 2024, Imre Deak <imre.deak@intel.com> wrote:
> On Thu, Dec 19, 2024 at 11:33:59PM +0200, Jani Nikula wrote:
>> Write the payload allocation table for 128b/132b SST. Use VCPID 1 and
>> start from slot 0, with dp_m_n.tu slots.
>> 
>> This is preparation for enabling 128b/132b SST. This path is not
>> reachable yet. Indeed, we don't yet compute TU for 128b/132b SST.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++++++++++
>>  1 file changed, 11 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index 6f813bf85b23..64528ff8856e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -2669,6 +2669,12 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>>  	/* 6.o Configure and enable FEC if needed */
>>  	intel_ddi_enable_fec(encoder, crtc_state);
>>  
>> +	/* 7.a 128b/132b SST. */
>> +	if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
>> +		/* VCPID 1, start slot 0 for 128b/132b, tu slots */
>> +		drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
>
> I would handle the error by sending a modeset retry uevent. Either way:

Mmmh. The MST code calls intel_dp_queue_modeset_retry_for_link() in
response to drm_dp_add_payload_part{1,2}() failures, but nothing
else. As in, we don't do anything else (we just plunge on with the
enable), and we don't even do that much in response to any other errors.

Our options are limited anyway.

Arguably the MST path payload update has more failure modes than SST,
but you'd like to do this:

	ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
	if (ret < 0)
		intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);

in mtl_ddi_pre_enable_dp() and tgl_ddi_pre_enable_dp()?

Overall I'm wondering if this too needs an overhaul. Instead of queueing
the retry all over the place, maybe we should just flag it in
crtc_state, and have intel_atomic_cleanup_work() do it once afterwards?


BR,
Jani.

>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
>
>> +	}
>> +
>>  	if (!is_mst)
>>  		intel_dsc_dp_pps_write(encoder, crtc_state);
>>  }
>> @@ -2808,6 +2814,11 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>>  	/* 7.l Configure and enable FEC if needed */
>>  	intel_ddi_enable_fec(encoder, crtc_state);
>>  
>> +	if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
>> +		/* VCPID 1, start slot 0 for 128b/132b, tu slots */
>> +		drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
>> +	}
>> +
>>  	if (!is_mst)
>>  		intel_dsc_dp_pps_write(encoder, crtc_state);
>>  }
>> -- 
>> 2.39.5
>> 

-- 
Jani Nikula, Intel

Re: [PATCH v2 10/16] drm/i915/ddi: write payload for 128b/132b SST

[Imre Deak]

On Thu, Jan 02, 2025 at 12:52:38PM +0200, Jani Nikula wrote:
> On Tue, 31 Dec 2024, Imre Deak <imre.deak@intel.com> wrote:
> > On Thu, Dec 19, 2024 at 11:33:59PM +0200, Jani Nikula wrote:
> >> Write the payload allocation table for 128b/132b SST. Use VCPID 1 and
> >> start from slot 0, with dp_m_n.tu slots.
> >> 
> >> This is preparation for enabling 128b/132b SST. This path is not
> >> reachable yet. Indeed, we don't yet compute TU for 128b/132b SST.
> >> 
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++++++++++
> >>  1 file changed, 11 insertions(+)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> index 6f813bf85b23..64528ff8856e 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> @@ -2669,6 +2669,12 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> >>  	/* 6.o Configure and enable FEC if needed */
> >>  	intel_ddi_enable_fec(encoder, crtc_state);
> >>  
> >> +	/* 7.a 128b/132b SST. */
> >> +	if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
> >> +		/* VCPID 1, start slot 0 for 128b/132b, tu slots */
> >> +		drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
> >
> > I would handle the error by sending a modeset retry uevent. Either way:
> 
> Mmmh. The MST code calls intel_dp_queue_modeset_retry_for_link() in
> response to drm_dp_add_payload_part{1,2}() failures, but nothing
> else. As in, we don't do anything else (we just plunge on with the
> enable), and we don't even do that much in response to any other errors.
> 
> Our options are limited anyway.

The right thing to do is to report all these errors to user space, so it
can recover from it.

> Arguably the MST path payload update has more failure modes than SST,
> but you'd like to do this:
> 
> 	ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
> 	if (ret < 0)
> 		intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
> 
> in mtl_ddi_pre_enable_dp() and tgl_ddi_pre_enable_dp()?

Yes.

> Overall I'm wondering if this too needs an overhaul. Instead of queueing
> the retry all over the place, maybe we should just flag it in
> crtc_state, and have intel_atomic_cleanup_work() do it once afterwards?

Atm it's queued once after detecting the first error, not sure if
deferring that would be better.

> BR,
> Jani.
> 
> >
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> >
> >> +	}
> >> +
> >>  	if (!is_mst)
> >>  		intel_dsc_dp_pps_write(encoder, crtc_state);
> >>  }
> >> @@ -2808,6 +2814,11 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> >>  	/* 7.l Configure and enable FEC if needed */
> >>  	intel_ddi_enable_fec(encoder, crtc_state);
> >>  
> >> +	if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
> >> +		/* VCPID 1, start slot 0 for 128b/132b, tu slots */
> >> +		drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
> >> +	}
> >> +
> >>  	if (!is_mst)
> >>  		intel_dsc_dp_pps_write(encoder, crtc_state);
> >>  }
> >> -- 
> >> 2.39.5
> >> 
> 
> -- 
> Jani Nikula, Intel

[PATCH v2 11/16] drm/i915/ddi: initialize 128b/132b SST DP2 VFREQ registers

[Jani Nikula]

Write the DP2 specific VFREQ registers.

This is preparation for enabling 128b/132b SST. This path is not
reachable yet.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 64528ff8856e..91e6cd91e91f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3467,8 +3467,20 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
 {
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_crtc *pipe_crtc;
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	int i;
 
+	/* 128b/132b SST */
+	if (intel_dp_is_uhbr(crtc_state)) {
+		const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+		u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
+
+		intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder),
+			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
+		intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder),
+			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
+	}
+
 	intel_ddi_enable_transcoder_func(encoder, crtc_state);
 
 	/* Enable/Disable DP2.0 SDP split config before transcoder */
-- 
2.39.5

Re: [PATCH v2 11/16] drm/i915/ddi: initialize 128b/132b SST DP2 VFREQ registers

[Imre Deak]

On Thu, Dec 19, 2024 at 11:34:00PM +0200, Jani Nikula wrote:
> Write the DP2 specific VFREQ registers.
> 
> This is preparation for enabling 128b/132b SST. This path is not
> reachable yet.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 64528ff8856e..91e6cd91e91f 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3467,8 +3467,20 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
>  {
>  	struct intel_display *display = to_intel_display(encoder);
>  	struct intel_crtc *pipe_crtc;
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	int i;
>  
> +	/* 128b/132b SST */
> +	if (intel_dp_is_uhbr(crtc_state)) {
> +		const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +		u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
> +
> +		intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder),
> +			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
> +		intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder),
> +			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
> +	}
> +

Nit: This could be in a helper, used by the MST encoder as well. Either way:

Reviewed-by: Imre Deak <imre.deak@intel.com>

>  	intel_ddi_enable_transcoder_func(encoder, crtc_state);
>  
>  	/* Enable/Disable DP2.0 SDP split config before transcoder */
> -- 
> 2.39.5
> 

Re: [PATCH v2 11/16] drm/i915/ddi: initialize 128b/132b SST DP2 VFREQ registers

[Imre Deak]

On Thu, Dec 19, 2024 at 11:34:00PM +0200, Jani Nikula wrote:
> Write the DP2 specific VFREQ registers.
> 
> This is preparation for enabling 128b/132b SST. This path is not
> reachable yet.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 64528ff8856e..91e6cd91e91f 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3467,8 +3467,20 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
>  {
>  	struct intel_display *display = to_intel_display(encoder);
>  	struct intel_crtc *pipe_crtc;
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	int i;
>  
> +	/* 128b/132b SST */
> +	if (intel_dp_is_uhbr(crtc_state)) {

Hm, not sure how this would work on HDMI (FRL), but to be sure shouldn't
this check that crtc_state is for a DP (SST) mode?

> +		const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +		u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
> +
> +		intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder),
> +			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
> +		intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder),
> +			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
> +	}
> +
>  	intel_ddi_enable_transcoder_func(encoder, crtc_state);
>  
>  	/* Enable/Disable DP2.0 SDP split config before transcoder */
> -- 
> 2.39.5
> 

Re: [PATCH v2 11/16] drm/i915/ddi: initialize 128b/132b SST DP2 VFREQ registers

[Jani Nikula]

On Tue, 31 Dec 2024, Imre Deak <imre.deak@intel.com> wrote:
> On Thu, Dec 19, 2024 at 11:34:00PM +0200, Jani Nikula wrote:
>> Write the DP2 specific VFREQ registers.
>> 
>> This is preparation for enabling 128b/132b SST. This path is not
>> reachable yet.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index 64528ff8856e..91e6cd91e91f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -3467,8 +3467,20 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
>>  {
>>  	struct intel_display *display = to_intel_display(encoder);
>>  	struct intel_crtc *pipe_crtc;
>> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>>  	int i;
>>  
>> +	/* 128b/132b SST */
>> +	if (intel_dp_is_uhbr(crtc_state)) {
>
> Hm, not sure how this would work on HDMI (FRL), but to be sure shouldn't
> this check that crtc_state is for a DP (SST) mode?

DP MST does not call intel_ddi_enable().

Yes, it's all very subtle, and I hate the way all of the
DDI/SST/MST/etc. is intertwined, but I feel like it's overall a bigger
refactoring to clean up.

BR,
Jani.


>
>> +		const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>> +		u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
>> +
>> +		intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder),
>> +			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
>> +		intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder),
>> +			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
>> +	}
>> +
>>  	intel_ddi_enable_transcoder_func(encoder, crtc_state);
>>  
>>  	/* Enable/Disable DP2.0 SDP split config before transcoder */
>> -- 
>> 2.39.5
>> 

-- 
Jani Nikula, Intel

Re: [PATCH v2 11/16] drm/i915/ddi: initialize 128b/132b SST DP2 VFREQ registers

[Imre Deak]

On Thu, Jan 02, 2025 at 11:39:07AM +0200, Jani Nikula wrote:
> On Tue, 31 Dec 2024, Imre Deak <imre.deak@intel.com> wrote:
> > On Thu, Dec 19, 2024 at 11:34:00PM +0200, Jani Nikula wrote:
> >> Write the DP2 specific VFREQ registers.
> >> 
> >> This is preparation for enabling 128b/132b SST. This path is not
> >> reachable yet.
> >> 
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++++++++
> >>  1 file changed, 12 insertions(+)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> index 64528ff8856e..91e6cd91e91f 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> @@ -3467,8 +3467,20 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
> >>  {
> >>  	struct intel_display *display = to_intel_display(encoder);
> >>  	struct intel_crtc *pipe_crtc;
> >> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >>  	int i;
> >>  
> >> +	/* 128b/132b SST */
> >> +	if (intel_dp_is_uhbr(crtc_state)) {
> >
> > Hm, not sure how this would work on HDMI (FRL), but to be sure shouldn't
> > this check that crtc_state is for a DP (SST) mode?
> 
> DP MST does not call intel_ddi_enable().

I meant that this function (intel_ddi_enable()) can be called for HDMI
as well, in case of HDMI FRL with port clock being >= 10G. In that case
this - and the payload related bits later - shouldn't be programmed. So
would need if (!hdmi && intel_dp_is_uhbr()).

> Yes, it's all very subtle, and I hate the way all of the
> DDI/SST/MST/etc. is intertwined, but I feel like it's overall a bigger
> refactoring to clean up.
> 
> BR,
> Jani.
> 
> 
> >
> >> +		const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> >> +		u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
> >> +
> >> +		intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder),
> >> +			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
> >> +		intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder),
> >> +			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
> >> +	}
> >> +
> >>  	intel_ddi_enable_transcoder_func(encoder, crtc_state);
> >>  
> >>  	/* Enable/Disable DP2.0 SDP split config before transcoder */
> >> -- 
> >> 2.39.5
> >> 
> 
> -- 
> Jani Nikula, Intel

[PATCH v2 12/16] drm/i915/ddi: enable ACT handling for 128b/132b SST

[Jani Nikula]

Add ACT handling for 128b/132b SST.

This is preparation for enabling 128b/132b SST. This path is not
reachable yet.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 91e6cd91e91f..7b739b9c5a06 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3486,6 +3486,19 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
 	/* Enable/Disable DP2.0 SDP split config before transcoder */
 	intel_audio_sdp_split_update(crtc_state);
 
+	/* 128b/132b SST */
+	if (intel_dp_is_uhbr(crtc_state)) {
+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+		intel_ddi_clear_act_sent(encoder, crtc_state);
+
+		intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0,
+			     TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
+
+		intel_ddi_wait_for_act_sent(encoder, crtc_state);
+		drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);
+	}
+
 	intel_enable_transcoder(crtc_state);
 
 	intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
-- 
2.39.5

Re: [PATCH v2 12/16] drm/i915/ddi: enable ACT handling for 128b/132b SST

[Imre Deak]

On Thu, Dec 19, 2024 at 11:34:01PM +0200, Jani Nikula wrote:
> Add ACT handling for 128b/132b SST.
> 
> This is preparation for enabling 128b/132b SST. This path is not
> reachable yet.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 91e6cd91e91f..7b739b9c5a06 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3486,6 +3486,19 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
>  	/* Enable/Disable DP2.0 SDP split config before transcoder */
>  	intel_audio_sdp_split_update(crtc_state);
>  
> +	/* 128b/132b SST */
> +	if (intel_dp_is_uhbr(crtc_state)) {

Imo, as before the above would also need !hdmi.

> +		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> +		intel_ddi_clear_act_sent(encoder, crtc_state);
> +
> +		intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0,
> +			     TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> +
> +		intel_ddi_wait_for_act_sent(encoder, crtc_state);
> +		drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);

The spec requires doing the reverse during disabling - delete the stream
in the payload table, clear the payload alloc flag and wait for both ACT
handled both in DP_TP_STATUS and DPCD, see bspec 68849 / Disable Sequence
steps g/h.

> +	}
> +
>  	intel_enable_transcoder(crtc_state);
>  
>  	intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
> -- 
> 2.39.5
> 

[PATCH v2 13/16] drm/i915/ddi: start distinguishing 128b/132b SST and MST at state readout

[Jani Nikula]

We'll want to distinguish 128b/132b SST and MST modes at state
readout. There's a catch, though. From the hardware perspective,
128b/132b SST and MST programming are pretty much the same. And we can't
really ask the sink at this point.

If we have more than one transcoder in 128b/132b mode associated with
the port, we can safely assume it's MST. But for MST with only a single
stream enabled, we are pretty much out of luck. Let's fall back to
looking at the software state, i.e. intel_dp->is_mst. It should be fine
for the state checker, but for hardware takeover at probe, we'll have to
trust the GOP has only enabled SST.

TODO: Not sure how this *or* our current code handles 128b/132b enabled
by GOP.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 29 +++++++++++++++++++-----
 1 file changed, 23 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7b739b9c5a06..04118f2eea94 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -786,7 +786,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 	intel_wakeref_t wakeref;
 	enum pipe p;
 	u32 tmp;
-	u8 mst_pipe_mask;
+	u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0;
 
 	*pipe_mask = 0;
 	*is_dp_mst = false;
@@ -823,7 +823,6 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 		goto out;
 	}
 
-	mst_pipe_mask = 0;
 	for_each_pipe(dev_priv, p) {
 		enum transcoder cpu_transcoder = (enum transcoder)p;
 		u32 port_mask, ddi_select, ddi_mode;
@@ -852,9 +851,10 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 
 		ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK;
 
-		if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST ||
-		    (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)))
+		if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)
 			mst_pipe_mask |= BIT(p);
+		else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))
+			dp128b132b_pipe_mask |= BIT(p);
 
 		*pipe_mask |= BIT(p);
 	}
@@ -864,6 +864,23 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 			    "No pipe for [ENCODER:%d:%s] found\n",
 			    encoder->base.base.id, encoder->base.name);
 
+	if (!mst_pipe_mask && dp128b132b_pipe_mask) {
+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+		/*
+		 * If we don't have 8b/10b MST, but have more than one
+		 * transcoder in 128b/132b mode, we know it must be 128b/132b
+		 * MST.
+		 *
+		 * Otherwise, we fall back to checking the current MST
+		 * state. It's not accurate for hardware takeover at probe, but
+		 * we don't expect MST to have been enabled at that point, and
+		 * can assume it's SST.
+		 */
+		if (hweight8(dp128b132b_pipe_mask) > 1 || intel_dp->is_mst)
+			mst_pipe_mask = dp128b132b_pipe_mask;
+	}
+
 	if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
@@ -874,9 +891,9 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 
 	if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
 		drm_dbg_kms(&dev_priv->drm,
-			    "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
+			    "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n",
 			    encoder->base.base.id, encoder->base.name,
-			    *pipe_mask, mst_pipe_mask);
+			    *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask);
 	else
 		*is_dp_mst = mst_pipe_mask;
 
-- 
2.39.5

Re: [PATCH v2 13/16] drm/i915/ddi: start distinguishing 128b/132b SST and MST at state readout

[Imre Deak]

On Thu, Dec 19, 2024 at 11:34:02PM +0200, Jani Nikula wrote:
> We'll want to distinguish 128b/132b SST and MST modes at state
> readout. There's a catch, though. From the hardware perspective,
> 128b/132b SST and MST programming are pretty much the same. And we can't
> really ask the sink at this point.
> 
> If we have more than one transcoder in 128b/132b mode associated with
> the port, we can safely assume it's MST. But for MST with only a single
> stream enabled, we are pretty much out of luck. Let's fall back to
> looking at the software state, i.e. intel_dp->is_mst. It should be fine
> for the state checker, but for hardware takeover at probe, we'll have to
> trust the GOP has only enabled SST.
> 
> TODO: Not sure how this *or* our current code handles 128b/132b enabled
> by GOP.
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 29 +++++++++++++++++++-----
>  1 file changed, 23 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 7b739b9c5a06..04118f2eea94 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -786,7 +786,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
>  	intel_wakeref_t wakeref;
>  	enum pipe p;
>  	u32 tmp;
> -	u8 mst_pipe_mask;
> +	u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0;
>  
>  	*pipe_mask = 0;
>  	*is_dp_mst = false;
> @@ -823,7 +823,6 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
>  		goto out;
>  	}
>  
> -	mst_pipe_mask = 0;
>  	for_each_pipe(dev_priv, p) {
>  		enum transcoder cpu_transcoder = (enum transcoder)p;
>  		u32 port_mask, ddi_select, ddi_mode;
> @@ -852,9 +851,10 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
>  
>  		ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK;
>  
> -		if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST ||
> -		    (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)))
> +		if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)
>  			mst_pipe_mask |= BIT(p);
> +		else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))
> +			dp128b132b_pipe_mask |= BIT(p);
>  
>  		*pipe_mask |= BIT(p);
>  	}
> @@ -864,6 +864,23 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
>  			    "No pipe for [ENCODER:%d:%s] found\n",
>  			    encoder->base.base.id, encoder->base.name);
>  
> +	if (!mst_pipe_mask && dp128b132b_pipe_mask) {
> +		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +

8b10b and 128b132b can't be mixed on one link, so the above could make
this clear (and more robust) by

	if (dp128b132b_pipe_mask) {
		if (WARN(mst_pipe_mask))
			mst_pipe_mask = 0;

In any case the patch is correct, so either way:

Reviewed-by: Imre Deak <imre.deak@intel.com>

> +		/*
> +		 * If we don't have 8b/10b MST, but have more than one
> +		 * transcoder in 128b/132b mode, we know it must be 128b/132b
> +		 * MST.
> +		 *
> +		 * Otherwise, we fall back to checking the current MST
> +		 * state. It's not accurate for hardware takeover at probe, but
> +		 * we don't expect MST to have been enabled at that point, and
> +		 * can assume it's SST.
> +		 */
> +		if (hweight8(dp128b132b_pipe_mask) > 1 || intel_dp->is_mst)
> +			mst_pipe_mask = dp128b132b_pipe_mask;
> +	}
> +
>  	if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
> @@ -874,9 +891,9 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
>  
>  	if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
>  		drm_dbg_kms(&dev_priv->drm,
> -			    "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
> +			    "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n",
>  			    encoder->base.base.id, encoder->base.name,
> -			    *pipe_mask, mst_pipe_mask);
> +			    *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask);
>  	else
>  		*is_dp_mst = mst_pipe_mask;
>  
> -- 
> 2.39.5
> 

Re: [PATCH v2 13/16] drm/i915/ddi: start distinguishing 128b/132b SST and MST at state readout

[Jani Nikula]

On Thu, 02 Jan 2025, Imre Deak <imre.deak@intel.com> wrote:
> On Thu, Dec 19, 2024 at 11:34:02PM +0200, Jani Nikula wrote:
>> We'll want to distinguish 128b/132b SST and MST modes at state
>> readout. There's a catch, though. From the hardware perspective,
>> 128b/132b SST and MST programming are pretty much the same. And we can't
>> really ask the sink at this point.
>> 
>> If we have more than one transcoder in 128b/132b mode associated with
>> the port, we can safely assume it's MST. But for MST with only a single
>> stream enabled, we are pretty much out of luck. Let's fall back to
>> looking at the software state, i.e. intel_dp->is_mst. It should be fine
>> for the state checker, but for hardware takeover at probe, we'll have to
>> trust the GOP has only enabled SST.
>> 
>> TODO: Not sure how this *or* our current code handles 128b/132b enabled
>> by GOP.
>> 
>> Cc: Imre Deak <imre.deak@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_ddi.c | 29 +++++++++++++++++++-----
>>  1 file changed, 23 insertions(+), 6 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index 7b739b9c5a06..04118f2eea94 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -786,7 +786,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
>>  	intel_wakeref_t wakeref;
>>  	enum pipe p;
>>  	u32 tmp;
>> -	u8 mst_pipe_mask;
>> +	u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0;
>>  
>>  	*pipe_mask = 0;
>>  	*is_dp_mst = false;
>> @@ -823,7 +823,6 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
>>  		goto out;
>>  	}
>>  
>> -	mst_pipe_mask = 0;
>>  	for_each_pipe(dev_priv, p) {
>>  		enum transcoder cpu_transcoder = (enum transcoder)p;
>>  		u32 port_mask, ddi_select, ddi_mode;
>> @@ -852,9 +851,10 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
>>  
>>  		ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK;
>>  
>> -		if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST ||
>> -		    (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)))
>> +		if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)
>>  			mst_pipe_mask |= BIT(p);
>> +		else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))
>> +			dp128b132b_pipe_mask |= BIT(p);
>>  
>>  		*pipe_mask |= BIT(p);
>>  	}
>> @@ -864,6 +864,23 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
>>  			    "No pipe for [ENCODER:%d:%s] found\n",
>>  			    encoder->base.base.id, encoder->base.name);
>>  
>> +	if (!mst_pipe_mask && dp128b132b_pipe_mask) {
>> +		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> +
>
> 8b10b and 128b132b can't be mixed on one link, so the above could make
> this clear (and more robust) by
>
> 	if (dp128b132b_pipe_mask) {
> 		if (WARN(mst_pipe_mask))
> 			mst_pipe_mask = 0;

They can't be mixed, but doesn't mean the registers can't contain that
stuff!

The point is any goof-ups like that get caught in one place below...

> In any case the patch is correct, so either way:
>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
>
>> +		/*
>> +		 * If we don't have 8b/10b MST, but have more than one
>> +		 * transcoder in 128b/132b mode, we know it must be 128b/132b
>> +		 * MST.
>> +		 *
>> +		 * Otherwise, we fall back to checking the current MST
>> +		 * state. It's not accurate for hardware takeover at probe, but
>> +		 * we don't expect MST to have been enabled at that point, and
>> +		 * can assume it's SST.
>> +		 */
>> +		if (hweight8(dp128b132b_pipe_mask) > 1 || intel_dp->is_mst)
>> +			mst_pipe_mask = dp128b132b_pipe_mask;
>> +	}
>> +
>>  	if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
>>  		drm_dbg_kms(&dev_priv->drm,
>>  			    "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
>> @@ -874,9 +891,9 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
>>  
>>  	if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)

...here. If both mst_pipe_mask != 0 and dp128b132b_pipe_mask != 0, then
mst_pipe_mask != *pipe_mask.

BR,
Jani.

>>  		drm_dbg_kms(&dev_priv->drm,
>> -			    "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
>> +			    "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n",
>>  			    encoder->base.base.id, encoder->base.name,
>> -			    *pipe_mask, mst_pipe_mask);
>> +			    *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask);
>>  	else
>>  		*is_dp_mst = mst_pipe_mask;
>>  
>> -- 
>> 2.39.5
>> 

-- 
Jani Nikula, Intel

[PATCH v2 14/16] drm/i915/ddi: handle 128b/132b SST in intel_ddi_read_func_ctl()

[Jani Nikula]

We'll only ever get here in MST mode from MST stream encoders; the
primary encoder's ->get_config() won't be called when we've detected
it's MST.

v2: Read mst_master_transcoder in 128b/132b SST path (Imre)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 04118f2eea94..37b771f07d59 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4026,6 +4026,11 @@ static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder,
 	crtc_state->lane_count =
 		((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
 
+	if (DISPLAY_VER(display) >= 12 &&
+	    (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)
+		crtc_state->mst_master_transcoder =
+			REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
+
 	intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
 	intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2);
 
@@ -4120,9 +4125,19 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
 		intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl);
 	} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) {
 		intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl);
-	} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST ||
-		   (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))) {
+	} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) {
 		intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl);
+	} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) {
+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+		/*
+		 * If this is true, we know we're being called from mst stream
+		 * encoder's ->get_config().
+		 */
+		if (intel_dp->is_mst)
+			intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl);
+		else
+			intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl);
 	}
 }
 
-- 
2.39.5

Re: [PATCH v2 14/16] drm/i915/ddi: handle 128b/132b SST in intel_ddi_read_func_ctl()

[Imre Deak]

On Thu, Dec 19, 2024 at 11:34:03PM +0200, Jani Nikula wrote:
> We'll only ever get here in MST mode from MST stream encoders; the
> primary encoder's ->get_config() won't be called when we've detected
> it's MST.
> 
> v2: Read mst_master_transcoder in 128b/132b SST path (Imre)
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 19 +++++++++++++++++--
>  1 file changed, 17 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 04118f2eea94..37b771f07d59 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4026,6 +4026,11 @@ static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder,
>  	crtc_state->lane_count =
>  		((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
>  
> +	if (DISPLAY_VER(display) >= 12 &&
> +	    (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)
> +		crtc_state->mst_master_transcoder =
> +			REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
> +
>  	intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
>  	intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2);
>  
> @@ -4120,9 +4125,19 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
>  		intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl);
>  	} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) {
>  		intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl);
> -	} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST ||
> -		   (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))) {
> +	} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) {
>  		intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl);
> +	} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) {
> +		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> +		/*
> +		 * If this is true, we know we're being called from mst stream
> +		 * encoder's ->get_config().
> +		 */
> +		if (intel_dp->is_mst)
> +			intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl);
> +		else
> +			intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl);
>  	}
>  }
>  
> -- 
> 2.39.5
> 

[PATCH v2 15/16] drm/i915/ddi: disable trancoder port select for 128b/132b SST

[Jani Nikula]

128b/1232b SST will have mst_master_transcoder set and matching
cpu_transcoder. Ensure disable also for 128b/132b SST.

Co-developed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 37b771f07d59..c74c3ab25589 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -657,6 +657,7 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
 	u32 ctl;
 
 	if (DISPLAY_VER(dev_priv) >= 11)
@@ -676,7 +677,8 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
 			 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
 
 	if (DISPLAY_VER(dev_priv) >= 12) {
-		if (!intel_dp_mst_is_master_trans(crtc_state)) {
+		if (!intel_dp_mst_is_master_trans(crtc_state) ||
+		    (!is_mst && intel_dp_is_uhbr(crtc_state))) {
 			ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
 				 TRANS_DDI_MODE_SELECT_MASK);
 		}
-- 
2.39.5

Re: [PATCH v2 15/16] drm/i915/ddi: disable trancoder port select for 128b/132b SST

[Imre Deak]

On Thu, Dec 19, 2024 at 11:34:04PM +0200, Jani Nikula wrote:
> 128b/1232b SST will have mst_master_transcoder set and matching
> cpu_transcoder. Ensure disable also for 128b/132b SST.
> 
> Co-developed-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 37b771f07d59..c74c3ab25589 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -657,6 +657,7 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
>  	u32 ctl;
>  
>  	if (DISPLAY_VER(dev_priv) >= 11)
> @@ -676,7 +677,8 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
>  			 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
>  
>  	if (DISPLAY_VER(dev_priv) >= 12) {
> -		if (!intel_dp_mst_is_master_trans(crtc_state)) {
> +		if (!intel_dp_mst_is_master_trans(crtc_state) ||
> +		    (!is_mst && intel_dp_is_uhbr(crtc_state))) {
>  			ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
>  				 TRANS_DDI_MODE_SELECT_MASK);
>  		}
> -- 
> 2.39.5
> 

[PATCH v2 16/16] drm/i915/dp: compute config for 128b/132b SST w/o DSC

[Jani Nikula]

Enable basic 128b/132b SST functionality without compression. Reuse
intel_dp_mtp_tu_compute_config() to figure out the TU after we've
determined we need to use an UHBR rate.

It's slightly complicated as the M/N computation is done in different
places in MST and SST paths, so we need to avoid trashing the values
later for UHBR.

If uncompressed UHBR fails, we drop to compressed non-UHBR, which is
quite likely to fail as well. We still lack 128b/132b SST+DSC.

We need mst_master_transcoder also for 128b/132b SST. Use cpu_transcoder
directly. Enhanced framing is "don't care" for 128b/132b link.

v2: mst_master_transcoder, enhanced framing (Imre)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++++++--------
 1 file changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fba3af338280..d14a42f02ba8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2525,8 +2525,8 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 	limits->min_rate = intel_dp_min_link_rate(intel_dp);
 	limits->max_rate = intel_dp_max_link_rate(intel_dp);
 
-	/* FIXME 128b/132b SST support missing */
-	if (!is_mst)
+	/* FIXME 128b/132b SST+DSC support missing */
+	if (!is_mst && dsc)
 		limits->max_rate = min(limits->max_rate, 810000);
 	limits->min_rate = min(limits->min_rate, limits->max_rate);
 
@@ -2640,6 +2640,13 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 		 */
 		ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
 							conn_state, &limits);
+		if (!ret && intel_dp_is_uhbr(pipe_config))
+			ret = intel_dp_mtp_tu_compute_config(intel_dp,
+							     pipe_config,
+							     pipe_config->pipe_bpp,
+							     pipe_config->pipe_bpp,
+							     conn_state,
+							     0, false);
 		if (ret)
 			dsc_needed = true;
 	}
@@ -3148,8 +3155,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	pipe_config->limited_color_range =
 		intel_dp_limited_color_range(pipe_config, conn_state);
 
-	pipe_config->enhanced_framing =
-		drm_dp_enhanced_frame_cap(intel_dp->dpcd);
+	if (intel_dp_is_uhbr(pipe_config)) {
+		/* 128b/132b SST also needs this */
+		pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder;
+	} else {
+		pipe_config->enhanced_framing =
+			drm_dp_enhanced_frame_cap(intel_dp->dpcd);
+	}
 
 	if (pipe_config->dsc.compression_enable)
 		link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
@@ -3180,12 +3192,14 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
 
-	intel_link_compute_m_n(link_bpp_x16,
-			       pipe_config->lane_count,
-			       adjusted_mode->crtc_clock,
-			       pipe_config->port_clock,
-			       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
-			       &pipe_config->dp_m_n);
+	if (!intel_dp_is_uhbr(pipe_config)) {
+		intel_link_compute_m_n(link_bpp_x16,
+				       pipe_config->lane_count,
+				       adjusted_mode->crtc_clock,
+				       pipe_config->port_clock,
+				       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
+				       &pipe_config->dp_m_n);
+	}
 
 	/* FIXME: abstract this better */
 	if (pipe_config->splitter.enable)
-- 
2.39.5

Re: [PATCH v2 16/16] drm/i915/dp: compute config for 128b/132b SST w/o DSC

[Imre Deak]

On Thu, Dec 19, 2024 at 11:34:05PM +0200, Jani Nikula wrote:
> Enable basic 128b/132b SST functionality without compression. Reuse
> intel_dp_mtp_tu_compute_config() to figure out the TU after we've
> determined we need to use an UHBR rate.
> 
> It's slightly complicated as the M/N computation is done in different
> places in MST and SST paths, so we need to avoid trashing the values
> later for UHBR.
> 
> If uncompressed UHBR fails, we drop to compressed non-UHBR, which is
> quite likely to fail as well. We still lack 128b/132b SST+DSC.
> 
> We need mst_master_transcoder also for 128b/132b SST. Use cpu_transcoder
> directly. Enhanced framing is "don't care" for 128b/132b link.
> 
> v2: mst_master_transcoder, enhanced framing (Imre)
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++++++--------
>  1 file changed, 24 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index fba3af338280..d14a42f02ba8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2525,8 +2525,8 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>  	limits->min_rate = intel_dp_min_link_rate(intel_dp);
>  	limits->max_rate = intel_dp_max_link_rate(intel_dp);
>  
> -	/* FIXME 128b/132b SST support missing */
> -	if (!is_mst)
> +	/* FIXME 128b/132b SST+DSC support missing */
> +	if (!is_mst && dsc)
>  		limits->max_rate = min(limits->max_rate, 810000);
>  	limits->min_rate = min(limits->min_rate, limits->max_rate);
>  
> @@ -2640,6 +2640,13 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  		 */
>  		ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
>  							conn_state, &limits);
> +		if (!ret && intel_dp_is_uhbr(pipe_config))
> +			ret = intel_dp_mtp_tu_compute_config(intel_dp,
> +							     pipe_config,
> +							     pipe_config->pipe_bpp,
> +							     pipe_config->pipe_bpp,
> +							     conn_state,
> +							     0, false);
>  		if (ret)
>  			dsc_needed = true;
>  	}
> @@ -3148,8 +3155,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  	pipe_config->limited_color_range =
>  		intel_dp_limited_color_range(pipe_config, conn_state);
>  
> -	pipe_config->enhanced_framing =
> -		drm_dp_enhanced_frame_cap(intel_dp->dpcd);
> +	if (intel_dp_is_uhbr(pipe_config)) {

Nit: no need for {} here and below.

The patch looks ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +		/* 128b/132b SST also needs this */
> +		pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder;
> +	} else {
> +		pipe_config->enhanced_framing =
> +			drm_dp_enhanced_frame_cap(intel_dp->dpcd);
> +	}
>  
>  	if (pipe_config->dsc.compression_enable)
>  		link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
> @@ -3180,12 +3192,14 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  
>  	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
>  
> -	intel_link_compute_m_n(link_bpp_x16,
> -			       pipe_config->lane_count,
> -			       adjusted_mode->crtc_clock,
> -			       pipe_config->port_clock,
> -			       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
> -			       &pipe_config->dp_m_n);
> +	if (!intel_dp_is_uhbr(pipe_config)) {
> +		intel_link_compute_m_n(link_bpp_x16,
> +				       pipe_config->lane_count,
> +				       adjusted_mode->crtc_clock,
> +				       pipe_config->port_clock,
> +				       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
> +				       &pipe_config->dp_m_n);
> +	}
>  
>  	/* FIXME: abstract this better */
>  	if (pipe_config->splitter.enable)
> -- 
> 2.39.5
> 

Re: [PATCH v2 16/16] drm/i915/dp: compute config for 128b/132b SST w/o DSC

[Jani Nikula]

On Thu, 02 Jan 2025, Imre Deak <imre.deak@intel.com> wrote:
> On Thu, Dec 19, 2024 at 11:34:05PM +0200, Jani Nikula wrote:
>> Enable basic 128b/132b SST functionality without compression. Reuse
>> intel_dp_mtp_tu_compute_config() to figure out the TU after we've
>> determined we need to use an UHBR rate.
>> 
>> It's slightly complicated as the M/N computation is done in different
>> places in MST and SST paths, so we need to avoid trashing the values
>> later for UHBR.
>> 
>> If uncompressed UHBR fails, we drop to compressed non-UHBR, which is
>> quite likely to fail as well. We still lack 128b/132b SST+DSC.
>> 
>> We need mst_master_transcoder also for 128b/132b SST. Use cpu_transcoder
>> directly. Enhanced framing is "don't care" for 128b/132b link.
>> 
>> v2: mst_master_transcoder, enhanced framing (Imre)
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++++++--------
>>  1 file changed, 24 insertions(+), 10 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index fba3af338280..d14a42f02ba8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -2525,8 +2525,8 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>>  	limits->min_rate = intel_dp_min_link_rate(intel_dp);
>>  	limits->max_rate = intel_dp_max_link_rate(intel_dp);
>>  
>> -	/* FIXME 128b/132b SST support missing */
>> -	if (!is_mst)
>> +	/* FIXME 128b/132b SST+DSC support missing */
>> +	if (!is_mst && dsc)
>>  		limits->max_rate = min(limits->max_rate, 810000);
>>  	limits->min_rate = min(limits->min_rate, limits->max_rate);
>>  
>> @@ -2640,6 +2640,13 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>>  		 */
>>  		ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
>>  							conn_state, &limits);
>> +		if (!ret && intel_dp_is_uhbr(pipe_config))
>> +			ret = intel_dp_mtp_tu_compute_config(intel_dp,
>> +							     pipe_config,
>> +							     pipe_config->pipe_bpp,
>> +							     pipe_config->pipe_bpp,
>> +							     conn_state,
>> +							     0, false);
>>  		if (ret)
>>  			dsc_needed = true;
>>  	}
>> @@ -3148,8 +3155,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>>  	pipe_config->limited_color_range =
>>  		intel_dp_limited_color_range(pipe_config, conn_state);
>>  
>> -	pipe_config->enhanced_framing =
>> -		drm_dp_enhanced_frame_cap(intel_dp->dpcd);
>> +	if (intel_dp_is_uhbr(pipe_config)) {
>
> Nit: no need for {} here and below.

I like this:

	if (foo)
		action();

but not this:

	if (foo)
		/* comment */
		action();

so I prefer to add the {} for clarity.

Below I think it's just because the action() spans six lines...

>
> The patch looks ok:
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Thanks!

>
>> +		/* 128b/132b SST also needs this */
>> +		pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder;
>> +	} else {
>> +		pipe_config->enhanced_framing =
>> +			drm_dp_enhanced_frame_cap(intel_dp->dpcd);
>> +	}
>>  
>>  	if (pipe_config->dsc.compression_enable)
>>  		link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
>> @@ -3180,12 +3192,14 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>>  
>>  	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
>>  
>> -	intel_link_compute_m_n(link_bpp_x16,
>> -			       pipe_config->lane_count,
>> -			       adjusted_mode->crtc_clock,
>> -			       pipe_config->port_clock,
>> -			       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
>> -			       &pipe_config->dp_m_n);
>> +	if (!intel_dp_is_uhbr(pipe_config)) {
>> +		intel_link_compute_m_n(link_bpp_x16,
>> +				       pipe_config->lane_count,
>> +				       adjusted_mode->crtc_clock,
>> +				       pipe_config->port_clock,
>> +				       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
>> +				       &pipe_config->dp_m_n);
>> +	}
>>  
>>  	/* FIXME: abstract this better */
>>  	if (pipe_config->splitter.enable)
>> -- 
>> 2.39.5
>> 

-- 
Jani Nikula, Intel

Re: [PATCH v2 16/16] drm/i915/dp: compute config for 128b/132b SST w/o DSC

[Imre Deak]

On Thu, Dec 19, 2024 at 11:34:05PM +0200, Jani Nikula wrote:
> Enable basic 128b/132b SST functionality without compression. Reuse
> intel_dp_mtp_tu_compute_config() to figure out the TU after we've
> determined we need to use an UHBR rate.
> 
> It's slightly complicated as the M/N computation is done in different
> places in MST and SST paths, so we need to avoid trashing the values
> later for UHBR.
> 
> If uncompressed UHBR fails, we drop to compressed non-UHBR, which is
> quite likely to fail as well. We still lack 128b/132b SST+DSC.
> 
> We need mst_master_transcoder also for 128b/132b SST. Use cpu_transcoder
> directly. Enhanced framing is "don't care" for 128b/132b link.
> 
> v2: mst_master_transcoder, enhanced framing (Imre)
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++++++--------
>  1 file changed, 24 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index fba3af338280..d14a42f02ba8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2525,8 +2525,8 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>  	limits->min_rate = intel_dp_min_link_rate(intel_dp);
>  	limits->max_rate = intel_dp_max_link_rate(intel_dp);
>  
> -	/* FIXME 128b/132b SST support missing */
> -	if (!is_mst)
> +	/* FIXME 128b/132b SST+DSC support missing */
> +	if (!is_mst && dsc)
>  		limits->max_rate = min(limits->max_rate, 810000);
>  	limits->min_rate = min(limits->min_rate, limits->max_rate);
>  
> @@ -2640,6 +2640,13 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  		 */
>  		ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
>  							conn_state, &limits);
> +		if (!ret && intel_dp_is_uhbr(pipe_config))
> +			ret = intel_dp_mtp_tu_compute_config(intel_dp,
> +							     pipe_config,
> +							     pipe_config->pipe_bpp,
> +							     pipe_config->pipe_bpp,
> +							     conn_state,
> +							     0, false);

Missed this in my review: intel_dp_mtp_tu_compute_config() for this to
work, it needs to handle step == 0, i.e. if (step == 0) break; at the
end of the bpp loop.

>  		if (ret)
>  			dsc_needed = true;
>  	}
> @@ -3148,8 +3155,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  	pipe_config->limited_color_range =
>  		intel_dp_limited_color_range(pipe_config, conn_state);
>  
> -	pipe_config->enhanced_framing =
> -		drm_dp_enhanced_frame_cap(intel_dp->dpcd);
> +	if (intel_dp_is_uhbr(pipe_config)) {
> +		/* 128b/132b SST also needs this */
> +		pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder;
> +	} else {
> +		pipe_config->enhanced_framing =
> +			drm_dp_enhanced_frame_cap(intel_dp->dpcd);
> +	}
>  
>  	if (pipe_config->dsc.compression_enable)
>  		link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
> @@ -3180,12 +3192,14 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  
>  	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
>  
> -	intel_link_compute_m_n(link_bpp_x16,
> -			       pipe_config->lane_count,
> -			       adjusted_mode->crtc_clock,
> -			       pipe_config->port_clock,
> -			       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
> -			       &pipe_config->dp_m_n);
> +	if (!intel_dp_is_uhbr(pipe_config)) {
> +		intel_link_compute_m_n(link_bpp_x16,
> +				       pipe_config->lane_count,
> +				       adjusted_mode->crtc_clock,
> +				       pipe_config->port_clock,
> +				       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
> +				       &pipe_config->dp_m_n);
> +	}
>  
>  	/* FIXME: abstract this better */
>  	if (pipe_config->splitter.enable)
> -- 
> 2.39.5
> 

Re: [PATCH v2 16/16] drm/i915/dp: compute config for 128b/132b SST w/o DSC

[Jani Nikula]

On Tue, 04 Feb 2025, Imre Deak <imre.deak@intel.com> wrote:
> On Thu, Dec 19, 2024 at 11:34:05PM +0200, Jani Nikula wrote:
>> Enable basic 128b/132b SST functionality without compression. Reuse
>> intel_dp_mtp_tu_compute_config() to figure out the TU after we've
>> determined we need to use an UHBR rate.
>> 
>> It's slightly complicated as the M/N computation is done in different
>> places in MST and SST paths, so we need to avoid trashing the values
>> later for UHBR.
>> 
>> If uncompressed UHBR fails, we drop to compressed non-UHBR, which is
>> quite likely to fail as well. We still lack 128b/132b SST+DSC.
>> 
>> We need mst_master_transcoder also for 128b/132b SST. Use cpu_transcoder
>> directly. Enhanced framing is "don't care" for 128b/132b link.
>> 
>> v2: mst_master_transcoder, enhanced framing (Imre)
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++++++--------
>>  1 file changed, 24 insertions(+), 10 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index fba3af338280..d14a42f02ba8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -2525,8 +2525,8 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>>  	limits->min_rate = intel_dp_min_link_rate(intel_dp);
>>  	limits->max_rate = intel_dp_max_link_rate(intel_dp);
>>  
>> -	/* FIXME 128b/132b SST support missing */
>> -	if (!is_mst)
>> +	/* FIXME 128b/132b SST+DSC support missing */
>> +	if (!is_mst && dsc)
>>  		limits->max_rate = min(limits->max_rate, 810000);
>>  	limits->min_rate = min(limits->min_rate, limits->max_rate);
>>  
>> @@ -2640,6 +2640,13 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>>  		 */
>>  		ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
>>  							conn_state, &limits);
>> +		if (!ret && intel_dp_is_uhbr(pipe_config))
>> +			ret = intel_dp_mtp_tu_compute_config(intel_dp,
>> +							     pipe_config,
>> +							     pipe_config->pipe_bpp,
>> +							     pipe_config->pipe_bpp,
>> +							     conn_state,
>> +							     0, false);
>
> Missed this in my review: intel_dp_mtp_tu_compute_config() for this to
> work, it needs to handle step == 0, i.e. if (step == 0) break; at the
> end of the bpp loop.

Right, good catch!

I wanted to pass 0 step to be explicit about doing it just once, but it
really only happens once if it succeeds! Otherwise it results in an
infinite loop.

Fix on the list.

Thanks,
Jani.

>
>>  		if (ret)
>>  			dsc_needed = true;
>>  	}
>> @@ -3148,8 +3155,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>>  	pipe_config->limited_color_range =
>>  		intel_dp_limited_color_range(pipe_config, conn_state);
>>  
>> -	pipe_config->enhanced_framing =
>> -		drm_dp_enhanced_frame_cap(intel_dp->dpcd);
>> +	if (intel_dp_is_uhbr(pipe_config)) {
>> +		/* 128b/132b SST also needs this */
>> +		pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder;
>> +	} else {
>> +		pipe_config->enhanced_framing =
>> +			drm_dp_enhanced_frame_cap(intel_dp->dpcd);
>> +	}
>>  
>>  	if (pipe_config->dsc.compression_enable)
>>  		link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
>> @@ -3180,12 +3192,14 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>>  
>>  	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
>>  
>> -	intel_link_compute_m_n(link_bpp_x16,
>> -			       pipe_config->lane_count,
>> -			       adjusted_mode->crtc_clock,
>> -			       pipe_config->port_clock,
>> -			       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
>> -			       &pipe_config->dp_m_n);
>> +	if (!intel_dp_is_uhbr(pipe_config)) {
>> +		intel_link_compute_m_n(link_bpp_x16,
>> +				       pipe_config->lane_count,
>> +				       adjusted_mode->crtc_clock,
>> +				       pipe_config->port_clock,
>> +				       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
>> +				       &pipe_config->dp_m_n);
>> +	}
>>  
>>  	/* FIXME: abstract this better */
>>  	if (pipe_config->splitter.enable)
>> -- 
>> 2.39.5
>> 

-- 
Jani Nikula, Intel

✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: 128b/132b uncompressed SST (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: 128b/132b uncompressed SST (rev2)
URL   : https://patchwork.freedesktop.org/series/142547/
State : warning

== Summary ==

Error: dim checkpatch failed
90b7afc2e7f6 drm/mst: remove mgr parameter and debug logging from drm_dp_get_vc_payload_bw()
ed57d41e01b7 drm/i915/mst: drop connector parameter from intel_dp_mst_bw_overhead()
291f57ed7a5d drm/i915/mst: drop connector parameter from intel_dp_mst_compute_m_n()
2a187752bed7 drm/i915/mst: change return value of mst_stream_find_vcpi_slots_for_bpp()
4ca1d2bec27d drm/i915/mst: remove crtc_state->pbn
b0336ce370dd drm/i915/mst: split out a helper for figuring out the TU
6d3e448027e4 drm/i915/mst: adapt intel_dp_mtp_tu_compute_config() for 128b/132b SST
-:86: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#86: FILE: drivers/gpu/drm/i915/display/intel_dp_mst.c:280:
+								      true, dsc_slice_count, link_bpp_x16);

total: 0 errors, 1 warnings, 0 checks, 128 lines checked
954663f25fee drm/i915/ddi: enable 128b/132b TRANS_DDI_FUNC_CTL mode for UHBR SST
529b77a98287 drm/i915/ddi: 128b/132b SST also needs DP_TP_CTL_MODE_MST
39e81c833cd1 drm/i915/ddi: write payload for 128b/132b SST
5db44ddb5088 drm/i915/ddi: initialize 128b/132b SST DP2 VFREQ registers
f85d6ff21655 drm/i915/ddi: enable ACT handling for 128b/132b SST
87f107d4fcaa drm/i915/ddi: start distinguishing 128b/132b SST and MST at state readout
c7988ad77965 drm/i915/ddi: handle 128b/132b SST in intel_ddi_read_func_ctl()
d681f30d6d5e drm/i915/ddi: disable trancoder port select for 128b/132b SST
5e6677cb059b drm/i915/dp: compute config for 128b/132b SST w/o DSC

✗ Fi.CI.SPARSE: warning for drm/i915/dp: 128b/132b uncompressed SST (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: 128b/132b uncompressed SST (rev2)
URL   : https://patchwork.freedesktop.org/series/142547/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✓ i915.CI.BAT: success for drm/i915/dp: 128b/132b uncompressed SST (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: 128b/132b uncompressed SST (rev2)
URL   : https://patchwork.freedesktop.org/series/142547/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_15873 -> Patchwork_142547v2
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/index.html

Participating hosts (45 -> 44)
------------------------------

  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_142547v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - fi-pnv-d510:        NOTRUN -> [SKIP][1] +3 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/fi-pnv-d510/igt@debugfs_test@basic-hwmon.html

  * igt@dmabuf@all-tests@dma_fence_chain:
    - fi-bsw-nick:        [PASS][2] -> [INCOMPLETE][3] ([i915#12904]) +1 other test incomplete
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/fi-bsw-nick/igt@dmabuf@all-tests@dma_fence_chain.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/fi-bsw-nick/igt@dmabuf@all-tests@dma_fence_chain.html

  * igt@gem_exec_gttfill@basic:
    - fi-pnv-d510:        NOTRUN -> [ABORT][4] ([i915#13169])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/fi-pnv-d510/igt@gem_exec_gttfill@basic.html

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [PASS][5] -> [ABORT][6] ([i915#12061]) +1 other test abort
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/bat-mtlp-8/igt@i915_selftest@live.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/bat-mtlp-8/igt@i915_selftest@live.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         [PASS][7] -> [SKIP][8] ([i915#9197]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  
#### Possible fixes ####

  * igt@i915_module_load@load:
    - fi-pnv-d510:        [ABORT][9] ([i915#13203]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/fi-pnv-d510/igt@i915_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/fi-pnv-d510/igt@i915_module_load@load.html

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-2:         [ABORT][11] ([i915#12061]) -> [PASS][12] +1 other test pass
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/bat-arlh-2/igt@i915_selftest@live@workarounds.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/bat-arlh-2/igt@i915_selftest@live@workarounds.html
    - {bat-arls-6}:       [ABORT][13] ([i915#12061]) -> [PASS][14] +1 other test pass
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/bat-arls-6/igt@i915_selftest@live@workarounds.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/bat-arls-6/igt@i915_selftest@live@workarounds.html

  * igt@kms_addfb_basic@too-high:
    - fi-cfl-8109u:       [DMESG-WARN][15] ([i915#11621]) -> [PASS][16] +92 other tests pass
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/fi-cfl-8109u/igt@kms_addfb_basic@too-high.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/fi-cfl-8109u/igt@kms_addfb_basic@too-high.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#11621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11621
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
  [i915#13169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13169
  [i915#13203]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13203
  [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197


Build changes
-------------

  * Linux: CI_DRM_15873 -> Patchwork_142547v2

  CI-20190529: 20190529
  CI_DRM_15873: a5b4c40929f3263a92e34e3f6b3c3c0de57e0e58 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8166: 197cca38ae5c494511843112d43351aeab2314be @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_142547v2: a5b4c40929f3263a92e34e3f6b3c3c0de57e0e58 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/index.html

✓ i915.CI.Full: success for drm/i915/dp: 128b/132b uncompressed SST (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 100273 bytes --]

== Series Details ==

Series: drm/i915/dp: 128b/132b uncompressed SST (rev2)
URL   : https://patchwork.freedesktop.org/series/142547/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_15873_full -> Patchwork_142547v2_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 11)
------------------------------

  Missing    (1): shard-dg2-set2 

Known issues
------------

  Here are the changes found in Patchwork_142547v2_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@crc32:
    - shard-dg1:          NOTRUN -> [SKIP][1] ([i915#6230])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@api_intel_bb@crc32.html

  * igt@device_reset@unbind-reset-rebind:
    - shard-tglu:         NOTRUN -> [ABORT][2] ([i915#12817] / [i915#5507])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@device_reset@unbind-reset-rebind.html

  * igt@drm_fdinfo@busy@rcs0:
    - shard-dg2:          NOTRUN -> [SKIP][3] ([i915#8414]) +16 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@drm_fdinfo@busy@rcs0.html

  * igt@drm_fdinfo@busy@vcs1:
    - shard-dg1:          NOTRUN -> [SKIP][4] ([i915#8414]) +21 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@drm_fdinfo@busy@vcs1.html

  * igt@gem_busy@semaphore:
    - shard-dg2:          NOTRUN -> [SKIP][5] ([i915#3936])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@gem_busy@semaphore.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-dg1:          NOTRUN -> [SKIP][6] ([i915#3555] / [i915#9323])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@block-multicopy-compressed:
    - shard-tglu-1:       NOTRUN -> [SKIP][7] ([i915#9323]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@gem_ccs@block-multicopy-compressed.html
    - shard-dg1:          NOTRUN -> [SKIP][8] ([i915#9323])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@gem_ccs@block-multicopy-compressed.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-tglu:         NOTRUN -> [SKIP][9] ([i915#13008])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-5/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-rkl:          NOTRUN -> [SKIP][10] ([i915#7697])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_create@create-ext-cpu-access-sanity-check:
    - shard-rkl:          NOTRUN -> [SKIP][11] ([i915#6335])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@gem_create@create-ext-cpu-access-sanity-check.html

  * igt@gem_create@create-ext-set-pat:
    - shard-dg1:          NOTRUN -> [SKIP][12] ([i915#8562])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@gem_create@create-ext-set-pat.html

  * igt@gem_ctx_persistence@engines-cleanup:
    - shard-snb:          NOTRUN -> [SKIP][13] ([i915#1099]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-snb2/igt@gem_ctx_persistence@engines-cleanup.html

  * igt@gem_ctx_persistence@heartbeat-many:
    - shard-dg1:          NOTRUN -> [SKIP][14] ([i915#8555])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@gem_ctx_persistence@heartbeat-many.html

  * igt@gem_ctx_persistence@saturated-hostile-nopreempt:
    - shard-dg2:          NOTRUN -> [SKIP][15] ([i915#5882]) +7 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@gem_ctx_persistence@saturated-hostile-nopreempt.html

  * igt@gem_eio@hibernate:
    - shard-dg1:          [PASS][16] -> [ABORT][17] ([i915#7975] / [i915#8213])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg1-12/igt@gem_eio@hibernate.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-14/igt@gem_eio@hibernate.html

  * igt@gem_exec_balancer@bonded-dual:
    - shard-dg1:          NOTRUN -> [SKIP][18] ([i915#4771])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@gem_exec_balancer@bonded-dual.html

  * igt@gem_exec_balancer@bonded-false-hang:
    - shard-dg2:          NOTRUN -> [SKIP][19] ([i915#4812]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@gem_exec_balancer@bonded-false-hang.html

  * igt@gem_exec_balancer@bonded-semaphore:
    - shard-mtlp:         NOTRUN -> [SKIP][20] ([i915#4812])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-6/igt@gem_exec_balancer@bonded-semaphore.html

  * igt@gem_exec_balancer@invalid-bonds:
    - shard-dg1:          NOTRUN -> [SKIP][21] ([i915#4036])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@gem_exec_balancer@invalid-bonds.html

  * igt@gem_exec_balancer@parallel-balancer:
    - shard-tglu:         NOTRUN -> [SKIP][22] ([i915#4525])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@gem_exec_balancer@parallel-balancer.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
    - shard-rkl:          NOTRUN -> [SKIP][23] ([i915#4525])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@gem_exec_balancer@parallel-keep-in-fence.html

  * igt@gem_exec_balancer@parallel-out-fence:
    - shard-tglu-1:       NOTRUN -> [SKIP][24] ([i915#4525])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@gem_exec_balancer@parallel-out-fence.html

  * igt@gem_exec_capture@capture-recoverable:
    - shard-rkl:          NOTRUN -> [SKIP][25] ([i915#6344])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@gem_exec_capture@capture-recoverable.html

  * igt@gem_exec_capture@capture@vecs0-lmem0:
    - shard-dg1:          NOTRUN -> [FAIL][26] ([i915#11965]) +2 other tests fail
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@gem_exec_capture@capture@vecs0-lmem0.html

  * igt@gem_exec_endless@dispatch:
    - shard-dg2:          [PASS][27] -> [TIMEOUT][28] ([i915#3778] / [i915#7016])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-6/igt@gem_exec_endless@dispatch.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-11/igt@gem_exec_endless@dispatch.html

  * igt@gem_exec_endless@dispatch@vecs1:
    - shard-dg2:          [PASS][29] -> [TIMEOUT][30] ([i915#7016])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-6/igt@gem_exec_endless@dispatch@vecs1.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-11/igt@gem_exec_endless@dispatch@vecs1.html

  * igt@gem_exec_flush@basic-batch-kernel-default-uc:
    - shard-dg2:          NOTRUN -> [SKIP][31] ([i915#3539] / [i915#4852]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@gem_exec_flush@basic-batch-kernel-default-uc.html

  * igt@gem_exec_flush@basic-wb-prw-default:
    - shard-dg1:          NOTRUN -> [SKIP][32] ([i915#3539] / [i915#4852]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-17/igt@gem_exec_flush@basic-wb-prw-default.html

  * igt@gem_exec_params@rsvd2-dirt:
    - shard-dg2:          NOTRUN -> [SKIP][33] ([i915#5107])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@gem_exec_params@rsvd2-dirt.html

  * igt@gem_exec_reloc@basic-wc-read-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][34] ([i915#3281]) +3 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-7/igt@gem_exec_reloc@basic-wc-read-noreloc.html

  * igt@gem_exec_reloc@basic-write-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][35] ([i915#3281]) +6 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@gem_exec_reloc@basic-write-gtt.html

  * igt@gem_exec_reloc@basic-write-gtt-active:
    - shard-dg1:          NOTRUN -> [SKIP][36] ([i915#3281]) +13 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@gem_exec_reloc@basic-write-gtt-active.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain:
    - shard-dg1:          NOTRUN -> [SKIP][37] ([i915#4812])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@gem_exec_schedule@preempt-queue-contexts-chain.html

  * igt@gem_exec_schedule@reorder-wide:
    - shard-dg2:          NOTRUN -> [SKIP][38] ([i915#4537] / [i915#4812]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@gem_exec_schedule@reorder-wide.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - shard-dg2:          [PASS][39] -> [INCOMPLETE][40] ([i915#11441] / [i915#13304]) +1 other test incomplete
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-5/igt@gem_exec_suspend@basic-s0@smem.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-2/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gem_exec_suspend@basic-s4-devices:
    - shard-tglu:         [PASS][41] -> [ABORT][42] ([i915#7975] / [i915#8213]) +1 other test abort
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-tglu-9/igt@gem_exec_suspend@basic-s4-devices.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-10/igt@gem_exec_suspend@basic-s4-devices.html
    - shard-dg2:          NOTRUN -> [ABORT][43] ([i915#7975] / [i915#8213]) +1 other test abort
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-8/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@gem_fence_thrash@bo-write-verify-y:
    - shard-dg2:          NOTRUN -> [SKIP][44] ([i915#4860])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@gem_fence_thrash@bo-write-verify-y.html
    - shard-dg1:          NOTRUN -> [SKIP][45] ([i915#4860])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@gem_fence_thrash@bo-write-verify-y.html

  * igt@gem_huc_copy@huc-copy:
    - shard-rkl:          NOTRUN -> [SKIP][46] ([i915#2190])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - shard-tglu:         NOTRUN -> [SKIP][47] ([i915#4613])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - shard-rkl:          NOTRUN -> [SKIP][48] ([i915#4613])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-7/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
    - shard-glk:          NOTRUN -> [SKIP][49] ([i915#4613])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-glk8/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg1:          NOTRUN -> [TIMEOUT][50] ([i915#5493]) +1 other test timeout
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_lmem_swapping@verify-random-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][51] ([i915#4613]) +2 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@gem_lmem_swapping@verify-random-ccs.html

  * igt@gem_media_vme:
    - shard-dg1:          NOTRUN -> [SKIP][52] ([i915#284])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@gem_media_vme.html

  * igt@gem_mmap_gtt@medium-copy:
    - shard-mtlp:         NOTRUN -> [SKIP][53] ([i915#4077])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-6/igt@gem_mmap_gtt@medium-copy.html

  * igt@gem_mmap_gtt@medium-copy-odd:
    - shard-dg1:          NOTRUN -> [SKIP][54] ([i915#4077]) +8 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-17/igt@gem_mmap_gtt@medium-copy-odd.html

  * igt@gem_mmap_wc@copy:
    - shard-dg2:          NOTRUN -> [SKIP][55] ([i915#4083]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@gem_mmap_wc@copy.html

  * igt@gem_mmap_wc@read:
    - shard-dg1:          NOTRUN -> [SKIP][56] ([i915#4083]) +5 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@gem_mmap_wc@read.html

  * igt@gem_partial_pwrite_pread@reads-uncached:
    - shard-dg2:          NOTRUN -> [SKIP][57] ([i915#3282]) +2 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@gem_partial_pwrite_pread@reads-uncached.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
    - shard-mtlp:         NOTRUN -> [SKIP][58] ([i915#3282])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-6/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html

  * igt@gem_pread@bench:
    - shard-dg1:          NOTRUN -> [SKIP][59] ([i915#3282]) +4 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@gem_pread@bench.html

  * igt@gem_pwrite_snooped:
    - shard-rkl:          NOTRUN -> [SKIP][60] ([i915#3282]) +3 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-7/igt@gem_pwrite_snooped.html

  * igt@gem_pxp@display-protected-crc:
    - shard-dg2:          NOTRUN -> [SKIP][61] ([i915#4270]) +2 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@gem_pxp@display-protected-crc.html

  * igt@gem_pxp@reject-modify-context-protection-off-3:
    - shard-rkl:          NOTRUN -> [SKIP][62] ([i915#4270])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@gem_pxp@reject-modify-context-protection-off-3.html

  * igt@gem_pxp@reject-modify-context-protection-on:
    - shard-rkl:          NOTRUN -> [TIMEOUT][63] ([i915#12917] / [i915#12964]) +2 other tests timeout
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@gem_pxp@reject-modify-context-protection-on.html

  * igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
    - shard-dg1:          NOTRUN -> [SKIP][64] ([i915#4270]) +4 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html

  * igt@gem_render_copy@linear-to-vebox-yf-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][65] ([i915#5190] / [i915#8428]) +4 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@gem_render_copy@linear-to-vebox-yf-tiled.html

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][66] ([i915#8428])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-6/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs.html

  * igt@gem_set_tiling_vs_blt@tiled-to-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][67] ([i915#4079]) +1 other test skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html

  * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
    - shard-dg1:          NOTRUN -> [SKIP][68] ([i915#4079]) +1 other test skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html

  * igt@gem_tiled_partial_pwrite_pread@writes:
    - shard-dg2:          NOTRUN -> [SKIP][69] ([i915#4077]) +5 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@gem_tiled_partial_pwrite_pread@writes.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-rkl:          NOTRUN -> [SKIP][70] ([i915#3297]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@readonly-unsync:
    - shard-dg2:          NOTRUN -> [SKIP][71] ([i915#3297]) +2 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@gem_userptr_blits@readonly-unsync.html

  * igt@gem_userptr_blits@relocations:
    - shard-dg1:          NOTRUN -> [SKIP][72] ([i915#3281] / [i915#3297])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@gem_userptr_blits@relocations.html

  * igt@gem_userptr_blits@sd-probe:
    - shard-dg2:          NOTRUN -> [SKIP][73] ([i915#3297] / [i915#4958])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@gem_userptr_blits@sd-probe.html

  * igt@gem_userptr_blits@unsync-unmap-after-close:
    - shard-tglu:         NOTRUN -> [SKIP][74] ([i915#3297]) +1 other test skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-5/igt@gem_userptr_blits@unsync-unmap-after-close.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-tglu-1:       NOTRUN -> [SKIP][75] ([i915#3297]) +1 other test skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@gem_userptr_blits@unsync-unmap-cycles.html
    - shard-dg1:          NOTRUN -> [SKIP][76] ([i915#3297]) +4 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-tglu-1:       NOTRUN -> [SKIP][77] ([i915#2527] / [i915#2856])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@gen9_exec_parse@bb-oversize.html
    - shard-mtlp:         NOTRUN -> [SKIP][78] ([i915#2856])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-6/igt@gen9_exec_parse@bb-oversize.html
    - shard-dg2:          NOTRUN -> [SKIP][79] ([i915#2856])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@gen9_exec_parse@bb-oversize.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-dg1:          NOTRUN -> [SKIP][80] ([i915#2527]) +2 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-17/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@gen9_exec_parse@bb-start-out:
    - shard-rkl:          NOTRUN -> [SKIP][81] ([i915#2527]) +2 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@gen9_exec_parse@bb-start-out.html

  * igt@gen9_exec_parse@unaligned-jump:
    - shard-tglu:         NOTRUN -> [SKIP][82] ([i915#2527] / [i915#2856]) +1 other test skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-5/igt@gen9_exec_parse@unaligned-jump.html

  * igt@i915_fb_tiling:
    - shard-dg1:          NOTRUN -> [SKIP][83] ([i915#4881])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@i915_fb_tiling.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-dg2:          [PASS][84] -> [ABORT][85] ([i915#9820])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-6/igt@i915_module_load@reload-with-fault-injection.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][86] ([i915#8399]) +1 other test skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_pm_freq_api@freq-suspend@gt0:
    - shard-dg2:          [PASS][87] -> [INCOMPLETE][88] ([i915#12455]) +1 other test incomplete
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-1/igt@i915_pm_freq_api@freq-suspend@gt0.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-4/igt@i915_pm_freq_api@freq-suspend@gt0.html

  * igt@i915_pm_freq_mult@media-freq@gt0:
    - shard-tglu:         NOTRUN -> [SKIP][89] ([i915#6590]) +1 other test skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@i915_pm_freq_mult@media-freq@gt0.html

  * igt@i915_pm_rps@thresholds-idle-park:
    - shard-dg2:          NOTRUN -> [SKIP][90] ([i915#11681])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@i915_pm_rps@thresholds-idle-park.html
    - shard-mtlp:         NOTRUN -> [SKIP][91] ([i915#11681])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-6/igt@i915_pm_rps@thresholds-idle-park.html

  * igt@i915_pm_rps@thresholds-park:
    - shard-dg1:          NOTRUN -> [SKIP][92] ([i915#11681]) +1 other test skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@i915_pm_rps@thresholds-park.html

  * igt@i915_query@query-topology-coherent-slice-mask:
    - shard-dg2:          NOTRUN -> [SKIP][93] ([i915#6188])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-8/igt@i915_query@query-topology-coherent-slice-mask.html

  * igt@i915_selftest@live@workarounds:
    - shard-mtlp:         [PASS][94] -> [ABORT][95] ([i915#12061]) +1 other test abort
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-mtlp-2/igt@i915_selftest@live@workarounds.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-7/igt@i915_selftest@live@workarounds.html

  * igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
    - shard-dg2:          NOTRUN -> [SKIP][96] ([i915#4212])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-dg2:          NOTRUN -> [SKIP][97] ([i915#5190]) +1 other test skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - shard-dg1:          NOTRUN -> [SKIP][98] ([i915#4212]) +1 other test skip
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  * igt@kms_async_flips@async-flip-with-page-flip-events:
    - shard-rkl:          [PASS][99] -> [DMESG-WARN][100] ([i915#12964])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-rkl-2/igt@kms_async_flips@async-flip-with-page-flip-events.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@kms_async_flips@async-flip-with-page-flip-events.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-d-hdmi-a-1-y-rc-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][101] ([i915#8709]) +7 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-5/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-d-hdmi-a-1-y-rc-ccs.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc:
    - shard-rkl:          NOTRUN -> [SKIP][102] ([i915#8709]) +3 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc.html

  * igt@kms_async_flips@crc:
    - shard-dg1:          NOTRUN -> [WARN][103] ([i915#13287])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@kms_async_flips@crc.html

  * igt@kms_async_flips@crc@pipe-b-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [CRASH][104] ([i915#13287]) +3 other tests crash
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-4/igt@kms_async_flips@crc@pipe-b-hdmi-a-1.html

  * igt@kms_async_flips@crc@pipe-b-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [CRASH][105] ([i915#13287]) +3 other tests crash
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@kms_async_flips@crc@pipe-b-hdmi-a-3.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-dg2:          NOTRUN -> [SKIP][106] ([i915#1769] / [i915#3555])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
    - shard-tglu-1:       NOTRUN -> [SKIP][107] ([i915#1769] / [i915#3555])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-180:
    - shard-rkl:          NOTRUN -> [SKIP][108] ([i915#5286]) +3 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-7/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-90:
    - shard-dg1:          NOTRUN -> [SKIP][109] ([i915#4538] / [i915#5286]) +5 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-addfb:
    - shard-tglu-1:       NOTRUN -> [SKIP][110] ([i915#5286])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_big_fb@4-tiled-addfb.html

  * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
    - shard-tglu:         NOTRUN -> [SKIP][111] ([i915#5286]) +2 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][112] ([i915#3638]) +2 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-90:
    - shard-dg1:          NOTRUN -> [SKIP][113] ([i915#3638]) +5 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-180:
    - shard-dg2:          NOTRUN -> [SKIP][114] ([i915#4538] / [i915#5190]) +9 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-8/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-rkl:          [PASS][115] -> [DMESG-WARN][116] ([i915#12917] / [i915#12964]) +1 other test dmesg-warn
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-rkl-1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
    - shard-dg1:          NOTRUN -> [SKIP][117] ([i915#4538]) +3 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html

  * igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][118] ([i915#10307] / [i915#6095]) +171 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][119] ([i915#12313])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][120] ([i915#6095]) +9 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][121] ([i915#12805])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][122] ([i915#6095]) +110 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-c-dp-4:
    - shard-dg2:          NOTRUN -> [SKIP][123] ([i915#6095]) +16 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-10/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-c-dp-4.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-a-hdmi-a-2:
    - shard-glk:          NOTRUN -> [INCOMPLETE][124] ([i915#12796]) +1 other test incomplete
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-glk8/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][125] ([i915#12313]) +1 other test skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][126] ([i915#6095]) +44 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][127] ([i915#12313]) +1 other test skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-2:
    - shard-glk:          NOTRUN -> [SKIP][128] +29 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-glk8/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][129] ([i915#6095]) +166 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][130] ([i915#10307] / [i915#10434] / [i915#6095]) +3 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-4/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][131] ([i915#4087]) +3 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-11/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-2.html

  * igt@kms_chamelium_color@ctm-0-50:
    - shard-dg1:          NOTRUN -> [SKIP][132] +47 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_chamelium_color@ctm-0-50.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - shard-dg2:          NOTRUN -> [SKIP][133] ([i915#7828]) +6 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@kms_chamelium_frames@dp-crc-fast.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-tglu:         NOTRUN -> [SKIP][134] ([i915#7828]) +3 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-5/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_chamelium_hpd@hdmi-hpd-fast:
    - shard-rkl:          NOTRUN -> [SKIP][135] ([i915#7828]) +5 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@kms_chamelium_hpd@hdmi-hpd-fast.html
    - shard-dg1:          NOTRUN -> [SKIP][136] ([i915#7828]) +9 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-17/igt@kms_chamelium_hpd@hdmi-hpd-fast.html

  * igt@kms_chamelium_hpd@vga-hpd-fast:
    - shard-tglu-1:       NOTRUN -> [SKIP][137] ([i915#7828]) +4 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_chamelium_hpd@vga-hpd-fast.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-tglu:         NOTRUN -> [SKIP][138] ([i915#3116] / [i915#3299])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][139] ([i915#3116] / [i915#3299])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_content_protection@dp-mst-type-1.html
    - shard-dg2:          NOTRUN -> [SKIP][140] ([i915#3299])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [TIMEOUT][141] ([i915#7173])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-10/igt@kms_content_protection@lic-type-0@pipe-a-dp-4.html

  * igt@kms_content_protection@mei-interface:
    - shard-rkl:          NOTRUN -> [SKIP][142] ([i915#9424])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@kms_content_protection@mei-interface.html
    - shard-dg1:          NOTRUN -> [SKIP][143] ([i915#9424])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-17/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@type1:
    - shard-rkl:          NOTRUN -> [SKIP][144] ([i915#7118] / [i915#9424])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@kms_content_protection@type1.html

  * igt@kms_content_protection@uevent:
    - shard-dg1:          NOTRUN -> [SKIP][145] ([i915#7116] / [i915#9424])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-32x32:
    - shard-dg1:          NOTRUN -> [SKIP][146] ([i915#3555]) +9 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-17/igt@kms_cursor_crc@cursor-offscreen-32x32.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-tglu-1:       NOTRUN -> [SKIP][147] ([i915#3555]) +3 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-tglu:         NOTRUN -> [SKIP][148] ([i915#13049])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-5/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-rkl:          NOTRUN -> [SKIP][149] ([i915#4103])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
    - shard-dg1:          NOTRUN -> [SKIP][150] ([i915#4103] / [i915#4213]) +1 other test skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-17/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][151] ([i915#13046] / [i915#5354]) +4 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-11/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
    - shard-mtlp:         NOTRUN -> [SKIP][152] ([i915#9809])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-6/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html

  * igt@kms_display_modes@mst-extended-mode-negative:
    - shard-dg2:          NOTRUN -> [SKIP][153] ([i915#8588])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@kms_display_modes@mst-extended-mode-negative.html
    - shard-rkl:          NOTRUN -> [SKIP][154] ([i915#8588])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-7/igt@kms_display_modes@mst-extended-mode-negative.html

  * igt@kms_dsc@dsc-basic:
    - shard-dg2:          NOTRUN -> [SKIP][155] ([i915#3555] / [i915#3840])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@kms_dsc@dsc-basic.html
    - shard-tglu-1:       NOTRUN -> [SKIP][156] ([i915#3555] / [i915#3840])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-rkl:          NOTRUN -> [SKIP][157] ([i915#3840])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-6/igt@kms_dsc@dsc-fractional-bpp.html
    - shard-tglu:         NOTRUN -> [SKIP][158] ([i915#3840])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-rkl:          NOTRUN -> [SKIP][159] ([i915#3555] / [i915#3840])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@kms_dsc@dsc-with-output-formats.html
    - shard-dg1:          NOTRUN -> [SKIP][160] ([i915#3555] / [i915#3840]) +1 other test skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-17/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-rkl:          NOTRUN -> [SKIP][161] ([i915#3840] / [i915#9053])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_feature_discovery@display-4x:
    - shard-rkl:          NOTRUN -> [SKIP][162] ([i915#1839])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-7/igt@kms_feature_discovery@display-4x.html
    - shard-dg2:          NOTRUN -> [SKIP][163] ([i915#1839])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@psr2:
    - shard-tglu-1:       NOTRUN -> [SKIP][164] ([i915#658])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_feature_discovery@psr2.html
    - shard-dg1:          NOTRUN -> [SKIP][165] ([i915#658])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@kms_feature_discovery@psr2.html
    - shard-dg2:          NOTRUN -> [SKIP][166] ([i915#658])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
    - shard-dg2:          NOTRUN -> [SKIP][167] ([i915#9934]) +3 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html

  * igt@kms_flip@2x-plain-flip:
    - shard-dg1:          NOTRUN -> [SKIP][168] ([i915#9934]) +4 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@2x-plain-flip-interruptible:
    - shard-rkl:          NOTRUN -> [SKIP][169] ([i915#9934]) +5 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-7/igt@kms_flip@2x-plain-flip-interruptible.html

  * igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
    - shard-tglu:         NOTRUN -> [SKIP][170] ([i915#3637]) +5 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html

  * igt@kms_flip@blocking-wf_vblank@a-hdmi-a1:
    - shard-tglu:         [PASS][171] -> [FAIL][172] ([i915#11989]) +1 other test fail
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-tglu-6/igt@kms_flip@blocking-wf_vblank@a-hdmi-a1.html
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-2/igt@kms_flip@blocking-wf_vblank@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1:
    - shard-glk:          [PASS][173] -> [FAIL][174] ([i915#11989]) +2 other tests fail
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-glk6/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1.html
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-glk8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-fences-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][175] ([i915#8381])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-17/igt@kms_flip@flip-vs-fences-interruptible.html

  * igt@kms_flip@plain-flip-fb-recreate@d-hdmi-a1:
    - shard-tglu:         NOTRUN -> [FAIL][176] ([i915#11989]) +3 other tests fail
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@kms_flip@plain-flip-fb-recreate@d-hdmi-a1.html

  * igt@kms_flip@wf_vblank-ts-check-interruptible:
    - shard-rkl:          NOTRUN -> [FAIL][177] ([i915#11989] / [i915#12840]) +1 other test fail
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@kms_flip@wf_vblank-ts-check-interruptible.html

  * igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a2:
    - shard-rkl:          NOTRUN -> [FAIL][178] ([i915#11989])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a2.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][179] ([i915#2672] / [i915#3555]) +3 other tests skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
    - shard-rkl:          NOTRUN -> [SKIP][180] ([i915#2672] / [i915#3555]) +3 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][181] ([i915#2672]) +3 other tests skip
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][182] ([i915#2672] / [i915#3555]) +2 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][183] ([i915#2672]) +2 other tests skip
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
    - shard-tglu-1:       NOTRUN -> [SKIP][184] ([i915#2587] / [i915#2672]) +3 other tests skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][185] ([i915#2587] / [i915#2672]) +5 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg1:          NOTRUN -> [SKIP][186] ([i915#2587] / [i915#2672] / [i915#3555])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
    - shard-dg1:          NOTRUN -> [SKIP][187] ([i915#2672] / [i915#3555]) +4 other tests skip
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][188] ([i915#8708])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][189] ([i915#5354]) +16 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][190] ([i915#8708]) +21 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt:
    - shard-snb:          [PASS][191] -> [SKIP][192]
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][193] ([i915#8708]) +19 other tests skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][194] ([i915#5439]) +1 other test skip
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
    - shard-dg1:          NOTRUN -> [SKIP][195] ([i915#5439])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][196] +19 other tests skip
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][197] ([i915#1825]) +31 other tests skip
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-mtlp:         NOTRUN -> [SKIP][198] ([i915#1825]) +1 other test skip
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
    - shard-tglu-1:       NOTRUN -> [SKIP][199] +38 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][200] ([i915#3023]) +24 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@pipe-fbc-rte:
    - shard-tglu-1:       NOTRUN -> [SKIP][201] ([i915#9766])
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
    - shard-dg1:          NOTRUN -> [SKIP][202] ([i915#9766])
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
    - shard-dg2:          NOTRUN -> [SKIP][203] ([i915#9766])
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
    - shard-dg2:          NOTRUN -> [SKIP][204] ([i915#3458]) +14 other tests skip
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render:
    - shard-tglu:         NOTRUN -> [SKIP][205] +52 other tests skip
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite:
    - shard-dg1:          NOTRUN -> [SKIP][206] ([i915#3458]) +22 other tests skip
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-tglu-1:       NOTRUN -> [SKIP][207] ([i915#3555] / [i915#8228])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-dg1:          NOTRUN -> [SKIP][208] ([i915#12713])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-dg2:          NOTRUN -> [SKIP][209] ([i915#3555] / [i915#8228]) +1 other test skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@kms_hdr@invalid-metadata-sizes.html
    - shard-rkl:          NOTRUN -> [SKIP][210] ([i915#3555] / [i915#8228])
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-7/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][211] ([i915#12339])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-7/igt@kms_joiner@basic-ultra-joiner.html
    - shard-dg2:          NOTRUN -> [SKIP][212] ([i915#12339])
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-dg1:          NOTRUN -> [SKIP][213] ([i915#12388])
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-dg1:          NOTRUN -> [SKIP][214] ([i915#12394])
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-dg1:          NOTRUN -> [SKIP][215] ([i915#12339])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-tglu:         NOTRUN -> [SKIP][216] ([i915#1839]) +1 other test skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-5/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c:
    - shard-dg2:          NOTRUN -> [SKIP][217] +7 other tests skip
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-rkl:          NOTRUN -> [SKIP][218] ([i915#3555]) +2 other tests skip
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-7/igt@kms_plane_multiple@tiling-yf.html
    - shard-dg2:          NOTRUN -> [SKIP][219] ([i915#3555] / [i915#8806])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-rkl:          NOTRUN -> [SKIP][220] ([i915#6953])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-c:
    - shard-tglu:         NOTRUN -> [SKIP][221] ([i915#12247]) +18 other tests skip
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-c.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25:
    - shard-tglu:         NOTRUN -> [SKIP][222] ([i915#12247] / [i915#6953])
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@kms_plane_scaling@planes-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
    - shard-dg2:          NOTRUN -> [SKIP][223] ([i915#12247] / [i915#6953] / [i915#9423])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html
    - shard-rkl:          NOTRUN -> [SKIP][224] ([i915#12247] / [i915#6953]) +2 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-7/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-a:
    - shard-dg2:          NOTRUN -> [SKIP][225] ([i915#12247]) +7 other tests skip
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-a.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b:
    - shard-rkl:          NOTRUN -> [SKIP][226] ([i915#12247]) +5 other tests skip
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25:
    - shard-dg1:          NOTRUN -> [SKIP][227] ([i915#12247] / [i915#6953])
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-17/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
    - shard-tglu-1:       NOTRUN -> [SKIP][228] ([i915#12247] / [i915#3555])
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
    - shard-dg1:          NOTRUN -> [SKIP][229] ([i915#12247] / [i915#3555])
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
    - shard-dg2:          NOTRUN -> [SKIP][230] ([i915#12247] / [i915#3555] / [i915#9423])
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a:
    - shard-tglu-1:       NOTRUN -> [SKIP][231] ([i915#12247]) +3 other tests skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a.html
    - shard-dg1:          NOTRUN -> [SKIP][232] ([i915#12247]) +12 other tests skip
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-rkl:          NOTRUN -> [SKIP][233] ([i915#5354])
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@kms_pm_backlight@basic-brightness.html
    - shard-dg1:          NOTRUN -> [SKIP][234] ([i915#5354])
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-17/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-rkl:          NOTRUN -> [SKIP][235] ([i915#3828])
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][236] ([i915#5978])
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@kms_pm_dc@dc6-dpms.html
    - shard-tglu-1:       NOTRUN -> [FAIL][237] ([i915#9295])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_pm_dc@dc6-dpms.html
    - shard-dg1:          NOTRUN -> [SKIP][238] ([i915#3361])
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu:         [PASS][239] -> [SKIP][240] ([i915#4281])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-tglu-6/igt@kms_pm_dc@dc9-dpms.html
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-7/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-dg2:          NOTRUN -> [SKIP][241] ([i915#9519])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-rkl:          [PASS][242] -> [SKIP][243] ([i915#9519]) +1 other test skip
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-2/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
    - shard-tglu:         NOTRUN -> [SKIP][244] ([i915#11520]) +4 other tests skip
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf:
    - shard-glk:          NOTRUN -> [SKIP][245] ([i915#11520]) +1 other test skip
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-glk8/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
    - shard-rkl:          NOTRUN -> [SKIP][246] ([i915#11520]) +9 other tests skip
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-snb:          NOTRUN -> [SKIP][247] ([i915#11520]) +5 other tests skip
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-snb2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area:
    - shard-tglu-1:       NOTRUN -> [SKIP][248] ([i915#11520]) +4 other tests skip
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-dg1:          NOTRUN -> [SKIP][249] ([i915#11520]) +11 other tests skip
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area:
    - shard-dg2:          NOTRUN -> [SKIP][250] ([i915#11520]) +6 other tests skip
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-dg2:          NOTRUN -> [SKIP][251] ([i915#9683])
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@kms_psr2_su@frontbuffer-xrgb8888.html
    - shard-rkl:          NOTRUN -> [SKIP][252] ([i915#9683])
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-7/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@fbc-psr-cursor-plane-move:
    - shard-tglu-1:       NOTRUN -> [SKIP][253] ([i915#9732]) +7 other tests skip
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_psr@fbc-psr-cursor-plane-move.html

  * igt@kms_psr@pr-primary-page-flip:
    - shard-mtlp:         NOTRUN -> [SKIP][254] ([i915#9688]) +4 other tests skip
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-6/igt@kms_psr@pr-primary-page-flip.html

  * igt@kms_psr@psr-primary-page-flip:
    - shard-tglu:         NOTRUN -> [SKIP][255] ([i915#9732]) +11 other tests skip
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_psr@psr2-cursor-blt:
    - shard-dg2:          NOTRUN -> [SKIP][256] ([i915#1072] / [i915#9732]) +13 other tests skip
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@kms_psr@psr2-cursor-blt.html
    - shard-rkl:          NOTRUN -> [SKIP][257] ([i915#1072] / [i915#9732]) +20 other tests skip
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-7/igt@kms_psr@psr2-cursor-blt.html

  * igt@kms_psr@psr2-sprite-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][258] ([i915#1072] / [i915#9732]) +25 other tests skip
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-17/igt@kms_psr@psr2-sprite-mmap-gtt.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-tglu-1:       NOTRUN -> [SKIP][259] ([i915#9685])
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
    - shard-dg1:          NOTRUN -> [SKIP][260] ([i915#9685]) +1 other test skip
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
    - shard-dg2:          NOTRUN -> [SKIP][261] ([i915#9685])
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-tglu-1:       NOTRUN -> [SKIP][262] ([i915#5289]) +1 other test skip
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
    - shard-mtlp:         NOTRUN -> [SKIP][263] ([i915#5289])
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-dg1:          NOTRUN -> [SKIP][264] ([i915#5289])
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-tglu:         NOTRUN -> [SKIP][265] ([i915#5289])
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-dg2:          NOTRUN -> [SKIP][266] ([i915#12755]) +1 other test skip
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-dg2:          NOTRUN -> [SKIP][267] ([i915#3555]) +3 other tests skip
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_selftest@drm_framebuffer:
    - shard-snb:          NOTRUN -> [ABORT][268] ([i915#13179]) +1 other test abort
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-snb4/igt@kms_selftest@drm_framebuffer.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-tglu:         NOTRUN -> [SKIP][269] ([i915#3555]) +1 other test skip
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-tglu:         NOTRUN -> [SKIP][270] ([i915#8623])
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vblank@ts-continuation-dpms-rpm:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][271] ([i915#12917] / [i915#12964])
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@kms_vblank@ts-continuation-dpms-rpm.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-2:
    - shard-glk:          NOTRUN -> [INCOMPLETE][272] ([i915#12276])
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-glk3/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-2.html

  * igt@kms_vrr@seamless-rr-switch-virtual:
    - shard-dg1:          NOTRUN -> [SKIP][273] ([i915#9906])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@kms_vrr@seamless-rr-switch-virtual.html

  * igt@kms_vrr@seamless-rr-switch-vrr:
    - shard-rkl:          NOTRUN -> [SKIP][274] ([i915#9906])
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-6/igt@kms_vrr@seamless-rr-switch-vrr.html

  * igt@kms_writeback@writeback-check-output-xrgb2101010:
    - shard-dg2:          NOTRUN -> [SKIP][275] ([i915#2437] / [i915#9412])
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@kms_writeback@writeback-check-output-xrgb2101010.html

  * igt@kms_writeback@writeback-fb-id-xrgb2101010:
    - shard-rkl:          NOTRUN -> [SKIP][276] ([i915#2437] / [i915#9412]) +1 other test skip
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@kms_writeback@writeback-fb-id-xrgb2101010.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-tglu:         NOTRUN -> [SKIP][277] ([i915#2437] / [i915#9412])
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-5/igt@kms_writeback@writeback-pixel-formats.html

  * igt@perf@polling@0-rcs0:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][278] ([i915#12964]) +14 other tests dmesg-warn
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-7/igt@perf@polling@0-rcs0.html

  * igt@perf_pmu@busy-accuracy-98:
    - shard-snb:          NOTRUN -> [SKIP][279] +229 other tests skip
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-snb4/igt@perf_pmu@busy-accuracy-98.html

  * igt@perf_pmu@busy-double-start@vecs1:
    - shard-dg2:          [PASS][280] -> [FAIL][281] ([i915#4349]) +4 other tests fail
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-11/igt@perf_pmu@busy-double-start@vecs1.html
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@perf_pmu@busy-double-start@vecs1.html

  * igt@perf_pmu@rc6-all-gts:
    - shard-tglu-1:       NOTRUN -> [SKIP][282] ([i915#8516])
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@perf_pmu@rc6-all-gts.html
    - shard-dg2:          NOTRUN -> [SKIP][283] ([i915#8516])
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@perf_pmu@rc6-all-gts.html

  * igt@prime_mmap@test_aperture_limit:
    - shard-dg2:          NOTRUN -> [WARN][284] ([i915#9351])
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@prime_mmap@test_aperture_limit.html

  * igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
    - shard-dg2:          NOTRUN -> [CRASH][285] ([i915#9351])
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html

  * igt@prime_vgem@basic-fence-mmap:
    - shard-dg1:          NOTRUN -> [SKIP][286] ([i915#3708] / [i915#4077])
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-fence-read:
    - shard-rkl:          NOTRUN -> [SKIP][287] ([i915#3291] / [i915#3708])
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][288] ([i915#3708] / [i915#4077])
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-6/igt@prime_vgem@basic-gtt.html
    - shard-dg2:          NOTRUN -> [SKIP][289] ([i915#3708] / [i915#4077])
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@prime_vgem@basic-gtt.html

  * igt@prime_vgem@fence-flip-hang:
    - shard-dg1:          NOTRUN -> [SKIP][290] ([i915#3708]) +1 other test skip
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-17/igt@prime_vgem@fence-flip-hang.html

  * igt@prime_vgem@fence-write-hang:
    - shard-dg2:          NOTRUN -> [SKIP][291] ([i915#3708])
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@prime_vgem@fence-write-hang.html
    - shard-rkl:          NOTRUN -> [SKIP][292] ([i915#3708]) +1 other test skip
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-7/igt@prime_vgem@fence-write-hang.html

  * igt@sriov_basic@bind-unbind-vf:
    - shard-dg1:          NOTRUN -> [SKIP][293] ([i915#9917])
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@sriov_basic@bind-unbind-vf.html

  * igt@sriov_basic@enable-vfs-autoprobe-off:
    - shard-rkl:          NOTRUN -> [SKIP][294] ([i915#9917]) +1 other test skip
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-6/igt@sriov_basic@enable-vfs-autoprobe-off.html

  * igt@sriov_basic@enable-vfs-autoprobe-off@numvfs-6:
    - shard-tglu:         NOTRUN -> [FAIL][295] ([i915#12910]) +9 other tests fail
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@sriov_basic@enable-vfs-autoprobe-off@numvfs-6.html

  * igt@sriov_basic@enable-vfs-autoprobe-on:
    - shard-dg2:          NOTRUN -> [SKIP][296] ([i915#9917]) +1 other test skip
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@sriov_basic@enable-vfs-autoprobe-on.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-tglu-1:       NOTRUN -> [FAIL][297] ([i915#12910])
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-1/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  * igt@tools_test@sysfs_l3_parity:
    - shard-dg1:          NOTRUN -> [SKIP][298] ([i915#4818])
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-12/igt@tools_test@sysfs_l3_parity.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3-devices:
    - shard-dg1:          [DMESG-WARN][299] ([i915#4423]) -> [PASS][300] +1 other test pass
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg1-18/igt@gem_exec_suspend@basic-s3-devices.html
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg1-13/igt@gem_exec_suspend@basic-s3-devices.html

  * igt@gem_mmap_offset@clear-via-pagefault:
    - shard-mtlp:         [ABORT][301] ([i915#10729]) -> [PASS][302] +1 other test pass
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-mtlp-1/igt@gem_mmap_offset@clear-via-pagefault.html
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-6/igt@gem_mmap_offset@clear-via-pagefault.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-tglu:         [FAIL][303] -> [PASS][304]
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-tglu-2/igt@gem_tiled_swapping@non-threaded.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-7/igt@gem_tiled_swapping@non-threaded.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-glk:          [ABORT][305] ([i915#5566]) -> [PASS][306]
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-glk6/igt@gen9_exec_parse@allowed-single.html
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-glk8/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_module_load@load:
    - shard-dg2:          ([PASS][307], [PASS][308], [PASS][309], [PASS][310], [PASS][311], [PASS][312], [PASS][313], [PASS][314], [PASS][315], [PASS][316], [PASS][317], [PASS][318], [DMESG-WARN][319], [PASS][320], [PASS][321], [DMESG-WARN][322], [PASS][323], [PASS][324], [PASS][325], [PASS][326], [PASS][327], [PASS][328]) ([i915#13368]) -> ([PASS][329], [PASS][330], [PASS][331], [PASS][332], [PASS][333], [PASS][334], [PASS][335], [PASS][336], [PASS][337], [PASS][338], [PASS][339], [PASS][340], [PASS][341], [PASS][342], [PASS][343], [PASS][344], [PASS][345], [PASS][346], [PASS][347], [PASS][348], [PASS][349], [PASS][350])
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-7/igt@i915_module_load@load.html
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-4/igt@i915_module_load@load.html
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-11/igt@i915_module_load@load.html
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-8/igt@i915_module_load@load.html
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-10/igt@i915_module_load@load.html
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-11/igt@i915_module_load@load.html
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-8/igt@i915_module_load@load.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-8/igt@i915_module_load@load.html
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-10/igt@i915_module_load@load.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-1/igt@i915_module_load@load.html
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-1/igt@i915_module_load@load.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-6/igt@i915_module_load@load.html
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-2/igt@i915_module_load@load.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-2/igt@i915_module_load@load.html
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-6/igt@i915_module_load@load.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-2/igt@i915_module_load@load.html
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-2/igt@i915_module_load@load.html
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-5/igt@i915_module_load@load.html
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-3/igt@i915_module_load@load.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-3/igt@i915_module_load@load.html
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-5/igt@i915_module_load@load.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-4/igt@i915_module_load@load.html
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-8/igt@i915_module_load@load.html
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@i915_module_load@load.html
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@i915_module_load@load.html
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-8/igt@i915_module_load@load.html
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-10/igt@i915_module_load@load.html
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@i915_module_load@load.html
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-11/igt@i915_module_load@load.html
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-6/igt@i915_module_load@load.html
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-4/igt@i915_module_load@load.html
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-4/igt@i915_module_load@load.html
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@i915_module_load@load.html
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-1/igt@i915_module_load@load.html
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@i915_module_load@load.html
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@i915_module_load@load.html
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-6/igt@i915_module_load@load.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-11/igt@i915_module_load@load.html
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@i915_module_load@load.html
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-2/igt@i915_module_load@load.html
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-7/igt@i915_module_load@load.html
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-2/igt@i915_module_load@load.html
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-2/igt@i915_module_load@load.html
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-6/igt@i915_module_load@load.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-tglu:         [ABORT][351] ([i915#12817] / [i915#9820]) -> [PASS][352]
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-tglu-2/igt@i915_module_load@reload-with-fault-injection.html
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-5/igt@i915_module_load@reload-with-fault-injection.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:
    - shard-glk:          [FAIL][353] ([i915#12238]) -> [PASS][354]
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-glk6/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs:
    - shard-glk:          [FAIL][355] ([i915#11859]) -> [PASS][356]
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs.html
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-glk6/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs.html

  * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
    - shard-mtlp:         [FAIL][357] ([i915#2346]) -> [PASS][358]
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-mtlp-6/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-2/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-vga1-hdmi-a1:
    - shard-snb:          [FAIL][359] ([i915#11989]) -> [PASS][360] +1 other test pass
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-snb7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-vga1-hdmi-a1.html
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-snb7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible@ab-vga1-hdmi-a1.html

  * igt@kms_flip@blocking-wf_vblank:
    - shard-rkl:          [FAIL][361] ([i915#11989] / [i915#12840]) -> [PASS][362]
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-rkl-7/igt@kms_flip@blocking-wf_vblank.html
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-3/igt@kms_flip@blocking-wf_vblank.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
    - shard-mtlp:         [FAIL][363] ([i915#12741]) -> [PASS][364]
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-mtlp-1/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-6/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1:
    - shard-mtlp:         [FAIL][365] ([i915#11989]) -> [PASS][366] +1 other test pass
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-mtlp-1/igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1.html
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-6/igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank@d-edp1:
    - shard-mtlp:         [FAIL][367] ([i915#11989] / [i915#12740]) -> [PASS][368] +1 other test pass
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-mtlp-1/igt@kms_flip@flip-vs-blocking-wf-vblank@d-edp1.html
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-6/igt@kms_flip@flip-vs-blocking-wf-vblank@d-edp1.html

  * igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a1:
    - shard-tglu:         [FAIL][369] ([i915#11989]) -> [PASS][370] +1 other test pass
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-tglu-4/igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a1.html
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-tglu-4/igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a1.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-rkl:          [SKIP][371] ([i915#9519]) -> [PASS][372] +1 other test pass
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-rkl-2/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-rkl:          [DMESG-WARN][373] ([i915#12964]) -> [PASS][374]
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-rkl-2/igt@kms_rotation_crc@primary-rotation-90.html
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1:
    - shard-glk:          [INCOMPLETE][375] ([i915#12276]) -> [PASS][376]
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-glk2/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1.html
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-glk3/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1.html

  * igt@perf_pmu@all-busy-check-all:
    - shard-mtlp:         [FAIL][377] -> [PASS][378]
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-mtlp-4/igt@perf_pmu@all-busy-check-all.html
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-3/igt@perf_pmu@all-busy-check-all.html

  * igt@perf_pmu@render-node-busy-idle:
    - shard-mtlp:         [FAIL][379] ([i915#4349]) -> [PASS][380] +1 other test pass
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-mtlp-2/igt@perf_pmu@render-node-busy-idle.html
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-5/igt@perf_pmu@render-node-busy-idle.html

  
#### Warnings ####

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-glk:          [ABORT][381] -> [ABORT][382] ([i915#9820])
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-glk8/igt@i915_module_load@reload-with-fault-injection.html
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-glk8/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-rkl:          [SKIP][383] ([i915#13328]) -> [DMESG-WARN][384] ([i915#12964])
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-rkl-2/igt@i915_pm_rpm@system-suspend.html
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-rkl-5/igt@i915_pm_rpm@system-suspend.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [DMESG-FAIL][385] ([i915#13314]) -> [DMESG-FAIL][386] ([i915#11627] / [i915#13314])
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_content_protection@lic-type-0:
    - shard-dg2:          [SKIP][387] ([i915#9424]) -> [TIMEOUT][388] ([i915#7173])
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-7/igt@kms_content_protection@lic-type-0.html
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-10/igt@kms_content_protection@lic-type-0.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu:
    - shard-dg2:          [SKIP][389] ([i915#3458]) -> [SKIP][390] ([i915#10433] / [i915#3458]) +1 other test skip
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu.html
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
    - shard-dg2:          [SKIP][391] ([i915#10433] / [i915#3458]) -> [SKIP][392] ([i915#3458]) +1 other test skip
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-dg2:          [SKIP][393] ([i915#13331]) -> [SKIP][394] ([i915#12713])
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15873/shard-dg2-10/igt@kms_hdr@brightness-with-hdr.html
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/shard-dg2-3/igt@kms_hdr@brightness-with-hdr.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#10729]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10729
  [i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
  [i915#11441]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11441
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11627]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11627
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#11823]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11823
  [i915#11859]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11859
  [i915#11965]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11965
  [i915#11989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11989
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12238]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12238
  [i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
  [i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
  [i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
  [i915#12394]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12394
  [i915#12455]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12455
  [i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
  [i915#12740]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12740
  [i915#12741]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12741
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12796]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12796
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#12817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12817
  [i915#12840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12840
  [i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
  [i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
  [i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
  [i915#13287]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13287
  [i915#13304]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13304
  [i915#13314]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13314
  [i915#13328]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13328
  [i915#13331]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13331
  [i915#13368]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13368
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
  [i915#2436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2436
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3778
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#3936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3936
  [i915#4036]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4036
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4818]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4818
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
  [i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
  [i915#4958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4958
  [i915#5107]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5107
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
  [i915#5507]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5507
  [i915#5566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5566
  [i915#5882]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5882
  [i915#5978]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5978
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6188]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6188
  [i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7016]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7016
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
  [i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
  [i915#8588]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8588
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/is

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v2/index.html

[-- Attachment #2: Type: text/html, Size: 123457 bytes --]

✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: 128b/132b uncompressed SST (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: 128b/132b uncompressed SST (rev3)
URL   : https://patchwork.freedesktop.org/series/142547/
State : warning

== Summary ==

Error: dim checkpatch failed
8c415b084cef drm/mst: remove mgr parameter and debug logging from drm_dp_get_vc_payload_bw()
65dac07c523a drm/i915/mst: drop connector parameter from intel_dp_mst_bw_overhead()
5c061d877fd8 drm/i915/mst: drop connector parameter from intel_dp_mst_compute_m_n()
bb57b6d91bc1 drm/i915/mst: change return value of mst_stream_find_vcpi_slots_for_bpp()
22e78a566711 drm/i915/mst: remove crtc_state->pbn
4161e0731bd4 drm/i915/mst: split out a helper for figuring out the TU
637a9bcb889c drm/i915/mst: adapt intel_dp_mtp_tu_compute_config() for 128b/132b SST
-:87: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#87: FILE: drivers/gpu/drm/i915/display/intel_dp_mst.c:280:
+								      true, dsc_slice_count, link_bpp_x16);

total: 0 errors, 1 warnings, 0 checks, 128 lines checked
8b52ae436c05 drm/i915/ddi: enable 128b/132b TRANS_DDI_FUNC_CTL mode for UHBR SST
59bb6a8fd137 drm/i915/ddi: 128b/132b SST also needs DP_TP_CTL_MODE_MST
1a61d7ad72b2 drm/i915/ddi: write payload for 128b/132b SST
1cf0d2a4e210 drm/i915/ddi: initialize 128b/132b SST DP2 VFREQ registers
335866dee88f drm/i915/ddi: enable ACT handling for 128b/132b SST
7dfcad31b374 drm/i915/ddi: start distinguishing 128b/132b SST and MST at state readout
10cf30f8ec6c drm/i915/ddi: handle 128b/132b SST in intel_ddi_read_func_ctl()
4334d0e093b0 drm/i915/ddi: disable trancoder port select for 128b/132b SST
e1d14691b9ef drm/i915/dp: compute config for 128b/132b SST w/o DSC

✗ Fi.CI.SPARSE: warning for drm/i915/dp: 128b/132b uncompressed SST (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: 128b/132b uncompressed SST (rev3)
URL   : https://patchwork.freedesktop.org/series/142547/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✓ i915.CI.BAT: success for drm/i915/dp: 128b/132b uncompressed SST (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: 128b/132b uncompressed SST (rev3)
URL   : https://patchwork.freedesktop.org/series/142547/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_15892 -> Patchwork_142547v3
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v3/index.html

Participating hosts (41 -> 39)
------------------------------

  Missing    (2): bat-twl-1 fi-snb-2520m 


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_8172 -> None
  * Linux: CI_DRM_15892 -> Patchwork_142547v3

  CI-20190529: 20190529
  CI_DRM_15892: 08bd590935a5258ffd79355c59adffd72fb2c642 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8172: 9112581619aa198fa03041d5c7e18e02f42ac00f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_142547v3: 08bd590935a5258ffd79355c59adffd72fb2c642 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v3/index.html

✓ i915.CI.Full: success for drm/i915/dp: 128b/132b uncompressed SST (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1142 bytes --]

== Series Details ==

Series: drm/i915/dp: 128b/132b uncompressed SST (rev3)
URL   : https://patchwork.freedesktop.org/series/142547/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_15892_full -> Patchwork_142547v3_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 9)
------------------------------

  Missing    (2): shard-snb-0 shard-glk-0 


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_8172 -> None
  * Linux: CI_DRM_15892 -> Patchwork_142547v3

  CI-20190529: 20190529
  CI_DRM_15892: 08bd590935a5258ffd79355c59adffd72fb2c642 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8172: 9112581619aa198fa03041d5c7e18e02f42ac00f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_142547v3: 08bd590935a5258ffd79355c59adffd72fb2c642 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142547v3/index.html

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