* [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset
@ 2022-10-04 12:53 Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 1/7] drm/i915/display: Pass struct drm_i915_private to DDI_BUF_CTL macro Balasubramani Vivekanandan
` (9 more replies)
0 siblings, 10 replies; 12+ messages in thread
From: Balasubramani Vivekanandan @ 2022-10-04 12:53 UTC (permalink / raw)
To: intel-gfx
Prior to display version 12, platforms had DDI ports A,B,C,D,E,F
represented by enums PORT_A,PORT_B...PORT_F. The DDI register offsets of
the ports were in the same order as the ports. So the port enums
were directly used as index to calculate the register offset of the
ports.
Starting in display version 12, TypeC ports were introduced in the
platforms. These were defined as new enums PORT_TC1,PORT_TC2... The
later generation platforms had DDI register offests of TypeC and
non-TypeC ports interleaved and the existing port enums didn't match the
order of the DDI register offests. So the enums could no more be used as
index to calculate the register offest.
This led to the creation of new platform specific enums for the ports
like PORT_D_XELPD, PORT_E_XELPD to match the index of the ports in those
platforms and additional code to handle the special enums.
So we want to make the port enums not tied to DDI register offset and
use the index from somewhere else to calculate the register offsets.
The index of the DDI ports in the platform is now defined as part of
device info.
Series includes few patches at the end which does some cleanup and
fixing made possible because of unique enums for the ports.
v2: ddi_index defined for platforms starting from Gen75. Many platforms
from Gen75 has ddi support.
v3: Updated DDI_CLK_SEL macro to use new index for DDI register offset
caculation.
v4: After removing d13_port_domains array, d12_port_domains is used for
all platforms with DISPLAY_VER 12 and above. So the port_end member had
to fixed to extend it for ports D and E.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Balasubramani Vivekanandan (7):
drm/i915/display: Pass struct drm_i915_private to DDI_BUF_CTL macro
drm/i915/display: Pass struct drm_i915_private to DDI_CLK_SEL macro
drm/i915/display: Define the DDI port indices inside device info
drm/i915/display: Free port enums from tied to register offset
drm/i915/display: Remove PORT_D_XELPD/PORT_E_XELPD platform specific
defintions
drm/i915/display: Fix port_identifier function
drm/i915/display: cleanup unused DDI port enums
drivers/gpu/drm/i915/display/icl_dsi.c | 12 +--
drivers/gpu/drm/i915/display/intel_bios.c | 7 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 80 ++++++++-----------
drivers/gpu/drm/i915/display/intel_display.c | 12 +--
drivers/gpu/drm/i915/display/intel_display.h | 29 ++++---
.../drm/i915/display/intel_display_power.c | 44 +---------
drivers/gpu/drm/i915/display/intel_fdi.c | 14 ++--
drivers/gpu/drm/i915/display/intel_tc.c | 6 +-
drivers/gpu/drm/i915/gvt/display.c | 30 +++----
drivers/gpu/drm/i915/gvt/handlers.c | 17 ++--
drivers/gpu/drm/i915/i915_pci.c | 46 ++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 7 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 10 +--
include/drm/i915_component.h | 2 +-
15 files changed, 153 insertions(+), 164 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v6 1/7] drm/i915/display: Pass struct drm_i915_private to DDI_BUF_CTL macro
2022-10-04 12:53 [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset Balasubramani Vivekanandan
@ 2022-10-04 12:53 ` Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 2/7] drm/i915/display: Pass struct drm_i915_private to DDI_CLK_SEL macro Balasubramani Vivekanandan
` (8 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Balasubramani Vivekanandan @ 2022-10-04 12:53 UTC (permalink / raw)
To: intel-gfx
This is a prep patch for a patch series in which register offset of the
DDI ports are not calculated using the port enums but using a different
datastructure part of the device info.
So the device info is passed as a parameter to the macro DDI_BUF_CTL but
unused yet.
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 12 +++---
drivers/gpu/drm/i915/display/intel_ddi.c | 39 +++++++++++---------
drivers/gpu/drm/i915/display/intel_display.c | 6 ++-
drivers/gpu/drm/i915/display/intel_fdi.c | 14 +++----
drivers/gpu/drm/i915/display/intel_tc.c | 6 +--
drivers/gpu/drm/i915/gvt/display.c | 30 +++++++--------
drivers/gpu/drm/i915/gvt/handlers.c | 17 +++++----
drivers/gpu/drm/i915/i915_reg.h | 6 ++-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 10 ++---
9 files changed, 76 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 47f13750f6fa..f7c1f6561423 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -548,11 +548,11 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
enum port port;
for_each_dsi_port(port, intel_dsi->ports) {
- tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
+ tmp = intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port));
tmp |= DDI_BUF_CTL_ENABLE;
- intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp);
+ intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, port), tmp);
- if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
+ if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port)) &
DDI_BUF_IS_IDLE),
500))
drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
@@ -1400,11 +1400,11 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder)
gen11_dsi_ungate_clocks(encoder);
for_each_dsi_port(port, intel_dsi->ports) {
- tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
+ tmp = intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port));
tmp &= ~DDI_BUF_CTL_ENABLE;
- intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp);
+ intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, port), tmp);
- if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
+ if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port)) &
DDI_BUF_IS_IDLE),
8))
drm_err(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 971356237eca..77a986696c76 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -172,7 +172,7 @@ void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
return;
}
- if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
+ if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port)) &
DDI_BUF_IS_IDLE), 8))
drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
port_name(port));
@@ -189,7 +189,7 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
return;
}
- ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
+ ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port)) &
DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10);
if (ret)
@@ -730,7 +730,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
if (!wakeref)
return;
- tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
+ tmp = intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port));
if (!(tmp & DDI_BUF_CTL_ENABLE))
goto out;
@@ -1397,8 +1397,8 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
intel_dp->DP &= ~DDI_BUF_EMP_MASK;
intel_dp->DP |= signal_levels;
- intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
- intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
+ intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, port), intel_dp->DP);
+ intel_de_posting_read(dev_priv, DDI_BUF_CTL(dev_priv, port));
}
static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
@@ -2577,10 +2577,10 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
bool wait = false;
u32 val;
- val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
+ val = intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port));
if (val & DDI_BUF_CTL_ENABLE) {
val &= ~DDI_BUF_CTL_ENABLE;
- intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
+ intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, port), val);
wait = true;
}
@@ -2909,7 +2909,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
}
- intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
+ intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, port), buf_ctl);
intel_audio_codec_enable(encoder, crtc_state, conn_state);
}
@@ -3113,9 +3113,9 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
- ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
+ ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port));
if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
- intel_de_write(dev_priv, DDI_BUF_CTL(port),
+ intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, port),
ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
wait = true;
}
@@ -3145,8 +3145,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
adlp_tbt_to_dp_alt_switch_wa(encoder);
intel_dp->DP |= DDI_BUF_CTL_ENABLE;
- intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
- intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
+ intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, port), intel_dp->DP);
+ intel_de_posting_read(dev_priv, DDI_BUF_CTL(dev_priv, port));
intel_wait_ddi_buf_active(dev_priv, port);
}
@@ -3823,13 +3823,15 @@ static struct intel_connector *
intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
{
struct intel_connector *connector;
- enum port port = dig_port->base.port;
+ struct intel_encoder *encoder = &dig_port->base;
+ enum port port = encoder->port;
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
connector = intel_connector_alloc();
if (!connector)
return NULL;
- dig_port->dp.output_reg = DDI_BUF_CTL(port);
+ dig_port->dp.output_reg = DDI_BUF_CTL(i915, port);
dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
dig_port->dp.set_link_train = intel_ddi_set_link_train;
dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
@@ -4061,12 +4063,13 @@ intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
{
struct intel_connector *connector;
enum port port = dig_port->base.port;
+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
connector = intel_connector_alloc();
if (!connector)
return NULL;
- dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
+ dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(dev_priv, port);
intel_hdmi_init_connector(dig_port, connector);
return connector;
@@ -4102,7 +4105,7 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_port)
return max_lanes;
if (port == PORT_A || port == PORT_E) {
- if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
+ if (intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, PORT_A)) & DDI_A_4_LANES)
max_lanes = port == PORT_A ? 4 : 0;
else
/* Both A and E share 2 lanes */
@@ -4464,11 +4467,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
if (DISPLAY_VER(dev_priv) >= 11)
dig_port->saved_port_bits =
- intel_de_read(dev_priv, DDI_BUF_CTL(port))
+ intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port))
& DDI_BUF_PORT_REVERSAL;
else
dig_port->saved_port_bits =
- intel_de_read(dev_priv, DDI_BUF_CTL(port))
+ intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port))
& (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
if (intel_bios_is_lane_reversal_needed(dev_priv, port))
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3ffd8fc0b05c..8681055843f0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7884,7 +7884,7 @@ static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
return false;
/* DDI E can't be used if DDI A requires 4 lanes */
- if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
+ if (intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, PORT_A)) & DDI_A_4_LANES)
return false;
if (!dev_priv->display.vbt.int_crt_support)
@@ -7970,7 +7970,9 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
intel_crt_init(dev_priv);
/* Haswell uses DDI functions to detect digital outputs. */
- found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
+ found = intel_de_read(dev_priv,
+ DDI_BUF_CTL(dev_priv, PORT_A)) &
+ DDI_INIT_DISPLAY_DETECTED;
if (found)
intel_ddi_init(dev_priv, PORT_A);
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 7f47e5c85c81..d3d92ac26099 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -818,9 +818,9 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
* DDI E does not support port reversal, the functionality is
* achieved on the PCH side in FDI_RX_CTL, so no need to set the
* port reversal bit */
- intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E),
+ intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, PORT_E),
DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2));
- intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
+ intel_de_posting_read(dev_priv, DDI_BUF_CTL(dev_priv, PORT_E));
udelay(600);
@@ -864,10 +864,10 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
- temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
+ temp = intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, PORT_E));
temp &= ~DDI_BUF_CTL_ENABLE;
- intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
- intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
+ intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, PORT_E), temp);
+ intel_de_posting_read(dev_priv, DDI_BUF_CTL(dev_priv, PORT_E));
/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
@@ -909,9 +909,9 @@ void hsw_fdi_disable(struct intel_encoder *encoder)
val &= ~FDI_RX_ENABLE;
intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
- val = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
+ val = intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, PORT_E));
val &= ~DDI_BUF_CTL_ENABLE;
- intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), val);
+ intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, PORT_E), val);
intel_wait_ddi_buf_idle(dev_priv, PORT_E);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index b0aa1edd8302..a308665340d4 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -410,12 +410,12 @@ static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
enum port port = dig_port->base.port;
u32 val;
- val = intel_uncore_read(uncore, DDI_BUF_CTL(port));
+ val = intel_uncore_read(uncore, DDI_BUF_CTL(i915, port));
if (take)
val |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
else
val &= ~DDI_BUF_CTL_TC_PHY_OWNERSHIP;
- intel_uncore_write(uncore, DDI_BUF_CTL(port), val);
+ intel_uncore_write(uncore, DDI_BUF_CTL(i915, port), val);
return true;
}
@@ -455,7 +455,7 @@ static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port)
enum port port = dig_port->base.port;
u32 val;
- val = intel_uncore_read(uncore, DDI_BUF_CTL(port));
+ val = intel_uncore_read(uncore, DDI_BUF_CTL(i915, port));
return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP;
}
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index c7722c818b4d..5e3cd306c41d 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -213,10 +213,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
PORT_PLL_REF_SEL | PORT_PLL_LOCK |
PORT_PLL_ENABLE);
- vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=
+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, port)) &=
~(DDI_INIT_DISPLAY_DETECTED |
DDI_BUF_CTL_ENABLE);
- vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, port)) |= DDI_BUF_IS_IDLE;
}
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK);
@@ -276,9 +276,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
PORT_PLL_REF_SEL | PORT_PLL_LOCK |
PORT_PLL_ENABLE);
- vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=
+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_A)) |=
(DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED);
- vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_A)) &=
~DDI_BUF_IS_IDLE;
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=
(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
@@ -305,9 +305,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
PORT_PLL_REF_SEL | PORT_PLL_LOCK |
PORT_PLL_ENABLE);
- vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=
+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_B)) |=
DDI_BUF_CTL_ENABLE;
- vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_B)) &=
~DDI_BUF_IS_IDLE;
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
@@ -335,9 +335,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
PORT_PLL_REF_SEL | PORT_PLL_LOCK |
PORT_PLL_ENABLE);
- vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=
+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_C)) |=
DDI_BUF_CTL_ENABLE;
- vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_C)) &=
~DDI_BUF_IS_IDLE;
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
@@ -416,8 +416,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
PORT_CLK_SEL_LCPLL_810;
}
- vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
- vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_B)) |= DDI_BUF_CTL_ENABLE;
+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_B)) &= ~DDI_BUF_IS_IDLE;
vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
}
@@ -442,8 +442,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
PORT_CLK_SEL_LCPLL_810;
}
- vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
- vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_C)) |= DDI_BUF_CTL_ENABLE;
+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_C)) &= ~DDI_BUF_IS_IDLE;
vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
}
@@ -468,8 +468,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
PORT_CLK_SEL_LCPLL_810;
}
- vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
- vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_D)) |= DDI_BUF_CTL_ENABLE;
+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_D)) &= ~DDI_BUF_IS_IDLE;
vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
}
@@ -488,7 +488,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
else
vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
- vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
}
/* Clear host CRT status, so guest couldn't detect this host CRT. */
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index daac2050d77d..15393c861721 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -787,13 +787,15 @@ static int force_nonpriv_write(struct intel_vgpu *vgpu,
static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
+
write_vreg(vgpu, offset, p_data, bytes);
if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
} else {
vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
- if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
+ if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(i915, PORT_E)))
vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))
&= ~DP_TP_STATUS_AUTOTRAIN_DONE;
}
@@ -812,7 +814,8 @@ static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
static int fdi_auto_training_started(struct intel_vgpu *vgpu)
{
- u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));
+ struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
+ u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(i915, PORT_E));
u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));
@@ -2333,11 +2336,11 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
dp_aux_ch_ctl_mmio_write);
- MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
- MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
- MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
- MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
- MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
+ MMIO_DH(DDI_BUF_CTL(dev_priv, PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
+ MMIO_DH(DDI_BUF_CTL(dev_priv, PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
+ MMIO_DH(DDI_BUF_CTL(dev_priv, PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
+ MMIO_DH(DDI_BUF_CTL(dev_priv, PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
+ MMIO_DH(DDI_BUF_CTL(dev_priv, PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2126e441199d..a91bbc6e1255 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6936,7 +6936,11 @@ enum skl_power_gate {
/* DDI Buffer Control */
#define _DDI_BUF_CTL_A 0x64000
#define _DDI_BUF_CTL_B 0x64100
-#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
+#define DDI_BUF_CTL(i915, port) ({ \
+ (void)i915; /* Suppress unused variable warning */ \
+ _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B); \
+ })
+
#define DDI_BUF_CTL_ENABLE (1 << 31)
#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
#define DDI_BUF_EMP_MASK (0xf << 24)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 8279dc580a3e..b55bdc2cdd84 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -503,11 +503,11 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(SBI_CTL_STAT);
MMIO_D(PIXCLK_GATE);
MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4);
- MMIO_D(DDI_BUF_CTL(PORT_A));
- MMIO_D(DDI_BUF_CTL(PORT_B));
- MMIO_D(DDI_BUF_CTL(PORT_C));
- MMIO_D(DDI_BUF_CTL(PORT_D));
- MMIO_D(DDI_BUF_CTL(PORT_E));
+ MMIO_D(DDI_BUF_CTL(dev_priv, PORT_A));
+ MMIO_D(DDI_BUF_CTL(dev_priv, PORT_B));
+ MMIO_D(DDI_BUF_CTL(dev_priv, PORT_C));
+ MMIO_D(DDI_BUF_CTL(dev_priv, PORT_D));
+ MMIO_D(DDI_BUF_CTL(dev_priv, PORT_E));
MMIO_D(DP_TP_CTL(PORT_A));
MMIO_D(DP_TP_CTL(PORT_B));
MMIO_D(DP_TP_CTL(PORT_C));
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v6 2/7] drm/i915/display: Pass struct drm_i915_private to DDI_CLK_SEL macro
2022-10-04 12:53 [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 1/7] drm/i915/display: Pass struct drm_i915_private to DDI_BUF_CTL macro Balasubramani Vivekanandan
@ 2022-10-04 12:53 ` Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 3/7] drm/i915/display: Define the DDI port indices inside device info Balasubramani Vivekanandan
` (7 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Balasubramani Vivekanandan @ 2022-10-04 12:53 UTC (permalink / raw)
To: intel-gfx
DDI_CLK_SEL is an another macro which returns the register offset based
on DDI port enum. So DDI_CLK_SEL has to be prepared for the new method
being developed for calculating the register offsets of DDI ports.
Macro receives i915 private structure as new parameter for the upcoming
changes.
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 17 +++++++++--------
drivers/gpu/drm/i915/i915_reg.h | 5 ++++-
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 77a986696c76..e7beafafb857 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -305,7 +305,8 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
enum port port)
{
- u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
+ u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(dev_priv, port)) &
+ DDI_CLK_SEL_MASK;
switch (val) {
case DDI_CLK_SEL_NONE:
@@ -1656,7 +1657,7 @@ static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
* "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
* MG does not exist, but the programming is required to ungate DDIC and DDID."
*/
- intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
+ intel_de_write(i915, DDI_CLK_SEL(i915, port), DDI_CLK_SEL_MG);
icl_ddi_combo_enable_clock(encoder, crtc_state);
}
@@ -1668,7 +1669,7 @@ static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
icl_ddi_combo_disable_clock(encoder);
- intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
+ intel_de_write(i915, DDI_CLK_SEL(i915, port), DDI_CLK_SEL_NONE);
}
static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
@@ -1677,7 +1678,7 @@ static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
enum port port = encoder->port;
u32 tmp;
- tmp = intel_de_read(i915, DDI_CLK_SEL(port));
+ tmp = intel_de_read(i915, DDI_CLK_SEL(i915, port));
if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
return false;
@@ -1696,7 +1697,7 @@ static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
if (drm_WARN_ON(&i915->drm, !pll))
return;
- intel_de_write(i915, DDI_CLK_SEL(port),
+ intel_de_write(i915, DDI_CLK_SEL(i915, port),
icl_pll_to_ddi_clk_sel(encoder, crtc_state));
mutex_lock(&i915->display.dpll.lock);
@@ -1720,7 +1721,7 @@ static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
mutex_unlock(&i915->display.dpll.lock);
- intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
+ intel_de_write(i915, DDI_CLK_SEL(i915, port), DDI_CLK_SEL_NONE);
}
static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
@@ -1730,7 +1731,7 @@ static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
enum port port = encoder->port;
u32 tmp;
- tmp = intel_de_read(i915, DDI_CLK_SEL(port));
+ tmp = intel_de_read(i915, DDI_CLK_SEL(i915, port));
if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
return false;
@@ -1748,7 +1749,7 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode
enum intel_dpll_id id;
u32 tmp;
- tmp = intel_de_read(i915, DDI_CLK_SEL(port));
+ tmp = intel_de_read(i915, DDI_CLK_SEL(i915, port));
switch (tmp & DDI_CLK_SEL_MASK) {
case DDI_CLK_SEL_TBT_162:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a91bbc6e1255..acb764755338 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7075,7 +7075,10 @@ enum skl_power_gate {
#define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7)
/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
-#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
+#define DDI_CLK_SEL(i915, port) ({ \
+ (void)i915; /* Suppress unused variable warning */ \
+ PORT_CLK_SEL(port); \
+ })
#define DDI_CLK_SEL_MASK REG_GENMASK(31, 28)
#define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
#define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v6 3/7] drm/i915/display: Define the DDI port indices inside device info
2022-10-04 12:53 [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 1/7] drm/i915/display: Pass struct drm_i915_private to DDI_BUF_CTL macro Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 2/7] drm/i915/display: Pass struct drm_i915_private to DDI_CLK_SEL macro Balasubramani Vivekanandan
@ 2022-10-04 12:53 ` Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 4/7] drm/i915/display: Free port enums from tied to register offset Balasubramani Vivekanandan
` (6 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Balasubramani Vivekanandan @ 2022-10-04 12:53 UTC (permalink / raw)
To: intel-gfx
Prior to display version 12, platforms had DDI ports A,B,C,D,E,F
represented by enums PORT_A,PORT_B...PORT_F. The DDI register offsets of
the ports was in the same order as the ports. So the port enums
were directly used as index to calculate the register offset of the
ports.
Starting in display version 12, TypeC ports were introduced in the
platforms. These were defined as new enums PORT_TC1,PORT_TC2... The
later generation platforms had DDI register offests of TypeC and
non-TypeC ports interleaved and the existing port enums didn't match the
order of the DDI register offests. So the enums could no more be used as
index to calculate the register offest.
This led to the creation of new platform specific enums for the ports
like PORT_D_XELPD, PORT_E_XELPD to match the index of the ports in those
platforms and additional code to handle the special enums.
So we want to make the port enums not tied to DDI register offset and
use the index from somewhere else to calculate the register offsets.
The index of the DDI ports in the platform is now defined as part of
device info. This patch just adds the indices to the device info. Later
patches in the series use that index for offset calculation.
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 46 ++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 44 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 38460a0bd7cb..b37a95755b77 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -132,6 +132,42 @@
[PIPE_D] = TGL_CURSOR_D_OFFSET, \
}
+#define GEN75_DDI_INDEX \
+ .display.ddi_index = { \
+ [PORT_A] = 0, \
+ [PORT_B] = 1, \
+ [PORT_C] = 2, \
+ [PORT_D] = 3, \
+ [PORT_E] = 4, \
+ [PORT_F] = 5, \
+ }
+
+#define GEN12_DDI_INDEX \
+ .display.ddi_index = { \
+ [PORT_A] = 0, \
+ [PORT_B] = 1, \
+ [PORT_C] = 2, \
+ [PORT_TC1] = 3, \
+ [PORT_TC2] = 4, \
+ [PORT_TC3] = 5, \
+ [PORT_TC4] = 6, \
+ [PORT_TC5] = 7, \
+ [PORT_TC6] = 8, \
+ }
+
+#define XE_LPD_DDI_INDEX \
+ .display.ddi_index = { \
+ [PORT_A] = 0, \
+ [PORT_B] = 1, \
+ [PORT_C] = 2, \
+ [PORT_TC1] = 3, \
+ [PORT_TC2] = 4, \
+ [PORT_TC3] = 5, \
+ [PORT_TC4] = 6, \
+ [PORT_D_XELPD] = 7, \
+ [PORT_E_XELPD] = 8, \
+ }
+
#define I9XX_COLORS \
.display.color = { .gamma_lut_size = 256 }
#define I965_COLORS \
@@ -562,7 +598,8 @@ static const struct intel_device_info vlv_info = {
.display.has_dp_mst = 1, \
.has_rc6p = 0 /* RC6p removed-by HSW */, \
HSW_PIPE_OFFSETS, \
- .has_runtime_pm = 1
+ .has_runtime_pm = 1, \
+ GEN75_DDI_INDEX
#define HSW_PLATFORM \
G75_FEATURES, \
@@ -733,7 +770,8 @@ static const struct intel_device_info skl_gt4_info = {
IVB_CURSOR_OFFSETS, \
IVB_COLORS, \
GEN9_DEFAULT_PAGE_SIZES, \
- GEN_DEFAULT_REGIONS
+ GEN_DEFAULT_REGIONS, \
+ GEN75_DDI_INDEX
static const struct intel_device_info bxt_info = {
GEN9_LP_FEATURES,
@@ -887,6 +925,7 @@ static const struct intel_device_info jsl_info = {
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
TGL_CURSOR_OFFSETS, \
+ GEN12_DDI_INDEX, \
.has_global_mocs = 1, \
.has_pxp = 1, \
.display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */
@@ -984,7 +1023,8 @@ static const struct intel_device_info adl_s_info = {
[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
- TGL_CURSOR_OFFSETS
+ TGL_CURSOR_OFFSETS, \
+ XE_LPD_DDI_INDEX
static const struct intel_device_info adl_p_info = {
GEN12_FEATURES,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index bc87d3156b14..a93f54990a01 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -292,6 +292,7 @@ struct intel_device_info {
u32 pipe_offsets[I915_MAX_TRANSCODERS];
u32 trans_offsets[I915_MAX_TRANSCODERS];
u32 cursor_offsets[I915_MAX_PIPES];
+ u32 ddi_index[I915_MAX_PORTS];
struct {
u32 degamma_lut_size;
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v6 4/7] drm/i915/display: Free port enums from tied to register offset
2022-10-04 12:53 [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset Balasubramani Vivekanandan
` (2 preceding siblings ...)
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 3/7] drm/i915/display: Define the DDI port indices inside device info Balasubramani Vivekanandan
@ 2022-10-04 12:53 ` Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 5/7] drm/i915/display: Remove PORT_D_XELPD/PORT_E_XELPD platform specific defintions Balasubramani Vivekanandan
` (5 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Balasubramani Vivekanandan @ 2022-10-04 12:53 UTC (permalink / raw)
To: intel-gfx
With the index required for DDI register offset calculation available in
the device info, the macros which used port enums to calculate the DDI
register offsets i.e. DDI_BUF_CTL and DDI_CLK_SEL are updated to make
use of the index rather than enum directly.
Any new macros access that DDI registers should follow the same
procedure.
This would free the port enums from tied to the register offset of DDI
registers. We can remove all the enum aliases and clean up the enum
definitions.
The key target of the patch series to remove platform specific
definitions of ports like PORT_D_XELPD, PORT_E_XELPD is not yet covered
here.
The definitions are still retained and will be handled in the follow
patch.
Removed a WARN_ON as it is no longer valid. The WARN was added in the
commit "327f8d8c336d drm/i915: simplify setting of ddi_io_power_domain"
The ddi_io_power_domain calculation has changed completely since the
commit and doesn't need this WARN_ON anymore.
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 -
drivers/gpu/drm/i915/display/intel_display.h | 8 +++-----
drivers/gpu/drm/i915/i915_reg.h | 12 ++++--------
include/drm/i915_component.h | 2 +-
4 files changed, 8 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e7beafafb857..74b4271063d1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4493,7 +4493,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->update_complete = intel_ddi_update_complete;
}
- drm_WARN_ON(&dev_priv->drm, port > PORT_I);
dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port);
if (init_dp) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 2af4a1925063..9112833b39eb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -212,18 +212,16 @@ enum port {
PORT_H,
PORT_I,
- /* tgl+ */
- PORT_TC1 = PORT_D,
+ /* Non-TypeC ports must be defined above */
+ PORT_TC1,
PORT_TC2,
PORT_TC3,
PORT_TC4,
PORT_TC5,
PORT_TC6,
- /* XE_LPD repositions D/E offsets and bitfields */
- PORT_D_XELPD = PORT_TC5,
+ PORT_D_XELPD,
PORT_E_XELPD,
-
I915_MAX_PORTS
};
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index acb764755338..15e6b9482ee8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -170,6 +170,7 @@
#define _MMIO_CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
DISPLAY_MMIO_BASE(dev_priv) + (reg))
+#define _MMIO_DDI(i915, port, a, b) _MMIO_PORT(INTEL_INFO(i915)->display.ddi_index[port], a, b)
#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
#define _MASKED_FIELD(mask, value) ({ \
@@ -6936,10 +6937,7 @@ enum skl_power_gate {
/* DDI Buffer Control */
#define _DDI_BUF_CTL_A 0x64000
#define _DDI_BUF_CTL_B 0x64100
-#define DDI_BUF_CTL(i915, port) ({ \
- (void)i915; /* Suppress unused variable warning */ \
- _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B); \
- })
+#define DDI_BUF_CTL(i915, port) _MMIO_DDI(i915, port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
#define DDI_BUF_CTL_ENABLE (1 << 31)
#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
@@ -7075,10 +7073,8 @@ enum skl_power_gate {
#define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7)
/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
-#define DDI_CLK_SEL(i915, port) ({ \
- (void)i915; /* Suppress unused variable warning */ \
- PORT_CLK_SEL(port); \
- })
+#define DDI_CLK_SEL(i915, port) _MMIO_DDI(i915, port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
+
#define DDI_CLK_SEL_MASK REG_GENMASK(31, 28)
#define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
#define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index c1e2a43d2d1e..f95ff82c3b4a 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -35,7 +35,7 @@ enum i915_component_type {
/* MAX_PORT is the number of port
* It must be sync with I915_MAX_PORTS defined i915_drv.h
*/
-#define MAX_PORTS 9
+#define MAX_PORTS 17
/**
* struct i915_audio_component - Used for direct communication between i915 and hda drivers
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v6 5/7] drm/i915/display: Remove PORT_D_XELPD/PORT_E_XELPD platform specific defintions
2022-10-04 12:53 [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset Balasubramani Vivekanandan
` (3 preceding siblings ...)
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 4/7] drm/i915/display: Free port enums from tied to register offset Balasubramani Vivekanandan
@ 2022-10-04 12:53 ` Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 6/7] drm/i915/display: Fix port_identifier function Balasubramani Vivekanandan
` (4 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Balasubramani Vivekanandan @ 2022-10-04 12:53 UTC (permalink / raw)
To: intel-gfx
Port enums are no more used in the DDI register offset caculcation. We
can remove the platform specific port redefinitions. Along with it we
also get rid of the code required for handling these special
definitions.
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 23 +---------
drivers/gpu/drm/i915/display/intel_display.c | 6 +--
drivers/gpu/drm/i915/display/intel_display.h | 2 -
.../drm/i915/display/intel_display_power.c | 44 ++-----------------
drivers/gpu/drm/i915/i915_pci.c | 4 +-
include/drm/i915_component.h | 2 +-
7 files changed, 12 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 4c543e8205ca..ab472fa757d8 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2436,8 +2436,8 @@ static enum port dvo_port_to_port(struct drm_i915_private *i915,
[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
[PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
- [PORT_D_XELPD] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
- [PORT_E_XELPD] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
+ [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+ [PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
[PORT_TC1] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
[PORT_TC2] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
[PORT_TC3] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 },
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 74b4271063d1..0b6f884650d3 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4134,17 +4134,6 @@ static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
i915->hti_state & HDPORT_DDI_USED(phy);
}
-static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
- enum port port)
-{
- if (port >= PORT_D_XELPD)
- return HPD_PORT_D + port - PORT_D_XELPD;
- else if (port >= PORT_TC1)
- return HPD_PORT_TC1 + port - PORT_TC1;
- else
- return HPD_PORT_A + port - PORT_A;
-}
-
static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -4313,13 +4302,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder = &dig_port->base;
encoder->devdata = devdata;
- if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
- drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
- DRM_MODE_ENCODER_TMDS,
- "DDI %c/PHY %c",
- port_name(port - PORT_D_XELPD + PORT_D),
- phy_name(phy));
- } else if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
@@ -4449,9 +4432,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
intel_ddi_buf_trans_init(encoder);
- if (DISPLAY_VER(dev_priv) >= 13)
- encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);
- else if (IS_DG1(dev_priv))
+ if (IS_DG1(dev_priv))
encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
else if (IS_ROCKETLAKE(dev_priv))
encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8681055843f0..febe85a8a9c8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2135,9 +2135,7 @@ bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
- if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
- return PHY_D + port - PORT_D_XELPD;
- else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
+ if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
return PHY_F + port - PORT_TC1;
else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
return PHY_B + port - PORT_TC1;
@@ -7907,7 +7905,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
- intel_ddi_init(dev_priv, PORT_D_XELPD);
+ intel_ddi_init(dev_priv, PORT_D);
intel_ddi_init(dev_priv, PORT_TC1);
} else if (IS_ALDERLAKE_P(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 9112833b39eb..62604cadf0b8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -220,8 +220,6 @@ enum port {
PORT_TC5,
PORT_TC6,
- PORT_D_XELPD,
- PORT_E_XELPD,
I915_MAX_PORTS
};
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1e608b9e5055..d900d8051a82 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -2338,9 +2338,9 @@ static const struct intel_ddi_port_domains
d12_port_domains[] = {
{
.port_start = PORT_A,
- .port_end = PORT_C,
+ .port_end = PORT_E,
.aux_ch_start = AUX_CH_A,
- .aux_ch_end = AUX_CH_C,
+ .aux_ch_end = AUX_CH_E,
.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
@@ -2359,50 +2359,12 @@ d12_port_domains[] = {
},
};
-static const struct intel_ddi_port_domains
-d13_port_domains[] = {
- {
- .port_start = PORT_A,
- .port_end = PORT_C,
- .aux_ch_start = AUX_CH_A,
- .aux_ch_end = AUX_CH_C,
-
- .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
- .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
- .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
- .aux_tbt = POWER_DOMAIN_INVALID,
- }, {
- .port_start = PORT_TC1,
- .port_end = PORT_TC4,
- .aux_ch_start = AUX_CH_USBC1,
- .aux_ch_end = AUX_CH_USBC4,
-
- .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
- .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
- .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
- .aux_tbt = POWER_DOMAIN_AUX_TBT1,
- }, {
- .port_start = PORT_D_XELPD,
- .port_end = PORT_E_XELPD,
- .aux_ch_start = AUX_CH_D_XELPD,
- .aux_ch_end = AUX_CH_E_XELPD,
-
- .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D,
- .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D,
- .aux_legacy_usbc = POWER_DOMAIN_AUX_D,
- .aux_tbt = POWER_DOMAIN_INVALID,
- },
-};
-
static void
intel_port_domains_for_platform(struct drm_i915_private *i915,
const struct intel_ddi_port_domains **domains,
int *domains_size)
{
- if (DISPLAY_VER(i915) >= 13) {
- *domains = d13_port_domains;
- *domains_size = ARRAY_SIZE(d13_port_domains);
- } else if (DISPLAY_VER(i915) >= 12) {
+ if (DISPLAY_VER(i915) >= 12) {
*domains = d12_port_domains;
*domains_size = ARRAY_SIZE(d12_port_domains);
} else if (DISPLAY_VER(i915) >= 11) {
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b37a95755b77..45eafe447546 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -164,8 +164,8 @@
[PORT_TC2] = 4, \
[PORT_TC3] = 5, \
[PORT_TC4] = 6, \
- [PORT_D_XELPD] = 7, \
- [PORT_E_XELPD] = 8, \
+ [PORT_D] = 7, \
+ [PORT_E] = 8, \
}
#define I9XX_COLORS \
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index f95ff82c3b4a..4b31bab5533a 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -35,7 +35,7 @@ enum i915_component_type {
/* MAX_PORT is the number of port
* It must be sync with I915_MAX_PORTS defined i915_drv.h
*/
-#define MAX_PORTS 17
+#define MAX_PORTS 15
/**
* struct i915_audio_component - Used for direct communication between i915 and hda drivers
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v6 6/7] drm/i915/display: Fix port_identifier function
2022-10-04 12:53 [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset Balasubramani Vivekanandan
` (4 preceding siblings ...)
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 5/7] drm/i915/display: Remove PORT_D_XELPD/PORT_E_XELPD platform specific defintions Balasubramani Vivekanandan
@ 2022-10-04 12:53 ` Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 7/7] drm/i915/display: cleanup unused DDI port enums Balasubramani Vivekanandan
` (3 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Balasubramani Vivekanandan @ 2022-10-04 12:53 UTC (permalink / raw)
To: intel-gfx
port_identifier function was broken when TypeC ports were using enum
aliases. It would return wrong string for TypeC ports.
With unique enums for DDI ports now, fix port_identifier to cover all
ports.
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 62604cadf0b8..4a5f7df7492b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -250,6 +250,18 @@ static inline const char *port_identifier(enum port port)
return "Port H";
case PORT_I:
return "Port I";
+ case PORT_TC1:
+ return "Port TC1";
+ case PORT_TC2:
+ return "Port TC2";
+ case PORT_TC3:
+ return "Port TC3";
+ case PORT_TC4:
+ return "Port TC4";
+ case PORT_TC5:
+ return "Port TC5";
+ case PORT_TC6:
+ return "Port TC6";
default:
return "<invalid>";
}
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v6 7/7] drm/i915/display: cleanup unused DDI port enums
2022-10-04 12:53 [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset Balasubramani Vivekanandan
` (5 preceding siblings ...)
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 6/7] drm/i915/display: Fix port_identifier function Balasubramani Vivekanandan
@ 2022-10-04 12:53 ` Balasubramani Vivekanandan
2022-10-04 13:03 ` [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset Jani Nikula
` (2 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Balasubramani Vivekanandan @ 2022-10-04 12:53 UTC (permalink / raw)
To: intel-gfx
DDI port enums PORT_G/H/I were added in the commit -
"6c8337dafaa9 drm/i915/tgl: Add additional ports for Tiger Lake" to
identify new ports added in the platform.
In the subsequent commits those ports were identified by new enums
PORT_TC1/TC2/TC3.. to differentiate TypeC ports from non-TypeC.
However, the enum definitions PORT_G/H/I and few usages of these enums
were left as it is.
These enums are unused as of today and can be removed.
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 3 ---
drivers/gpu/drm/i915/display/intel_display.h | 9 ---------
include/drm/i915_component.h | 2 +-
3 files changed, 1 insertion(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index ab472fa757d8..b0dfb37e402a 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2404,9 +2404,6 @@ static enum port dvo_port_to_port(struct drm_i915_private *i915,
[PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
[PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT },
[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
- [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
- [PORT_H] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 },
- [PORT_I] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },
};
/*
* RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 4a5f7df7492b..5a55b9f43ce3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -208,9 +208,6 @@ enum port {
PORT_D,
PORT_E,
PORT_F,
- PORT_G,
- PORT_H,
- PORT_I,
/* Non-TypeC ports must be defined above */
PORT_TC1,
@@ -244,12 +241,6 @@ static inline const char *port_identifier(enum port port)
return "Port E";
case PORT_F:
return "Port F";
- case PORT_G:
- return "Port G";
- case PORT_H:
- return "Port H";
- case PORT_I:
- return "Port I";
case PORT_TC1:
return "Port TC1";
case PORT_TC2:
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 4b31bab5533a..335822d6960a 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -35,7 +35,7 @@ enum i915_component_type {
/* MAX_PORT is the number of port
* It must be sync with I915_MAX_PORTS defined i915_drv.h
*/
-#define MAX_PORTS 15
+#define MAX_PORTS 12
/**
* struct i915_audio_component - Used for direct communication between i915 and hda drivers
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset
2022-10-04 12:53 [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset Balasubramani Vivekanandan
` (6 preceding siblings ...)
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 7/7] drm/i915/display: cleanup unused DDI port enums Balasubramani Vivekanandan
@ 2022-10-04 13:03 ` Jani Nikula
2022-10-04 13:40 ` Balasubramani Vivekanandan
2022-10-04 13:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: Don't use port enum as register offset (rev8) Patchwork
2022-10-04 13:53 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
9 siblings, 1 reply; 12+ messages in thread
From: Jani Nikula @ 2022-10-04 13:03 UTC (permalink / raw)
To: Balasubramani Vivekanandan, intel-gfx
On Tue, 04 Oct 2022, Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> wrote:
> Prior to display version 12, platforms had DDI ports A,B,C,D,E,F
> represented by enums PORT_A,PORT_B...PORT_F. The DDI register offsets of
> the ports were in the same order as the ports. So the port enums
> were directly used as index to calculate the register offset of the
> ports.
> Starting in display version 12, TypeC ports were introduced in the
> platforms. These were defined as new enums PORT_TC1,PORT_TC2... The
> later generation platforms had DDI register offests of TypeC and
> non-TypeC ports interleaved and the existing port enums didn't match the
> order of the DDI register offests. So the enums could no more be used as
> index to calculate the register offest.
> This led to the creation of new platform specific enums for the ports
> like PORT_D_XELPD, PORT_E_XELPD to match the index of the ports in those
> platforms and additional code to handle the special enums.
>
> So we want to make the port enums not tied to DDI register offset and
> use the index from somewhere else to calculate the register offsets.
> The index of the DDI ports in the platform is now defined as part of
> device info.
>
> Series includes few patches at the end which does some cleanup and
> fixing made possible because of unique enums for the ports.
>
> v2: ddi_index defined for platforms starting from Gen75. Many platforms
> from Gen75 has ddi support.
> v3: Updated DDI_CLK_SEL macro to use new index for DDI register offset
> caculation.
> v4: After removing d13_port_domains array, d12_port_domains is used for
> all platforms with DISPLAY_VER 12 and above. So the port_end member had
> to fixed to extend it for ports D and E.
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Why do you keep sending several new versions within days when there's
been no replies to the previous ones?
BR,
Jani.
>
> Balasubramani Vivekanandan (7):
> drm/i915/display: Pass struct drm_i915_private to DDI_BUF_CTL macro
> drm/i915/display: Pass struct drm_i915_private to DDI_CLK_SEL macro
> drm/i915/display: Define the DDI port indices inside device info
> drm/i915/display: Free port enums from tied to register offset
> drm/i915/display: Remove PORT_D_XELPD/PORT_E_XELPD platform specific
> defintions
> drm/i915/display: Fix port_identifier function
> drm/i915/display: cleanup unused DDI port enums
>
> drivers/gpu/drm/i915/display/icl_dsi.c | 12 +--
> drivers/gpu/drm/i915/display/intel_bios.c | 7 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 80 ++++++++-----------
> drivers/gpu/drm/i915/display/intel_display.c | 12 +--
> drivers/gpu/drm/i915/display/intel_display.h | 29 ++++---
> .../drm/i915/display/intel_display_power.c | 44 +---------
> drivers/gpu/drm/i915/display/intel_fdi.c | 14 ++--
> drivers/gpu/drm/i915/display/intel_tc.c | 6 +-
> drivers/gpu/drm/i915/gvt/display.c | 30 +++----
> drivers/gpu/drm/i915/gvt/handlers.c | 17 ++--
> drivers/gpu/drm/i915/i915_pci.c | 46 ++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 7 +-
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 10 +--
> include/drm/i915_component.h | 2 +-
> 15 files changed, 153 insertions(+), 164 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: Don't use port enum as register offset (rev8)
2022-10-04 12:53 [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset Balasubramani Vivekanandan
` (7 preceding siblings ...)
2022-10-04 13:03 ` [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset Jani Nikula
@ 2022-10-04 13:37 ` Patchwork
2022-10-04 13:53 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
9 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-10-04 13:37 UTC (permalink / raw)
To: Balasubramani Vivekanandan; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: Don't use port enum as register offset (rev8)
URL : https://patchwork.freedesktop.org/series/108833/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset
2022-10-04 13:03 ` [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset Jani Nikula
@ 2022-10-04 13:40 ` Balasubramani Vivekanandan
0 siblings, 0 replies; 12+ messages in thread
From: Balasubramani Vivekanandan @ 2022-10-04 13:40 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 04.10.2022 16:03, Jani Nikula wrote:
> On Tue, 04 Oct 2022, Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> wrote:
> > Prior to display version 12, platforms had DDI ports A,B,C,D,E,F
> > represented by enums PORT_A,PORT_B...PORT_F. The DDI register offsets of
> > the ports were in the same order as the ports. So the port enums
> > were directly used as index to calculate the register offset of the
> > ports.
> > Starting in display version 12, TypeC ports were introduced in the
> > platforms. These were defined as new enums PORT_TC1,PORT_TC2... The
> > later generation platforms had DDI register offests of TypeC and
> > non-TypeC ports interleaved and the existing port enums didn't match the
> > order of the DDI register offests. So the enums could no more be used as
> > index to calculate the register offest.
> > This led to the creation of new platform specific enums for the ports
> > like PORT_D_XELPD, PORT_E_XELPD to match the index of the ports in those
> > platforms and additional code to handle the special enums.
> >
> > So we want to make the port enums not tied to DDI register offset and
> > use the index from somewhere else to calculate the register offsets.
> > The index of the DDI ports in the platform is now defined as part of
> > device info.
> >
> > Series includes few patches at the end which does some cleanup and
> > fixing made possible because of unique enums for the ports.
> >
> > v2: ddi_index defined for platforms starting from Gen75. Many platforms
> > from Gen75 has ddi support.
> > v3: Updated DDI_CLK_SEL macro to use new index for DDI register offset
> > caculation.
> > v4: After removing d13_port_domains array, d12_port_domains is used for
> > all platforms with DISPLAY_VER 12 and above. So the port_end member had
> > to fixed to extend it for ports D and E.
> >
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Why do you keep sending several new versions within days when there's
> been no replies to the previous ones?
>
> BR,
> Jani.
Apologies for the frequent revisions. These are to fix the CI failures.
I created v4 to fix few reported CI failures. When I further analyzed
the CI report, some failures which were suppressed saying results are
from untrusted machines, tests, or statuses were actually regressions.
So I had to create new revisions though BAT and IGT CI results were
successful.
I have fixed all the CI failures with the recent revision.
Regards,
Bala
>
>
> >
> > Balasubramani Vivekanandan (7):
> > drm/i915/display: Pass struct drm_i915_private to DDI_BUF_CTL macro
> > drm/i915/display: Pass struct drm_i915_private to DDI_CLK_SEL macro
> > drm/i915/display: Define the DDI port indices inside device info
> > drm/i915/display: Free port enums from tied to register offset
> > drm/i915/display: Remove PORT_D_XELPD/PORT_E_XELPD platform specific
> > defintions
> > drm/i915/display: Fix port_identifier function
> > drm/i915/display: cleanup unused DDI port enums
> >
> > drivers/gpu/drm/i915/display/icl_dsi.c | 12 +--
> > drivers/gpu/drm/i915/display/intel_bios.c | 7 +-
> > drivers/gpu/drm/i915/display/intel_ddi.c | 80 ++++++++-----------
> > drivers/gpu/drm/i915/display/intel_display.c | 12 +--
> > drivers/gpu/drm/i915/display/intel_display.h | 29 ++++---
> > .../drm/i915/display/intel_display_power.c | 44 +---------
> > drivers/gpu/drm/i915/display/intel_fdi.c | 14 ++--
> > drivers/gpu/drm/i915/display/intel_tc.c | 6 +-
> > drivers/gpu/drm/i915/gvt/display.c | 30 +++----
> > drivers/gpu/drm/i915/gvt/handlers.c | 17 ++--
> > drivers/gpu/drm/i915/i915_pci.c | 46 ++++++++++-
> > drivers/gpu/drm/i915/i915_reg.h | 7 +-
> > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 10 +--
> > include/drm/i915_component.h | 2 +-
> > 15 files changed, 153 insertions(+), 164 deletions(-)
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Don't use port enum as register offset (rev8)
2022-10-04 12:53 [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset Balasubramani Vivekanandan
` (8 preceding siblings ...)
2022-10-04 13:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: Don't use port enum as register offset (rev8) Patchwork
@ 2022-10-04 13:53 ` Patchwork
9 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-10-04 13:53 UTC (permalink / raw)
To: Balasubramani Vivekanandan; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 13122 bytes --]
== Series Details ==
Series: drm/i915/display: Don't use port enum as register offset (rev8)
URL : https://patchwork.freedesktop.org/series/108833/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12211 -> Patchwork_108833v8
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_108833v8 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108833v8, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/index.html
Participating hosts (31 -> 44)
------------------------------
Additional (15): fi-bxt-dsi bat-dg1-5 bat-dg2-8 bat-adlm-1 bat-dg2-9 bat-adlp-6 bat-adlp-4 fi-hsw-4770 bat-adln-1 bat-jsl-3 bat-rplp-1 bat-rpls-1 bat-rpls-2 bat-dg2-11 bat-jsl-1
Missing (2): fi-bdw-samus fi-hsw-4200u
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_108833v8:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@load:
- bat-adlp-4: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-adlp-4/igt@i915_module_load@load.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@load:
- {bat-rpls-1}: NOTRUN -> [DMESG-WARN][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-rpls-1/igt@i915_module_load@load.html
- {bat-adln-1}: NOTRUN -> [INCOMPLETE][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-adln-1/igt@i915_module_load@load.html
- {bat-rplp-1}: NOTRUN -> [INCOMPLETE][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-rplp-1/igt@i915_module_load@load.html
- {bat-rpls-2}: NOTRUN -> [DMESG-WARN][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-rpls-2/igt@i915_module_load@load.html
- {bat-adlp-6}: NOTRUN -> [INCOMPLETE][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-adlp-6/igt@i915_module_load@load.html
- {bat-adlm-1}: NOTRUN -> [INCOMPLETE][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-adlm-1/igt@i915_module_load@load.html
Known issues
------------
Here are the changes found in Patchwork_108833v8 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@nullptr:
- bat-dg1-5: NOTRUN -> [SKIP][8] ([i915#2582]) +4 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@fbdev@nullptr.html
* igt@gem_huc_copy@huc-copy:
- fi-bxt-dsi: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/fi-bxt-dsi/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-bxt-dsi: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/fi-bxt-dsi/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_mmap@basic:
- bat-dg1-5: NOTRUN -> [SKIP][11] ([i915#4083])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@gem_mmap@basic.html
* igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770: NOTRUN -> [SKIP][12] ([fdo#109271]) +9 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/fi-hsw-4770/igt@gem_softpin@allocator-basic-reserve.html
* igt@gem_tiled_blits@basic:
- fi-bxt-dsi: NOTRUN -> [SKIP][13] ([fdo#109271]) +12 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/fi-bxt-dsi/igt@gem_tiled_blits@basic.html
- bat-dg1-5: NOTRUN -> [SKIP][14] ([i915#4077]) +2 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-5: NOTRUN -> [SKIP][15] ([i915#4079]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@gem_tiled_pread_basic.html
* igt@i915_module_load@load:
- fi-adl-ddr5: [PASS][16] -> [INCOMPLETE][17] ([i915#1982])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12211/fi-adl-ddr5/igt@i915_module_load@load.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/fi-adl-ddr5/igt@i915_module_load@load.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3012])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/fi-hsw-4770/igt@i915_pm_backlight@basic-brightness.html
- bat-dg1-5: NOTRUN -> [SKIP][19] ([i915#1155])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-5: NOTRUN -> [SKIP][20] ([i915#6621])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@i915_pm_rps@basic-api.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][21] ([i915#4212]) +7 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][22] ([i915#4215])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_busy@basic:
- bat-dg1-5: NOTRUN -> [SKIP][23] ([i915#1845] / [i915#4303])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@kms_busy@basic.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770: NOTRUN -> [SKIP][24] ([fdo#109271] / [fdo#111827]) +8 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/fi-hsw-4770/igt@kms_chamelium@dp-crc-fast.html
- bat-dg1-5: NOTRUN -> [SKIP][25] ([fdo#111827]) +8 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-bxt-dsi: NOTRUN -> [SKIP][26] ([fdo#109271] / [fdo#111827]) +8 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/fi-bxt-dsi/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-5: NOTRUN -> [SKIP][27] ([fdo#109285])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@nonblocking-crc:
- bat-dg1-5: NOTRUN -> [SKIP][28] ([i915#4078]) +14 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@kms_pipe_crc_basic@nonblocking-crc.html
* igt@kms_psr@primary_page_flip:
- bat-dg1-5: NOTRUN -> [SKIP][29] ([i915#1072] / [i915#4078]) +3 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@kms_psr@primary_page_flip.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#1072]) +3 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-5: NOTRUN -> [SKIP][31] ([i915#3555])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg1-5: NOTRUN -> [SKIP][32] ([i915#1845] / [i915#3708])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-read:
- bat-dg1-5: NOTRUN -> [SKIP][33] ([i915#3708]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- bat-dg1-5: NOTRUN -> [SKIP][34] ([i915#3708] / [i915#4077]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-userptr:
- bat-dg1-5: NOTRUN -> [SKIP][35] ([i915#3708] / [i915#4873])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-dg1-5/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][36] ([i915#4312])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/bat-adlp-4/igt@runner@aborted.html
- fi-adl-ddr5: NOTRUN -> [FAIL][37] ([i915#4312])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/fi-adl-ddr5/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4303]: https://gitlab.freedesktop.org/drm/intel/issues/4303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6641]: https://gitlab.freedesktop.org/drm/intel/issues/6641
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6816]: https://gitlab.freedesktop.org/drm/intel/issues/6816
[i915#6856]: https://gitlab.freedesktop.org/drm/intel/issues/6856
Build changes
-------------
* Linux: CI_DRM_12211 -> Patchwork_108833v8
CI-20190529: 20190529
CI_DRM_12211: d61e57aeb3588986411150a834f08edeb3344bb1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6676: 4730ad6fa95e74b30a7c7acff7041b591e6ce276 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108833v8: d61e57aeb3588986411150a834f08edeb3344bb1 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
71d7dc4c5b09 drm/i915/display: cleanup unused DDI port enums
14a755f0bde3 drm/i915/display: Fix port_identifier function
f547063d4974 drm/i915/display: Remove PORT_D_XELPD/PORT_E_XELPD platform specific defintions
755d34b08a6f drm/i915/display: Free port enums from tied to register offset
68c5065a686c drm/i915/display: Define the DDI port indices inside device info
1ce944b7d477 drm/i915/display: Pass struct drm_i915_private to DDI_CLK_SEL macro
320528e22515 drm/i915/display: Pass struct drm_i915_private to DDI_BUF_CTL macro
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108833v8/index.html
[-- Attachment #2: Type: text/html, Size: 14753 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-10-04 13:54 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-10-04 12:53 [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 1/7] drm/i915/display: Pass struct drm_i915_private to DDI_BUF_CTL macro Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 2/7] drm/i915/display: Pass struct drm_i915_private to DDI_CLK_SEL macro Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 3/7] drm/i915/display: Define the DDI port indices inside device info Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 4/7] drm/i915/display: Free port enums from tied to register offset Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 5/7] drm/i915/display: Remove PORT_D_XELPD/PORT_E_XELPD platform specific defintions Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 6/7] drm/i915/display: Fix port_identifier function Balasubramani Vivekanandan
2022-10-04 12:53 ` [Intel-gfx] [PATCH v6 7/7] drm/i915/display: cleanup unused DDI port enums Balasubramani Vivekanandan
2022-10-04 13:03 ` [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset Jani Nikula
2022-10-04 13:40 ` Balasubramani Vivekanandan
2022-10-04 13:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: Don't use port enum as register offset (rev8) Patchwork
2022-10-04 13:53 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox