Re: [Intel-gfx] [PATCH 6/7] drm/i915/hwmon: Expose power1_max_interval

["Dixit, Ashutosh" <ashutosh.dixit@intel.com>]

On Thu, 22 Sep 2022 19:51:45 -0700, Dixit, Ashutosh wrote:
>
> On Thu, 22 Sep 2022 00:13:00 -0700, Gupta, Anshuman wrote:
> >
>
> Hi Anshuman,
>
> > > +static ssize_t
> > > +hwm_power1_max_interval_store(struct device *dev,
> > > +			      struct device_attribute *attr,
> > > +			      const char *buf, size_t count)
> > > +{
> > > +	struct hwm_drvdata *ddat = dev_get_drvdata(dev);
> > > +	struct i915_hwmon *hwmon = ddat->hwmon;
> > > +	long val, max_win, ret;
> > > +	u32 x, y, rxy, x_w = 2; /* 2 bits */
> > > +	u64 tau4, r;
> > > +
> > > +#define PKG_MAX_WIN_DEFAULT 0x12ull
> > > +
> > > +	ret = kstrtoul(buf, 0, &val);
> > > +	if (ret)
> > > +		return ret;
> > > +
> > > +	/*
> > > +	 * val must be < max in hwmon interface units. The steps below are
> > > +	 * explained in i915_power1_max_interval_show()
> > > +	 */
> > > +	r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
> >
> > AFAIU we need to read r from PACKAGE_POWER_SKU reg untill unless it has
> > some known issue?
>
> The platform on which I tried had an incorrect value (that is why I didn't
> read it from PACKAGE_POWER_SKU) but let me investigate it some more for
> other platforms and get back.

I checked, the value is correct on DG1/DG2 which have a valid
PACKAGE_POWER_SKU (XEHPSDV does not have a valid
PACKAGE_POWER_SKU). Therefore the one line above should be replaced with
the code below:

	if (i915_mmio_reg_valid(hwmon->rg.pkg_power_sku))
		with_intel_runtime_pm(ddat->uncore->rpm, wakeref)
			r = intel_uncore_read64(ddat->uncore, hwmon->rg.pkg_power_sku);
	else
		r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);

> > > +	x = REG_FIELD_GET(PKG_MAX_WIN_X, r);
> > > +	y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);
> > > +	tau4 = ((1 << x_w) | x) << y;
> > > +	max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
> > > +
> > > +	if (val > max_win)
> > > +		return -EINVAL;
> > > +
> > > +	/* val in hw units */
> > > +	val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);
> > > +	/* Convert to 1.x * power(2,y) */
> > > +	if (!val)
> > > +		return -EINVAL;
> > > +	y = ilog2(val);
> > > +	/* x = (val - (1 << y)) >> (y - 2); */
> > > +	x = (val - (1ul << y)) << x_w >> y;
> > > +
> > > +	rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
> > > +
> > > +	hwm_locked_with_pm_intel_uncore_rmw(ddat, hwmon->rg.pkg_rapl_limit,
> > > +					    PKG_PWR_LIM_1_TIME, rxy);
> > > +	return count;
> > > +}
> > > +
> > /snip
> > >	if (IS_ERR(hwmon_dev)) {
> > >		mutex_destroy(&hwmon->hwmon_lock);
> > >		i915->hwmon = NULL;
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 956e5298ef1e..68e7cc85dc53 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -1811,6 +1811,9 @@
> > >    * *_PACKAGE_POWER_SKU - SKU power and timing parameters.
> > >    */
> > >   #define   PKG_PKG_TDP			GENMASK_ULL(14, 0)
> > > +#define   PKG_MAX_WIN			GENMASK_ULL(54, 48)
> > > +#define     PKG_MAX_WIN_X		GENMASK_ULL(54, 53)
> > > +#define     PKG_MAX_WIN_Y		GENMASK_ULL(52, 48)
> > These GENMASK fields needs a reg definition.
>
> Yes this is the same _PACKAGE_POWER_SKU register so should get fixed when
> we add it in Patch 3.

Looks like PCU_PACKAGE_POWER_SKU for DG1/DG2 will need to be declared in
intel_mchbar_regs.h so these fields will need to also move there (in
Patch 3).

Thanks.
--
Ashutosh