[PATCH] drm/i915/display: Add WA_14018221282

[PATCH] drm/i915/display: Add WA_14018221282

[Nemesa Garg]

It was observed that the first write to DKL DP Mode register
was not taking effect, hence rewrite this register.

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Signed-off-by: Kulkarni, Vandita <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 769bd1f26db2..16a1d18f3aa1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2104,6 +2104,16 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 	encoder->disable_clock(encoder);
 }
 
+static void
+tgl_wa_14018221282(struct drm_i915_private *dev_priv, enum tc_port tc_port,
+		   u32 ln0, u32 ln1)
+{
+	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
+		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
+	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
+		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+}
+
 static void
 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 		       const struct intel_crtc_state *crtc_state)
@@ -2185,6 +2195,10 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 	if (DISPLAY_VER(dev_priv) >= 12) {
 		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
 		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+		 /* WA_14018221282 */
+		if (DISPLAY_VER(dev_priv) == 12)
+			tgl_wa_14018221282(dev_priv, tc_port, ln0, ln1);
+
 	} else {
 		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
 		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
-- 
2.25.1

RE: [PATCH] drm/i915/display: Add WA_14018221282

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Nemesa Garg
> Sent: 08 November 2024 13:31
> To: intel-gfx@lists.freedesktop.org
> Cc: Garg, Nemesa <nemesa.garg@intel.com>; Kulkarni@freedesktop.org;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Subject: [PATCH] drm/i915/display: Add WA_14018221282
> 
> It was observed that the first write to DKL DP Mode register was not taking
> effect, hence rewrite this register.
> 
> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> Signed-off-by: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 769bd1f26db2..16a1d18f3aa1 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2104,6 +2104,16 @@ void
> intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
>  	encoder->disable_clock(encoder);
>  }
> 
> +static void
> +tgl_wa_14018221282(struct drm_i915_private *dev_priv, enum tc_port
> tc_port,

1. I recommend, Need to think on naming here, as doesn't clarify on anything.
2. Also adding on thought to have pre-check of return if values are already updated.

> +		   u32 ln0, u32 ln1)
> +{
> +	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
> +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0),
> ln0);
> +	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
> +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1),
> ln1); }
> +
>  static void
>  icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>  		       const struct intel_crtc_state *crtc_state) @@ -2185,6
> +2195,10 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>  	if (DISPLAY_VER(dev_priv) >= 12) {
>  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0),
> ln0);
>  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1),
> ln1);
> +		 /* WA_14018221282 */
> +		if (DISPLAY_VER(dev_priv) == 12)
> +			tgl_wa_14018221282(dev_priv, tc_port, ln0, ln1);

Always use the display local var when possible. DISPLAY_VER(display)

> +
>  	} else {
>  		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
>  		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
> --
> 2.25.1

RE: [PATCH] drm/i915/display: Add WA_14018221282

[Garg, Nemesa]

> -----Original Message-----
> From: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>
> Sent: Friday, November 8, 2024 1:47 PM
> To: Garg, Nemesa <nemesa.garg@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Garg, Nemesa <nemesa.garg@intel.com>; Kulkarni@freedesktop.org;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Subject: RE: [PATCH] drm/i915/display: Add WA_14018221282
> 
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Nemesa Garg
> > Sent: 08 November 2024 13:31
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Garg, Nemesa <nemesa.garg@intel.com>; Kulkarni@freedesktop.org;
> > Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > Subject: [PATCH] drm/i915/display: Add WA_14018221282
> >
> > It was observed that the first write to DKL DP Mode register was not
> > taking effect, hence rewrite this register.
> >
> > Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> > Signed-off-by: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 769bd1f26db2..16a1d18f3aa1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -2104,6 +2104,16 @@ void
> > intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
> >  	encoder->disable_clock(encoder);
> >  }
> >
> > +static void
> > +tgl_wa_14018221282(struct drm_i915_private *dev_priv, enum tc_port
> > tc_port,
> 
> 1. I recommend, Need to think on naming here, as doesn't clarify on anything.
Sure will rename it.
> 2. Also adding on thought to have pre-check of return if values are already
> updated.
I guess return is not required because before writing the values I am checking whether
values are updated or not, then only writing the values.
> 
> > +		   u32 ln0, u32 ln1)
> > +{
> > +	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
> > +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0),
> > ln0);
> > +	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
> > +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1),
> > ln1); }
> > +
> >  static void
> >  icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
> >  		       const struct intel_crtc_state *crtc_state) @@ -2185,6
> > +2195,10 @@ icl_program_mg_dp_mode(struct intel_digital_port
> > +*dig_port,
> >  	if (DISPLAY_VER(dev_priv) >= 12) {
> >  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
> >  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
> > +		 /* WA_14018221282 */
> > +		if (DISPLAY_VER(dev_priv) == 12)
> > +			tgl_wa_14018221282(dev_priv, tc_port, ln0, ln1);
> 
> Always use the display local var when possible. DISPLAY_VER(display)
Sure will do.
> 
> > +
> >  	} else {
> >  		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
> >  		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
> > --
> > 2.25.1

RE: [PATCH] drm/i915/display: Add WA_14018221282

[Jani Nikula]

On Fri, 08 Nov 2024, "Golani, Mitulkumar Ajitkumar" <mitulkumar.ajitkumar.golani@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
>> Nemesa Garg
>> Sent: 08 November 2024 13:31
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Garg, Nemesa <nemesa.garg@intel.com>; Kulkarni@freedesktop.org;
>> Kulkarni, Vandita <vandita.kulkarni@intel.com>
>> Subject: [PATCH] drm/i915/display: Add WA_14018221282
>> 
>> It was observed that the first write to DKL DP Mode register was not taking
>> effect, hence rewrite this register.
>> 
>> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
>> Signed-off-by: Kulkarni, Vandita <vandita.kulkarni@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_ddi.c | 14 ++++++++++++++
>>  1 file changed, 14 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>> b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index 769bd1f26db2..16a1d18f3aa1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -2104,6 +2104,16 @@ void
>> intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
>>  	encoder->disable_clock(encoder);
>>  }
>> 
>> +static void
>> +tgl_wa_14018221282(struct drm_i915_private *dev_priv, enum tc_port
>> tc_port,
>
> 1. I recommend, Need to think on naming here, as doesn't clarify on anything.

Yes please everyone stop with the madness of naming functions
bla_bla_wa_124235432().

BR,
Jani.


> 2. Also adding on thought to have pre-check of return if values are already updated.
>
>> +		   u32 ln0, u32 ln1)
>> +{
>> +	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
>> +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0),
>> ln0);
>> +	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
>> +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1),
>> ln1); }
>> +
>>  static void
>>  icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>>  		       const struct intel_crtc_state *crtc_state) @@ -2185,6
>> +2195,10 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>>  	if (DISPLAY_VER(dev_priv) >= 12) {
>>  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0),
>> ln0);
>>  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1),
>> ln1);
>> +		 /* WA_14018221282 */
>> +		if (DISPLAY_VER(dev_priv) == 12)
>> +			tgl_wa_14018221282(dev_priv, tc_port, ln0, ln1);
>
> Always use the display local var when possible. DISPLAY_VER(display)
>
>> +
>>  	} else {
>>  		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
>>  		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
>> --
>> 2.25.1
>

-- 
Jani Nikula, Intel

✗ Fi.CI.BAT: failure for drm/i915/display: Add WA_14018221282

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 11485 bytes --]

== Series Details ==

Series: drm/i915/display: Add WA_14018221282
URL   : https://patchwork.freedesktop.org/series/141087/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_15656 -> Patchwork_141087v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_141087v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_141087v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/index.html

Participating hosts (44 -> 44)
------------------------------

  Additional (1): bat-arls-5 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_141087v1:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_dsc@dsc-basic:
    - bat-arls-5:         NOTRUN -> [SKIP][1] +16 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@kms_dsc@dsc-basic.html

  
Known issues
------------

  Here are the changes found in Patchwork_141087v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-arls-5:         NOTRUN -> [SKIP][2] ([i915#9318])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@debugfs_test@basic-hwmon.html

  * igt@fbdev@eof:
    - bat-arls-5:         NOTRUN -> [SKIP][3] ([i915#11191] / [i915#11345]) +3 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@fbdev@eof.html

  * igt@fbdev@info:
    - bat-arls-5:         NOTRUN -> [SKIP][4] ([i915#1849])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@fbdev@info.html

  * igt@gem_lmem_swapping@basic:
    - bat-arls-5:         NOTRUN -> [SKIP][5] ([i915#10213] / [i915#11671]) +3 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@gem_lmem_swapping@basic.html

  * igt@gem_mmap@basic:
    - bat-arls-5:         NOTRUN -> [SKIP][6] ([i915#11343] / [i915#4083])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@gem_mmap@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-arls-5:         NOTRUN -> [SKIP][7] ([i915#10197] / [i915#10211] / [i915#4079])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@gem_render_tiled_blits@basic.html

  * igt@gem_tiled_blits@basic:
    - bat-arls-5:         NOTRUN -> [SKIP][8] ([i915#12637] / [i915#4077]) +2 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@gem_tiled_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-arls-5:         NOTRUN -> [SKIP][9] ([i915#10206] / [i915#4079])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-arls-5:         NOTRUN -> [SKIP][10] ([i915#10209] / [i915#11681])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live:
    - bat-arlh-3:         [PASS][11] -> [ABORT][12] ([i915#10341] / [i915#12061])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15656/bat-arlh-3/igt@i915_selftest@live.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arlh-3/igt@i915_selftest@live.html

  * igt@i915_selftest@live@gt_heartbeat:
    - bat-arls-5:         NOTRUN -> [DMESG-WARN][13] ([i915#12727]) +33 other tests dmesg-warn
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_mocs:
    - bat-arls-5:         NOTRUN -> [DMESG-WARN][14] ([i915#10341] / [i915#12727])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@sanitycheck:
    - bat-arls-5:         NOTRUN -> [DMESG-WARN][15] ([i915#10341]) +6 other tests dmesg-warn
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@i915_selftest@live@sanitycheck.html

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-3:         [PASS][16] -> [ABORT][17] ([i915#12061])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15656/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arlh-3/igt@i915_selftest@live@workarounds.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-arls-5:         NOTRUN -> [SKIP][18] ([i915#10200] / [i915#12203])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@clobberred-modifier:
    - bat-arls-5:         NOTRUN -> [SKIP][19] ([i915#10200]) +8 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@kms_addfb_basic@clobberred-modifier.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - bat-arls-5:         NOTRUN -> [SKIP][20] ([i915#3637]) +3 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@kms_flip@basic-flip-vs-wf_vblank.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-arls-5:         NOTRUN -> [SKIP][21] ([i915#10207])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_frontbuffer_tracking@basic:
    - bat-arls-5:         NOTRUN -> [SKIP][22] ([i915#4342] / [i915#5354])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-arls-5:         NOTRUN -> [SKIP][23] ([i915#9812])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr-primary-page-flip:
    - bat-arls-5:         NOTRUN -> [SKIP][24] ([i915#9732]) +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-arls-5:         NOTRUN -> [SKIP][25] ([i915#10208] / [i915#8809])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-arls-5:         NOTRUN -> [SKIP][26] ([i915#3708])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-read:
    - bat-arls-5:         NOTRUN -> [SKIP][27] ([i915#10212] / [i915#3708])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-gtt:
    - bat-arls-5:         NOTRUN -> [SKIP][28] ([i915#12637] / [i915#3708] / [i915#4077]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@prime_vgem@basic-gtt.html

  * igt@prime_vgem@basic-read:
    - bat-arls-5:         NOTRUN -> [SKIP][29] ([i915#10214] / [i915#3708])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@basic-write:
    - bat-arls-5:         NOTRUN -> [SKIP][30] ([i915#10216] / [i915#3708])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-arls-5/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [ABORT][31] ([i915#12061]) -> [PASS][32] +1 other test pass
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15656/bat-mtlp-8/igt@i915_selftest@live.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/bat-mtlp-8/igt@i915_selftest@live.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10197
  [i915#10200]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10200
  [i915#10206]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10206
  [i915#10207]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10207
  [i915#10208]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10208
  [i915#10209]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10209
  [i915#10211]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10211
  [i915#10212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10212
  [i915#10213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10213
  [i915#10214]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10214
  [i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
  [i915#10341]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10341
  [i915#11191]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11191
  [i915#11343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11343
  [i915#11345]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11345
  [i915#11671]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11671
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12203]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12203
  [i915#12637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12637
  [i915#12727]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12727
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4342]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4342
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
  [i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812


Build changes
-------------

  * Linux: CI_DRM_15656 -> Patchwork_141087v1

  CI-20190529: 20190529
  CI_DRM_15656: 5f445c6723de9ac7087170f4ee8fcb2050ab8346 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8100: 84e42580f918da926481fd2fb37be01451d6ee9a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_141087v1: 5f445c6723de9ac7087170f4ee8fcb2050ab8346 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141087v1/index.html

[-- Attachment #2: Type: text/html, Size: 13765 bytes --]

[PATCH] drm/i915/display: Add WA_14018221282

[Nemesa Garg]

It was observed that the first write to DKL PHY DP Mode
register was not taking effect, hence rewrite this register.

v2: Rename function [Mitul]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Signed-off-by: Kulkarni, Vandita <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 769bd1f26db2..f955d89951b8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2104,10 +2104,21 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 	encoder->disable_clock(encoder);
 }
 
+static void
+tgl_is_dp_mode_enabled(struct drm_i915_private *dev_priv,
+		       enum tc_port tc_port, u32 ln0, u32 ln1)
+{
+	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
+		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
+	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
+		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+}
+
 static void
 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 		       const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
 	u32 ln0, ln1, pin_assignment;
@@ -2185,6 +2196,10 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 	if (DISPLAY_VER(dev_priv) >= 12) {
 		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
 		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+		 /* WA_14018221282 */
+		if (DISPLAY_VER(display) == 12)
+			tgl_is_dp_mode_enabled(dev_priv, tc_port, ln0, ln1);
+
 	} else {
 		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
 		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
-- 
2.25.1

Re: [PATCH] drm/i915/display: Add WA_14018221282

[Jani Nikula]

On Mon, 11 Nov 2024, Nemesa Garg <nemesa.garg@intel.com> wrote:
> It was observed that the first write to DKL PHY DP Mode
> register was not taking effect, hence rewrite this register.
>
> v2: Rename function [Mitul]
>
> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> Signed-off-by: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 769bd1f26db2..f955d89951b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2104,10 +2104,21 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
>  	encoder->disable_clock(encoder);
>  }
>  
> +static void
> +tgl_is_dp_mode_enabled(struct drm_i915_private *dev_priv,
> +		       enum tc_port tc_port, u32 ln0, u32 ln1)

I went ahead and asked ChatGPT what it thinks of the function name:

If a function's name is tgl_is_dp_mode_enabled(), do you expect it to
return a value, and what would you expect it to return?


It replied:

Yes, based on the function's name, I would expect
`tgl_is_dp_mode_enabled()` to return a value. The naming convention
suggests that it checks whether "DP mode" (perhaps "DisplayPort mode")
is enabled and returns a Boolean value (`true` or `false`).

In this context:

- `tgl_` might be a prefix denoting a specific category or module (e.g.,
  "toggle" or "Tiger Lake" if it's hardware-specific).

- `is_` implies a question, typical of Boolean-returning functions.

- `dp_mode_enabled` likely refers to a state or condition ("DisplayPort
  mode enabled" in this case).

So, I would expect `tgl_is_dp_mode_enabled()` to return `true` if DP
mode is currently enabled, and `false` otherwise.


> +{
> +	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
> +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
> +	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
> +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
> +}
> +
>  static void
>  icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>  		       const struct intel_crtc_state *crtc_state)
>  {
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>  	enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
>  	u32 ln0, ln1, pin_assignment;
> @@ -2185,6 +2196,10 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>  	if (DISPLAY_VER(dev_priv) >= 12) {
>  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
>  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
> +		 /* WA_14018221282 */
> +		if (DISPLAY_VER(display) == 12)
> +			tgl_is_dp_mode_enabled(dev_priv, tc_port, ln0, ln1);
> +
>  	} else {
>  		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
>  		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);

-- 
Jani Nikula, Intel

RE: [PATCH] drm/i915/display: Add WA_14018221282

[Garg, Nemesa]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Monday, November 11, 2024 2:03 PM
> To: Garg, Nemesa <nemesa.garg@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Garg, Nemesa <nemesa.garg@intel.com>; Kulkarni@freedesktop.org;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Subject: Re: [PATCH] drm/i915/display: Add WA_14018221282
> 
> On Mon, 11 Nov 2024, Nemesa Garg <nemesa.garg@intel.com> wrote:
> > It was observed that the first write to DKL PHY DP Mode register was
> > not taking effect, hence rewrite this register.
> >
> > v2: Rename function [Mitul]
> >
> > Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> > Signed-off-by: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 15 +++++++++++++++
> >  1 file changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 769bd1f26db2..f955d89951b8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -2104,10 +2104,21 @@ void
> intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
> >  	encoder->disable_clock(encoder);
> >  }
> >
> > +static void
> > +tgl_is_dp_mode_enabled(struct drm_i915_private *dev_priv,
> > +		       enum tc_port tc_port, u32 ln0, u32 ln1)
> 
> I went ahead and asked ChatGPT what it thinks of the function name:
> 
> If a function's name is tgl_is_dp_mode_enabled(), do you expect it to return a
> value, and what would you expect it to return?
> 
> 
> It replied:
> 
> Yes, based on the function's name, I would expect `tgl_is_dp_mode_enabled()` to
> return a value. The naming convention suggests that it checks whether "DP
> mode" (perhaps "DisplayPort mode") is enabled and returns a Boolean value
> (`true` or `false`).
> 
> In this context:
> 
> - `tgl_` might be a prefix denoting a specific category or module (e.g.,
>   "toggle" or "Tiger Lake" if it's hardware-specific).
> 
> - `is_` implies a question, typical of Boolean-returning functions.
> 
> - `dp_mode_enabled` likely refers to a state or condition ("DisplayPort
>   mode enabled" in this case).
> 
> So, I would expect `tgl_is_dp_mode_enabled()` to return `true` if DP mode is
> currently enabled, and `false` otherwise.
> 
> I will try to come up with some better name. Here if first write fails only then need to re-write the 
register again so don't need to return any value.
Something like icl_dkl_phy_read will be fine?

Thanks and Regard,
Nemesa
> > 
> > +	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
> > +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
> > +	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
> > +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); }
> > +
> >  static void
> >  icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
> >  		       const struct intel_crtc_state *crtc_state)  {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> >  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> >  	enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
> >  	u32 ln0, ln1, pin_assignment;
> > @@ -2185,6 +2196,10 @@ icl_program_mg_dp_mode(struct intel_digital_port
> *dig_port,
> >  	if (DISPLAY_VER(dev_priv) >= 12) {
> >  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
> >  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
> > +		 /* WA_14018221282 */
> > +		if (DISPLAY_VER(display) == 12)
> > +			tgl_is_dp_mode_enabled(dev_priv, tc_port, ln0, ln1);
> > +
> >  	} else {
> >  		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
> >  		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
> 
> --
> Jani Nikula, Intel

[PATCH] drm/i915/display: Add WA_14018221282

[Nemesa Garg]

It was observed that the first write to DKL PHY DP Mode
register was not taking effect, hence rewrite this register.

v2: Rename function [Mitul]
v3: Rename function [Jani]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Signed-off-by: Kulkarni, Vandita <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4f9c50996446..85b7c30aa9e5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2099,10 +2099,21 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 	encoder->disable_clock(encoder);
 }
 
+static void
+tgl_dkl_phy_check_and_rewrite(struct drm_i915_private *dev_priv,
+			      enum tc_port tc_port, u32 ln0, u32 ln1)
+{
+	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
+		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
+	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
+		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+}
+
 static void
 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 		       const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
 	u32 ln0, ln1, pin_assignment;
@@ -2180,6 +2191,10 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 	if (DISPLAY_VER(dev_priv) >= 12) {
 		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
 		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+		 /* WA_14018221282 */
+		if (DISPLAY_VER(display) == 12)
+			tgl_dkl_phy_check_and_rewrite(dev_priv, tc_port, ln0, ln1);
+
 	} else {
 		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
 		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
-- 
2.25.1

Re: [PATCH] drm/i915/display: Add WA_14018221282

[Matt Roper]

On Thu, Dec 12, 2024 at 03:10:43PM +0530, Nemesa Garg wrote:
> It was observed that the first write to DKL PHY DP Mode
> register was not taking effect, hence rewrite this register.
> 
> v2: Rename function [Mitul]
> v3: Rename function [Jani]
> 
> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> Signed-off-by: Kulkarni, Vandita <vandita.kulkarni@intel.com>

"Last, first" name format with a comma like this causes problems for
git-send-email (it thinks the comma is separating two separate email
addresses and winds up sending a copy of the message to a bogus email
address).

Although that also raises the question what Vandita's s-o-b represents.
If she was involved in the original development of the patch, should
there also be a "Co-developed-by:" line too (as described in
Documentation/process/submitting-patches.rst)?

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4f9c50996446..85b7c30aa9e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2099,10 +2099,21 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
>  	encoder->disable_clock(encoder);
>  }
>  
> +static void
> +tgl_dkl_phy_check_and_rewrite(struct drm_i915_private *dev_priv,
> +			      enum tc_port tc_port, u32 ln0, u32 ln1)
> +{
> +	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
> +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
> +	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
> +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
> +}
> +
>  static void
>  icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>  		       const struct intel_crtc_state *crtc_state)
>  {
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>  	enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
>  	u32 ln0, ln1, pin_assignment;
> @@ -2180,6 +2191,10 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>  	if (DISPLAY_VER(dev_priv) >= 12) {
>  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
>  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
> +		 /* WA_14018221282 */
> +		if (DISPLAY_VER(display) == 12)

The workaround database lists this for both TGL (display version 12) and
ADL-P (display version 13).

At first I was worried that we might be applying this too widely since
it's not listed for other display version 12 platforms (RKL, ADL-S,
DG1), but I see now that won't be a problem since none of those
platforms have MG / DKL PHYs so they'll never descend down to this level
of the code.

So just changing this to "IS_DISPLAY_VER(display, 12, 13)" is probably
sufficient to cover the appropriate platforms (DG2 is also display
version 13, but as with RKL/ADL-S/DG1 it doesn't have MG/DKL PHYs so it
won't see this code anyway).


Matt

> +			tgl_dkl_phy_check_and_rewrite(dev_priv, tc_port, ln0, ln1);
> +
>  	} else {
>  		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
>  		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH] drm/i915/display: Add WA_14018221282

[Nemesa Garg]

It was observed that the first write to DKL PHY DP Mode
register was not taking effect, hence rewrite this register.

v2: Rename function [Mitul]
v3: Rename function [Jani]
v4: Add check for display ver 13 [Matt]

Co-developed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4f9c50996446..112a37a58be3 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2099,10 +2099,21 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 	encoder->disable_clock(encoder);
 }
 
+static void
+tgl_dkl_phy_check_and_rewrite(struct drm_i915_private *dev_priv,
+			      enum tc_port tc_port, u32 ln0, u32 ln1)
+{
+	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
+		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
+	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
+		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+}
+
 static void
 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 		       const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
 	u32 ln0, ln1, pin_assignment;
@@ -2180,6 +2191,10 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 	if (DISPLAY_VER(dev_priv) >= 12) {
 		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
 		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+		 /* WA_14018221282 */
+		if (IS_DISPLAY_VER(display, 12, 13))
+			tgl_dkl_phy_check_and_rewrite(dev_priv, tc_port, ln0, ln1);
+
 	} else {
 		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
 		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
-- 
2.25.1

RE: [PATCH] drm/i915/display: Add WA_14018221282

[Kahola, Mika]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Nemesa
> Garg
> Sent: Thursday, 26 December 2024 8.07
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Garg, Nemesa <nemesa.garg@intel.com>; Vandita Kulkarni
> <vandita.kulkarni@intel.com>
> Subject: [PATCH] drm/i915/display: Add WA_14018221282
> 
> It was observed that the first write to DKL PHY DP Mode register was not taking
> effect, hence rewrite this register.
> 
> v2: Rename function [Mitul]
> v3: Rename function [Jani]
> v4: Add check for display ver 13 [Matt]
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Co-developed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4f9c50996446..112a37a58be3 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2099,10 +2099,21 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct
> intel_encoder *encoder)
>  	encoder->disable_clock(encoder);
>  }
> 
> +static void
> +tgl_dkl_phy_check_and_rewrite(struct drm_i915_private *dev_priv,
> +			      enum tc_port tc_port, u32 ln0, u32 ln1) {
> +	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
> +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
> +	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
> +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); }
> +
>  static void
>  icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>  		       const struct intel_crtc_state *crtc_state)  {
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>  	enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
>  	u32 ln0, ln1, pin_assignment;
> @@ -2180,6 +2191,10 @@ icl_program_mg_dp_mode(struct intel_digital_port
> *dig_port,
>  	if (DISPLAY_VER(dev_priv) >= 12) {
>  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
>  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
> +		 /* WA_14018221282 */
> +		if (IS_DISPLAY_VER(display, 12, 13))
> +			tgl_dkl_phy_check_and_rewrite(dev_priv, tc_port, ln0,
> ln1);
> +
>  	} else {
>  		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
>  		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
> --
> 2.25.1