Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Jani Nikula <jani.nikula@intel.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v2 3/5] drm/dsi: add missing DSI DCS commands
Date: Tue, 05 Nov 2019 16:06:40 +0200	[thread overview]
Message-ID: <878sou76z3.fsf@intel.com> (raw)
In-Reply-To: <20191105091801.GA1607358@ulmo>

On Tue, 05 Nov 2019, Thierry Reding <thierry.reding@gmail.com> wrote:
> On Mon, Oct 28, 2019 at 05:00:45PM +0200, Jani Nikula wrote:
>> Update from the DCS specification.
>> 
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  include/video/mipi_display.h | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>> 
>> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
>> index 6b6390dfa203..928f8c4b6658 100644
>> --- a/include/video/mipi_display.h
>> +++ b/include/video/mipi_display.h
>> @@ -79,7 +79,9 @@ enum {
>>  enum {
>>  	MIPI_DCS_NOP			= 0x00,
>>  	MIPI_DCS_SOFT_RESET		= 0x01,
>> +	MIPI_DCS_GET_COMPRESSION_MODE	= 0x03,
>>  	MIPI_DCS_GET_DISPLAY_ID		= 0x04,
>> +	MIPI_DCS_GET_ERROR_COUNT_ON_DSI	= 0x05,
>>  	MIPI_DCS_GET_RED_CHANNEL	= 0x06,
>>  	MIPI_DCS_GET_GREEN_CHANNEL	= 0x07,
>>  	MIPI_DCS_GET_BLUE_CHANNEL	= 0x08,
>> @@ -94,6 +96,8 @@ enum {
>>  	MIPI_DCS_EXIT_SLEEP_MODE	= 0x11,
>>  	MIPI_DCS_ENTER_PARTIAL_MODE	= 0x12,
>>  	MIPI_DCS_ENTER_NORMAL_MODE	= 0x13,
>> +	MIPI_DCS_GET_IMAGE_CHECKSUM_RGB	= 0x14,
>> +	MIPI_DCS_GET_IMAGE_CHECKSUM_CT	= 0x15,
>>  	MIPI_DCS_EXIT_INVERT_MODE	= 0x20,
>>  	MIPI_DCS_ENTER_INVERT_MODE	= 0x21,
>>  	MIPI_DCS_SET_GAMMA_CURVE	= 0x26,
>> @@ -105,6 +109,7 @@ enum {
>>  	MIPI_DCS_WRITE_LUT		= 0x2D,
>>  	MIPI_DCS_READ_MEMORY_START	= 0x2E,
>>  	MIPI_DCS_SET_PARTIAL_AREA	= 0x30,
>> +	MIPI_DCS_SET_PARTIAL_COLUMNS	= 0x31,
>>  	MIPI_DCS_SET_SCROLL_AREA	= 0x33,
>>  	MIPI_DCS_SET_TEAR_OFF		= 0x34,
>>  	MIPI_DCS_SET_TEAR_ON		= 0x35,
>> @@ -114,7 +119,10 @@ enum {
>>  	MIPI_DCS_ENTER_IDLE_MODE	= 0x39,
>>  	MIPI_DCS_SET_PIXEL_FORMAT	= 0x3A,
>>  	MIPI_DCS_WRITE_MEMORY_CONTINUE	= 0x3C,
>> +	MIPI_DCS_SET_3D_CONTROL		= 0x3D,
>>  	MIPI_DCS_READ_MEMORY_CONTINUE	= 0x3E,
>> +	MIPI_DCS_GET_3D_CONTROL		= 0x3F,
>> +	MIPI_DCS_SET_VSYNC_TIMING	= 0x40,
>>  	MIPI_DCS_SET_TEAR_SCANLINE	= 0x44,
>>  	MIPI_DCS_GET_SCANLINE		= 0x45,
>>  	MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51,		/* MIPI DCS 1.3 */
>> @@ -126,7 +134,9 @@ enum {
>>  	MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E,	/* MIPI DCS 1.3 */
>>  	MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F,	/* MIPI DCS 1.3 */
>>  	MIPI_DCS_READ_DDB_START		= 0xA1,
>> +	MIPI_DCS_READ_PPS_START		= 0xA2,
>>  	MIPI_DCS_READ_DDB_CONTINUE	= 0xA8,
>> +	MIPI_DCS_READ_PPS_CONTINUE	= 0xA9,
>>  };
>>  
>>  /* MIPI DCS pixel formats */
>
> Okay, found a copy of DCS v1.4 and the above matches the specification,
> so:
>
> Reviewed-by: Thierry Reding <treding@nvidia.com>
>
> Does it perhaps make sense to add comments about the version number that
> these were introduced with?

The trouble is, I don't have the complete chronology of the
specifications, so I can't be sure at which point each one was added.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Jani Nikula <jani.nikula@intel.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 3/5] drm/dsi: add missing DSI DCS commands
Date: Tue, 05 Nov 2019 16:06:40 +0200	[thread overview]
Message-ID: <878sou76z3.fsf@intel.com> (raw)
Message-ID: <20191105140640.ut_ozkQtqZ858clANw_O3UF5KzCxxzevNfUGKaNxcXI@z> (raw)
In-Reply-To: <20191105091801.GA1607358@ulmo>

On Tue, 05 Nov 2019, Thierry Reding <thierry.reding@gmail.com> wrote:
> On Mon, Oct 28, 2019 at 05:00:45PM +0200, Jani Nikula wrote:
>> Update from the DCS specification.
>> 
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  include/video/mipi_display.h | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>> 
>> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
>> index 6b6390dfa203..928f8c4b6658 100644
>> --- a/include/video/mipi_display.h
>> +++ b/include/video/mipi_display.h
>> @@ -79,7 +79,9 @@ enum {
>>  enum {
>>  	MIPI_DCS_NOP			= 0x00,
>>  	MIPI_DCS_SOFT_RESET		= 0x01,
>> +	MIPI_DCS_GET_COMPRESSION_MODE	= 0x03,
>>  	MIPI_DCS_GET_DISPLAY_ID		= 0x04,
>> +	MIPI_DCS_GET_ERROR_COUNT_ON_DSI	= 0x05,
>>  	MIPI_DCS_GET_RED_CHANNEL	= 0x06,
>>  	MIPI_DCS_GET_GREEN_CHANNEL	= 0x07,
>>  	MIPI_DCS_GET_BLUE_CHANNEL	= 0x08,
>> @@ -94,6 +96,8 @@ enum {
>>  	MIPI_DCS_EXIT_SLEEP_MODE	= 0x11,
>>  	MIPI_DCS_ENTER_PARTIAL_MODE	= 0x12,
>>  	MIPI_DCS_ENTER_NORMAL_MODE	= 0x13,
>> +	MIPI_DCS_GET_IMAGE_CHECKSUM_RGB	= 0x14,
>> +	MIPI_DCS_GET_IMAGE_CHECKSUM_CT	= 0x15,
>>  	MIPI_DCS_EXIT_INVERT_MODE	= 0x20,
>>  	MIPI_DCS_ENTER_INVERT_MODE	= 0x21,
>>  	MIPI_DCS_SET_GAMMA_CURVE	= 0x26,
>> @@ -105,6 +109,7 @@ enum {
>>  	MIPI_DCS_WRITE_LUT		= 0x2D,
>>  	MIPI_DCS_READ_MEMORY_START	= 0x2E,
>>  	MIPI_DCS_SET_PARTIAL_AREA	= 0x30,
>> +	MIPI_DCS_SET_PARTIAL_COLUMNS	= 0x31,
>>  	MIPI_DCS_SET_SCROLL_AREA	= 0x33,
>>  	MIPI_DCS_SET_TEAR_OFF		= 0x34,
>>  	MIPI_DCS_SET_TEAR_ON		= 0x35,
>> @@ -114,7 +119,10 @@ enum {
>>  	MIPI_DCS_ENTER_IDLE_MODE	= 0x39,
>>  	MIPI_DCS_SET_PIXEL_FORMAT	= 0x3A,
>>  	MIPI_DCS_WRITE_MEMORY_CONTINUE	= 0x3C,
>> +	MIPI_DCS_SET_3D_CONTROL		= 0x3D,
>>  	MIPI_DCS_READ_MEMORY_CONTINUE	= 0x3E,
>> +	MIPI_DCS_GET_3D_CONTROL		= 0x3F,
>> +	MIPI_DCS_SET_VSYNC_TIMING	= 0x40,
>>  	MIPI_DCS_SET_TEAR_SCANLINE	= 0x44,
>>  	MIPI_DCS_GET_SCANLINE		= 0x45,
>>  	MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51,		/* MIPI DCS 1.3 */
>> @@ -126,7 +134,9 @@ enum {
>>  	MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E,	/* MIPI DCS 1.3 */
>>  	MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F,	/* MIPI DCS 1.3 */
>>  	MIPI_DCS_READ_DDB_START		= 0xA1,
>> +	MIPI_DCS_READ_PPS_START		= 0xA2,
>>  	MIPI_DCS_READ_DDB_CONTINUE	= 0xA8,
>> +	MIPI_DCS_READ_PPS_CONTINUE	= 0xA9,
>>  };
>>  
>>  /* MIPI DCS pixel formats */
>
> Okay, found a copy of DCS v1.4 and the above matches the specification,
> so:
>
> Reviewed-by: Thierry Reding <treding@nvidia.com>
>
> Does it perhaps make sense to add comments about the version number that
> these were introduced with?

The trouble is, I don't have the complete chronology of the
specifications, so I can't be sure at which point each one was added.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-11-05 14:06 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-28 15:00 [PATCH v2 1/5] drm/dsi: clean up DSI data type definitions Jani Nikula
2019-10-28 15:00 ` [Intel-gfx] " Jani Nikula
2019-10-28 15:00 ` [PATCH v2 2/5] drm/dsi: add missing DSI data types Jani Nikula
2019-10-28 15:00   ` [Intel-gfx] " Jani Nikula
2019-10-30  8:28   ` Kulkarni, Vandita
2019-10-30  8:28     ` [Intel-gfx] " Kulkarni, Vandita
2019-11-04 15:24   ` Thierry Reding
2019-11-04 15:24     ` [Intel-gfx] " Thierry Reding
2019-10-28 15:00 ` [PATCH v2 3/5] drm/dsi: add missing DSI DCS commands Jani Nikula
2019-10-28 15:00   ` [Intel-gfx] " Jani Nikula
2019-11-04 15:29   ` Thierry Reding
2019-11-04 15:29     ` [Intel-gfx] " Thierry Reding
2019-11-05  9:18   ` Thierry Reding
2019-11-05  9:18     ` Thierry Reding
2019-11-05 14:06     ` Jani Nikula [this message]
2019-11-05 14:06       ` Jani Nikula
2019-10-28 15:00 ` [PATCH v2 4/5] drm/dsi: rename MIPI_DCS_SET_PARTIAL_AREA to MIPI_DCS_SET_PARTIAL_ROWS Jani Nikula
2019-10-28 15:00   ` [Intel-gfx] " Jani Nikula
2019-11-05  9:42   ` Thierry Reding
2019-11-05  9:42     ` Thierry Reding
2019-10-28 15:00 ` [PATCH v2 5/5] drm/dsi: add helpers for DSI compression mode and PPS packets Jani Nikula
2019-10-28 15:00   ` [Intel-gfx] " Jani Nikula
2019-11-05  9:55   ` Thierry Reding
2019-11-05  9:55     ` [Intel-gfx] " Thierry Reding
2019-10-28 19:17 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/5] drm/dsi: clean up DSI data type definitions Patchwork
2019-10-28 19:17   ` [Intel-gfx] " Patchwork
2019-10-28 19:37 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-28 19:37   ` [Intel-gfx] " Patchwork
2019-10-29 14:04 ` ✓ Fi.CI.IGT: " Patchwork
2019-10-29 14:04   ` [Intel-gfx] " Patchwork
2019-11-04 14:07 ` [PATCH v2 1/5] " Jani Nikula
2019-11-04 14:07   ` [Intel-gfx] " Jani Nikula
2019-11-07 13:21   ` Jani Nikula
2019-11-07 13:21     ` [Intel-gfx] " Jani Nikula
2019-11-04 15:20 ` Thierry Reding
2019-11-04 15:20   ` [Intel-gfx] " Thierry Reding
2019-11-05  9:18   ` Jani Nikula
2019-11-05  9:18     ` Jani Nikula

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=878sou76z3.fsf@intel.com \
    --to=jani.nikula@intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=thierry.reding@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox