[PATCH 0/3] drm/i915: Fix DP MST SB message timeouts due to PPS delays

[PATCH 0/3] drm/i915: Fix DP MST SB message timeouts due to PPS delays

[Imre Deak]

This patchset fixes DP MST down request side-band message timeouts on
one port caused by long PPS (panel/backlight, power-cycle) delays on
another eDP port.

Imre Deak (3):
  drm/i915/pps: Add helpers to lock PPS for AUX transfers
  drm/i915/dp_mst: Fix side-band message timeouts due to long PPS delays
  drm/i915/pps: Use intel_pps_is_pipe_instance() instead of open-coding
    it

 drivers/gpu/drm/i915/display/g4x_dp.c       |  6 +-
 drivers/gpu/drm/i915/display/intel_dp.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_dp_aux.c | 16 +----
 drivers/gpu/drm/i915/display/intel_pps.c    | 79 ++++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_pps.h    |  5 +-
 5 files changed, 80 insertions(+), 28 deletions(-)

-- 
2.44.2

[PATCH 1/3] drm/i915/pps: Add helpers to lock PPS for AUX transfers

[Imre Deak]

Factor out from the DP AUX transfer function the logic to lock/unlock
the Panel Power Sequencer state and enable/disable the VDD power
required for the AUX transfer, adding these to helpers in intel_pps.c .
This prepares for a follow-up change making these steps dependent on the
platform and output type.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_aux.c | 16 ++----------
 drivers/gpu/drm/i915/display/intel_pps.c    | 29 ++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_pps.h    |  3 ++-
 3 files changed, 32 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index ec27bbd70bcf0..bf5ccfa24ca0b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -272,15 +272,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
 	aux_domain = intel_aux_power_domain(dig_port);
 
 	aux_wakeref = intel_display_power_get(display, aux_domain);
-	pps_wakeref = intel_pps_lock(intel_dp);
-
-	/*
-	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
-	 * In such cases we want to leave VDD enabled and it's up to upper layers
-	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
-	 * ourselves.
-	 */
-	vdd = intel_pps_vdd_on_unlocked(intel_dp);
+	pps_wakeref = intel_pps_lock_for_aux(intel_dp, &vdd);
 
 	/*
 	 * dp aux is extremely sensitive to irq latency, hence request the
@@ -289,8 +281,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
 	 */
 	cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
 
-	intel_pps_check_power_unlocked(intel_dp);
-
 	/*
 	 * FIXME PSR should be disabled here to prevent
 	 * it using the same AUX CH simultaneously
@@ -427,10 +417,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
 out:
 	cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
 
-	if (vdd)
-		intel_pps_vdd_off_unlocked(intel_dp, false);
+	intel_pps_unlock_for_aux(intel_dp, pps_wakeref, vdd);
 
-	intel_pps_unlock(intel_dp, pps_wakeref);
 	intel_display_power_put_async(display, aux_domain, aux_wakeref);
 out_unlock:
 	intel_digital_port_unlock(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 617ce49931726..3c078fd53fbfa 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -571,7 +571,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 	return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 }
 
-void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
+static void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -955,6 +955,33 @@ void intel_pps_vdd_off(struct intel_dp *intel_dp)
 		intel_pps_vdd_off_unlocked(intel_dp, false);
 }
 
+intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
+{
+	intel_wakeref_t wakeref;
+
+	wakeref = intel_pps_lock(intel_dp);
+
+	/*
+	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
+	 * In such cases we want to leave VDD enabled and it's up to upper layers
+	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
+	 * ourselves.
+	 */
+	*vdd_ref = intel_pps_vdd_on_unlocked(intel_dp);
+
+	intel_pps_check_power_unlocked(intel_dp);
+
+	return wakeref;
+}
+
+void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref)
+{
+	if (vdd_ref)
+		intel_pps_vdd_off_unlocked(intel_dp, false);
+
+	intel_pps_unlock(intel_dp, wakeref);
+}
+
 void intel_pps_on_unlocked(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index c83007152f07d..4390d05892325 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -31,10 +31,11 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
 void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
 void intel_pps_on_unlocked(struct intel_dp *intel_dp);
 void intel_pps_off_unlocked(struct intel_dp *intel_dp);
-void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
 
 void intel_pps_vdd_on(struct intel_dp *intel_dp);
 void intel_pps_vdd_off(struct intel_dp *intel_dp);
+intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref);
+void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref);
 void intel_pps_on(struct intel_dp *intel_dp);
 void intel_pps_off(struct intel_dp *intel_dp);
 void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
-- 
2.44.2

Re: [PATCH 1/3] drm/i915/pps: Add helpers to lock PPS for AUX transfers

[Jani Nikula]

On Fri, 21 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
> Factor out from the DP AUX transfer function the logic to lock/unlock
> the Panel Power Sequencer state and enable/disable the VDD power
> required for the AUX transfer, adding these to helpers in intel_pps.c .
> This prepares for a follow-up change making these steps dependent on the
> platform and output type.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_aux.c | 16 ++----------
>  drivers/gpu/drm/i915/display/intel_pps.c    | 29 ++++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_pps.h    |  3 ++-
>  3 files changed, 32 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index ec27bbd70bcf0..bf5ccfa24ca0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -272,15 +272,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>  	aux_domain = intel_aux_power_domain(dig_port);
>  
>  	aux_wakeref = intel_display_power_get(display, aux_domain);
> -	pps_wakeref = intel_pps_lock(intel_dp);
> -
> -	/*
> -	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
> -	 * In such cases we want to leave VDD enabled and it's up to upper layers
> -	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
> -	 * ourselves.
> -	 */
> -	vdd = intel_pps_vdd_on_unlocked(intel_dp);
> +	pps_wakeref = intel_pps_lock_for_aux(intel_dp, &vdd);
>  
>  	/*
>  	 * dp aux is extremely sensitive to irq latency, hence request the
> @@ -289,8 +281,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>  	 */
>  	cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
>  
> -	intel_pps_check_power_unlocked(intel_dp);
> -
>  	/*
>  	 * FIXME PSR should be disabled here to prevent
>  	 * it using the same AUX CH simultaneously
> @@ -427,10 +417,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>  out:
>  	cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
>  
> -	if (vdd)
> -		intel_pps_vdd_off_unlocked(intel_dp, false);
> +	intel_pps_unlock_for_aux(intel_dp, pps_wakeref, vdd);
>  
> -	intel_pps_unlock(intel_dp, pps_wakeref);
>  	intel_display_power_put_async(display, aux_domain, aux_wakeref);
>  out_unlock:
>  	intel_digital_port_unlock(encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index 617ce49931726..3c078fd53fbfa 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -571,7 +571,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>  	return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
>  }
>  
> -void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
> +static void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> @@ -955,6 +955,33 @@ void intel_pps_vdd_off(struct intel_dp *intel_dp)
>  		intel_pps_vdd_off_unlocked(intel_dp, false);
>  }
>  
> +intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
> +{
> +	intel_wakeref_t wakeref;
> +
> +	wakeref = intel_pps_lock(intel_dp);
> +
> +	/*
> +	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
> +	 * In such cases we want to leave VDD enabled and it's up to upper layers
> +	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
> +	 * ourselves.
> +	 */
> +	*vdd_ref = intel_pps_vdd_on_unlocked(intel_dp);
> +
> +	intel_pps_check_power_unlocked(intel_dp);
> +
> +	return wakeref;
> +}
> +
> +void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref)
> +{
> +	if (vdd_ref)
> +		intel_pps_vdd_off_unlocked(intel_dp, false);
> +
> +	intel_pps_unlock(intel_dp, wakeref);
> +}

It took me a while to pinpoint what exactly I don't like about this
interface.

And I mean the whole intel_pps.h interface is already really difficult
to understand.

This flips the lock/unlock and vdd on/off logic inside out.

Normally you have functions for doing vdd or power or backlight, or
anything PPS really, and they're either unlocked (assuming the caller
handles PPS lock) or locked (the function itself takes the lock).

This one purports to be an interface for lock/unlock, but in reality it
also does VDD internally. And that feels really quite wrong to me.

---

These are a single-use interface that I think make intel_pps.[ch] more
difficult to understand. I'd suggest checking how you'd implement this
logic inside intel_dp_aux_xfer() *without* changing the intel_pps.[ch]
interface at all.

Okay, took a quick stab at it, and unless I'm missing something it's
super easy:


diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index ec27bbd70bcf..a5608659df59 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -247,7 +247,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
 	u32 aux_clock_divider;
 	enum intel_display_power_domain aux_domain;
 	intel_wakeref_t aux_wakeref;
-	intel_wakeref_t pps_wakeref;
+	intel_wakeref_t pps_wakeref = NULL;
 	int i, ret, recv_bytes;
 	int try, clock = 0;
 	u32 status;
@@ -272,7 +272,10 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
 	aux_domain = intel_aux_power_domain(dig_port);
 
 	aux_wakeref = intel_display_power_get(display, aux_domain);
-	pps_wakeref = intel_pps_lock(intel_dp);
+
+	if (intel_dp_is_edp(intel_dp) ||
+	    (display->platform.valleyview || display->platform.cherryview))
+		pps_wakeref = intel_pps_lock(intel_dp);
 
 	/*
 	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
@@ -430,7 +433,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
 	if (vdd)
 		intel_pps_vdd_off_unlocked(intel_dp, false);
 
-	intel_pps_unlock(intel_dp, pps_wakeref);
+	if (pps_wakeref)
+		intel_pps_unlock(intel_dp, pps_wakeref);
 	intel_display_power_put_async(display, aux_domain, aux_wakeref);
 out_unlock:
 	intel_digital_port_unlock(encoder);


Please let's not make intel_pps.[ch] harder to understand.


BR,
Jani.


> +
>  void intel_pps_on_unlocked(struct intel_dp *intel_dp)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
> index c83007152f07d..4390d05892325 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.h
> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> @@ -31,10 +31,11 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
>  void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
>  void intel_pps_on_unlocked(struct intel_dp *intel_dp);
>  void intel_pps_off_unlocked(struct intel_dp *intel_dp);
> -void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
>  
>  void intel_pps_vdd_on(struct intel_dp *intel_dp);
>  void intel_pps_vdd_off(struct intel_dp *intel_dp);
> +intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref);
> +void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref);
>  void intel_pps_on(struct intel_dp *intel_dp);
>  void intel_pps_off(struct intel_dp *intel_dp);
>  void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);

-- 
Jani Nikula, Intel

Re: [PATCH 1/3] drm/i915/pps: Add helpers to lock PPS for AUX transfers

[Imre Deak]

On Mon, Mar 24, 2025 at 12:33:22PM +0200, Jani Nikula wrote:
> On Fri, 21 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
> > Factor out from the DP AUX transfer function the logic to lock/unlock
> > the Panel Power Sequencer state and enable/disable the VDD power
> > required for the AUX transfer, adding these to helpers in intel_pps.c .
> > This prepares for a follow-up change making these steps dependent on the
> > platform and output type.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp_aux.c | 16 ++----------
> >  drivers/gpu/drm/i915/display/intel_pps.c    | 29 ++++++++++++++++++++-
> >  drivers/gpu/drm/i915/display/intel_pps.h    |  3 ++-
> >  3 files changed, 32 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > index ec27bbd70bcf0..bf5ccfa24ca0b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > @@ -272,15 +272,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >  	aux_domain = intel_aux_power_domain(dig_port);
> >  
> >  	aux_wakeref = intel_display_power_get(display, aux_domain);
> > -	pps_wakeref = intel_pps_lock(intel_dp);
> > -
> > -	/*
> > -	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
> > -	 * In such cases we want to leave VDD enabled and it's up to upper layers
> > -	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
> > -	 * ourselves.
> > -	 */
> > -	vdd = intel_pps_vdd_on_unlocked(intel_dp);
> > +	pps_wakeref = intel_pps_lock_for_aux(intel_dp, &vdd);
> >  
> >  	/*
> >  	 * dp aux is extremely sensitive to irq latency, hence request the
> > @@ -289,8 +281,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >  	 */
> >  	cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
> >  
> > -	intel_pps_check_power_unlocked(intel_dp);
> > -
> >  	/*
> >  	 * FIXME PSR should be disabled here to prevent
> >  	 * it using the same AUX CH simultaneously
> > @@ -427,10 +417,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >  out:
> >  	cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
> >  
> > -	if (vdd)
> > -		intel_pps_vdd_off_unlocked(intel_dp, false);
> > +	intel_pps_unlock_for_aux(intel_dp, pps_wakeref, vdd);
> >  
> > -	intel_pps_unlock(intel_dp, pps_wakeref);
> >  	intel_display_power_put_async(display, aux_domain, aux_wakeref);
> >  out_unlock:
> >  	intel_digital_port_unlock(encoder);
> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> > index 617ce49931726..3c078fd53fbfa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> > @@ -571,7 +571,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
> >  	return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
> >  }
> >  
> > -void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
> > +static void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
> >  {
> >  	struct intel_display *display = to_intel_display(intel_dp);
> >  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > @@ -955,6 +955,33 @@ void intel_pps_vdd_off(struct intel_dp *intel_dp)
> >  		intel_pps_vdd_off_unlocked(intel_dp, false);
> >  }
> >  
> > +intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
> > +{
> > +	intel_wakeref_t wakeref;
> > +
> > +	wakeref = intel_pps_lock(intel_dp);
> > +
> > +	/*
> > +	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
> > +	 * In such cases we want to leave VDD enabled and it's up to upper layers
> > +	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
> > +	 * ourselves.
> > +	 */
> > +	*vdd_ref = intel_pps_vdd_on_unlocked(intel_dp);
> > +
> > +	intel_pps_check_power_unlocked(intel_dp);
> > +
> > +	return wakeref;
> > +}
> > +
> > +void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref)
> > +{
> > +	if (vdd_ref)
> > +		intel_pps_vdd_off_unlocked(intel_dp, false);
> > +
> > +	intel_pps_unlock(intel_dp, wakeref);
> > +}
> 
> It took me a while to pinpoint what exactly I don't like about this
> interface.
> 
> And I mean the whole intel_pps.h interface is already really difficult
> to understand.
> 
> This flips the lock/unlock and vdd on/off logic inside out.
> 
> Normally you have functions for doing vdd or power or backlight, or
> anything PPS really, and they're either unlocked (assuming the caller
> handles PPS lock) or locked (the function itself takes the lock).

The PPS and VDD handling steps are dependent (PPS must be locked for
enabling VDD) and both are skipped for the same reason during AUX
transfers. So I thought it makes sense to move these to a separate
function and skip both based on the same platform/output type check.

> This one purports to be an interface for lock/unlock, but in reality it
> also does VDD internally. And that feels really quite wrong to me.
> 
> ---
> 
> These are a single-use interface that I think make intel_pps.[ch] more
> difficult to understand. I'd suggest checking how you'd implement this
> logic inside intel_dp_aux_xfer() *without* changing the intel_pps.[ch]
> interface at all.
> 
> Okay, took a quick stab at it, and unless I'm missing something it's
> super easy:

I still think it'd be better to have a separate function for both
locking PPS and enabling VDD for the reason I described above, that is
to clarify that the PPS state must be locked to enable VDD.

I guess the above could be done separately later in any case, so I can
inline the fix as you suggest.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index ec27bbd70bcf..a5608659df59 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -247,7 +247,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>  	u32 aux_clock_divider;
>  	enum intel_display_power_domain aux_domain;
>  	intel_wakeref_t aux_wakeref;
> -	intel_wakeref_t pps_wakeref;
> +	intel_wakeref_t pps_wakeref = NULL;
>  	int i, ret, recv_bytes;
>  	int try, clock = 0;
>  	u32 status;
> @@ -272,7 +272,10 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>  	aux_domain = intel_aux_power_domain(dig_port);
>  
>  	aux_wakeref = intel_display_power_get(display, aux_domain);
> -	pps_wakeref = intel_pps_lock(intel_dp);
> +
> +	if (intel_dp_is_edp(intel_dp) ||
> +	    (display->platform.valleyview || display->platform.cherryview))
> +		pps_wakeref = intel_pps_lock(intel_dp);
>  
>  	/*
>  	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
> @@ -430,7 +433,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>  	if (vdd)
>  		intel_pps_vdd_off_unlocked(intel_dp, false);
>  
> -	intel_pps_unlock(intel_dp, pps_wakeref);
> +	if (pps_wakeref)
> +		intel_pps_unlock(intel_dp, pps_wakeref);
>  	intel_display_power_put_async(display, aux_domain, aux_wakeref);
>  out_unlock:
>  	intel_digital_port_unlock(encoder);
> 
> 
> Please let's not make intel_pps.[ch] harder to understand.
> 
> 
> BR,
> Jani.
> 
> 
> > +
> >  void intel_pps_on_unlocked(struct intel_dp *intel_dp)
> >  {
> >  	struct intel_display *display = to_intel_display(intel_dp);
> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
> > index c83007152f07d..4390d05892325 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pps.h
> > +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> > @@ -31,10 +31,11 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
> >  void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
> >  void intel_pps_on_unlocked(struct intel_dp *intel_dp);
> >  void intel_pps_off_unlocked(struct intel_dp *intel_dp);
> > -void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
> >  
> >  void intel_pps_vdd_on(struct intel_dp *intel_dp);
> >  void intel_pps_vdd_off(struct intel_dp *intel_dp);
> > +intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref);
> > +void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref);
> >  void intel_pps_on(struct intel_dp *intel_dp);
> >  void intel_pps_off(struct intel_dp *intel_dp);
> >  void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
> 
> -- 
> Jani Nikula, Intel

Re: [PATCH 1/3] drm/i915/pps: Add helpers to lock PPS for AUX transfers

[Jani Nikula]

On Mon, 24 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
> On Mon, Mar 24, 2025 at 12:33:22PM +0200, Jani Nikula wrote:
>> On Fri, 21 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
>> > Factor out from the DP AUX transfer function the logic to lock/unlock
>> > the Panel Power Sequencer state and enable/disable the VDD power
>> > required for the AUX transfer, adding these to helpers in intel_pps.c .
>> > This prepares for a follow-up change making these steps dependent on the
>> > platform and output type.
>> >
>> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_dp_aux.c | 16 ++----------
>> >  drivers/gpu/drm/i915/display/intel_pps.c    | 29 ++++++++++++++++++++-
>> >  drivers/gpu/drm/i915/display/intel_pps.h    |  3 ++-
>> >  3 files changed, 32 insertions(+), 16 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> > index ec27bbd70bcf0..bf5ccfa24ca0b 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> > @@ -272,15 +272,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> >  	aux_domain = intel_aux_power_domain(dig_port);
>> >  
>> >  	aux_wakeref = intel_display_power_get(display, aux_domain);
>> > -	pps_wakeref = intel_pps_lock(intel_dp);
>> > -
>> > -	/*
>> > -	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
>> > -	 * In such cases we want to leave VDD enabled and it's up to upper layers
>> > -	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
>> > -	 * ourselves.
>> > -	 */
>> > -	vdd = intel_pps_vdd_on_unlocked(intel_dp);
>> > +	pps_wakeref = intel_pps_lock_for_aux(intel_dp, &vdd);
>> >  
>> >  	/*
>> >  	 * dp aux is extremely sensitive to irq latency, hence request the
>> > @@ -289,8 +281,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> >  	 */
>> >  	cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
>> >  
>> > -	intel_pps_check_power_unlocked(intel_dp);
>> > -
>> >  	/*
>> >  	 * FIXME PSR should be disabled here to prevent
>> >  	 * it using the same AUX CH simultaneously
>> > @@ -427,10 +417,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> >  out:
>> >  	cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
>> >  
>> > -	if (vdd)
>> > -		intel_pps_vdd_off_unlocked(intel_dp, false);
>> > +	intel_pps_unlock_for_aux(intel_dp, pps_wakeref, vdd);
>> >  
>> > -	intel_pps_unlock(intel_dp, pps_wakeref);
>> >  	intel_display_power_put_async(display, aux_domain, aux_wakeref);
>> >  out_unlock:
>> >  	intel_digital_port_unlock(encoder);
>> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
>> > index 617ce49931726..3c078fd53fbfa 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> > @@ -571,7 +571,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>> >  	return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
>> >  }
>> >  
>> > -void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
>> > +static void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
>> >  {
>> >  	struct intel_display *display = to_intel_display(intel_dp);
>> >  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> > @@ -955,6 +955,33 @@ void intel_pps_vdd_off(struct intel_dp *intel_dp)
>> >  		intel_pps_vdd_off_unlocked(intel_dp, false);
>> >  }
>> >  
>> > +intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
>> > +{
>> > +	intel_wakeref_t wakeref;
>> > +
>> > +	wakeref = intel_pps_lock(intel_dp);
>> > +
>> > +	/*
>> > +	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
>> > +	 * In such cases we want to leave VDD enabled and it's up to upper layers
>> > +	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
>> > +	 * ourselves.
>> > +	 */
>> > +	*vdd_ref = intel_pps_vdd_on_unlocked(intel_dp);
>> > +
>> > +	intel_pps_check_power_unlocked(intel_dp);
>> > +
>> > +	return wakeref;
>> > +}
>> > +
>> > +void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref)
>> > +{
>> > +	if (vdd_ref)
>> > +		intel_pps_vdd_off_unlocked(intel_dp, false);
>> > +
>> > +	intel_pps_unlock(intel_dp, wakeref);
>> > +}
>> 
>> It took me a while to pinpoint what exactly I don't like about this
>> interface.
>> 
>> And I mean the whole intel_pps.h interface is already really difficult
>> to understand.
>> 
>> This flips the lock/unlock and vdd on/off logic inside out.
>> 
>> Normally you have functions for doing vdd or power or backlight, or
>> anything PPS really, and they're either unlocked (assuming the caller
>> handles PPS lock) or locked (the function itself takes the lock).
>
> The PPS and VDD handling steps are dependent (PPS must be locked for
> enabling VDD) and both are skipped for the same reason during AUX
> transfers. So I thought it makes sense to move these to a separate
> function and skip both based on the same platform/output type check.

On the contrary, I think the reasons are different.

VDD is only needed for eDP.

The PPS must be locked for VDD change (IOW for eDP) and for VLV/CHV pipe
based PPS. But these two cases are independent.

>> This one purports to be an interface for lock/unlock, but in reality it
>> also does VDD internally. And that feels really quite wrong to me.
>> 
>> ---
>> 
>> These are a single-use interface that I think make intel_pps.[ch] more
>> difficult to understand. I'd suggest checking how you'd implement this
>> logic inside intel_dp_aux_xfer() *without* changing the intel_pps.[ch]
>> interface at all.
>> 
>> Okay, took a quick stab at it, and unless I'm missing something it's
>> super easy:
>
> I still think it'd be better to have a separate function for both
> locking PPS and enabling VDD for the reason I described above, that is
> to clarify that the PPS state must be locked to enable VDD.

But there's no requirement that they must be done at the same time. The
PPS lock could be held for a much longer period or for other things than
just VDD. And in this case, the PPS lock may indeed protect *other*
things than just VDD. Adding the separate function ties these unrelated
cases together for IMO not good enough reason.

intel_pps_vdd_on_unlocked() does check that it's called with the PPS
lock held.

But I realize it needs to be relaxed a bit like this:


diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 617ce4993172..c883e872c9c8 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -744,11 +744,11 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
 	i915_reg_t pp_stat_reg, pp_ctrl_reg;
 	bool need_to_disable = !intel_dp->pps.want_panel_vdd;
 
-	lockdep_assert_held(&display->pps.mutex);
-
 	if (!intel_dp_is_edp(intel_dp))
 		return false;
 
+	lockdep_assert_held(&display->pps.mutex);
+
 	cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
 	intel_dp->pps.want_panel_vdd = true;
 
@@ -925,11 +925,11 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 
-	lockdep_assert_held(&display->pps.mutex);
-
 	if (!intel_dp_is_edp(intel_dp))
 		return;
 
+	lockdep_assert_held(&display->pps.mutex);
+
 	INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,
 				 "[ENCODER:%d:%s] %s VDD not forced on",
 				 dp_to_dig_port(intel_dp)->base.base.base.id,


> I guess the above could be done separately later in any case, so I can
> inline the fix as you suggest.
>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> index ec27bbd70bcf..a5608659df59 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> @@ -247,7 +247,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>>  	u32 aux_clock_divider;
>>  	enum intel_display_power_domain aux_domain;
>>  	intel_wakeref_t aux_wakeref;
>> -	intel_wakeref_t pps_wakeref;
>> +	intel_wakeref_t pps_wakeref = NULL;
>>  	int i, ret, recv_bytes;
>>  	int try, clock = 0;
>>  	u32 status;
>> @@ -272,7 +272,10 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>>  	aux_domain = intel_aux_power_domain(dig_port);
>>  
>>  	aux_wakeref = intel_display_power_get(display, aux_domain);
>> -	pps_wakeref = intel_pps_lock(intel_dp);
>> +
>> +	if (intel_dp_is_edp(intel_dp) ||
>> +	    (display->platform.valleyview || display->platform.cherryview))
>> +		pps_wakeref = intel_pps_lock(intel_dp);
>>  
>>  	/*
>>  	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
>> @@ -430,7 +433,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>>  	if (vdd)
>>  		intel_pps_vdd_off_unlocked(intel_dp, false);
>>  
>> -	intel_pps_unlock(intel_dp, pps_wakeref);
>> +	if (pps_wakeref)
>> +		intel_pps_unlock(intel_dp, pps_wakeref);
>>  	intel_display_power_put_async(display, aux_domain, aux_wakeref);
>>  out_unlock:
>>  	intel_digital_port_unlock(encoder);
>> 
>> 
>> Please let's not make intel_pps.[ch] harder to understand.
>> 
>> 
>> BR,
>> Jani.
>> 
>> 
>> > +
>> >  void intel_pps_on_unlocked(struct intel_dp *intel_dp)
>> >  {
>> >  	struct intel_display *display = to_intel_display(intel_dp);
>> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
>> > index c83007152f07d..4390d05892325 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_pps.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_pps.h
>> > @@ -31,10 +31,11 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
>> >  void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
>> >  void intel_pps_on_unlocked(struct intel_dp *intel_dp);
>> >  void intel_pps_off_unlocked(struct intel_dp *intel_dp);
>> > -void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
>> >  
>> >  void intel_pps_vdd_on(struct intel_dp *intel_dp);
>> >  void intel_pps_vdd_off(struct intel_dp *intel_dp);
>> > +intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref);
>> > +void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref);
>> >  void intel_pps_on(struct intel_dp *intel_dp);
>> >  void intel_pps_off(struct intel_dp *intel_dp);
>> >  void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
>> 
>> -- 
>> Jani Nikula, Intel

-- 
Jani Nikula, Intel

Re: [PATCH 1/3] drm/i915/pps: Add helpers to lock PPS for AUX transfers

[Imre Deak]

On Mon, Mar 24, 2025 at 02:28:35PM +0200, Jani Nikula wrote:
> On Mon, 24 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
> > On Mon, Mar 24, 2025 at 12:33:22PM +0200, Jani Nikula wrote:
> >> On Fri, 21 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
> >> > Factor out from the DP AUX transfer function the logic to lock/unlock
> >> > the Panel Power Sequencer state and enable/disable the VDD power
> >> > required for the AUX transfer, adding these to helpers in intel_pps.c .
> >> > This prepares for a follow-up change making these steps dependent on the
> >> > platform and output type.
> >> >
> >> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/display/intel_dp_aux.c | 16 ++----------
> >> >  drivers/gpu/drm/i915/display/intel_pps.c    | 29 ++++++++++++++++++++-
> >> >  drivers/gpu/drm/i915/display/intel_pps.h    |  3 ++-
> >> >  3 files changed, 32 insertions(+), 16 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> >> > index ec27bbd70bcf0..bf5ccfa24ca0b 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> >> > @@ -272,15 +272,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >> >  	aux_domain = intel_aux_power_domain(dig_port);
> >> >  
> >> >  	aux_wakeref = intel_display_power_get(display, aux_domain);
> >> > -	pps_wakeref = intel_pps_lock(intel_dp);
> >> > -
> >> > -	/*
> >> > -	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
> >> > -	 * In such cases we want to leave VDD enabled and it's up to upper layers
> >> > -	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
> >> > -	 * ourselves.
> >> > -	 */
> >> > -	vdd = intel_pps_vdd_on_unlocked(intel_dp);
> >> > +	pps_wakeref = intel_pps_lock_for_aux(intel_dp, &vdd);
> >> >  
> >> >  	/*
> >> >  	 * dp aux is extremely sensitive to irq latency, hence request the
> >> > @@ -289,8 +281,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >> >  	 */
> >> >  	cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
> >> >  
> >> > -	intel_pps_check_power_unlocked(intel_dp);
> >> > -
> >> >  	/*
> >> >  	 * FIXME PSR should be disabled here to prevent
> >> >  	 * it using the same AUX CH simultaneously
> >> > @@ -427,10 +417,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >> >  out:
> >> >  	cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
> >> >  
> >> > -	if (vdd)
> >> > -		intel_pps_vdd_off_unlocked(intel_dp, false);
> >> > +	intel_pps_unlock_for_aux(intel_dp, pps_wakeref, vdd);
> >> >  
> >> > -	intel_pps_unlock(intel_dp, pps_wakeref);
> >> >  	intel_display_power_put_async(display, aux_domain, aux_wakeref);
> >> >  out_unlock:
> >> >  	intel_digital_port_unlock(encoder);
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> >> > index 617ce49931726..3c078fd53fbfa 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> >> > @@ -571,7 +571,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
> >> >  	return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
> >> >  }
> >> >  
> >> > -void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
> >> > +static void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
> >> >  {
> >> >  	struct intel_display *display = to_intel_display(intel_dp);
> >> >  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >> > @@ -955,6 +955,33 @@ void intel_pps_vdd_off(struct intel_dp *intel_dp)
> >> >  		intel_pps_vdd_off_unlocked(intel_dp, false);
> >> >  }
> >> >  
> >> > +intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
> >> > +{
> >> > +	intel_wakeref_t wakeref;
> >> > +
> >> > +	wakeref = intel_pps_lock(intel_dp);
> >> > +
> >> > +	/*
> >> > +	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
> >> > +	 * In such cases we want to leave VDD enabled and it's up to upper layers
> >> > +	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
> >> > +	 * ourselves.
> >> > +	 */
> >> > +	*vdd_ref = intel_pps_vdd_on_unlocked(intel_dp);
> >> > +
> >> > +	intel_pps_check_power_unlocked(intel_dp);
> >> > +
> >> > +	return wakeref;
> >> > +}
> >> > +
> >> > +void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref)
> >> > +{
> >> > +	if (vdd_ref)
> >> > +		intel_pps_vdd_off_unlocked(intel_dp, false);
> >> > +
> >> > +	intel_pps_unlock(intel_dp, wakeref);
> >> > +}
> >> 
> >> It took me a while to pinpoint what exactly I don't like about this
> >> interface.
> >> 
> >> And I mean the whole intel_pps.h interface is already really difficult
> >> to understand.
> >> 
> >> This flips the lock/unlock and vdd on/off logic inside out.
> >> 
> >> Normally you have functions for doing vdd or power or backlight, or
> >> anything PPS really, and they're either unlocked (assuming the caller
> >> handles PPS lock) or locked (the function itself takes the lock).
> >
> > The PPS and VDD handling steps are dependent (PPS must be locked for
> > enabling VDD) and both are skipped for the same reason during AUX
> > transfers. So I thought it makes sense to move these to a separate
> > function and skip both based on the same platform/output type check.
> 
> On the contrary, I think the reasons are different.
> 
> VDD is only needed for eDP.
> 
> The PPS must be locked for VDD change (IOW for eDP) and for VLV/CHV pipe
> based PPS. But these two cases are independent.

The case requiring VDD (eDP) is a subset of the cases requring PPS to be
locked (eDP or VLV/CHV). These are not independent cases.

> >> This one purports to be an interface for lock/unlock, but in reality it
> >> also does VDD internally. And that feels really quite wrong to me.
> >> 
> >> ---
> >> 
> >> These are a single-use interface that I think make intel_pps.[ch] more
> >> difficult to understand. I'd suggest checking how you'd implement this
> >> logic inside intel_dp_aux_xfer() *without* changing the intel_pps.[ch]
> >> interface at all.
> >> 
> >> Okay, took a quick stab at it, and unless I'm missing something it's
> >> super easy:
> >
> > I still think it'd be better to have a separate function for both
> > locking PPS and enabling VDD for the reason I described above, that is
> > to clarify that the PPS state must be locked to enable VDD.
> 
> But there's no requirement that they must be done at the same time.

There is also no reason not do them at the same time for AUX. A benefit
of doing that would be to clarify the dependency of VDD on PPS and also
simplify intel_dp_aux_xfer().

> The PPS lock could be held for a much longer period or for other
> things than just VDD. And in this case, the PPS lock may indeed
> protect *other* things than just VDD. Adding the separate function
> ties these unrelated cases together for IMO not good enough reason.
> intel_pps_vdd_on_unlocked() does check that it's called with the PPS
> lock held.
> 
> But I realize it needs to be relaxed a bit like this:

Yes, noticed this too. It was one reason I opted for skipping PPS
locking / VDD enabling from one spot.

> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index 617ce4993172..c883e872c9c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -744,11 +744,11 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
>  	i915_reg_t pp_stat_reg, pp_ctrl_reg;
>  	bool need_to_disable = !intel_dp->pps.want_panel_vdd;
>  
> -	lockdep_assert_held(&display->pps.mutex);
> -
>  	if (!intel_dp_is_edp(intel_dp))
>  		return false;
>  
> +	lockdep_assert_held(&display->pps.mutex);
> +
>  	cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
>  	intel_dp->pps.want_panel_vdd = true;
>  
> @@ -925,11 +925,11 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  
> -	lockdep_assert_held(&display->pps.mutex);
> -
>  	if (!intel_dp_is_edp(intel_dp))
>  		return;
>  
> +	lockdep_assert_held(&display->pps.mutex);
> +
>  	INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,
>  				 "[ENCODER:%d:%s] %s VDD not forced on",
>  				 dp_to_dig_port(intel_dp)->base.base.base.id,
> 
> 
> > I guess the above could be done separately later in any case, so I can
> > inline the fix as you suggest.
> >
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> >> index ec27bbd70bcf..a5608659df59 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> >> @@ -247,7 +247,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >>  	u32 aux_clock_divider;
> >>  	enum intel_display_power_domain aux_domain;
> >>  	intel_wakeref_t aux_wakeref;
> >> -	intel_wakeref_t pps_wakeref;
> >> +	intel_wakeref_t pps_wakeref = NULL;
> >>  	int i, ret, recv_bytes;
> >>  	int try, clock = 0;
> >>  	u32 status;
> >> @@ -272,7 +272,10 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >>  	aux_domain = intel_aux_power_domain(dig_port);
> >>  
> >>  	aux_wakeref = intel_display_power_get(display, aux_domain);
> >> -	pps_wakeref = intel_pps_lock(intel_dp);
> >> +
> >> +	if (intel_dp_is_edp(intel_dp) ||
> >> +	    (display->platform.valleyview || display->platform.cherryview))
> >> +		pps_wakeref = intel_pps_lock(intel_dp);
> >>  
> >>  	/*
> >>  	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
> >> @@ -430,7 +433,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >>  	if (vdd)
> >>  		intel_pps_vdd_off_unlocked(intel_dp, false);
> >>  
> >> -	intel_pps_unlock(intel_dp, pps_wakeref);
> >> +	if (pps_wakeref)
> >> +		intel_pps_unlock(intel_dp, pps_wakeref);
> >>  	intel_display_power_put_async(display, aux_domain, aux_wakeref);
> >>  out_unlock:
> >>  	intel_digital_port_unlock(encoder);
> >> 
> >> 
> >> Please let's not make intel_pps.[ch] harder to understand.
> >> 
> >> 
> >> BR,
> >> Jani.
> >> 
> >> 
> >> > +
> >> >  void intel_pps_on_unlocked(struct intel_dp *intel_dp)
> >> >  {
> >> >  	struct intel_display *display = to_intel_display(intel_dp);
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
> >> > index c83007152f07d..4390d05892325 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_pps.h
> >> > +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> >> > @@ -31,10 +31,11 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
> >> >  void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
> >> >  void intel_pps_on_unlocked(struct intel_dp *intel_dp);
> >> >  void intel_pps_off_unlocked(struct intel_dp *intel_dp);
> >> > -void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
> >> >  
> >> >  void intel_pps_vdd_on(struct intel_dp *intel_dp);
> >> >  void intel_pps_vdd_off(struct intel_dp *intel_dp);
> >> > +intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref);
> >> > +void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref);
> >> >  void intel_pps_on(struct intel_dp *intel_dp);
> >> >  void intel_pps_off(struct intel_dp *intel_dp);
> >> >  void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
> >> 
> >> -- 
> >> Jani Nikula, Intel
> 
> -- 
> Jani Nikula, Intel

Re: [PATCH 1/3] drm/i915/pps: Add helpers to lock PPS for AUX transfers

[Jani Nikula]

On Mon, 24 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
> On Mon, Mar 24, 2025 at 02:28:35PM +0200, Jani Nikula wrote:
>> On Mon, 24 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
>> > On Mon, Mar 24, 2025 at 12:33:22PM +0200, Jani Nikula wrote:
>> >> On Fri, 21 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
>> >> > Factor out from the DP AUX transfer function the logic to lock/unlock
>> >> > the Panel Power Sequencer state and enable/disable the VDD power
>> >> > required for the AUX transfer, adding these to helpers in intel_pps.c .
>> >> > This prepares for a follow-up change making these steps dependent on the
>> >> > platform and output type.
>> >> >
>> >> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>> >> > ---
>> >> >  drivers/gpu/drm/i915/display/intel_dp_aux.c | 16 ++----------
>> >> >  drivers/gpu/drm/i915/display/intel_pps.c    | 29 ++++++++++++++++++++-
>> >> >  drivers/gpu/drm/i915/display/intel_pps.h    |  3 ++-
>> >> >  3 files changed, 32 insertions(+), 16 deletions(-)
>> >> >
>> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> >> > index ec27bbd70bcf0..bf5ccfa24ca0b 100644
>> >> > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> >> > @@ -272,15 +272,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> >> >  	aux_domain = intel_aux_power_domain(dig_port);
>> >> >  
>> >> >  	aux_wakeref = intel_display_power_get(display, aux_domain);
>> >> > -	pps_wakeref = intel_pps_lock(intel_dp);
>> >> > -
>> >> > -	/*
>> >> > -	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
>> >> > -	 * In such cases we want to leave VDD enabled and it's up to upper layers
>> >> > -	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
>> >> > -	 * ourselves.
>> >> > -	 */
>> >> > -	vdd = intel_pps_vdd_on_unlocked(intel_dp);
>> >> > +	pps_wakeref = intel_pps_lock_for_aux(intel_dp, &vdd);
>> >> >  
>> >> >  	/*
>> >> >  	 * dp aux is extremely sensitive to irq latency, hence request the
>> >> > @@ -289,8 +281,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> >> >  	 */
>> >> >  	cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
>> >> >  
>> >> > -	intel_pps_check_power_unlocked(intel_dp);
>> >> > -
>> >> >  	/*
>> >> >  	 * FIXME PSR should be disabled here to prevent
>> >> >  	 * it using the same AUX CH simultaneously
>> >> > @@ -427,10 +417,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> >> >  out:
>> >> >  	cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
>> >> >  
>> >> > -	if (vdd)
>> >> > -		intel_pps_vdd_off_unlocked(intel_dp, false);
>> >> > +	intel_pps_unlock_for_aux(intel_dp, pps_wakeref, vdd);
>> >> >  
>> >> > -	intel_pps_unlock(intel_dp, pps_wakeref);
>> >> >  	intel_display_power_put_async(display, aux_domain, aux_wakeref);
>> >> >  out_unlock:
>> >> >  	intel_digital_port_unlock(encoder);
>> >> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
>> >> > index 617ce49931726..3c078fd53fbfa 100644
>> >> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> >> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> >> > @@ -571,7 +571,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>> >> >  	return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
>> >> >  }
>> >> >  
>> >> > -void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
>> >> > +static void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
>> >> >  {
>> >> >  	struct intel_display *display = to_intel_display(intel_dp);
>> >> >  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> >> > @@ -955,6 +955,33 @@ void intel_pps_vdd_off(struct intel_dp *intel_dp)
>> >> >  		intel_pps_vdd_off_unlocked(intel_dp, false);
>> >> >  }
>> >> >  
>> >> > +intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
>> >> > +{
>> >> > +	intel_wakeref_t wakeref;
>> >> > +
>> >> > +	wakeref = intel_pps_lock(intel_dp);
>> >> > +
>> >> > +	/*
>> >> > +	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
>> >> > +	 * In such cases we want to leave VDD enabled and it's up to upper layers
>> >> > +	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
>> >> > +	 * ourselves.
>> >> > +	 */
>> >> > +	*vdd_ref = intel_pps_vdd_on_unlocked(intel_dp);
>> >> > +
>> >> > +	intel_pps_check_power_unlocked(intel_dp);
>> >> > +
>> >> > +	return wakeref;
>> >> > +}
>> >> > +
>> >> > +void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref)
>> >> > +{
>> >> > +	if (vdd_ref)
>> >> > +		intel_pps_vdd_off_unlocked(intel_dp, false);
>> >> > +
>> >> > +	intel_pps_unlock(intel_dp, wakeref);
>> >> > +}
>> >> 
>> >> It took me a while to pinpoint what exactly I don't like about this
>> >> interface.
>> >> 
>> >> And I mean the whole intel_pps.h interface is already really difficult
>> >> to understand.
>> >> 
>> >> This flips the lock/unlock and vdd on/off logic inside out.
>> >> 
>> >> Normally you have functions for doing vdd or power or backlight, or
>> >> anything PPS really, and they're either unlocked (assuming the caller
>> >> handles PPS lock) or locked (the function itself takes the lock).
>> >
>> > The PPS and VDD handling steps are dependent (PPS must be locked for
>> > enabling VDD) and both are skipped for the same reason during AUX
>> > transfers. So I thought it makes sense to move these to a separate
>> > function and skip both based on the same platform/output type check.
>> 
>> On the contrary, I think the reasons are different.
>> 
>> VDD is only needed for eDP.
>> 
>> The PPS must be locked for VDD change (IOW for eDP) and for VLV/CHV pipe
>> based PPS. But these two cases are independent.
>
> The case requiring VDD (eDP) is a subset of the cases requring PPS to be
> locked (eDP or VLV/CHV). These are not independent cases.

Logically, they are. VLV/CHV requires the PPS lock also for
non-eDP. It's not a subset.

BR,
Jani.



>
>> >> This one purports to be an interface for lock/unlock, but in reality it
>> >> also does VDD internally. And that feels really quite wrong to me.
>> >> 
>> >> ---
>> >> 
>> >> These are a single-use interface that I think make intel_pps.[ch] more
>> >> difficult to understand. I'd suggest checking how you'd implement this
>> >> logic inside intel_dp_aux_xfer() *without* changing the intel_pps.[ch]
>> >> interface at all.
>> >> 
>> >> Okay, took a quick stab at it, and unless I'm missing something it's
>> >> super easy:
>> >
>> > I still think it'd be better to have a separate function for both
>> > locking PPS and enabling VDD for the reason I described above, that is
>> > to clarify that the PPS state must be locked to enable VDD.
>> 
>> But there's no requirement that they must be done at the same time.
>
> There is also no reason not do them at the same time for AUX. A benefit
> of doing that would be to clarify the dependency of VDD on PPS and also
> simplify intel_dp_aux_xfer().
>
>> The PPS lock could be held for a much longer period or for other
>> things than just VDD. And in this case, the PPS lock may indeed
>> protect *other* things than just VDD. Adding the separate function
>> ties these unrelated cases together for IMO not good enough reason.
>> intel_pps_vdd_on_unlocked() does check that it's called with the PPS
>> lock held.
>> 
>> But I realize it needs to be relaxed a bit like this:
>
> Yes, noticed this too. It was one reason I opted for skipping PPS
> locking / VDD enabling from one spot.
>
>> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
>> index 617ce4993172..c883e872c9c8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> @@ -744,11 +744,11 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
>>  	i915_reg_t pp_stat_reg, pp_ctrl_reg;
>>  	bool need_to_disable = !intel_dp->pps.want_panel_vdd;
>>  
>> -	lockdep_assert_held(&display->pps.mutex);
>> -
>>  	if (!intel_dp_is_edp(intel_dp))
>>  		return false;
>>  
>> +	lockdep_assert_held(&display->pps.mutex);
>> +
>>  	cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
>>  	intel_dp->pps.want_panel_vdd = true;
>>  
>> @@ -925,11 +925,11 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
>>  {
>>  	struct intel_display *display = to_intel_display(intel_dp);
>>  
>> -	lockdep_assert_held(&display->pps.mutex);
>> -
>>  	if (!intel_dp_is_edp(intel_dp))
>>  		return;
>>  
>> +	lockdep_assert_held(&display->pps.mutex);
>> +
>>  	INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,
>>  				 "[ENCODER:%d:%s] %s VDD not forced on",
>>  				 dp_to_dig_port(intel_dp)->base.base.base.id,
>> 
>> 
>> > I guess the above could be done separately later in any case, so I can
>> > inline the fix as you suggest.
>> >
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> >> index ec27bbd70bcf..a5608659df59 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> >> @@ -247,7 +247,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> >>  	u32 aux_clock_divider;
>> >>  	enum intel_display_power_domain aux_domain;
>> >>  	intel_wakeref_t aux_wakeref;
>> >> -	intel_wakeref_t pps_wakeref;
>> >> +	intel_wakeref_t pps_wakeref = NULL;
>> >>  	int i, ret, recv_bytes;
>> >>  	int try, clock = 0;
>> >>  	u32 status;
>> >> @@ -272,7 +272,10 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> >>  	aux_domain = intel_aux_power_domain(dig_port);
>> >>  
>> >>  	aux_wakeref = intel_display_power_get(display, aux_domain);
>> >> -	pps_wakeref = intel_pps_lock(intel_dp);
>> >> +
>> >> +	if (intel_dp_is_edp(intel_dp) ||
>> >> +	    (display->platform.valleyview || display->platform.cherryview))
>> >> +		pps_wakeref = intel_pps_lock(intel_dp);
>> >>  
>> >>  	/*
>> >>  	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
>> >> @@ -430,7 +433,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> >>  	if (vdd)
>> >>  		intel_pps_vdd_off_unlocked(intel_dp, false);
>> >>  
>> >> -	intel_pps_unlock(intel_dp, pps_wakeref);
>> >> +	if (pps_wakeref)
>> >> +		intel_pps_unlock(intel_dp, pps_wakeref);
>> >>  	intel_display_power_put_async(display, aux_domain, aux_wakeref);
>> >>  out_unlock:
>> >>  	intel_digital_port_unlock(encoder);
>> >> 
>> >> 
>> >> Please let's not make intel_pps.[ch] harder to understand.
>> >> 
>> >> 
>> >> BR,
>> >> Jani.
>> >> 
>> >> 
>> >> > +
>> >> >  void intel_pps_on_unlocked(struct intel_dp *intel_dp)
>> >> >  {
>> >> >  	struct intel_display *display = to_intel_display(intel_dp);
>> >> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
>> >> > index c83007152f07d..4390d05892325 100644
>> >> > --- a/drivers/gpu/drm/i915/display/intel_pps.h
>> >> > +++ b/drivers/gpu/drm/i915/display/intel_pps.h
>> >> > @@ -31,10 +31,11 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
>> >> >  void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
>> >> >  void intel_pps_on_unlocked(struct intel_dp *intel_dp);
>> >> >  void intel_pps_off_unlocked(struct intel_dp *intel_dp);
>> >> > -void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
>> >> >  
>> >> >  void intel_pps_vdd_on(struct intel_dp *intel_dp);
>> >> >  void intel_pps_vdd_off(struct intel_dp *intel_dp);
>> >> > +intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref);
>> >> > +void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref);
>> >> >  void intel_pps_on(struct intel_dp *intel_dp);
>> >> >  void intel_pps_off(struct intel_dp *intel_dp);
>> >> >  void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
>> >> 
>> >> -- 
>> >> Jani Nikula, Intel
>> 
>> -- 
>> Jani Nikula, Intel

-- 
Jani Nikula, Intel

Re: [PATCH 1/3] drm/i915/pps: Add helpers to lock PPS for AUX transfers

[Imre Deak]

On Mon, Mar 24, 2025 at 03:59:50PM +0200, Jani Nikula wrote:
> On Mon, 24 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
> > On Mon, Mar 24, 2025 at 02:28:35PM +0200, Jani Nikula wrote:
> >> On Mon, 24 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
> >> > On Mon, Mar 24, 2025 at 12:33:22PM +0200, Jani Nikula wrote:
> >> >> On Fri, 21 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
> >> >> > Factor out from the DP AUX transfer function the logic to lock/unlock
> >> >> > the Panel Power Sequencer state and enable/disable the VDD power
> >> >> > required for the AUX transfer, adding these to helpers in intel_pps.c .
> >> >> > This prepares for a follow-up change making these steps dependent on the
> >> >> > platform and output type.
> >> >> >
> >> >> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> >> >> > ---
> >> >> >  drivers/gpu/drm/i915/display/intel_dp_aux.c | 16 ++----------
> >> >> >  drivers/gpu/drm/i915/display/intel_pps.c    | 29 ++++++++++++++++++++-
> >> >> >  drivers/gpu/drm/i915/display/intel_pps.h    |  3 ++-
> >> >> >  3 files changed, 32 insertions(+), 16 deletions(-)
> >> >> >
> >> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> >> >> > index ec27bbd70bcf0..bf5ccfa24ca0b 100644
> >> >> > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> >> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> >> >> > @@ -272,15 +272,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >> >> >  	aux_domain = intel_aux_power_domain(dig_port);
> >> >> >  
> >> >> >  	aux_wakeref = intel_display_power_get(display, aux_domain);
> >> >> > -	pps_wakeref = intel_pps_lock(intel_dp);
> >> >> > -
> >> >> > -	/*
> >> >> > -	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
> >> >> > -	 * In such cases we want to leave VDD enabled and it's up to upper layers
> >> >> > -	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
> >> >> > -	 * ourselves.
> >> >> > -	 */
> >> >> > -	vdd = intel_pps_vdd_on_unlocked(intel_dp);
> >> >> > +	pps_wakeref = intel_pps_lock_for_aux(intel_dp, &vdd);
> >> >> >  
> >> >> >  	/*
> >> >> >  	 * dp aux is extremely sensitive to irq latency, hence request the
> >> >> > @@ -289,8 +281,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >> >> >  	 */
> >> >> >  	cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
> >> >> >  
> >> >> > -	intel_pps_check_power_unlocked(intel_dp);
> >> >> > -
> >> >> >  	/*
> >> >> >  	 * FIXME PSR should be disabled here to prevent
> >> >> >  	 * it using the same AUX CH simultaneously
> >> >> > @@ -427,10 +417,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >> >> >  out:
> >> >> >  	cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
> >> >> >  
> >> >> > -	if (vdd)
> >> >> > -		intel_pps_vdd_off_unlocked(intel_dp, false);
> >> >> > +	intel_pps_unlock_for_aux(intel_dp, pps_wakeref, vdd);
> >> >> >  
> >> >> > -	intel_pps_unlock(intel_dp, pps_wakeref);
> >> >> >  	intel_display_power_put_async(display, aux_domain, aux_wakeref);
> >> >> >  out_unlock:
> >> >> >  	intel_digital_port_unlock(encoder);
> >> >> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> >> >> > index 617ce49931726..3c078fd53fbfa 100644
> >> >> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
> >> >> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> >> >> > @@ -571,7 +571,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
> >> >> >  	return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
> >> >> >  }
> >> >> >  
> >> >> > -void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
> >> >> > +static void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
> >> >> >  {
> >> >> >  	struct intel_display *display = to_intel_display(intel_dp);
> >> >> >  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >> >> > @@ -955,6 +955,33 @@ void intel_pps_vdd_off(struct intel_dp *intel_dp)
> >> >> >  		intel_pps_vdd_off_unlocked(intel_dp, false);
> >> >> >  }
> >> >> >  
> >> >> > +intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
> >> >> > +{
> >> >> > +	intel_wakeref_t wakeref;
> >> >> > +
> >> >> > +	wakeref = intel_pps_lock(intel_dp);
> >> >> > +
> >> >> > +	/*
> >> >> > +	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
> >> >> > +	 * In such cases we want to leave VDD enabled and it's up to upper layers
> >> >> > +	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
> >> >> > +	 * ourselves.
> >> >> > +	 */
> >> >> > +	*vdd_ref = intel_pps_vdd_on_unlocked(intel_dp);
> >> >> > +
> >> >> > +	intel_pps_check_power_unlocked(intel_dp);
> >> >> > +
> >> >> > +	return wakeref;
> >> >> > +}
> >> >> > +
> >> >> > +void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref)
> >> >> > +{
> >> >> > +	if (vdd_ref)
> >> >> > +		intel_pps_vdd_off_unlocked(intel_dp, false);
> >> >> > +
> >> >> > +	intel_pps_unlock(intel_dp, wakeref);
> >> >> > +}
> >> >> 
> >> >> It took me a while to pinpoint what exactly I don't like about this
> >> >> interface.
> >> >> 
> >> >> And I mean the whole intel_pps.h interface is already really difficult
> >> >> to understand.
> >> >> 
> >> >> This flips the lock/unlock and vdd on/off logic inside out.
> >> >> 
> >> >> Normally you have functions for doing vdd or power or backlight, or
> >> >> anything PPS really, and they're either unlocked (assuming the caller
> >> >> handles PPS lock) or locked (the function itself takes the lock).
> >> >
> >> > The PPS and VDD handling steps are dependent (PPS must be locked for
> >> > enabling VDD) and both are skipped for the same reason during AUX
> >> > transfers. So I thought it makes sense to move these to a separate
> >> > function and skip both based on the same platform/output type check.
> >> 
> >> On the contrary, I think the reasons are different.
> >> 
> >> VDD is only needed for eDP.
> >> 
> >> The PPS must be locked for VDD change (IOW for eDP) and for VLV/CHV pipe
> >> based PPS. But these two cases are independent.
> >
> > The case requiring VDD (eDP) is a subset of the cases requring PPS to be
> > locked (eDP or VLV/CHV). These are not independent cases.
> 
> Logically, they are. VLV/CHV requires the PPS lock also for
> non-eDP. 

Yes, that is what I meant.

1. Cases needing PPS lock: eDP or non-eDP on VLV/CHV.
2. Case needing VDD: eDP.

2. is a subset of 1.

> It's not a subset.

> 
> BR,
> Jani.
> 
> 
> 
> >
> >> >> This one purports to be an interface for lock/unlock, but in reality it
> >> >> also does VDD internally. And that feels really quite wrong to me.
> >> >> 
> >> >> ---
> >> >> 
> >> >> These are a single-use interface that I think make intel_pps.[ch] more
> >> >> difficult to understand. I'd suggest checking how you'd implement this
> >> >> logic inside intel_dp_aux_xfer() *without* changing the intel_pps.[ch]
> >> >> interface at all.
> >> >> 
> >> >> Okay, took a quick stab at it, and unless I'm missing something it's
> >> >> super easy:
> >> >
> >> > I still think it'd be better to have a separate function for both
> >> > locking PPS and enabling VDD for the reason I described above, that is
> >> > to clarify that the PPS state must be locked to enable VDD.
> >> 
> >> But there's no requirement that they must be done at the same time.
> >
> > There is also no reason not do them at the same time for AUX. A benefit
> > of doing that would be to clarify the dependency of VDD on PPS and also
> > simplify intel_dp_aux_xfer().
> >
> >> The PPS lock could be held for a much longer period or for other
> >> things than just VDD. And in this case, the PPS lock may indeed
> >> protect *other* things than just VDD. Adding the separate function
> >> ties these unrelated cases together for IMO not good enough reason.
> >> intel_pps_vdd_on_unlocked() does check that it's called with the PPS
> >> lock held.
> >> 
> >> But I realize it needs to be relaxed a bit like this:
> >
> > Yes, noticed this too. It was one reason I opted for skipping PPS
> > locking / VDD enabling from one spot.
> >
> >> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> >> index 617ce4993172..c883e872c9c8 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> >> @@ -744,11 +744,11 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
> >>  	i915_reg_t pp_stat_reg, pp_ctrl_reg;
> >>  	bool need_to_disable = !intel_dp->pps.want_panel_vdd;
> >>  
> >> -	lockdep_assert_held(&display->pps.mutex);
> >> -
> >>  	if (!intel_dp_is_edp(intel_dp))
> >>  		return false;
> >>  
> >> +	lockdep_assert_held(&display->pps.mutex);
> >> +
> >>  	cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
> >>  	intel_dp->pps.want_panel_vdd = true;
> >>  
> >> @@ -925,11 +925,11 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
> >>  {
> >>  	struct intel_display *display = to_intel_display(intel_dp);
> >>  
> >> -	lockdep_assert_held(&display->pps.mutex);
> >> -
> >>  	if (!intel_dp_is_edp(intel_dp))
> >>  		return;
> >>  
> >> +	lockdep_assert_held(&display->pps.mutex);
> >> +
> >>  	INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,
> >>  				 "[ENCODER:%d:%s] %s VDD not forced on",
> >>  				 dp_to_dig_port(intel_dp)->base.base.base.id,
> >> 
> >> 
> >> > I guess the above could be done separately later in any case, so I can
> >> > inline the fix as you suggest.
> >> >
> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> >> >> index ec27bbd70bcf..a5608659df59 100644
> >> >> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> >> >> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> >> >> @@ -247,7 +247,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >> >>  	u32 aux_clock_divider;
> >> >>  	enum intel_display_power_domain aux_domain;
> >> >>  	intel_wakeref_t aux_wakeref;
> >> >> -	intel_wakeref_t pps_wakeref;
> >> >> +	intel_wakeref_t pps_wakeref = NULL;
> >> >>  	int i, ret, recv_bytes;
> >> >>  	int try, clock = 0;
> >> >>  	u32 status;
> >> >> @@ -272,7 +272,10 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >> >>  	aux_domain = intel_aux_power_domain(dig_port);
> >> >>  
> >> >>  	aux_wakeref = intel_display_power_get(display, aux_domain);
> >> >> -	pps_wakeref = intel_pps_lock(intel_dp);
> >> >> +
> >> >> +	if (intel_dp_is_edp(intel_dp) ||
> >> >> +	    (display->platform.valleyview || display->platform.cherryview))
> >> >> +		pps_wakeref = intel_pps_lock(intel_dp);
> >> >>  
> >> >>  	/*
> >> >>  	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
> >> >> @@ -430,7 +433,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> >> >>  	if (vdd)
> >> >>  		intel_pps_vdd_off_unlocked(intel_dp, false);
> >> >>  
> >> >> -	intel_pps_unlock(intel_dp, pps_wakeref);
> >> >> +	if (pps_wakeref)
> >> >> +		intel_pps_unlock(intel_dp, pps_wakeref);
> >> >>  	intel_display_power_put_async(display, aux_domain, aux_wakeref);
> >> >>  out_unlock:
> >> >>  	intel_digital_port_unlock(encoder);
> >> >> 
> >> >> 
> >> >> Please let's not make intel_pps.[ch] harder to understand.
> >> >> 
> >> >> 
> >> >> BR,
> >> >> Jani.
> >> >> 
> >> >> 
> >> >> > +
> >> >> >  void intel_pps_on_unlocked(struct intel_dp *intel_dp)
> >> >> >  {
> >> >> >  	struct intel_display *display = to_intel_display(intel_dp);
> >> >> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
> >> >> > index c83007152f07d..4390d05892325 100644
> >> >> > --- a/drivers/gpu/drm/i915/display/intel_pps.h
> >> >> > +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> >> >> > @@ -31,10 +31,11 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
> >> >> >  void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
> >> >> >  void intel_pps_on_unlocked(struct intel_dp *intel_dp);
> >> >> >  void intel_pps_off_unlocked(struct intel_dp *intel_dp);
> >> >> > -void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
> >> >> >  
> >> >> >  void intel_pps_vdd_on(struct intel_dp *intel_dp);
> >> >> >  void intel_pps_vdd_off(struct intel_dp *intel_dp);
> >> >> > +intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref);
> >> >> > +void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref);
> >> >> >  void intel_pps_on(struct intel_dp *intel_dp);
> >> >> >  void intel_pps_off(struct intel_dp *intel_dp);
> >> >> >  void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
> >> >> 
> >> >> -- 
> >> >> Jani Nikula, Intel
> >> 
> >> -- 
> >> Jani Nikula, Intel
> 
> -- 
> Jani Nikula, Intel

Re: [PATCH 1/3] drm/i915/pps: Add helpers to lock PPS for AUX transfers

[Jani Nikula]

On Mon, 24 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
> On Mon, Mar 24, 2025 at 03:59:50PM +0200, Jani Nikula wrote:
>> On Mon, 24 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
>> > On Mon, Mar 24, 2025 at 02:28:35PM +0200, Jani Nikula wrote:
>> >> On Mon, 24 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
>> >> > On Mon, Mar 24, 2025 at 12:33:22PM +0200, Jani Nikula wrote:
>> >> >> On Fri, 21 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
>> >> >> > Factor out from the DP AUX transfer function the logic to lock/unlock
>> >> >> > the Panel Power Sequencer state and enable/disable the VDD power
>> >> >> > required for the AUX transfer, adding these to helpers in intel_pps.c .
>> >> >> > This prepares for a follow-up change making these steps dependent on the
>> >> >> > platform and output type.
>> >> >> >
>> >> >> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>> >> >> > ---
>> >> >> >  drivers/gpu/drm/i915/display/intel_dp_aux.c | 16 ++----------
>> >> >> >  drivers/gpu/drm/i915/display/intel_pps.c    | 29 ++++++++++++++++++++-
>> >> >> >  drivers/gpu/drm/i915/display/intel_pps.h    |  3 ++-
>> >> >> >  3 files changed, 32 insertions(+), 16 deletions(-)
>> >> >> >
>> >> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> >> >> > index ec27bbd70bcf0..bf5ccfa24ca0b 100644
>> >> >> > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> >> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> >> >> > @@ -272,15 +272,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> >> >> >  	aux_domain = intel_aux_power_domain(dig_port);
>> >> >> >  
>> >> >> >  	aux_wakeref = intel_display_power_get(display, aux_domain);
>> >> >> > -	pps_wakeref = intel_pps_lock(intel_dp);
>> >> >> > -
>> >> >> > -	/*
>> >> >> > -	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
>> >> >> > -	 * In such cases we want to leave VDD enabled and it's up to upper layers
>> >> >> > -	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
>> >> >> > -	 * ourselves.
>> >> >> > -	 */
>> >> >> > -	vdd = intel_pps_vdd_on_unlocked(intel_dp);
>> >> >> > +	pps_wakeref = intel_pps_lock_for_aux(intel_dp, &vdd);
>> >> >> >  
>> >> >> >  	/*
>> >> >> >  	 * dp aux is extremely sensitive to irq latency, hence request the
>> >> >> > @@ -289,8 +281,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> >> >> >  	 */
>> >> >> >  	cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
>> >> >> >  
>> >> >> > -	intel_pps_check_power_unlocked(intel_dp);
>> >> >> > -
>> >> >> >  	/*
>> >> >> >  	 * FIXME PSR should be disabled here to prevent
>> >> >> >  	 * it using the same AUX CH simultaneously
>> >> >> > @@ -427,10 +417,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> >> >> >  out:
>> >> >> >  	cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
>> >> >> >  
>> >> >> > -	if (vdd)
>> >> >> > -		intel_pps_vdd_off_unlocked(intel_dp, false);
>> >> >> > +	intel_pps_unlock_for_aux(intel_dp, pps_wakeref, vdd);
>> >> >> >  
>> >> >> > -	intel_pps_unlock(intel_dp, pps_wakeref);
>> >> >> >  	intel_display_power_put_async(display, aux_domain, aux_wakeref);
>> >> >> >  out_unlock:
>> >> >> >  	intel_digital_port_unlock(encoder);
>> >> >> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
>> >> >> > index 617ce49931726..3c078fd53fbfa 100644
>> >> >> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> >> >> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> >> >> > @@ -571,7 +571,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>> >> >> >  	return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
>> >> >> >  }
>> >> >> >  
>> >> >> > -void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
>> >> >> > +static void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
>> >> >> >  {
>> >> >> >  	struct intel_display *display = to_intel_display(intel_dp);
>> >> >> >  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> >> >> > @@ -955,6 +955,33 @@ void intel_pps_vdd_off(struct intel_dp *intel_dp)
>> >> >> >  		intel_pps_vdd_off_unlocked(intel_dp, false);
>> >> >> >  }
>> >> >> >  
>> >> >> > +intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
>> >> >> > +{
>> >> >> > +	intel_wakeref_t wakeref;
>> >> >> > +
>> >> >> > +	wakeref = intel_pps_lock(intel_dp);
>> >> >> > +
>> >> >> > +	/*
>> >> >> > +	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
>> >> >> > +	 * In such cases we want to leave VDD enabled and it's up to upper layers
>> >> >> > +	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
>> >> >> > +	 * ourselves.
>> >> >> > +	 */
>> >> >> > +	*vdd_ref = intel_pps_vdd_on_unlocked(intel_dp);
>> >> >> > +
>> >> >> > +	intel_pps_check_power_unlocked(intel_dp);
>> >> >> > +
>> >> >> > +	return wakeref;
>> >> >> > +}
>> >> >> > +
>> >> >> > +void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref)
>> >> >> > +{
>> >> >> > +	if (vdd_ref)
>> >> >> > +		intel_pps_vdd_off_unlocked(intel_dp, false);
>> >> >> > +
>> >> >> > +	intel_pps_unlock(intel_dp, wakeref);
>> >> >> > +}
>> >> >> 
>> >> >> It took me a while to pinpoint what exactly I don't like about this
>> >> >> interface.
>> >> >> 
>> >> >> And I mean the whole intel_pps.h interface is already really difficult
>> >> >> to understand.
>> >> >> 
>> >> >> This flips the lock/unlock and vdd on/off logic inside out.
>> >> >> 
>> >> >> Normally you have functions for doing vdd or power or backlight, or
>> >> >> anything PPS really, and they're either unlocked (assuming the caller
>> >> >> handles PPS lock) or locked (the function itself takes the lock).
>> >> >
>> >> > The PPS and VDD handling steps are dependent (PPS must be locked for
>> >> > enabling VDD) and both are skipped for the same reason during AUX
>> >> > transfers. So I thought it makes sense to move these to a separate
>> >> > function and skip both based on the same platform/output type check.
>> >> 
>> >> On the contrary, I think the reasons are different.
>> >> 
>> >> VDD is only needed for eDP.
>> >> 
>> >> The PPS must be locked for VDD change (IOW for eDP) and for VLV/CHV pipe
>> >> based PPS. But these two cases are independent.
>> >
>> > The case requiring VDD (eDP) is a subset of the cases requring PPS to be
>> > locked (eDP or VLV/CHV). These are not independent cases.
>> 
>> Logically, they are. VLV/CHV requires the PPS lock also for
>> non-eDP. 
>
> Yes, that is what I meant.
>
> 1. Cases needing PPS lock: eDP or non-eDP on VLV/CHV.
> 2. Case needing VDD: eDP.
>
> 2. is a subset of 1.

I see what you mean but I disagree that they should be tied together
this way. I think they should remain separate as they are, and I think
it's easier to understand that way.

BR,
Jani.



>
>> It's not a subset.
>
>> 
>> BR,
>> Jani.
>> 
>> 
>> 
>> >
>> >> >> This one purports to be an interface for lock/unlock, but in reality it
>> >> >> also does VDD internally. And that feels really quite wrong to me.
>> >> >> 
>> >> >> ---
>> >> >> 
>> >> >> These are a single-use interface that I think make intel_pps.[ch] more
>> >> >> difficult to understand. I'd suggest checking how you'd implement this
>> >> >> logic inside intel_dp_aux_xfer() *without* changing the intel_pps.[ch]
>> >> >> interface at all.
>> >> >> 
>> >> >> Okay, took a quick stab at it, and unless I'm missing something it's
>> >> >> super easy:
>> >> >
>> >> > I still think it'd be better to have a separate function for both
>> >> > locking PPS and enabling VDD for the reason I described above, that is
>> >> > to clarify that the PPS state must be locked to enable VDD.
>> >> 
>> >> But there's no requirement that they must be done at the same time.
>> >
>> > There is also no reason not do them at the same time for AUX. A benefit
>> > of doing that would be to clarify the dependency of VDD on PPS and also
>> > simplify intel_dp_aux_xfer().
>> >
>> >> The PPS lock could be held for a much longer period or for other
>> >> things than just VDD. And in this case, the PPS lock may indeed
>> >> protect *other* things than just VDD. Adding the separate function
>> >> ties these unrelated cases together for IMO not good enough reason.
>> >> intel_pps_vdd_on_unlocked() does check that it's called with the PPS
>> >> lock held.
>> >> 
>> >> But I realize it needs to be relaxed a bit like this:
>> >
>> > Yes, noticed this too. It was one reason I opted for skipping PPS
>> > locking / VDD enabling from one spot.
>> >
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
>> >> index 617ce4993172..c883e872c9c8 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> >> @@ -744,11 +744,11 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
>> >>  	i915_reg_t pp_stat_reg, pp_ctrl_reg;
>> >>  	bool need_to_disable = !intel_dp->pps.want_panel_vdd;
>> >>  
>> >> -	lockdep_assert_held(&display->pps.mutex);
>> >> -
>> >>  	if (!intel_dp_is_edp(intel_dp))
>> >>  		return false;
>> >>  
>> >> +	lockdep_assert_held(&display->pps.mutex);
>> >> +
>> >>  	cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
>> >>  	intel_dp->pps.want_panel_vdd = true;
>> >>  
>> >> @@ -925,11 +925,11 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
>> >>  {
>> >>  	struct intel_display *display = to_intel_display(intel_dp);
>> >>  
>> >> -	lockdep_assert_held(&display->pps.mutex);
>> >> -
>> >>  	if (!intel_dp_is_edp(intel_dp))
>> >>  		return;
>> >>  
>> >> +	lockdep_assert_held(&display->pps.mutex);
>> >> +
>> >>  	INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,
>> >>  				 "[ENCODER:%d:%s] %s VDD not forced on",
>> >>  				 dp_to_dig_port(intel_dp)->base.base.base.id,
>> >> 
>> >> 
>> >> > I guess the above could be done separately later in any case, so I can
>> >> > inline the fix as you suggest.
>> >> >
>> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> >> >> index ec27bbd70bcf..a5608659df59 100644
>> >> >> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> >> >> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
>> >> >> @@ -247,7 +247,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> >> >>  	u32 aux_clock_divider;
>> >> >>  	enum intel_display_power_domain aux_domain;
>> >> >>  	intel_wakeref_t aux_wakeref;
>> >> >> -	intel_wakeref_t pps_wakeref;
>> >> >> +	intel_wakeref_t pps_wakeref = NULL;
>> >> >>  	int i, ret, recv_bytes;
>> >> >>  	int try, clock = 0;
>> >> >>  	u32 status;
>> >> >> @@ -272,7 +272,10 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> >> >>  	aux_domain = intel_aux_power_domain(dig_port);
>> >> >>  
>> >> >>  	aux_wakeref = intel_display_power_get(display, aux_domain);
>> >> >> -	pps_wakeref = intel_pps_lock(intel_dp);
>> >> >> +
>> >> >> +	if (intel_dp_is_edp(intel_dp) ||
>> >> >> +	    (display->platform.valleyview || display->platform.cherryview))
>> >> >> +		pps_wakeref = intel_pps_lock(intel_dp);
>> >> >>  
>> >> >>  	/*
>> >> >>  	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
>> >> >> @@ -430,7 +433,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>> >> >>  	if (vdd)
>> >> >>  		intel_pps_vdd_off_unlocked(intel_dp, false);
>> >> >>  
>> >> >> -	intel_pps_unlock(intel_dp, pps_wakeref);
>> >> >> +	if (pps_wakeref)
>> >> >> +		intel_pps_unlock(intel_dp, pps_wakeref);
>> >> >>  	intel_display_power_put_async(display, aux_domain, aux_wakeref);
>> >> >>  out_unlock:
>> >> >>  	intel_digital_port_unlock(encoder);
>> >> >> 
>> >> >> 
>> >> >> Please let's not make intel_pps.[ch] harder to understand.
>> >> >> 
>> >> >> 
>> >> >> BR,
>> >> >> Jani.
>> >> >> 
>> >> >> 
>> >> >> > +
>> >> >> >  void intel_pps_on_unlocked(struct intel_dp *intel_dp)
>> >> >> >  {
>> >> >> >  	struct intel_display *display = to_intel_display(intel_dp);
>> >> >> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
>> >> >> > index c83007152f07d..4390d05892325 100644
>> >> >> > --- a/drivers/gpu/drm/i915/display/intel_pps.h
>> >> >> > +++ b/drivers/gpu/drm/i915/display/intel_pps.h
>> >> >> > @@ -31,10 +31,11 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
>> >> >> >  void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
>> >> >> >  void intel_pps_on_unlocked(struct intel_dp *intel_dp);
>> >> >> >  void intel_pps_off_unlocked(struct intel_dp *intel_dp);
>> >> >> > -void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
>> >> >> >  
>> >> >> >  void intel_pps_vdd_on(struct intel_dp *intel_dp);
>> >> >> >  void intel_pps_vdd_off(struct intel_dp *intel_dp);
>> >> >> > +intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref);
>> >> >> > +void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref);
>> >> >> >  void intel_pps_on(struct intel_dp *intel_dp);
>> >> >> >  void intel_pps_off(struct intel_dp *intel_dp);
>> >> >> >  void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
>> >> >> 
>> >> >> -- 
>> >> >> Jani Nikula, Intel
>> >> 
>> >> -- 
>> >> Jani Nikula, Intel
>> 
>> -- 
>> Jani Nikula, Intel

-- 
Jani Nikula, Intel

[PATCH 2/3] drm/i915/dp_mst: Fix side-band message timeouts due to long PPS delays

[Imre Deak]

The Panel Power Sequencer lock held on an eDP port (a) blocks a DP AUX
transfer on another port (b), since the PPS lock is device global, thus
shared by all ports. The PPS lock can be held on port (a) for a longer
period due to the various PPS delays (panel/backlight on/off,
power-cycle delays). This in turn can cause an MST down-message request
on port (b) time out, if the above PPS delay defers the handling of the
reply to the request by more than 100ms: the MST branch device sending
the reply (signaling this via the DP_DOWN_REP_MSG_RDY flag in the
DP_DEVICE_SERVICE_IRQ_VECTOR DPCD register) may cancel the reply
(clearing DP_DOWN_REP_MSG_RDY and the reply message buffer) after 110
ms, if the reply is not processed by that time.

Avoid MST down-message timeouts described above, by locking the PPS
state for AUX transfers only if this is actually required: on eDP ports,
where the VDD power depends on the PPS state and on all DP and eDP ports
on VLV/CHV, where the PPS is a pipe instance and hence a modeset on any
port possibly affecting the PPS state.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_pps.c | 34 ++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 3c078fd53fbfa..7d7157983f25e 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -26,6 +26,11 @@ static void vlv_steal_power_sequencer(struct intel_display *display,
 static void pps_init_delays(struct intel_dp *intel_dp);
 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
 
+static bool intel_pps_is_pipe_instance(struct intel_display *display)
+{
+	return display->platform.valleyview || display->platform.cherryview;
+}
+
 static const char *pps_name(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
@@ -955,10 +960,32 @@ void intel_pps_vdd_off(struct intel_dp *intel_dp)
 		intel_pps_vdd_off_unlocked(intel_dp, false);
 }
 
+static bool aux_needs_pps_lock(struct intel_dp *intel_dp)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	/*
+	 * The PPS state needs to be locked for:
+	 * - eDP on all platforms, since AUX transfers on eDP need VDD power
+	 *   (either forced or via panel power) which depends on the PPS
+	 *   state.
+	 * - non-eDP on platforms where the PPS is a pipe instance (VLV/CHV),
+	 *   since changing the PPS state (via a parallel modeset for
+	 *   instance) may interfere with the AUX transfers on a non-eDP
+	 *   output as well.
+	 */
+	return intel_dp_is_edp(intel_dp) || intel_pps_is_pipe_instance(display);
+}
+
 intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
 {
 	intel_wakeref_t wakeref;
 
+	if (!aux_needs_pps_lock(intel_dp)) {
+		*vdd_ref = false;
+		return NULL;
+	}
+
 	wakeref = intel_pps_lock(intel_dp);
 
 	/*
@@ -976,6 +1003,13 @@ intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
 
 void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref)
 {
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	if (!wakeref) {
+		drm_WARN_ON(display->drm, vdd_ref || aux_needs_pps_lock(intel_dp));
+		return;
+	}
+
 	if (vdd_ref)
 		intel_pps_vdd_off_unlocked(intel_dp, false);
 
-- 
2.44.2

Re: [PATCH 2/3] drm/i915/dp_mst: Fix side-band message timeouts due to long PPS delays

[Ville Syrjälä]

On Fri, Mar 21, 2025 at 04:56:25PM +0200, Imre Deak wrote:
> The Panel Power Sequencer lock held on an eDP port (a) blocks a DP AUX
> transfer on another port (b), since the PPS lock is device global, thus
> shared by all ports. The PPS lock can be held on port (a) for a longer
> period due to the various PPS delays (panel/backlight on/off,
> power-cycle delays). This in turn can cause an MST down-message request
> on port (b) time out, if the above PPS delay defers the handling of the
> reply to the request by more than 100ms: the MST branch device sending
> the reply (signaling this via the DP_DOWN_REP_MSG_RDY flag in the
> DP_DEVICE_SERVICE_IRQ_VECTOR DPCD register) may cancel the reply
> (clearing DP_DOWN_REP_MSG_RDY and the reply message buffer) after 110
> ms, if the reply is not processed by that time.
> 
> Avoid MST down-message timeouts described above, by locking the PPS
> state for AUX transfers only if this is actually required: on eDP ports,
> where the VDD power depends on the PPS state and on all DP and eDP ports
> on VLV/CHV, where the PPS is a pipe instance and hence a modeset on any
> port possibly affecting the PPS state.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_pps.c | 34 ++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index 3c078fd53fbfa..7d7157983f25e 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -26,6 +26,11 @@ static void vlv_steal_power_sequencer(struct intel_display *display,
>  static void pps_init_delays(struct intel_dp *intel_dp);
>  static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
>  
> +static bool intel_pps_is_pipe_instance(struct intel_display *display)
> +{
> +	return display->platform.valleyview || display->platform.cherryview;
> +}
> +
>  static const char *pps_name(struct intel_dp *intel_dp)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> @@ -955,10 +960,32 @@ void intel_pps_vdd_off(struct intel_dp *intel_dp)
>  		intel_pps_vdd_off_unlocked(intel_dp, false);
>  }
>  
> +static bool aux_needs_pps_lock(struct intel_dp *intel_dp)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +
> +	/*
> +	 * The PPS state needs to be locked for:
> +	 * - eDP on all platforms, since AUX transfers on eDP need VDD power
> +	 *   (either forced or via panel power) which depends on the PPS
> +	 *   state.
> +	 * - non-eDP on platforms where the PPS is a pipe instance (VLV/CHV),
> +	 *   since changing the PPS state (via a parallel modeset for
> +	 *   instance) may interfere with the AUX transfers on a non-eDP
> +	 *   output as well.
> +	 */
> +	return intel_dp_is_edp(intel_dp) || intel_pps_is_pipe_instance(display);
> +}
> +
>  intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
>  {
>  	intel_wakeref_t wakeref;
>  
> +	if (!aux_needs_pps_lock(intel_dp)) {
> +		*vdd_ref = false;
> +		return NULL;

I was pondering if we need a define for this since intel_wakeref_t
doesn't look like a pointer, but apparently we use NULLs elsewhere
as well for this stuff.

> +	}
> +
>  	wakeref = intel_pps_lock(intel_dp);
>  
>  	/*
> @@ -976,6 +1003,13 @@ intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
>  
>  void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref)
>  {
> +	struct intel_display *display = to_intel_display(intel_dp);
> +
> +	if (!wakeref) {
> +		drm_WARN_ON(display->drm, vdd_ref || aux_needs_pps_lock(intel_dp));
> +		return;
> +	}
> +
>  	if (vdd_ref)
>  		intel_pps_vdd_off_unlocked(intel_dp, false);
>  
> -- 
> 2.44.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 2/3] drm/i915/dp_mst: Fix side-band message timeouts due to long PPS delays

[Imre Deak]

On Fri, Mar 21, 2025 at 08:00:29PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 21, 2025 at 04:56:25PM +0200, Imre Deak wrote:
> > The Panel Power Sequencer lock held on an eDP port (a) blocks a DP AUX
> > transfer on another port (b), since the PPS lock is device global, thus
> > shared by all ports. The PPS lock can be held on port (a) for a longer
> > period due to the various PPS delays (panel/backlight on/off,
> > power-cycle delays). This in turn can cause an MST down-message request
> > on port (b) time out, if the above PPS delay defers the handling of the
> > reply to the request by more than 100ms: the MST branch device sending
> > the reply (signaling this via the DP_DOWN_REP_MSG_RDY flag in the
> > DP_DEVICE_SERVICE_IRQ_VECTOR DPCD register) may cancel the reply
> > (clearing DP_DOWN_REP_MSG_RDY and the reply message buffer) after 110
> > ms, if the reply is not processed by that time.
> > 
> > Avoid MST down-message timeouts described above, by locking the PPS
> > state for AUX transfers only if this is actually required: on eDP ports,
> > where the VDD power depends on the PPS state and on all DP and eDP ports
> > on VLV/CHV, where the PPS is a pipe instance and hence a modeset on any
> > port possibly affecting the PPS state.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_pps.c | 34 ++++++++++++++++++++++++
> >  1 file changed, 34 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> > index 3c078fd53fbfa..7d7157983f25e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> > @@ -26,6 +26,11 @@ static void vlv_steal_power_sequencer(struct intel_display *display,
> >  static void pps_init_delays(struct intel_dp *intel_dp);
> >  static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
> >  
> > +static bool intel_pps_is_pipe_instance(struct intel_display *display)
> > +{
> > +	return display->platform.valleyview || display->platform.cherryview;
> > +}
> > +
> >  static const char *pps_name(struct intel_dp *intel_dp)
> >  {
> >  	struct intel_display *display = to_intel_display(intel_dp);
> > @@ -955,10 +960,32 @@ void intel_pps_vdd_off(struct intel_dp *intel_dp)
> >  		intel_pps_vdd_off_unlocked(intel_dp, false);
> >  }
> >  
> > +static bool aux_needs_pps_lock(struct intel_dp *intel_dp)
> > +{
> > +	struct intel_display *display = to_intel_display(intel_dp);
> > +
> > +	/*
> > +	 * The PPS state needs to be locked for:
> > +	 * - eDP on all platforms, since AUX transfers on eDP need VDD power
> > +	 *   (either forced or via panel power) which depends on the PPS
> > +	 *   state.
> > +	 * - non-eDP on platforms where the PPS is a pipe instance (VLV/CHV),
> > +	 *   since changing the PPS state (via a parallel modeset for
> > +	 *   instance) may interfere with the AUX transfers on a non-eDP
> > +	 *   output as well.
> > +	 */
> > +	return intel_dp_is_edp(intel_dp) || intel_pps_is_pipe_instance(display);
> > +}
> > +
> >  intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
> >  {
> >  	intel_wakeref_t wakeref;
> >  
> > +	if (!aux_needs_pps_lock(intel_dp)) {
> > +		*vdd_ref = false;
> > +		return NULL;
> 
> I was pondering if we need a define for this since intel_wakeref_t
> doesn't look like a pointer, but apparently we use NULLs elsewhere
> as well for this stuff.

Ok, makes sense. It is a bigger a change though, so is it ok to do that
as a follow up?

> > +	}
> > +
> >  	wakeref = intel_pps_lock(intel_dp);
> >  
> >  	/*
> > @@ -976,6 +1003,13 @@ intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
> >  
> >  void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref)
> >  {
> > +	struct intel_display *display = to_intel_display(intel_dp);
> > +
> > +	if (!wakeref) {
> > +		drm_WARN_ON(display->drm, vdd_ref || aux_needs_pps_lock(intel_dp));
> > +		return;
> > +	}
> > +
> >  	if (vdd_ref)
> >  		intel_pps_vdd_off_unlocked(intel_dp, false);
> >  
> > -- 
> > 2.44.2
> 
> -- 
> Ville Syrjälä
> Intel

Re: [PATCH 2/3] drm/i915/dp_mst: Fix side-band message timeouts due to long PPS delays

[Ville Syrjälä]

On Fri, Mar 21, 2025 at 08:38:45PM +0200, Imre Deak wrote:
> On Fri, Mar 21, 2025 at 08:00:29PM +0200, Ville Syrjälä wrote:
> > On Fri, Mar 21, 2025 at 04:56:25PM +0200, Imre Deak wrote:
> > > The Panel Power Sequencer lock held on an eDP port (a) blocks a DP AUX
> > > transfer on another port (b), since the PPS lock is device global, thus
> > > shared by all ports. The PPS lock can be held on port (a) for a longer
> > > period due to the various PPS delays (panel/backlight on/off,
> > > power-cycle delays). This in turn can cause an MST down-message request
> > > on port (b) time out, if the above PPS delay defers the handling of the
> > > reply to the request by more than 100ms: the MST branch device sending
> > > the reply (signaling this via the DP_DOWN_REP_MSG_RDY flag in the
> > > DP_DEVICE_SERVICE_IRQ_VECTOR DPCD register) may cancel the reply
> > > (clearing DP_DOWN_REP_MSG_RDY and the reply message buffer) after 110
> > > ms, if the reply is not processed by that time.
> > > 
> > > Avoid MST down-message timeouts described above, by locking the PPS
> > > state for AUX transfers only if this is actually required: on eDP ports,
> > > where the VDD power depends on the PPS state and on all DP and eDP ports
> > > on VLV/CHV, where the PPS is a pipe instance and hence a modeset on any
> > > port possibly affecting the PPS state.
> > > 
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_pps.c | 34 ++++++++++++++++++++++++
> > >  1 file changed, 34 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> > > index 3c078fd53fbfa..7d7157983f25e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_pps.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> > > @@ -26,6 +26,11 @@ static void vlv_steal_power_sequencer(struct intel_display *display,
> > >  static void pps_init_delays(struct intel_dp *intel_dp);
> > >  static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
> > >  
> > > +static bool intel_pps_is_pipe_instance(struct intel_display *display)
> > > +{
> > > +	return display->platform.valleyview || display->platform.cherryview;
> > > +}
> > > +
> > >  static const char *pps_name(struct intel_dp *intel_dp)
> > >  {
> > >  	struct intel_display *display = to_intel_display(intel_dp);
> > > @@ -955,10 +960,32 @@ void intel_pps_vdd_off(struct intel_dp *intel_dp)
> > >  		intel_pps_vdd_off_unlocked(intel_dp, false);
> > >  }
> > >  
> > > +static bool aux_needs_pps_lock(struct intel_dp *intel_dp)
> > > +{
> > > +	struct intel_display *display = to_intel_display(intel_dp);
> > > +
> > > +	/*
> > > +	 * The PPS state needs to be locked for:
> > > +	 * - eDP on all platforms, since AUX transfers on eDP need VDD power
> > > +	 *   (either forced or via panel power) which depends on the PPS
> > > +	 *   state.
> > > +	 * - non-eDP on platforms where the PPS is a pipe instance (VLV/CHV),
> > > +	 *   since changing the PPS state (via a parallel modeset for
> > > +	 *   instance) may interfere with the AUX transfers on a non-eDP
> > > +	 *   output as well.
> > > +	 */
> > > +	return intel_dp_is_edp(intel_dp) || intel_pps_is_pipe_instance(display);
> > > +}
> > > +
> > >  intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
> > >  {
> > >  	intel_wakeref_t wakeref;
> > >  
> > > +	if (!aux_needs_pps_lock(intel_dp)) {
> > > +		*vdd_ref = false;
> > > +		return NULL;
> > 
> > I was pondering if we need a define for this since intel_wakeref_t
> > doesn't look like a pointer, but apparently we use NULLs elsewhere
> > as well for this stuff.
> 
> Ok, makes sense. It is a bigger a change though, so is it ok to do that
> as a follow up?

I'm not sure what we even should do about it. Should all the
naked NULLs be hidden, or should we make the thing look like the
pointer it actually is?

> 
> > > +	}
> > > +
> > >  	wakeref = intel_pps_lock(intel_dp);
> > >  
> > >  	/*
> > > @@ -976,6 +1003,13 @@ intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
> > >  
> > >  void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref)
> > >  {
> > > +	struct intel_display *display = to_intel_display(intel_dp);
> > > +
> > > +	if (!wakeref) {
> > > +		drm_WARN_ON(display->drm, vdd_ref || aux_needs_pps_lock(intel_dp));
> > > +		return;
> > > +	}
> > > +
> > >  	if (vdd_ref)
> > >  		intel_pps_vdd_off_unlocked(intel_dp, false);
> > >  
> > > -- 
> > > 2.44.2
> > 
> > -- 
> > Ville Syrjälä
> > Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH 2/3] drm/i915/dp_mst: Fix side-band message timeouts due to long PPS delays

[Imre Deak]

On Fri, Mar 21, 2025 at 08:44:22PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 21, 2025 at 08:38:45PM +0200, Imre Deak wrote:
> > On Fri, Mar 21, 2025 at 08:00:29PM +0200, Ville Syrjälä wrote:
> > > On Fri, Mar 21, 2025 at 04:56:25PM +0200, Imre Deak wrote:
> > > > The Panel Power Sequencer lock held on an eDP port (a) blocks a DP AUX
> > > > transfer on another port (b), since the PPS lock is device global, thus
> > > > shared by all ports. The PPS lock can be held on port (a) for a longer
> > > > period due to the various PPS delays (panel/backlight on/off,
> > > > power-cycle delays). This in turn can cause an MST down-message request
> > > > on port (b) time out, if the above PPS delay defers the handling of the
> > > > reply to the request by more than 100ms: the MST branch device sending
> > > > the reply (signaling this via the DP_DOWN_REP_MSG_RDY flag in the
> > > > DP_DEVICE_SERVICE_IRQ_VECTOR DPCD register) may cancel the reply
> > > > (clearing DP_DOWN_REP_MSG_RDY and the reply message buffer) after 110
> > > > ms, if the reply is not processed by that time.
> > > > 
> > > > Avoid MST down-message timeouts described above, by locking the PPS
> > > > state for AUX transfers only if this is actually required: on eDP ports,
> > > > where the VDD power depends on the PPS state and on all DP and eDP ports
> > > > on VLV/CHV, where the PPS is a pipe instance and hence a modeset on any
> > > > port possibly affecting the PPS state.
> > > > 
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_pps.c | 34 ++++++++++++++++++++++++
> > > >  1 file changed, 34 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> > > > index 3c078fd53fbfa..7d7157983f25e 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_pps.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> > > > @@ -26,6 +26,11 @@ static void vlv_steal_power_sequencer(struct intel_display *display,
> > > >  static void pps_init_delays(struct intel_dp *intel_dp);
> > > >  static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
> > > >  
> > > > +static bool intel_pps_is_pipe_instance(struct intel_display *display)
> > > > +{
> > > > +	return display->platform.valleyview || display->platform.cherryview;
> > > > +}
> > > > +
> > > >  static const char *pps_name(struct intel_dp *intel_dp)
> > > >  {
> > > >  	struct intel_display *display = to_intel_display(intel_dp);
> > > > @@ -955,10 +960,32 @@ void intel_pps_vdd_off(struct intel_dp *intel_dp)
> > > >  		intel_pps_vdd_off_unlocked(intel_dp, false);
> > > >  }
> > > >  
> > > > +static bool aux_needs_pps_lock(struct intel_dp *intel_dp)
> > > > +{
> > > > +	struct intel_display *display = to_intel_display(intel_dp);
> > > > +
> > > > +	/*
> > > > +	 * The PPS state needs to be locked for:
> > > > +	 * - eDP on all platforms, since AUX transfers on eDP need VDD power
> > > > +	 *   (either forced or via panel power) which depends on the PPS
> > > > +	 *   state.
> > > > +	 * - non-eDP on platforms where the PPS is a pipe instance (VLV/CHV),
> > > > +	 *   since changing the PPS state (via a parallel modeset for
> > > > +	 *   instance) may interfere with the AUX transfers on a non-eDP
> > > > +	 *   output as well.
> > > > +	 */
> > > > +	return intel_dp_is_edp(intel_dp) || intel_pps_is_pipe_instance(display);
> > > > +}
> > > > +
> > > >  intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
> > > >  {
> > > >  	intel_wakeref_t wakeref;
> > > >  
> > > > +	if (!aux_needs_pps_lock(intel_dp)) {
> > > > +		*vdd_ref = false;
> > > > +		return NULL;
> > > 
> > > I was pondering if we need a define for this since intel_wakeref_t
> > > doesn't look like a pointer, but apparently we use NULLs elsewhere
> > > as well for this stuff.
> > 
> > Ok, makes sense. It is a bigger a change though, so is it ok to do that
> > as a follow up?
> 
> I'm not sure what we even should do about it. Should all the
> naked NULLs be hidden, or should we make the thing look like the
> pointer it actually is?

The latter, i.e.

#define INTEL_WAKEREF_NONE ((intel_wakeref_t)0)

?

> > > > +	}
> > > > +
> > > >  	wakeref = intel_pps_lock(intel_dp);
> > > >  
> > > >  	/*
> > > > @@ -976,6 +1003,13 @@ intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
> > > >  
> > > >  void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref)
> > > >  {
> > > > +	struct intel_display *display = to_intel_display(intel_dp);
> > > > +
> > > > +	if (!wakeref) {
> > > > +		drm_WARN_ON(display->drm, vdd_ref || aux_needs_pps_lock(intel_dp));
> > > > +		return;
> > > > +	}
> > > > +
> > > >  	if (vdd_ref)
> > > >  		intel_pps_vdd_off_unlocked(intel_dp, false);
> > > >  
> > > > -- 
> > > > 2.44.2
> > > 
> > > -- 
> > > Ville Syrjälä
> > > Intel
> 
> -- 
> Ville Syrjälä
> Intel

Re: [PATCH 2/3] drm/i915/dp_mst: Fix side-band message timeouts due to long PPS delays

[Jani Nikula]

On Fri, 21 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
> On Fri, Mar 21, 2025 at 08:44:22PM +0200, Ville Syrjälä wrote:
>> On Fri, Mar 21, 2025 at 08:38:45PM +0200, Imre Deak wrote:
>> > On Fri, Mar 21, 2025 at 08:00:29PM +0200, Ville Syrjälä wrote:
>> > > On Fri, Mar 21, 2025 at 04:56:25PM +0200, Imre Deak wrote:
>> > > > The Panel Power Sequencer lock held on an eDP port (a) blocks a DP AUX
>> > > > transfer on another port (b), since the PPS lock is device global, thus
>> > > > shared by all ports. The PPS lock can be held on port (a) for a longer
>> > > > period due to the various PPS delays (panel/backlight on/off,
>> > > > power-cycle delays). This in turn can cause an MST down-message request
>> > > > on port (b) time out, if the above PPS delay defers the handling of the
>> > > > reply to the request by more than 100ms: the MST branch device sending
>> > > > the reply (signaling this via the DP_DOWN_REP_MSG_RDY flag in the
>> > > > DP_DEVICE_SERVICE_IRQ_VECTOR DPCD register) may cancel the reply
>> > > > (clearing DP_DOWN_REP_MSG_RDY and the reply message buffer) after 110
>> > > > ms, if the reply is not processed by that time.
>> > > > 
>> > > > Avoid MST down-message timeouts described above, by locking the PPS
>> > > > state for AUX transfers only if this is actually required: on eDP ports,
>> > > > where the VDD power depends on the PPS state and on all DP and eDP ports
>> > > > on VLV/CHV, where the PPS is a pipe instance and hence a modeset on any
>> > > > port possibly affecting the PPS state.
>> > > > 
>> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
>> > > > ---
>> > > >  drivers/gpu/drm/i915/display/intel_pps.c | 34 ++++++++++++++++++++++++
>> > > >  1 file changed, 34 insertions(+)
>> > > > 
>> > > > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
>> > > > index 3c078fd53fbfa..7d7157983f25e 100644
>> > > > --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> > > > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> > > > @@ -26,6 +26,11 @@ static void vlv_steal_power_sequencer(struct intel_display *display,
>> > > >  static void pps_init_delays(struct intel_dp *intel_dp);
>> > > >  static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
>> > > >  
>> > > > +static bool intel_pps_is_pipe_instance(struct intel_display *display)
>> > > > +{
>> > > > +	return display->platform.valleyview || display->platform.cherryview;
>> > > > +}
>> > > > +
>> > > >  static const char *pps_name(struct intel_dp *intel_dp)
>> > > >  {
>> > > >  	struct intel_display *display = to_intel_display(intel_dp);
>> > > > @@ -955,10 +960,32 @@ void intel_pps_vdd_off(struct intel_dp *intel_dp)
>> > > >  		intel_pps_vdd_off_unlocked(intel_dp, false);
>> > > >  }
>> > > >  
>> > > > +static bool aux_needs_pps_lock(struct intel_dp *intel_dp)
>> > > > +{
>> > > > +	struct intel_display *display = to_intel_display(intel_dp);
>> > > > +
>> > > > +	/*
>> > > > +	 * The PPS state needs to be locked for:
>> > > > +	 * - eDP on all platforms, since AUX transfers on eDP need VDD power
>> > > > +	 *   (either forced or via panel power) which depends on the PPS
>> > > > +	 *   state.
>> > > > +	 * - non-eDP on platforms where the PPS is a pipe instance (VLV/CHV),
>> > > > +	 *   since changing the PPS state (via a parallel modeset for
>> > > > +	 *   instance) may interfere with the AUX transfers on a non-eDP
>> > > > +	 *   output as well.
>> > > > +	 */
>> > > > +	return intel_dp_is_edp(intel_dp) || intel_pps_is_pipe_instance(display);
>> > > > +}
>> > > > +
>> > > >  intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
>> > > >  {
>> > > >  	intel_wakeref_t wakeref;
>> > > >  
>> > > > +	if (!aux_needs_pps_lock(intel_dp)) {
>> > > > +		*vdd_ref = false;
>> > > > +		return NULL;
>> > > 
>> > > I was pondering if we need a define for this since intel_wakeref_t
>> > > doesn't look like a pointer, but apparently we use NULLs elsewhere
>> > > as well for this stuff.
>> > 
>> > Ok, makes sense. It is a bigger a change though, so is it ok to do that
>> > as a follow up?
>> 
>> I'm not sure what we even should do about it. Should all the
>> naked NULLs be hidden, or should we make the thing look like the
>> pointer it actually is?
>
> The latter, i.e.
>
> #define INTEL_WAKEREF_NONE ((intel_wakeref_t)0)

I've been leaning towards making it the pointer it actually is,
i.e. struct ref_tracker *. See the new intel_display_rpm.[ch].

But I have much stronger objections to patches 1 and 2 than this [1].


BR,
Jani.


[1] https://lore.kernel.org/r/874izibtvx.fsf@intel.com




>
> ?
>
>> > > > +	}
>> > > > +
>> > > >  	wakeref = intel_pps_lock(intel_dp);
>> > > >  
>> > > >  	/*
>> > > > @@ -976,6 +1003,13 @@ intel_wakeref_t intel_pps_lock_for_aux(struct intel_dp *intel_dp, bool *vdd_ref)
>> > > >  
>> > > >  void intel_pps_unlock_for_aux(struct intel_dp *intel_dp, intel_wakeref_t wakeref, bool vdd_ref)
>> > > >  {
>> > > > +	struct intel_display *display = to_intel_display(intel_dp);
>> > > > +
>> > > > +	if (!wakeref) {
>> > > > +		drm_WARN_ON(display->drm, vdd_ref || aux_needs_pps_lock(intel_dp));
>> > > > +		return;
>> > > > +	}
>> > > > +
>> > > >  	if (vdd_ref)
>> > > >  		intel_pps_vdd_off_unlocked(intel_dp, false);
>> > > >  
>> > > > -- 
>> > > > 2.44.2
>> > > 
>> > > -- 
>> > > Ville Syrjälä
>> > > Intel
>> 
>> -- 
>> Ville Syrjälä
>> Intel

-- 
Jani Nikula, Intel

[PATCH 3/3] drm/i915/pps: Use intel_pps_is_pipe_instance() instead of open-coding it

[Imre Deak]

Use intel_pps_is_pipe_instance() instead of open-coding the same for all
conditional PPS programming required for a pipe instance PPS.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c    |  6 +++---
 drivers/gpu/drm/i915/display/intel_dp.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_pps.c | 18 +++++++++---------
 drivers/gpu/drm/i915/display/intel_pps.h |  2 ++
 4 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 55b9e9bfcc4d0..f527b455ce904 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -474,7 +474,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
 
 	msleep(intel_dp->pps.panel_power_down_delay);
 
-	if (display->platform.valleyview || display->platform.cherryview)
+	if (intel_pps_is_pipe_instance(display))
 		vlv_pps_port_disable(encoder, old_crtc_state);
 }
 
@@ -685,7 +685,7 @@ static void intel_enable_dp(struct intel_atomic_state *state,
 		return;
 
 	with_intel_pps_lock(intel_dp, wakeref) {
-		if (display->platform.valleyview || display->platform.cherryview)
+		if (intel_pps_is_pipe_instance(display))
 			vlv_pps_port_enable_unlocked(encoder, pipe_config);
 
 		intel_dp_enable_port(intel_dp, pipe_config);
@@ -1265,7 +1265,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
 	intel_dp->reset_link_params = true;
 	intel_dp_invalidate_source_oui(intel_dp);
 
-	if (display->platform.valleyview || display->platform.cherryview)
+	if (intel_pps_is_pipe_instance(display))
 		vlv_pps_pipe_reset(intel_dp);
 
 	intel_pps_encoder_reset(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e3821ccfabe30..b4a0e3775b7b4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6518,7 +6518,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
 	intel_dp_set_default_sink_rates(intel_dp);
 	intel_dp_set_default_max_sink_lane_count(intel_dp);
 
-	if (display->platform.valleyview || display->platform.cherryview)
+	if (intel_pps_is_pipe_instance(display))
 		vlv_pps_pipe_init(intel_dp);
 
 	intel_dp_aux_init(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 7d7157983f25e..7b47346d4d559 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -26,7 +26,7 @@ static void vlv_steal_power_sequencer(struct intel_display *display,
 static void pps_init_delays(struct intel_dp *intel_dp);
 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
 
-static bool intel_pps_is_pipe_instance(struct intel_display *display)
+bool intel_pps_is_pipe_instance(struct intel_display *display)
 {
 	return display->platform.valleyview || display->platform.cherryview;
 }
@@ -36,7 +36,7 @@ static const char *pps_name(struct intel_dp *intel_dp)
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_pps *pps = &intel_dp->pps;
 
-	if (display->platform.valleyview || display->platform.cherryview) {
+	if (intel_pps_is_pipe_instance(display)) {
 		switch (pps->vlv_pps_pipe) {
 		case INVALID_PIPE:
 			/*
@@ -411,7 +411,7 @@ pps_initial_setup(struct intel_dp *intel_dp)
 
 	lockdep_assert_held(&display->pps.mutex);
 
-	if (display->platform.valleyview || display->platform.cherryview) {
+	if (intel_pps_is_pipe_instance(display)) {
 		vlv_initial_power_sequencer_setup(intel_dp);
 		return true;
 	}
@@ -510,7 +510,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
 
 	memset(regs, 0, sizeof(*regs));
 
-	if (display->platform.valleyview || display->platform.cherryview)
+	if (intel_pps_is_pipe_instance(display))
 		pps_idx = vlv_power_sequencer_pipe(intel_dp);
 	else if (display->platform.geminilake || display->platform.broxton)
 		pps_idx = bxt_power_sequencer_idx(intel_dp);
@@ -556,7 +556,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
 
 	lockdep_assert_held(&display->pps.mutex);
 
-	if ((display->platform.valleyview || display->platform.cherryview) &&
+	if (intel_pps_is_pipe_instance(display) &&
 	    intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
 		return false;
 
@@ -569,7 +569,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 
 	lockdep_assert_held(&display->pps.mutex);
 
-	if ((display->platform.valleyview || display->platform.cherryview) &&
+	if (intel_pps_is_pipe_instance(display) &&
 	    intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
 		return false;
 
@@ -1758,7 +1758,7 @@ void intel_pps_encoder_reset(struct intel_dp *intel_dp)
 		 * Reinit the power sequencer also on the resume path, in case
 		 * BIOS did something nasty with it.
 		 */
-		if (display->platform.valleyview || display->platform.cherryview)
+		if (intel_pps_is_pipe_instance(display))
 			vlv_initial_power_sequencer_setup(intel_dp);
 
 		pps_init_delays(intel_dp);
@@ -1797,7 +1797,7 @@ static void pps_init_late(struct intel_dp *intel_dp)
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	struct intel_connector *connector = intel_dp->attached_connector;
 
-	if (display->platform.valleyview || display->platform.cherryview)
+	if (intel_pps_is_pipe_instance(display))
 		return;
 
 	if (intel_num_pps(display) < 2)
@@ -1931,7 +1931,7 @@ void assert_pps_unlocked(struct intel_display *display, enum pipe pipe)
 			MISSING_CASE(port_sel);
 			break;
 		}
-	} else if (display->platform.valleyview || display->platform.cherryview) {
+	} else if (intel_pps_is_pipe_instance(display)) {
 		/* presumably write lock depends on pipe, not port select */
 		pp_reg = PP_CONTROL(display, pipe);
 		panel_pipe = pipe;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index 4390d05892325..1f4eed5fc55b8 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -17,6 +17,8 @@ struct intel_display;
 struct intel_dp;
 struct intel_encoder;
 
+bool intel_pps_is_pipe_instance(struct intel_display *display);
+
 intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp);
 intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref);
 
-- 
2.44.2

Re: [PATCH 3/3] drm/i915/pps: Use intel_pps_is_pipe_instance() instead of open-coding it

[Ville Syrjälä]

On Fri, Mar 21, 2025 at 04:56:26PM +0200, Imre Deak wrote:
> Use intel_pps_is_pipe_instance() instead of open-coding the same for all
> conditional PPS programming required for a pipe instance PPS.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/g4x_dp.c    |  6 +++---
>  drivers/gpu/drm/i915/display/intel_dp.c  |  2 +-
>  drivers/gpu/drm/i915/display/intel_pps.c | 18 +++++++++---------
>  drivers/gpu/drm/i915/display/intel_pps.h |  2 ++
>  4 files changed, 15 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 55b9e9bfcc4d0..f527b455ce904 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -474,7 +474,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
>  
>  	msleep(intel_dp->pps.panel_power_down_delay);
>  
> -	if (display->platform.valleyview || display->platform.cherryview)
> +	if (intel_pps_is_pipe_instance(display))
>  		vlv_pps_port_disable(encoder, old_crtc_state);

Most of these are of this form

if (intel_pps_is_pipe_instance())
	vlv_something();

so using an abstract name for intel_pps_is_pipe_instance()
feels a bit confusing. Maybe it should just be
intel_pps_is_vlv() or somehing?

>  }
>  
> @@ -685,7 +685,7 @@ static void intel_enable_dp(struct intel_atomic_state *state,
>  		return;
>  
>  	with_intel_pps_lock(intel_dp, wakeref) {
> -		if (display->platform.valleyview || display->platform.cherryview)
> +		if (intel_pps_is_pipe_instance(display))
>  			vlv_pps_port_enable_unlocked(encoder, pipe_config);
>  
>  		intel_dp_enable_port(intel_dp, pipe_config);
> @@ -1265,7 +1265,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
>  	intel_dp->reset_link_params = true;
>  	intel_dp_invalidate_source_oui(intel_dp);
>  
> -	if (display->platform.valleyview || display->platform.cherryview)
> +	if (intel_pps_is_pipe_instance(display))
>  		vlv_pps_pipe_reset(intel_dp);
>  
>  	intel_pps_encoder_reset(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index e3821ccfabe30..b4a0e3775b7b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6518,7 +6518,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>  	intel_dp_set_default_sink_rates(intel_dp);
>  	intel_dp_set_default_max_sink_lane_count(intel_dp);
>  
> -	if (display->platform.valleyview || display->platform.cherryview)
> +	if (intel_pps_is_pipe_instance(display))
>  		vlv_pps_pipe_init(intel_dp);
>  
>  	intel_dp_aux_init(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index 7d7157983f25e..7b47346d4d559 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -26,7 +26,7 @@ static void vlv_steal_power_sequencer(struct intel_display *display,
>  static void pps_init_delays(struct intel_dp *intel_dp);
>  static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
>  
> -static bool intel_pps_is_pipe_instance(struct intel_display *display)
> +bool intel_pps_is_pipe_instance(struct intel_display *display)
>  {
>  	return display->platform.valleyview || display->platform.cherryview;
>  }
> @@ -36,7 +36,7 @@ static const char *pps_name(struct intel_dp *intel_dp)
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	struct intel_pps *pps = &intel_dp->pps;
>  
> -	if (display->platform.valleyview || display->platform.cherryview) {
> +	if (intel_pps_is_pipe_instance(display)) {
>  		switch (pps->vlv_pps_pipe) {
>  		case INVALID_PIPE:
>  			/*
> @@ -411,7 +411,7 @@ pps_initial_setup(struct intel_dp *intel_dp)
>  
>  	lockdep_assert_held(&display->pps.mutex);
>  
> -	if (display->platform.valleyview || display->platform.cherryview) {
> +	if (intel_pps_is_pipe_instance(display)) {
>  		vlv_initial_power_sequencer_setup(intel_dp);
>  		return true;
>  	}
> @@ -510,7 +510,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
>  
>  	memset(regs, 0, sizeof(*regs));
>  
> -	if (display->platform.valleyview || display->platform.cherryview)
> +	if (intel_pps_is_pipe_instance(display))
>  		pps_idx = vlv_power_sequencer_pipe(intel_dp);
>  	else if (display->platform.geminilake || display->platform.broxton)
>  		pps_idx = bxt_power_sequencer_idx(intel_dp);
> @@ -556,7 +556,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
>  
>  	lockdep_assert_held(&display->pps.mutex);
>  
> -	if ((display->platform.valleyview || display->platform.cherryview) &&
> +	if (intel_pps_is_pipe_instance(display) &&
>  	    intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
>  		return false;
>  
> @@ -569,7 +569,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>  
>  	lockdep_assert_held(&display->pps.mutex);
>  
> -	if ((display->platform.valleyview || display->platform.cherryview) &&
> +	if (intel_pps_is_pipe_instance(display) &&
>  	    intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
>  		return false;
>  
> @@ -1758,7 +1758,7 @@ void intel_pps_encoder_reset(struct intel_dp *intel_dp)
>  		 * Reinit the power sequencer also on the resume path, in case
>  		 * BIOS did something nasty with it.
>  		 */
> -		if (display->platform.valleyview || display->platform.cherryview)
> +		if (intel_pps_is_pipe_instance(display))
>  			vlv_initial_power_sequencer_setup(intel_dp);
>  
>  		pps_init_delays(intel_dp);
> @@ -1797,7 +1797,7 @@ static void pps_init_late(struct intel_dp *intel_dp)
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	struct intel_connector *connector = intel_dp->attached_connector;
>  
> -	if (display->platform.valleyview || display->platform.cherryview)
> +	if (intel_pps_is_pipe_instance(display))
>  		return;
>  
>  	if (intel_num_pps(display) < 2)
> @@ -1931,7 +1931,7 @@ void assert_pps_unlocked(struct intel_display *display, enum pipe pipe)
>  			MISSING_CASE(port_sel);
>  			break;
>  		}
> -	} else if (display->platform.valleyview || display->platform.cherryview) {
> +	} else if (intel_pps_is_pipe_instance(display)) {
>  		/* presumably write lock depends on pipe, not port select */
>  		pp_reg = PP_CONTROL(display, pipe);
>  		panel_pipe = pipe;
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
> index 4390d05892325..1f4eed5fc55b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.h
> +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> @@ -17,6 +17,8 @@ struct intel_display;
>  struct intel_dp;
>  struct intel_encoder;
>  
> +bool intel_pps_is_pipe_instance(struct intel_display *display);
> +
>  intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp);
>  intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref);
>  
> -- 
> 2.44.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 3/3] drm/i915/pps: Use intel_pps_is_pipe_instance() instead of open-coding it

[Imre Deak]

On Fri, Mar 21, 2025 at 08:03:01PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 21, 2025 at 04:56:26PM +0200, Imre Deak wrote:
> > Use intel_pps_is_pipe_instance() instead of open-coding the same for all
> > conditional PPS programming required for a pipe instance PPS.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/g4x_dp.c    |  6 +++---
> >  drivers/gpu/drm/i915/display/intel_dp.c  |  2 +-
> >  drivers/gpu/drm/i915/display/intel_pps.c | 18 +++++++++---------
> >  drivers/gpu/drm/i915/display/intel_pps.h |  2 ++
> >  4 files changed, 15 insertions(+), 13 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> > index 55b9e9bfcc4d0..f527b455ce904 100644
> > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> > @@ -474,7 +474,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
> >  
> >  	msleep(intel_dp->pps.panel_power_down_delay);
> >  
> > -	if (display->platform.valleyview || display->platform.cherryview)
> > +	if (intel_pps_is_pipe_instance(display))
> >  		vlv_pps_port_disable(encoder, old_crtc_state);
> 
> Most of these are of this form
> 
> if (intel_pps_is_pipe_instance())
> 	vlv_something();
> 
> so using an abstract name for intel_pps_is_pipe_instance()
> feels a bit confusing. Maybe it should just be
> intel_pps_is_vlv() or somehing?

Ok. Imo it makes sense to also indicate that the PPS is not port
specific (which would be the logical way), so how about
intel_pps_is_vlv_pipe_instance() ?

> >  }
> >  
> > @@ -685,7 +685,7 @@ static void intel_enable_dp(struct intel_atomic_state *state,
> >  		return;
> >  
> >  	with_intel_pps_lock(intel_dp, wakeref) {
> > -		if (display->platform.valleyview || display->platform.cherryview)
> > +		if (intel_pps_is_pipe_instance(display))
> >  			vlv_pps_port_enable_unlocked(encoder, pipe_config);
> >  
> >  		intel_dp_enable_port(intel_dp, pipe_config);
> > @@ -1265,7 +1265,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
> >  	intel_dp->reset_link_params = true;
> >  	intel_dp_invalidate_source_oui(intel_dp);
> >  
> > -	if (display->platform.valleyview || display->platform.cherryview)
> > +	if (intel_pps_is_pipe_instance(display))
> >  		vlv_pps_pipe_reset(intel_dp);
> >  
> >  	intel_pps_encoder_reset(intel_dp);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index e3821ccfabe30..b4a0e3775b7b4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -6518,7 +6518,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> >  	intel_dp_set_default_sink_rates(intel_dp);
> >  	intel_dp_set_default_max_sink_lane_count(intel_dp);
> >  
> > -	if (display->platform.valleyview || display->platform.cherryview)
> > +	if (intel_pps_is_pipe_instance(display))
> >  		vlv_pps_pipe_init(intel_dp);
> >  
> >  	intel_dp_aux_init(intel_dp);
> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> > index 7d7157983f25e..7b47346d4d559 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> > @@ -26,7 +26,7 @@ static void vlv_steal_power_sequencer(struct intel_display *display,
> >  static void pps_init_delays(struct intel_dp *intel_dp);
> >  static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
> >  
> > -static bool intel_pps_is_pipe_instance(struct intel_display *display)
> > +bool intel_pps_is_pipe_instance(struct intel_display *display)
> >  {
> >  	return display->platform.valleyview || display->platform.cherryview;
> >  }
> > @@ -36,7 +36,7 @@ static const char *pps_name(struct intel_dp *intel_dp)
> >  	struct intel_display *display = to_intel_display(intel_dp);
> >  	struct intel_pps *pps = &intel_dp->pps;
> >  
> > -	if (display->platform.valleyview || display->platform.cherryview) {
> > +	if (intel_pps_is_pipe_instance(display)) {
> >  		switch (pps->vlv_pps_pipe) {
> >  		case INVALID_PIPE:
> >  			/*
> > @@ -411,7 +411,7 @@ pps_initial_setup(struct intel_dp *intel_dp)
> >  
> >  	lockdep_assert_held(&display->pps.mutex);
> >  
> > -	if (display->platform.valleyview || display->platform.cherryview) {
> > +	if (intel_pps_is_pipe_instance(display)) {
> >  		vlv_initial_power_sequencer_setup(intel_dp);
> >  		return true;
> >  	}
> > @@ -510,7 +510,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
> >  
> >  	memset(regs, 0, sizeof(*regs));
> >  
> > -	if (display->platform.valleyview || display->platform.cherryview)
> > +	if (intel_pps_is_pipe_instance(display))
> >  		pps_idx = vlv_power_sequencer_pipe(intel_dp);
> >  	else if (display->platform.geminilake || display->platform.broxton)
> >  		pps_idx = bxt_power_sequencer_idx(intel_dp);
> > @@ -556,7 +556,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
> >  
> >  	lockdep_assert_held(&display->pps.mutex);
> >  
> > -	if ((display->platform.valleyview || display->platform.cherryview) &&
> > +	if (intel_pps_is_pipe_instance(display) &&
> >  	    intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
> >  		return false;
> >  
> > @@ -569,7 +569,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
> >  
> >  	lockdep_assert_held(&display->pps.mutex);
> >  
> > -	if ((display->platform.valleyview || display->platform.cherryview) &&
> > +	if (intel_pps_is_pipe_instance(display) &&
> >  	    intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
> >  		return false;
> >  
> > @@ -1758,7 +1758,7 @@ void intel_pps_encoder_reset(struct intel_dp *intel_dp)
> >  		 * Reinit the power sequencer also on the resume path, in case
> >  		 * BIOS did something nasty with it.
> >  		 */
> > -		if (display->platform.valleyview || display->platform.cherryview)
> > +		if (intel_pps_is_pipe_instance(display))
> >  			vlv_initial_power_sequencer_setup(intel_dp);
> >  
> >  		pps_init_delays(intel_dp);
> > @@ -1797,7 +1797,7 @@ static void pps_init_late(struct intel_dp *intel_dp)
> >  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> >  	struct intel_connector *connector = intel_dp->attached_connector;
> >  
> > -	if (display->platform.valleyview || display->platform.cherryview)
> > +	if (intel_pps_is_pipe_instance(display))
> >  		return;
> >  
> >  	if (intel_num_pps(display) < 2)
> > @@ -1931,7 +1931,7 @@ void assert_pps_unlocked(struct intel_display *display, enum pipe pipe)
> >  			MISSING_CASE(port_sel);
> >  			break;
> >  		}
> > -	} else if (display->platform.valleyview || display->platform.cherryview) {
> > +	} else if (intel_pps_is_pipe_instance(display)) {
> >  		/* presumably write lock depends on pipe, not port select */
> >  		pp_reg = PP_CONTROL(display, pipe);
> >  		panel_pipe = pipe;
> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
> > index 4390d05892325..1f4eed5fc55b8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pps.h
> > +++ b/drivers/gpu/drm/i915/display/intel_pps.h
> > @@ -17,6 +17,8 @@ struct intel_display;
> >  struct intel_dp;
> >  struct intel_encoder;
> >  
> > +bool intel_pps_is_pipe_instance(struct intel_display *display);
> > +
> >  intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp);
> >  intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref);
> >  
> > -- 
> > 2.44.2
> 
> -- 
> Ville Syrjälä
> Intel

Re: [PATCH 3/3] drm/i915/pps: Use intel_pps_is_pipe_instance() instead of open-coding it

[Jani Nikula]

On Fri, 21 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
> On Fri, Mar 21, 2025 at 08:03:01PM +0200, Ville Syrjälä wrote:
>> On Fri, Mar 21, 2025 at 04:56:26PM +0200, Imre Deak wrote:
>> > Use intel_pps_is_pipe_instance() instead of open-coding the same for all
>> > conditional PPS programming required for a pipe instance PPS.
>> > 
>> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/g4x_dp.c    |  6 +++---
>> >  drivers/gpu/drm/i915/display/intel_dp.c  |  2 +-
>> >  drivers/gpu/drm/i915/display/intel_pps.c | 18 +++++++++---------
>> >  drivers/gpu/drm/i915/display/intel_pps.h |  2 ++
>> >  4 files changed, 15 insertions(+), 13 deletions(-)
>> > 
>> > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
>> > index 55b9e9bfcc4d0..f527b455ce904 100644
>> > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
>> > @@ -474,7 +474,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
>> >  
>> >  	msleep(intel_dp->pps.panel_power_down_delay);
>> >  
>> > -	if (display->platform.valleyview || display->platform.cherryview)
>> > +	if (intel_pps_is_pipe_instance(display))
>> >  		vlv_pps_port_disable(encoder, old_crtc_state);
>> 
>> Most of these are of this form
>> 
>> if (intel_pps_is_pipe_instance())
>> 	vlv_something();
>> 
>> so using an abstract name for intel_pps_is_pipe_instance()
>> feels a bit confusing. Maybe it should just be
>> intel_pps_is_vlv() or somehing?
>
> Ok. Imo it makes sense to also indicate that the PPS is not port
> specific (which would be the logical way), so how about
> intel_pps_is_vlv_pipe_instance() ?

That makes it feel like you could *not* have a pipe based PPS on
vlv/chv, and you'd have to check.

I wanted to hide all those details from the callers by moving it inside
intel_pps.c i.e. this is just a thing you do on vlv/chv.

I'd probably be more receptive to a patch that just moved all the checks
inside intel_pps.c without an additional function.

BR,
Jani.

>
>> >  }
>> >  
>> > @@ -685,7 +685,7 @@ static void intel_enable_dp(struct intel_atomic_state *state,
>> >  		return;
>> >  
>> >  	with_intel_pps_lock(intel_dp, wakeref) {
>> > -		if (display->platform.valleyview || display->platform.cherryview)
>> > +		if (intel_pps_is_pipe_instance(display))
>> >  			vlv_pps_port_enable_unlocked(encoder, pipe_config);
>> >  
>> >  		intel_dp_enable_port(intel_dp, pipe_config);
>> > @@ -1265,7 +1265,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
>> >  	intel_dp->reset_link_params = true;
>> >  	intel_dp_invalidate_source_oui(intel_dp);
>> >  
>> > -	if (display->platform.valleyview || display->platform.cherryview)
>> > +	if (intel_pps_is_pipe_instance(display))
>> >  		vlv_pps_pipe_reset(intel_dp);
>> >  
>> >  	intel_pps_encoder_reset(intel_dp);
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> > index e3821ccfabe30..b4a0e3775b7b4 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> > @@ -6518,7 +6518,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>> >  	intel_dp_set_default_sink_rates(intel_dp);
>> >  	intel_dp_set_default_max_sink_lane_count(intel_dp);
>> >  
>> > -	if (display->platform.valleyview || display->platform.cherryview)
>> > +	if (intel_pps_is_pipe_instance(display))
>> >  		vlv_pps_pipe_init(intel_dp);
>> >  
>> >  	intel_dp_aux_init(intel_dp);
>> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
>> > index 7d7157983f25e..7b47346d4d559 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> > @@ -26,7 +26,7 @@ static void vlv_steal_power_sequencer(struct intel_display *display,
>> >  static void pps_init_delays(struct intel_dp *intel_dp);
>> >  static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
>> >  
>> > -static bool intel_pps_is_pipe_instance(struct intel_display *display)
>> > +bool intel_pps_is_pipe_instance(struct intel_display *display)
>> >  {
>> >  	return display->platform.valleyview || display->platform.cherryview;
>> >  }
>> > @@ -36,7 +36,7 @@ static const char *pps_name(struct intel_dp *intel_dp)
>> >  	struct intel_display *display = to_intel_display(intel_dp);
>> >  	struct intel_pps *pps = &intel_dp->pps;
>> >  
>> > -	if (display->platform.valleyview || display->platform.cherryview) {
>> > +	if (intel_pps_is_pipe_instance(display)) {
>> >  		switch (pps->vlv_pps_pipe) {
>> >  		case INVALID_PIPE:
>> >  			/*
>> > @@ -411,7 +411,7 @@ pps_initial_setup(struct intel_dp *intel_dp)
>> >  
>> >  	lockdep_assert_held(&display->pps.mutex);
>> >  
>> > -	if (display->platform.valleyview || display->platform.cherryview) {
>> > +	if (intel_pps_is_pipe_instance(display)) {
>> >  		vlv_initial_power_sequencer_setup(intel_dp);
>> >  		return true;
>> >  	}
>> > @@ -510,7 +510,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
>> >  
>> >  	memset(regs, 0, sizeof(*regs));
>> >  
>> > -	if (display->platform.valleyview || display->platform.cherryview)
>> > +	if (intel_pps_is_pipe_instance(display))
>> >  		pps_idx = vlv_power_sequencer_pipe(intel_dp);
>> >  	else if (display->platform.geminilake || display->platform.broxton)
>> >  		pps_idx = bxt_power_sequencer_idx(intel_dp);
>> > @@ -556,7 +556,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
>> >  
>> >  	lockdep_assert_held(&display->pps.mutex);
>> >  
>> > -	if ((display->platform.valleyview || display->platform.cherryview) &&
>> > +	if (intel_pps_is_pipe_instance(display) &&
>> >  	    intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
>> >  		return false;
>> >  
>> > @@ -569,7 +569,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>> >  
>> >  	lockdep_assert_held(&display->pps.mutex);
>> >  
>> > -	if ((display->platform.valleyview || display->platform.cherryview) &&
>> > +	if (intel_pps_is_pipe_instance(display) &&
>> >  	    intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
>> >  		return false;
>> >  
>> > @@ -1758,7 +1758,7 @@ void intel_pps_encoder_reset(struct intel_dp *intel_dp)
>> >  		 * Reinit the power sequencer also on the resume path, in case
>> >  		 * BIOS did something nasty with it.
>> >  		 */
>> > -		if (display->platform.valleyview || display->platform.cherryview)
>> > +		if (intel_pps_is_pipe_instance(display))
>> >  			vlv_initial_power_sequencer_setup(intel_dp);
>> >  
>> >  		pps_init_delays(intel_dp);
>> > @@ -1797,7 +1797,7 @@ static void pps_init_late(struct intel_dp *intel_dp)
>> >  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>> >  	struct intel_connector *connector = intel_dp->attached_connector;
>> >  
>> > -	if (display->platform.valleyview || display->platform.cherryview)
>> > +	if (intel_pps_is_pipe_instance(display))
>> >  		return;
>> >  
>> >  	if (intel_num_pps(display) < 2)
>> > @@ -1931,7 +1931,7 @@ void assert_pps_unlocked(struct intel_display *display, enum pipe pipe)
>> >  			MISSING_CASE(port_sel);
>> >  			break;
>> >  		}
>> > -	} else if (display->platform.valleyview || display->platform.cherryview) {
>> > +	} else if (intel_pps_is_pipe_instance(display)) {
>> >  		/* presumably write lock depends on pipe, not port select */
>> >  		pp_reg = PP_CONTROL(display, pipe);
>> >  		panel_pipe = pipe;
>> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
>> > index 4390d05892325..1f4eed5fc55b8 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_pps.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_pps.h
>> > @@ -17,6 +17,8 @@ struct intel_display;
>> >  struct intel_dp;
>> >  struct intel_encoder;
>> >  
>> > +bool intel_pps_is_pipe_instance(struct intel_display *display);
>> > +
>> >  intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp);
>> >  intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref);
>> >  
>> > -- 
>> > 2.44.2
>> 
>> -- 
>> Ville Syrjälä
>> Intel

-- 
Jani Nikula, Intel

✓ i915.CI.BAT: success for drm/i915: Fix DP MST SB message timeouts due to PPS delays

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3043 bytes --]

== Series Details ==

Series: drm/i915: Fix DP MST SB message timeouts due to PPS delays
URL   : https://patchwork.freedesktop.org/series/146600/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_16299 -> Patchwork_146600v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/index.html

Participating hosts (42 -> 41)
------------------------------

  Missing    (1): bat-arlh-2 

Known issues
------------

  Here are the changes found in Patchwork_146600v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@gt_engines:
    - bat-twl-2:          [PASS][1] -> [INCOMPLETE][2] ([i915#12445]) +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/bat-twl-2/igt@i915_selftest@live@gt_engines.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/bat-twl-2/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@workarounds:
    - bat-mtlp-9:         [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-arls-5:         [DMESG-FAIL][5] ([i915#12061]) -> [PASS][6] +1 other test pass
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/bat-arls-5/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/bat-arls-5/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-6:         [DMESG-FAIL][7] ([i915#12061]) -> [PASS][8] +1 other test pass
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
    - bat-arls-6:         [DMESG-FAIL][9] ([i915#12061]) -> [PASS][10] +1 other test pass
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/bat-arls-6/igt@i915_selftest@live@workarounds.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/bat-arls-6/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12445]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12445


Build changes
-------------

  * Linux: CI_DRM_16299 -> Patchwork_146600v1

  CI-20190529: 20190529
  CI_DRM_16299: b15a87713d14b1c2986f47a622c5a8c5458e2396 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8277: 8277
  Patchwork_146600v1: b15a87713d14b1c2986f47a622c5a8c5458e2396 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/index.html

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✗ i915.CI.Full: failure for drm/i915: Fix DP MST SB message timeouts due to PPS delays

[Patchwork]

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== Series Details ==

Series: drm/i915: Fix DP MST SB message timeouts due to PPS delays
URL   : https://patchwork.freedesktop.org/series/146600/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16299_full -> Patchwork_146600v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_146600v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_146600v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 10)
------------------------------

  Missing    (1): shard-snb-0 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_146600v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@plain-flip-fb-recreate-interruptible:
    - shard-tglu:         [PASS][1] -> [FAIL][2] +1 other test fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-tglu-9/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-9/igt@kms_flip@plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-vga1:
    - shard-snb:          [PASS][3] -> [FAIL][4] +2 other tests fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb4/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-vga1.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb7/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-vga1.html

  
Known issues
------------

  Here are the changes found in Patchwork_146600v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@crc32:
    - shard-rkl:          NOTRUN -> [SKIP][5] ([i915#6230])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@api_intel_bb@crc32.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-mtlp:         NOTRUN -> [SKIP][6] ([i915#11078])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-6/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@drm_fdinfo@busy-idle-check-all@vcs0:
    - shard-dg2-9:        NOTRUN -> [SKIP][7] ([i915#11527] / [i915#8414]) +6 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@drm_fdinfo@busy-idle-check-all@vcs0.html

  * igt@drm_fdinfo@busy@rcs0:
    - shard-dg2-9:        NOTRUN -> [SKIP][8] ([i915#8414]) +9 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@drm_fdinfo@busy@rcs0.html

  * igt@drm_fdinfo@virtual-busy:
    - shard-mtlp:         NOTRUN -> [SKIP][9] ([i915#8414])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-6/igt@drm_fdinfo@virtual-busy.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-tglu:         NOTRUN -> [SKIP][10] ([i915#3555] / [i915#9323])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-rkl:          NOTRUN -> [SKIP][11] ([i915#9323])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-rkl:          NOTRUN -> [SKIP][12] ([i915#13008])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_compute@compute-square:
    - shard-dg2:          NOTRUN -> [FAIL][13] ([i915#13665])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@gem_compute@compute-square.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-tglu:         NOTRUN -> [SKIP][14] ([i915#6335])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_create@create-ext-set-pat:
    - shard-tglu:         NOTRUN -> [SKIP][15] ([i915#8562])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@gem_create@create-ext-set-pat.html

  * igt@gem_ctx_persistence@hang:
    - shard-dg2-9:        NOTRUN -> [SKIP][16] ([i915#8555])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_ctx_persistence@hang.html

  * igt@gem_ctx_persistence@legacy-engines-hostile:
    - shard-snb:          NOTRUN -> [SKIP][17] ([i915#1099])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb2/igt@gem_ctx_persistence@legacy-engines-hostile.html

  * igt@gem_ctx_sseu@engines:
    - shard-tglu-1:       NOTRUN -> [SKIP][18] ([i915#280]) +1 other test skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@gem_ctx_sseu@engines.html
    - shard-dg2-9:        NOTRUN -> [SKIP][19] ([i915#280])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_ctx_sseu@engines.html

  * igt@gem_eio@reset-stress:
    - shard-dg1:          [PASS][20] -> [FAIL][21] ([i915#12543] / [i915#5784])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg1-16/igt@gem_eio@reset-stress.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg1-16/igt@gem_eio@reset-stress.html

  * igt@gem_eio@throttle:
    - shard-mtlp:         [PASS][22] -> [ABORT][23] ([i915#13193]) +1 other test abort
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-mtlp-4/igt@gem_eio@throttle.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-7/igt@gem_eio@throttle.html

  * igt@gem_eio@unwedge-stress:
    - shard-snb:          NOTRUN -> [FAIL][24] ([i915#8898])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb2/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_balancer@bonded-true-hang:
    - shard-dg2:          NOTRUN -> [SKIP][25] ([i915#4812])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@gem_exec_balancer@bonded-true-hang.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
    - shard-tglu-1:       NOTRUN -> [SKIP][26] ([i915#4525])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@gem_exec_balancer@parallel-keep-in-fence.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-rkl:          NOTRUN -> [SKIP][27] ([i915#4525])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_fence@submit:
    - shard-dg2-9:        NOTRUN -> [SKIP][28] ([i915#4812])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_exec_fence@submit.html

  * igt@gem_exec_flush@basic-wb-ro-before-default:
    - shard-dg2:          NOTRUN -> [SKIP][29] ([i915#3539] / [i915#4852]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@gem_exec_flush@basic-wb-ro-before-default.html

  * igt@gem_exec_params@rsvd2-dirt:
    - shard-dg2-9:        NOTRUN -> [SKIP][30] ([i915#5107])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_exec_params@rsvd2-dirt.html

  * igt@gem_exec_reloc@basic-wc:
    - shard-dg2-9:        NOTRUN -> [SKIP][31] ([i915#3281]) +4 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_exec_reloc@basic-wc.html

  * igt@gem_exec_reloc@basic-write-read:
    - shard-rkl:          NOTRUN -> [SKIP][32] ([i915#3281]) +4 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@gem_exec_reloc@basic-write-read.html

  * igt@gem_exec_reloc@basic-write-read-active:
    - shard-dg2:          NOTRUN -> [SKIP][33] ([i915#3281]) +6 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@gem_exec_reloc@basic-write-read-active.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain:
    - shard-dg2-9:        NOTRUN -> [SKIP][34] ([i915#4537] / [i915#4812])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_exec_schedule@preempt-queue-contexts-chain.html

  * igt@gem_fence_thrash@bo-write-verify-threaded-none:
    - shard-mtlp:         NOTRUN -> [SKIP][35] ([i915#4860])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-6/igt@gem_fence_thrash@bo-write-verify-threaded-none.html

  * igt@gem_fence_thrash@bo-write-verify-y:
    - shard-dg2-9:        NOTRUN -> [SKIP][36] ([i915#4860]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_fence_thrash@bo-write-verify-y.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-tglu-1:       NOTRUN -> [SKIP][37] ([i915#4613]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_lmem_swapping@parallel-multi:
    - shard-rkl:          NOTRUN -> [SKIP][38] ([i915#4613]) +2 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@gem_lmem_swapping@parallel-multi.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-tglu:         NOTRUN -> [SKIP][39] ([i915#4613])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg2:          [PASS][40] -> [TIMEOUT][41] ([i915#5493]) +1 other test timeout
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg2-6/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-3/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_media_vme:
    - shard-dg2-9:        NOTRUN -> [SKIP][42] ([i915#284])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_media_vme.html

  * igt@gem_mmap_gtt@basic-small-bo:
    - shard-dg2:          NOTRUN -> [SKIP][43] ([i915#4077]) +7 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@gem_mmap_gtt@basic-small-bo.html

  * igt@gem_mmap_wc@bad-object:
    - shard-dg2-9:        NOTRUN -> [SKIP][44] ([i915#4083]) +1 other test skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_mmap_wc@bad-object.html

  * igt@gem_mmap_wc@read-write:
    - shard-mtlp:         NOTRUN -> [SKIP][45] ([i915#4083])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-4/igt@gem_mmap_wc@read-write.html

  * igt@gem_mmap_wc@write-cpu-read-wc:
    - shard-dg2:          NOTRUN -> [SKIP][46] ([i915#4083]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@gem_mmap_wc@write-cpu-read-wc.html

  * igt@gem_partial_pwrite_pread@write:
    - shard-dg2-9:        NOTRUN -> [SKIP][47] ([i915#3282]) +5 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_partial_pwrite_pread@write.html

  * igt@gem_pread@exhaustion:
    - shard-snb:          NOTRUN -> [WARN][48] ([i915#2658])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb2/igt@gem_pread@exhaustion.html

  * igt@gem_pwrite@basic-self:
    - shard-rkl:          NOTRUN -> [SKIP][49] ([i915#3282]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@gem_pwrite@basic-self.html

  * igt@gem_pxp@hw-rejects-pxp-context:
    - shard-tglu:         NOTRUN -> [SKIP][50] ([i915#13398])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@gem_pxp@hw-rejects-pxp-context.html

  * igt@gem_pxp@reject-modify-context-protection-off-1:
    - shard-rkl:          [PASS][51] -> [TIMEOUT][52] ([i915#12917] / [i915#12964]) +1 other test timeout
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-rkl-8/igt@gem_pxp@reject-modify-context-protection-off-1.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-7/igt@gem_pxp@reject-modify-context-protection-off-1.html

  * igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
    - shard-dg2:          NOTRUN -> [SKIP][53] ([i915#4270]) +2 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html

  * igt@gem_pxp@verify-pxp-stale-buf-execution:
    - shard-dg2-9:        NOTRUN -> [SKIP][54] ([i915#4270]) +3 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_pxp@verify-pxp-stale-buf-execution.html
    - shard-rkl:          NOTRUN -> [TIMEOUT][55] ([i915#12917] / [i915#12964]) +1 other test timeout
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@gem_pxp@verify-pxp-stale-buf-execution.html

  * igt@gem_readwrite@read-bad-handle:
    - shard-dg2:          NOTRUN -> [SKIP][56] ([i915#3282])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@gem_readwrite@read-bad-handle.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs:
    - shard-dg2-9:        NOTRUN -> [SKIP][57] ([i915#5190] / [i915#8428]) +1 other test skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs.html

  * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][58] ([i915#5190] / [i915#8428])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html

  * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
    - shard-dg2-9:        NOTRUN -> [SKIP][59] ([i915#4079]) +2 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
    - shard-rkl:          NOTRUN -> [SKIP][60] ([i915#8411])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html

  * igt@gem_softpin@evict-snoop:
    - shard-mtlp:         NOTRUN -> [SKIP][61] ([i915#4885])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-6/igt@gem_softpin@evict-snoop.html

  * igt@gem_tiled_partial_pwrite_pread@writes-after-reads:
    - shard-dg2-9:        NOTRUN -> [SKIP][62] ([i915#4077]) +3 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_tiled_partial_pwrite_pread@writes-after-reads.html

  * igt@gem_tiled_pread_pwrite:
    - shard-dg2:          NOTRUN -> [SKIP][63] ([i915#4079])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@gem_tiled_pread_pwrite.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-rkl:          [PASS][64] -> [FAIL][65] ([i915#12941])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-rkl-3/igt@gem_tiled_swapping@non-threaded.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-7/igt@gem_tiled_swapping@non-threaded.html
    - shard-mtlp:         NOTRUN -> [SKIP][66] ([i915#4077])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-6/igt@gem_tiled_swapping@non-threaded.html

  * igt@gem_unfence_active_buffers:
    - shard-dg2-9:        NOTRUN -> [SKIP][67] ([i915#4879])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_unfence_active_buffers.html

  * igt@gem_userptr_blits@access-control:
    - shard-rkl:          NOTRUN -> [SKIP][68] ([i915#3297])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@gem_userptr_blits@access-control.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-dg2-9:        NOTRUN -> [SKIP][69] ([i915#3297])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-rkl:          NOTRUN -> [SKIP][70] ([i915#3297] / [i915#3323])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-tglu-1:       NOTRUN -> [SKIP][71] ([i915#3297])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@map-fixed-invalidate:
    - shard-dg2-9:        NOTRUN -> [SKIP][72] ([i915#3297] / [i915#4880])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gem_userptr_blits@map-fixed-invalidate.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][73] ([i915#12964]) +7 other tests dmesg-warn
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-rkl:          NOTRUN -> [SKIP][74] ([i915#2527])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@bb-secure:
    - shard-tglu-1:       NOTRUN -> [SKIP][75] ([i915#2527] / [i915#2856])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@gen9_exec_parse@bb-secure.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-dg2-9:        NOTRUN -> [SKIP][76] ([i915#2856]) +2 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@gen9_exec_parse@bb-start-far.html

  * igt@gen9_exec_parse@secure-batches:
    - shard-dg2:          NOTRUN -> [SKIP][77] ([i915#2856]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@gen9_exec_parse@secure-batches.html

  * igt@i915_pm_freq_api@freq-reset-multiple:
    - shard-rkl:          NOTRUN -> [SKIP][78] ([i915#8399])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@i915_pm_freq_api@freq-reset-multiple.html

  * igt@i915_pm_freq_api@freq-suspend@gt0:
    - shard-dg2:          [PASS][79] -> [INCOMPLETE][80] ([i915#12455] / [i915#13820]) +1 other test incomplete
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg2-4/igt@i915_pm_freq_api@freq-suspend@gt0.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-3/igt@i915_pm_freq_api@freq-suspend@gt0.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-tglu:         NOTRUN -> [WARN][81] ([i915#13790] / [i915#2681]) +4 other tests warn
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_pm_sseu@full-enable:
    - shard-mtlp:         NOTRUN -> [SKIP][82] ([i915#8437])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-6/igt@i915_pm_sseu@full-enable.html

  * igt@i915_power@sanity:
    - shard-rkl:          NOTRUN -> [SKIP][83] ([i915#7984])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@i915_power@sanity.html

  * igt@i915_query@hwconfig_table:
    - shard-rkl:          NOTRUN -> [SKIP][84] ([i915#6245])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@i915_query@hwconfig_table.html

  * igt@i915_query@query-topology-coherent-slice-mask:
    - shard-dg2-9:        NOTRUN -> [SKIP][85] ([i915#6188])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@i915_query@query-topology-coherent-slice-mask.html

  * igt@i915_selftest@mock@memory_region:
    - shard-dg2:          NOTRUN -> [DMESG-WARN][86] ([i915#9311]) +1 other test dmesg-warn
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@i915_selftest@mock@memory_region.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - shard-dg1:          [PASS][87] -> [DMESG-WARN][88] ([i915#4391] / [i915#4423])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg1-17/igt@i915_suspend@basic-s2idle-without-i915.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg1-12/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - shard-dg2-9:        NOTRUN -> [SKIP][89] ([i915#4212])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
    - shard-dg2:          NOTRUN -> [SKIP][90] ([i915#4212])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@kms_addfb_basic@tile-pitch-mismatch.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-tglu:         [PASS][91] -> [FAIL][92] ([i915#10991]) +1 other test fail
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-tglu-4/igt@kms_async_flips@alternate-sync-async-flip.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-6/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-dp-4-4-mc-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][93] ([i915#8709]) +15 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-10/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-dp-4-4-mc-ccs.html

  * igt@kms_async_flips@invalid-async-flip-atomic:
    - shard-dg2-9:        NOTRUN -> [SKIP][94] ([i915#12967])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_async_flips@invalid-async-flip-atomic.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking:
    - shard-glk:          [PASS][95] -> [FAIL][96] ([i915#12177])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-glk4/igt@kms_atomic_transition@modeset-transition-nonblocking.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs:
    - shard-glk:          [PASS][97] -> [FAIL][98] ([i915#11859])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-glk4/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-tglu-1:       NOTRUN -> [SKIP][99] ([i915#1769] / [i915#3555])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-dg2-9:        NOTRUN -> [SKIP][100] ([i915#1769] / [i915#3555])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1:
    - shard-tglu:         [PASS][101] -> [FAIL][102] ([i915#11808]) +1 other test fail
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-tglu-2/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-6/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-180:
    - shard-rkl:          NOTRUN -> [SKIP][103] ([i915#5286])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@kms_big_fb@4-tiled-16bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-90:
    - shard-dg2-9:        NOTRUN -> [SKIP][104] +9 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-tglu-1:       NOTRUN -> [SKIP][105] ([i915#5286]) +1 other test skip
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-tglu:         NOTRUN -> [SKIP][106] ([i915#5286]) +3 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@linear-64bpp-rotate-270:
    - shard-mtlp:         NOTRUN -> [SKIP][107] +4 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-6/igt@kms_big_fb@linear-64bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][108] ([i915#3638]) +2 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-dg2-9:        NOTRUN -> [SKIP][109] ([i915#5190]) +1 other test skip
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-dg2:          NOTRUN -> [SKIP][110] ([i915#4538] / [i915#5190]) +5 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
    - shard-dg2-9:        NOTRUN -> [SKIP][111] ([i915#4538] / [i915#5190]) +6 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][112] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-4/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-dg2-9:        NOTRUN -> [SKIP][113] ([i915#12313]) +1 other test skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
    - shard-tglu-1:       NOTRUN -> [SKIP][114] ([i915#12313])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-c-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][115] ([i915#6095]) +9 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-6/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-c-edp-1.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-2:
    - shard-dg2-9:        NOTRUN -> [SKIP][116] ([i915#10307] / [i915#6095]) +54 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][117] ([i915#10307] / [i915#6095]) +115 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-8/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][118] ([i915#6095]) +24 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][119] ([i915#12313])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][120] ([i915#12313])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][121] ([i915#12805])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][122] ([i915#6095]) +85 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-5/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][123] ([i915#6095]) +19 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-11/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-dp-3.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][124] ([i915#6095]) +34 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][125] ([i915#6095]) +139 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg1-12/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-dg2:          NOTRUN -> [SKIP][126] ([i915#13784])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][127] ([i915#13781]) +3 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-6/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html

  * igt@kms_chamelium_color@ctm-green-to-red:
    - shard-dg2:          NOTRUN -> [SKIP][128] +7 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@kms_chamelium_color@ctm-green-to-red.html

  * igt@kms_chamelium_hpd@dp-hpd:
    - shard-mtlp:         NOTRUN -> [SKIP][129] ([i915#11151] / [i915#7828])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-4/igt@kms_chamelium_hpd@dp-hpd.html

  * igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
    - shard-rkl:          NOTRUN -> [SKIP][130] ([i915#11151] / [i915#7828]) +3 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html

  * igt@kms_chamelium_hpd@dp-hpd-fast:
    - shard-tglu:         NOTRUN -> [SKIP][131] ([i915#11151] / [i915#7828]) +3 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_chamelium_hpd@dp-hpd-fast.html

  * igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
    - shard-dg2:          NOTRUN -> [SKIP][132] ([i915#11151] / [i915#7828]) +1 other test skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
    - shard-tglu-1:       NOTRUN -> [SKIP][133] ([i915#11151] / [i915#7828]) +2 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html

  * igt@kms_chamelium_hpd@vga-hpd-for-each-pipe:
    - shard-dg2-9:        NOTRUN -> [SKIP][134] ([i915#11151] / [i915#7828]) +5 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html

  * igt@kms_content_protection@content-type-change:
    - shard-dg2-9:        NOTRUN -> [SKIP][135] ([i915#9424])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-dg2:          NOTRUN -> [SKIP][136] ([i915#3299])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@legacy:
    - shard-tglu:         NOTRUN -> [SKIP][137] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@srm:
    - shard-rkl:          NOTRUN -> [SKIP][138] ([i915#7118])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-offscreen-32x32:
    - shard-tglu-1:       NOTRUN -> [SKIP][139] ([i915#3555]) +3 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_cursor_crc@cursor-offscreen-32x32.html
    - shard-dg2-9:        NOTRUN -> [SKIP][140] ([i915#3555]) +2 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_cursor_crc@cursor-offscreen-32x32.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-dg2:          NOTRUN -> [SKIP][141] ([i915#13049])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-dg2-9:        NOTRUN -> [SKIP][142] ([i915#13049]) +1 other test skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_cursor_crc@cursor-random-512x512.html
    - shard-tglu-1:       NOTRUN -> [SKIP][143] ([i915#13049])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-random-64x21:
    - shard-rkl:          NOTRUN -> [FAIL][144] ([i915#13566]) +2 other tests fail
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@kms_cursor_crc@cursor-random-64x21.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][145] ([i915#13049])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-tglu:         NOTRUN -> [FAIL][146] ([i915#13566]) +1 other test fail
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_crc@cursor-sliding-256x85@pipe-a-hdmi-a-2:
    - shard-rkl:          [PASS][147] -> [FAIL][148] ([i915#13566]) +1 other test fail
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-rkl-5/igt@kms_cursor_crc@cursor-sliding-256x85@pipe-a-hdmi-a-2.html
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-6/igt@kms_cursor_crc@cursor-sliding-256x85@pipe-a-hdmi-a-2.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-tglu:         NOTRUN -> [SKIP][149] ([i915#4103]) +1 other test skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-mtlp:         NOTRUN -> [SKIP][150] ([i915#9809])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-6/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][151] ([i915#13046] / [i915#5354]) +1 other test skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-rkl:          NOTRUN -> [SKIP][152] +11 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
    - shard-dg2-9:        NOTRUN -> [SKIP][153] ([i915#13046] / [i915#5354]) +3 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html

  * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
    - shard-dg2-9:        NOTRUN -> [SKIP][154] ([i915#9067])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
    - shard-tglu-1:       NOTRUN -> [SKIP][155] ([i915#9067])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-dg2-9:        NOTRUN -> [SKIP][156] ([i915#4103] / [i915#4213])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-dg2-9:        NOTRUN -> [SKIP][157] ([i915#9833])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-tglu-1:       NOTRUN -> [SKIP][158] ([i915#1769] / [i915#3555] / [i915#3804])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][159] ([i915#3804])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
    - shard-tglu-1:       NOTRUN -> [SKIP][160] ([i915#3804])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-dg2-9:        NOTRUN -> [SKIP][161] ([i915#13749])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_dp_link_training@non-uhbr-mst.html
    - shard-rkl:          NOTRUN -> [SKIP][162] ([i915#13749])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-rkl:          NOTRUN -> [SKIP][163] ([i915#13748])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-dg2:          NOTRUN -> [SKIP][164] ([i915#13707])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-tglu:         NOTRUN -> [SKIP][165] ([i915#13707])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-tglu:         NOTRUN -> [SKIP][166] ([i915#3555] / [i915#3840])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-rkl:          NOTRUN -> [SKIP][167] ([i915#3555] / [i915#3840])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
    - shard-dg2:          NOTRUN -> [SKIP][168] ([i915#13798])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
    - shard-tglu-1:       NOTRUN -> [SKIP][169] ([i915#2575])
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
    - shard-dg2-9:        NOTRUN -> [SKIP][170] ([i915#13798])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-dg2-9:        NOTRUN -> [SKIP][171] ([i915#9934]) +3 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@2x-flip-vs-panning-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][172] ([i915#9934]) +2 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@kms_flip@2x-flip-vs-panning-interruptible.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-tglu:         NOTRUN -> [SKIP][173] ([i915#3637]) +2 other tests skip
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@2x-plain-flip-interruptible:
    - shard-rkl:          NOTRUN -> [SKIP][174] ([i915#9934]) +6 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@kms_flip@2x-plain-flip-interruptible.html

  * igt@kms_flip@2x-wf_vblank-ts-check:
    - shard-tglu-1:       NOTRUN -> [SKIP][175] ([i915#3637])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_flip@2x-wf_vblank-ts-check.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2:
    - shard-glk:          [PASS][176] -> [FAIL][177] ([i915#13734]) +1 other test fail
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html

  * igt@kms_flip@flip-vs-fences:
    - shard-dg2-9:        NOTRUN -> [SKIP][178] ([i915#8381])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_flip@flip-vs-fences.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-hdmi-a1:
    - shard-tglu:         [PASS][179] -> [FAIL][180] ([i915#13734])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-tglu-9/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-hdmi-a1.html
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-9/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][181] ([i915#2672]) +3 other tests skip
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling:
    - shard-dg2:          NOTRUN -> [SKIP][182] ([i915#2672] / [i915#3555]) +1 other test skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
    - shard-tglu:         NOTRUN -> [SKIP][183] ([i915#2672] / [i915#3555])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][184] ([i915#2587] / [i915#2672])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode:
    - shard-dg2-9:        NOTRUN -> [SKIP][185] ([i915#2672]) +2 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][186] ([i915#2672] / [i915#3555] / [i915#5190])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][187] ([i915#2587] / [i915#2672] / [i915#3555])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
    - shard-rkl:          NOTRUN -> [SKIP][188] ([i915#2672] / [i915#3555]) +3 other tests skip
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][189] ([i915#2672] / [i915#3555])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-tglu-1:       NOTRUN -> [SKIP][190] ([i915#2587] / [i915#2672]) +1 other test skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][191] ([i915#2672]) +2 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-dg2-9:        NOTRUN -> [SKIP][192] ([i915#2672] / [i915#3555])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-dg2-9:        NOTRUN -> [SKIP][193] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][194] ([i915#8708]) +4 other tests skip
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][195] ([i915#5354]) +17 other tests skip
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-dg2-9:        NOTRUN -> [SKIP][196] ([i915#10055])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][197] ([i915#3023]) +8 other tests skip
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-mtlp:         NOTRUN -> [SKIP][198] ([i915#1825]) +4 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render:
    - shard-dg2-9:        NOTRUN -> [SKIP][199] ([i915#5354]) +17 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@pipe-fbc-rte:
    - shard-rkl:          NOTRUN -> [SKIP][200] ([i915#9766])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
    - shard-dg2-9:        NOTRUN -> [SKIP][201] ([i915#9766])
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render:
    - shard-dg2-9:        NOTRUN -> [SKIP][202] ([i915#3458]) +11 other tests skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-tglu-1:       NOTRUN -> [SKIP][203] +38 other tests skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
    - shard-dg2:          NOTRUN -> [SKIP][204] ([i915#3458]) +8 other tests skip
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-dg2-9:        NOTRUN -> [SKIP][205] ([i915#8708]) +13 other tests skip
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-tglu:         NOTRUN -> [SKIP][206] +29 other tests skip
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][207] ([i915#1825]) +18 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_getfb@getfb-reject-ccs:
    - shard-dg2-9:        NOTRUN -> [SKIP][208] ([i915#6118])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_getfb@getfb-reject-ccs.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][209] ([i915#3555] / [i915#8228])
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@invalid-hdr:
    - shard-tglu:         NOTRUN -> [SKIP][210] ([i915#3555] / [i915#8228])
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@static-swap:
    - shard-tglu-1:       NOTRUN -> [SKIP][211] ([i915#3555] / [i915#8228])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_hdr@static-swap.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-dg2:          NOTRUN -> [SKIP][212] ([i915#10656])
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-dg2:          NOTRUN -> [SKIP][213] ([i915#13688])
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][214] ([i915#10656])
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-dg2-9:        NOTRUN -> [SKIP][215] ([i915#12388])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_joiner@invalid-modeset-force-big-joiner.html
    - shard-rkl:          NOTRUN -> [SKIP][216] ([i915#12388])
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][217] ([i915#12339])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][218] ([i915#13522])
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
    - shard-dg2-9:        NOTRUN -> [SKIP][219] ([i915#13522])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-tglu-1:       NOTRUN -> [SKIP][220] ([i915#1839])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_panel_fitting@legacy:
    - shard-rkl:          NOTRUN -> [SKIP][221] ([i915#6301])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@kms_panel_fitting@legacy.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-dg2-9:        NOTRUN -> [SKIP][222] ([i915#13705])
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane_cursor@viewport:
    - shard-rkl:          [PASS][223] -> [DMESG-WARN][224] ([i915#12917] / [i915#12964])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-rkl-8/igt@kms_plane_cursor@viewport.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-7/igt@kms_plane_cursor@viewport.html

  * igt@kms_plane_multiple@tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][225] ([i915#3555]) +2 other tests skip
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@kms_plane_multiple@tiling-4.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-dg2-9:        NOTRUN -> [SKIP][226] ([i915#6953] / [i915#9423])
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_plane_scaling@intel-max-src-size.html
    - shard-tglu-1:       NOTRUN -> [SKIP][227] ([i915#6953])
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-c:
    - shard-tglu:         NOTRUN -> [SKIP][228] ([i915#12247]) +4 other tests skip
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-c.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25:
    - shard-dg2:          NOTRUN -> [SKIP][229] ([i915#12247] / [i915#6953] / [i915#9423]) +1 other test skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@kms_plane_scaling@planes-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling:
    - shard-dg2:          NOTRUN -> [SKIP][230] ([i915#12247] / [i915#9423])
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d:
    - shard-dg2:          NOTRUN -> [SKIP][231] ([i915#12247]) +11 other tests skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d:
    - shard-tglu-1:       NOTRUN -> [SKIP][232] ([i915#12247]) +9 other tests skip
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
    - shard-rkl:          NOTRUN -> [SKIP][233] ([i915#12247] / [i915#3555])
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a:
    - shard-rkl:          NOTRUN -> [SKIP][234] ([i915#12247]) +10 other tests skip
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-tglu-1:       NOTRUN -> [SKIP][235] ([i915#9812])
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-dg2-9:        NOTRUN -> [SKIP][236] ([i915#9685])
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_pm_dc@dc3co-vpb-simulation.html
    - shard-rkl:          NOTRUN -> [SKIP][237] ([i915#9685])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-dg2-9:        NOTRUN -> [SKIP][238] ([i915#3828])
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][239] ([i915#5978])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-tglu:         NOTRUN -> [SKIP][240] ([i915#9685])
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-dg2:          [PASS][241] -> [SKIP][242] ([i915#9340])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg2-8/igt@kms_pm_lpsp@kms-lpsp.html
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-6/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-dg2:          NOTRUN -> [SKIP][243] ([i915#8430])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-dg2:          [PASS][244] -> [SKIP][245] ([i915#9519])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg2-11/igt@kms_pm_rpm@modeset-non-lpsp.html
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-8/igt@kms_pm_rpm@modeset-non-lpsp.html
    - shard-rkl:          NOTRUN -> [SKIP][246] ([i915#9519])
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-rkl:          [PASS][247] -> [SKIP][248] ([i915#9519])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-rkl-6/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-mtlp:         NOTRUN -> [SKIP][249] ([i915#9519])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-tglu-1:       NOTRUN -> [SKIP][250] ([i915#6524])
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_prime@basic-modeset-hybrid.html
    - shard-dg2-9:        NOTRUN -> [SKIP][251] ([i915#6524] / [i915#6805]) +1 other test skip
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf:
    - shard-tglu:         NOTRUN -> [SKIP][252] ([i915#11520]) +3 other tests skip
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-snb:          NOTRUN -> [SKIP][253] ([i915#11520]) +2 other tests skip
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area:
    - shard-tglu-1:       NOTRUN -> [SKIP][254] ([i915#11520]) +3 other tests skip
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area:
    - shard-rkl:          NOTRUN -> [SKIP][255] ([i915#11520]) +3 other tests skip
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
    - shard-dg2-9:        NOTRUN -> [SKIP][256] ([i915#11520]) +4 other tests skip
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
    - shard-dg2:          NOTRUN -> [SKIP][257] ([i915#11520]) +2 other tests skip
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-dg2-9:        NOTRUN -> [SKIP][258] ([i915#9683])
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_psr2_su@page_flip-p010.html
    - shard-rkl:          NOTRUN -> [SKIP][259] ([i915#9683])
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-pr-primary-mmap-cpu:
    - shard-tglu:         NOTRUN -> [SKIP][260] ([i915#9732]) +8 other tests skip
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_psr@fbc-pr-primary-mmap-cpu.html

  * igt@kms_psr@fbc-psr2-sprite-mmap-cpu@edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][261] ([i915#9688]) +1 other test skip
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-4/igt@kms_psr@fbc-psr2-sprite-mmap-cpu@edp-1.html

  * igt@kms_psr@psr-cursor-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][262] ([i915#1072] / [i915#9732]) +10 other tests skip
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@kms_psr@psr-cursor-mmap-cpu.html

  * igt@kms_psr@psr-sprite-mmap-cpu:
    - shard-tglu-1:       NOTRUN -> [SKIP][263] ([i915#9732]) +9 other tests skip
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-1/igt@kms_psr@psr-sprite-mmap-cpu.html

  * igt@kms_psr@psr2-cursor-blt:
    - shard-dg2-9:        NOTRUN -> [SKIP][264] ([i915#1072] / [i915#9732]) +14 other tests skip
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_psr@psr2-cursor-blt.html
    - shard-rkl:          NOTRUN -> [SKIP][265] ([i915#1072] / [i915#9732]) +10 other tests skip
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@kms_psr@psr2-cursor-blt.html

  * igt@kms_rotation_crc@primary-x-tiled-reflect-x-0:
    - shard-dg1:          [PASS][266] -> [DMESG-WARN][267] ([i915#4423])
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg1-19/igt@kms_rotation_crc@primary-x-tiled-reflect-x-0.html
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg1-18/igt@kms_rotation_crc@primary-x-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-dg2:          NOTRUN -> [SKIP][268] ([i915#12755] / [i915#5190])
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-tglu:         NOTRUN -> [SKIP][269] ([i915#5289])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@sprite-rotation-270:
    - shard-dg2-9:        NOTRUN -> [SKIP][270] ([i915#12755]) +1 other test skip
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_rotation_crc@sprite-rotation-270.html

  * igt@kms_scaling_modes@scaling-mode-full-aspect:
    - shard-tglu:         NOTRUN -> [SKIP][271] ([i915#3555]) +3 other tests skip
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_scaling_modes@scaling-mode-full-aspect.html

  * igt@kms_selftest@drm_framebuffer:
    - shard-tglu:         NOTRUN -> [ABORT][272] ([i915#13179]) +1 other test abort
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_selftest@drm_framebuffer.html

  * igt@kms_vrr@flip-basic:
    - shard-dg2:          NOTRUN -> [SKIP][273] ([i915#3555]) +2 other tests skip
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-1/igt@kms_vrr@flip-basic.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-dg2-9:        NOTRUN -> [SKIP][274] ([i915#9906])
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@negative-basic:
    - shard-dg2:          [PASS][275] -> [SKIP][276] ([i915#3555] / [i915#9906])
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg2-10/igt@kms_vrr@negative-basic.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-4/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-tglu:         NOTRUN -> [SKIP][277] ([i915#9906]) +1 other test skip
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-tglu-10/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@kms_writeback@writeback-check-output-xrgb2101010:
    - shard-dg2-9:        NOTRUN -> [SKIP][278] ([i915#2437] / [i915#9412])
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@kms_writeback@writeback-check-output-xrgb2101010.html
    - shard-rkl:          NOTRUN -> [SKIP][279] ([i915#2437] / [i915#9412])
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@kms_writeback@writeback-check-output-xrgb2101010.html

  * igt@perf@gen12-oa-tlb-invalidate:
    - shard-rkl:          [PASS][280] -> [DMESG-WARN][281] ([i915#12964]) +7 other tests dmesg-warn
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-rkl-8/igt@perf@gen12-oa-tlb-invalidate.html
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-5/igt@perf@gen12-oa-tlb-invalidate.html

  * igt@perf@global-sseu-config:
    - shard-dg2-9:        NOTRUN -> [SKIP][282] ([i915#7387])
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@perf@global-sseu-config.html

  * igt@perf_pmu@busy-accuracy-98:
    - shard-snb:          NOTRUN -> [SKIP][283] +93 other tests skip
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb2/igt@perf_pmu@busy-accuracy-98.html

  * igt@prime_vgem@coherency-gtt:
    - shard-dg2-9:        NOTRUN -> [SKIP][284] ([i915#3708] / [i915#4077])
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@prime_vgem@coherency-gtt.html

  * igt@prime_vgem@fence-flip-hang:
    - shard-mtlp:         NOTRUN -> [SKIP][285] ([i915#3708])
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-6/igt@prime_vgem@fence-flip-hang.html

  * igt@prime_vgem@fence-read-hang:
    - shard-dg2-9:        NOTRUN -> [SKIP][286] ([i915#3708]) +1 other test skip
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-9/igt@prime_vgem@fence-read-hang.html
    - shard-rkl:          NOTRUN -> [SKIP][287] ([i915#3708]) +1 other test skip
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@prime_vgem@fence-read-hang.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-4:
    - shard-mtlp:         NOTRUN -> [FAIL][288] ([i915#12910]) +8 other tests fail
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-6/igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-4.html

  
#### Possible fixes ####

  * igt@drm_buddy@drm_buddy:
    - shard-rkl:          [DMESG-WARN][289] ([i915#12964]) -> [PASS][290] +2 other tests pass
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-rkl-5/igt@drm_buddy@drm_buddy.html
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-6/igt@drm_buddy@drm_buddy.html

  * igt@gem_eio@kms:
    - shard-mtlp:         [ABORT][291] ([i915#13193]) -> [PASS][292] +1 other test pass
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-mtlp-7/igt@gem_eio@kms.html
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-4/igt@gem_eio@kms.html

  * igt@gem_pxp@display-protected-crc:
    - shard-rkl:          [TIMEOUT][293] ([i915#12917] / [i915#12964]) -> [PASS][294] +1 other test pass
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-rkl-1/igt@gem_pxp@display-protected-crc.html
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-8/igt@gem_pxp@display-protected-crc.html

  * igt@gem_pxp@reject-modify-context-protection-off-3:
    - shard-rkl:          [SKIP][295] ([i915#4270]) -> [PASS][296]
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-rkl-8/igt@gem_pxp@reject-modify-context-protection-off-3.html
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-8/igt@gem_pxp@reject-modify-context-protection-off-3.html

  * igt@i915_module_load@load:
    - shard-snb:          ([PASS][297], [PASS][298], [SKIP][299], [PASS][300], [PASS][301], [PASS][302], [PASS][303], [PASS][304], [PASS][305], [PASS][306], [PASS][307], [PASS][308], [PASS][309], [PASS][310], [PASS][311], [PASS][312], [PASS][313], [PASS][314], [PASS][315], [PASS][316], [PASS][317], [PASS][318], [PASS][319], [PASS][320], [PASS][321]) -> ([PASS][322], [PASS][323], [PASS][324], [PASS][325], [PASS][326], [PASS][327], [PASS][328], [PASS][329], [PASS][330], [PASS][331], [PASS][332], [PASS][333], [PASS][334], [PASS][335], [PASS][336], [PASS][337], [PASS][338], [PASS][339], [PASS][340], [PASS][341], [PASS][342], [PASS][343], [PASS][344], [PASS][345], [PASS][346])
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb2/igt@i915_module_load@load.html
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb2/igt@i915_module_load@load.html
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb7/igt@i915_module_load@load.html
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb2/igt@i915_module_load@load.html
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb7/igt@i915_module_load@load.html
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb2/igt@i915_module_load@load.html
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb7/igt@i915_module_load@load.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb2/igt@i915_module_load@load.html
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb7/igt@i915_module_load@load.html
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb7/igt@i915_module_load@load.html
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb4/igt@i915_module_load@load.html
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb6/igt@i915_module_load@load.html
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb4/igt@i915_module_load@load.html
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb6/igt@i915_module_load@load.html
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb4/igt@i915_module_load@load.html
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb6/igt@i915_module_load@load.html
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb4/igt@i915_module_load@load.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb6/igt@i915_module_load@load.html
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb4/igt@i915_module_load@load.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb6/igt@i915_module_load@load.html
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb5/igt@i915_module_load@load.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb5/igt@i915_module_load@load.html
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb5/igt@i915_module_load@load.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb5/igt@i915_module_load@load.html
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb5/igt@i915_module_load@load.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb2/igt@i915_module_load@load.html
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb6/igt@i915_module_load@load.html
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb7/igt@i915_module_load@load.html
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb2/igt@i915_module_load@load.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb7/igt@i915_module_load@load.html
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb7/igt@i915_module_load@load.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb2/igt@i915_module_load@load.html
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb4/igt@i915_module_load@load.html
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb7/igt@i915_module_load@load.html
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb6/igt@i915_module_load@load.html
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb7/igt@i915_module_load@load.html
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb6/igt@i915_module_load@load.html
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb2/igt@i915_module_load@load.html
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb4/igt@i915_module_load@load.html
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb1/igt@i915_module_load@load.html
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb5/igt@i915_module_load@load.html
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb5/igt@i915_module_load@load.html
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb1/igt@i915_module_load@load.html
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb4/igt@i915_module_load@load.html
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb5/igt@i915_module_load@load.html
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb1/igt@i915_module_load@load.html
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb1/igt@i915_module_load@load.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb5/igt@i915_module_load@load.html
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb4/igt@i915_module_load@load.html
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb1/igt@i915_module_load@load.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-rkl:          [ABORT][347] ([i915#13592]) -> [PASS][348]
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-rkl-5/igt@i915_module_load@reload-with-fault-injection.html
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-1/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [INCOMPLETE][349] ([i915#13729] / [i915#13821]) -> [PASS][350]
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-snb5/igt@i915_pm_rps@reset.html
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-snb4/igt@i915_pm_rps@reset.html

  * igt@i915_power@sanity:
    - shard-mtlp:         [SKIP][351] ([i915#7984]) -> [PASS][352]
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-mtlp-6/igt@i915_power@sanity.html
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-6/igt@i915_power@sanity.html

  * igt@i915_selftest@live:
    - shard-rkl:          [DMESG-FAIL][353] ([i915#13550]) -> [PASS][354] +1 other test pass
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-rkl-6/igt@i915_selftest@live.html
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-4/igt@i915_selftest@live.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-rkl:          [FAIL][355] ([i915#11808]) -> [PASS][356] +1 other test pass
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-rkl-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - shard-mtlp:         [FAIL][357] ([i915#12469] / [i915#5138]) -> [PASS][358]
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-mtlp-7/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-6/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-dg2:          [SKIP][359] ([i915#13749]) -> [PASS][360]
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg2-8/igt@kms_dp_link_training@non-uhbr-sst.html
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-10/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_flip@flip-vs-suspend@d-hdmi-a4:
    - shard-dg1:          [DMESG-WARN][361] ([i915#4423]) -> [PASS][362] +2 other tests pass
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg1-16/igt@kms_flip@flip-vs-suspend@d-hdmi-a4.html
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg1-16/igt@kms_flip@flip-vs-suspend@d-hdmi-a4.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
    - shard-dg2:          [FAIL][363] ([i915#6880]) -> [PASS][364] +1 other test pass
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-dg2:          [SKIP][365] ([i915#3555] / [i915#8228]) -> [PASS][366]
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg2-2/igt@kms_hdr@bpc-switch-suspend.html
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-11/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-dg2:          [SKIP][367] ([i915#9519]) -> [PASS][368]
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg2-1/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-8/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          [SKIP][369] ([i915#9519]) -> [PASS][370] +1 other test pass
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-rkl-7/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@perf_pmu@busy-double-start@vcs0:
    - shard-dg2:          [FAIL][371] ([i915#4349]) -> [PASS][372]
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg2-8/igt@perf_pmu@busy-double-start@vcs0.html
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-6/igt@perf_pmu@busy-double-start@vcs0.html

  
#### Warnings ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - shard-mtlp:         [ABORT][373] ([i915#7975]) -> [ABORT][374] ([i915#13193] / [i915#7975]) +1 other test abort
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-mtlp-1/igt@gem_exec_suspend@basic-s4-devices.html
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-mtlp-7/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@kms_content_protection@srm:
    - shard-dg2:          [FAIL][375] ([i915#7173]) -> [SKIP][376] ([i915#7118])
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg2-11/igt@kms_content_protection@srm.html
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-8/igt@kms_content_protection@srm.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-glk:          [INCOMPLETE][377] ([i915#12314] / [i915#12745] / [i915#4839]) -> [INCOMPLETE][378] ([i915#12745] / [i915#4839])
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-glk8/igt@kms_flip@2x-flip-vs-suspend.html
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-glk7/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [INCOMPLETE][379] ([i915#12314] / [i915#4839]) -> [INCOMPLETE][380] ([i915#4839])
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-glk8/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-glk7/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
    - shard-dg1:          [SKIP][381] ([i915#2672] / [i915#3555] / [i915#4423]) -> [SKIP][382] ([i915#2672] / [i915#3555])
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg1-13/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg1-13/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode:
    - shard-dg1:          [SKIP][383] ([i915#2587] / [i915#2672] / [i915#4423]) -> [SKIP][384] ([i915#2587] / [i915#2672])
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg1-13/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode.html
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg1-13/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render:
    - shard-dg2:          [SKIP][385] ([i915#10433] / [i915#3458]) -> [SKIP][386] ([i915#3458]) +1 other test skip
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu:
    - shard-dg2:          [SKIP][387] ([i915#3458]) -> [SKIP][388] ([i915#10433] / [i915#3458])
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-rkl:          [SKIP][389] ([i915#1187] / [i915#12713]) -> [SKIP][390] ([i915#12713])
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-rkl-3/igt@kms_hdr@brightness-with-hdr.html
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-7/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][391] ([i915#4070] / [i915#4816]) -> [SKIP][392] ([i915#1839] / [i915#4816])
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-rkl-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-8/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-rkl:          [SKIP][393] ([i915#9340]) -> [SKIP][394] ([i915#3828])
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-rkl-8/igt@kms_pm_lpsp@kms-lpsp.html
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-rkl-7/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@prime_mmap@test_aperture_limit:
    - shard-dg2:          [INCOMPLETE][395] ([i915#5493]) -> [WARN][396] ([i915#9351])
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg2-10/igt@prime_mmap@test_aperture_limit.html
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-10/igt@prime_mmap@test_aperture_limit.html

  * igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
    - shard-dg2:          [INCOMPLETE][397] ([i915#5493]) -> [CRASH][398] ([i915#9351])
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16299/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html

  
  [i915#10055]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10055
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
  [i915#10991]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10991
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11527
  [i915#11808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11808
  [i915#11859]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11859
  [i915#1187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1187
  [i915#12177]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12177
  [i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12314]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12314
  [i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
  [i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
  [i915#12455]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12455
  [i915#12469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12469
  [i915#12543]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12543
  [i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
  [i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
  [i915#12941]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12941
  [i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
  [i915#12967]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12967
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
  [i915#13193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13193
  [i915#13398]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13398
  [i915#13522]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13522
  [i915#13550]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13550
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13592]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13592
  [i915#13665]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13665
  [i915#13688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13688
  [i915#13705]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13705
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13729]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13729
  [i915#13734]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13734
  [i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
  [i915#13784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13784
  [i915#13790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13790
  [i915#13798]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13798
  [i915#13820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13820
  [i915#13821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13821
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4391]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4879]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4879
  [i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
  [i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
  [i915#5107]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5107
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
  [i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
  [i915#5978]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5978
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6118
  [i915#6188]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6188
  [i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
  [i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
  [i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7387
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
  [i915#8437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8437
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
  [i915#8898]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8898
  [i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
  [i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9351]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9351
  [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
  [i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9833]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9833
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_16299 -> Patchwork_146600v1

  CI-20190529: 20190529
  CI_DRM_16299: b15a87713d14b1c2986f47a622c5a8c5458e2396 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8277: 8277
  Patchwork_146600v1: b15a87713d14b1c2986f47a622c5a8c5458e2396 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146600v1/index.html

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