From: Jani Nikula <jani.nikula@linux.intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: Define each HBR link rate
Date: Tue, 03 Dec 2019 11:08:52 +0200 [thread overview]
Message-ID: <87a789kc7v.fsf@intel.com> (raw)
In-Reply-To: <20191203023110.488972-1-jose.souza@intel.com>
On Mon, 02 Dec 2019, José Roberto de Souza <jose.souza@intel.com> wrote:
> This is better than keep those values in the code that you always
> need to check the DP spec to know what level of HBR it is.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a976606d21c7..914f0cc4d237 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -49,6 +49,10 @@
> #include "intel_tc.h"
> #include "intel_vdsc.h"
>
> +#define HBR_RATE 270000
> +#define HBR2_RATE 540000
> +#define HBR3_RATE 810000
> +
> struct ddi_buf_trans {
> u32 trans1; /* balance leg enable, de-emph level */
> u32 trans2; /* vref sel, vswing */
> @@ -888,7 +892,7 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> if (type == INTEL_OUTPUT_HDMI) {
> *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> return icl_combo_phy_ddi_translations_hdmi;
> - } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
> + } else if (rate > HBR2_RATE && type == INTEL_OUTPUT_EDP) {
I don't want a patch switching some random place to using a
macro. Either we stick to numbers or switch all.
And if switch all, add the rates to drm core, not locally to
intel_ddi.c. (And then wonder what to do with the intermediate rates in
intel_dp_set_source_rates()...)
Personally, HBR<N> is less useful to me in code, it's the actual rate
that helps me.
But I'll trust Ville's judgement on this one.
BR,
Jani.
> *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> return icl_combo_phy_ddi_translations_edp_hbr3;
> } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
--
Jani Nikula, Intel Open Source Graphics Center
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next prev parent reply other threads:[~2019-12-03 9:09 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-03 2:31 [PATCH 1/2] drm/i915/dp: Define each HBR link rate José Roberto de Souza
2019-12-03 2:31 ` [Intel-gfx] " José Roberto de Souza
2019-12-03 2:31 ` [PATCH 2/2] drm/i915/dp/tgl+: Update combo phy vswing tables José Roberto de Souza
2019-12-03 2:31 ` [Intel-gfx] " José Roberto de Souza
2019-12-03 13:18 ` Ville Syrjälä
2019-12-03 16:35 ` Matt Roper
2019-12-03 3:09 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: Define each HBR link rate Patchwork
2019-12-03 3:09 ` [Intel-gfx] " Patchwork
2019-12-03 9:08 ` Jani Nikula [this message]
2019-12-03 13:11 ` [Intel-gfx] [PATCH 1/2] " Ville Syrjälä
2019-12-03 21:48 ` Souza, Jose
2019-12-03 22:01 ` Manasi Navare
2019-12-03 9:21 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork
2019-12-03 16:17 ` [Intel-gfx] [PATCH 1/2] " Matt Roper
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