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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Apply post-sync write for pipe control invalidates
Date: Fri, 10 Aug 2012 13:46:17 +0300	[thread overview]
Message-ID: <87a9y3ja86.fsf@intel.com> (raw)
In-Reply-To: <1344593270_68850@CP5-2952>

On Fri, 10 Aug 2012, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Fri, 10 Aug 2012 12:57:59 +0300, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>> On Fri, 10 Aug 2012, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>> > When invalidating the TLBs it is documentated as requiring a post-sync
>> > write. Failure to do so seems to result in a GPU hang.
>> >
>> > Exposure to this hang on IVB seems to be a result of removing the extra
>> > stalls required for SNB pipecontrol workarounds:
>> 
>> Hi Chris, AFAICT TLB invalidate requires PIPE_CONTROL_CS_STALL set per
>> the spec. I can't find a mention of the post-sync write, though. Could
>> you double check, please?
>
> Considering replacing it with a CS_STALL just hard hung my box, I remain
> unconvinced. :-p

I meant you could check the spec, not actually try it! ;) But I accept
that's a good reason not to use it.

BR,
Jani.

  parent reply	other threads:[~2012-08-10 10:42 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-08-10  9:05 [PATCH] drm/i915: Apply post-sync write for pipe control invalidates Chris Wilson
2012-08-10  9:18 ` Chris Wilson
2012-08-10  9:57   ` Jani Nikula
2012-08-10 10:07     ` Chris Wilson
2012-08-10 10:11       ` Chris Wilson
2012-08-10 10:46       ` Jani Nikula [this message]
2012-08-11 19:20   ` Ben Widawsky
2012-08-11 19:47     ` Daniel Vetter
2012-08-14  7:57     ` Daniel Vetter

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