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* [PATCH] drm/i915/xe3p_lpd: Reduce lowest CDCLK PLL ratio to 18
@ 2026-10-05 18:38 Gustavo Sousa
  2026-10-05 19:55 ` ✓ i915.CI.BAT: success for " Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Gustavo Sousa @ 2026-10-05 18:38 UTC (permalink / raw)
  To: intel-xe, intel-gfx; +Cc: stable, Gustavo Sousa

The CDCLK table has been updated on Bspec to reduce the lowest PLL
ratio to 18 and improve voltage selection in some SKUs.  Update the
driver to match the new table.

Bspec: 68861
Fixes: af28e607fc75 ("drm/i915/xe3p_lpd: Add CDCLK table")
Cc: stable@vger.kernel.org # v6.19+
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 92e6fca861f6..dad5fbeaa1bd 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1593,16 +1593,18 @@ static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = {
 };
 
 static const struct intel_cdclk_vals xe3p_lpd_cdclk_table[] = {
-	{ .refclk = 38400, .cdclk = 151200, .ratio = 21, .waveform = 0xa4a4 },
-	{ .refclk = 38400, .cdclk = 176400, .ratio = 21, .waveform = 0xaa54 },
-	{ .refclk = 38400, .cdclk = 201600, .ratio = 21, .waveform = 0xaaaa },
-	{ .refclk = 38400, .cdclk = 226800, .ratio = 21, .waveform = 0xad5a },
-	{ .refclk = 38400, .cdclk = 252000, .ratio = 21, .waveform = 0xb6b6 },
-	{ .refclk = 38400, .cdclk = 277200, .ratio = 21, .waveform = 0xdbb6 },
-	{ .refclk = 38400, .cdclk = 302400, .ratio = 21, .waveform = 0xeeee },
-	{ .refclk = 38400, .cdclk = 327600, .ratio = 21, .waveform = 0xf7de },
-	{ .refclk = 38400, .cdclk = 352800, .ratio = 21, .waveform = 0xfefe },
-	{ .refclk = 38400, .cdclk = 378000, .ratio = 21, .waveform = 0xfffe },
+	{ .refclk = 38400, .cdclk = 151200, .ratio = 18, .waveform = 0xa54a },
+	{ .refclk = 38400, .cdclk = 172800, .ratio = 18, .waveform = 0xaaaa },
+	{ .refclk = 38400, .cdclk = 194400, .ratio = 18, .waveform = 0xad5a },
+	{ .refclk = 38400, .cdclk = 216000, .ratio = 18, .waveform = 0xb6b6 },
+	{ .refclk = 38400, .cdclk = 237600, .ratio = 18, .waveform = 0xdbb6 },
+	{ .refclk = 38400, .cdclk = 259200, .ratio = 18, .waveform = 0xeeee },
+	{ .refclk = 38400, .cdclk = 280800, .ratio = 18, .waveform = 0xf7de },
+	{ .refclk = 38400, .cdclk = 302400, .ratio = 18, .waveform = 0xfefe },
+	{ .refclk = 38400, .cdclk = 324000, .ratio = 18, .waveform = 0xfffe },
+	{ .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff },
 	{ .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
 	{ .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
 	{ .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },

---
base-commit: 28a2edb89a25a41d2a45e27d74dfd946872d0faf
change-id: 20261002-xe3p-cdclk-pll-18-59bd79cb5b4b

Best regards,
--  
Gustavo Sousa <gustavo.sousa@intel.com>


^ permalink raw reply related	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2026-10-07 20:08 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-10-05 18:38 [PATCH] drm/i915/xe3p_lpd: Reduce lowest CDCLK PLL ratio to 18 Gustavo Sousa
2026-10-05 19:55 ` ✓ i915.CI.BAT: success for " Patchwork
2026-10-06  0:24 ` ✓ i915.CI.Full: " Patchwork
2026-10-07  5:56 ` [PATCH] " Kandpal, Suraj
2026-10-07 20:08   ` Gustavo Sousa

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