From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 1/6] drm/i915: Handle all MCR ranges
Date: Thu, 12 Mar 2020 18:25:58 +0200 [thread overview]
Message-ID: <87d09h1qw9.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20200311162300.1838847-2-matthew.d.roper@intel.com>
Matt Roper <matthew.d.roper@intel.com> writes:
> The bspec documents multiple MCR ranges; make sure they're all captured
> by the driver.
>
> Bspec: 13991, 52079
> Fixes: 592a7c5e082e ("drm/i915: Extend non readable mcr range")
Yeah it seems that the ranges drip feed into documentation slowly.
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
> 1 file changed, 22 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 391f39b1fb26..3e352e2a5b79 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1648,15 +1648,34 @@ create_scratch(struct i915_address_space *vm, int count)
> return ERR_PTR(err);
> }
>
> +static const struct {
> + u32 start;
> + u32 end;
> +} mcr_ranges_gen8[] = {
> + { .start = 0x5500, .end = 0x55ff },
> + { .start = 0x7000, .end = 0x7fff },
> + { .start = 0x9400, .end = 0x97ff },
> + { .start = 0xb000, .end = 0xb3ff },
> + { .start = 0xe000, .end = 0xe7ff },
> + {},
> +};
> +
> static bool mcr_range(struct drm_i915_private *i915, u32 offset)
> {
> + int i;
> +
> + if (INTEL_GEN(i915) < 8)
> + return false;
> +
> /*
> - * Registers in this range are affected by the MCR selector
> + * Registers in these ranges are affected by the MCR selector
> * which only controls CPU initiated MMIO. Routing does not
> * work for CS access so we cannot verify them on this path.
> */
> - if (INTEL_GEN(i915) >= 8 && (offset >= 0xb000 && offset <= 0xb4ff))
> - return true;
> + for (i = 0; mcr_ranges_gen8[i].start; i++)
> + if (offset >= mcr_ranges_gen8[i].start &&
> + offset <= mcr_ranges_gen8[i].end)
> + return true;
>
> return false;
> }
> --
> 2.24.1
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next prev parent reply other threads:[~2020-03-12 16:27 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20200311162300.1838847-1-matthew.d.roper@intel.com>
2020-03-12 1:11 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Gen11 workarounds (rev2) Patchwork
2020-03-12 3:59 ` Matt Roper
2020-03-12 5:09 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Gen11 workarounds (rev3) Patchwork
2020-03-12 6:05 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Gen11 workarounds (rev4) Patchwork
[not found] ` <20200311162300.1838847-2-matthew.d.roper@intel.com>
2020-03-12 16:25 ` Mika Kuoppala [this message]
[not found] ` <20200311162300.1838847-6-matthew.d.roper@intel.com>
2020-03-12 16:27 ` [Intel-gfx] [PATCH v2 5/6] drm/i915: Apply Wa_1406680159:icl, ehl as an engine workaround Mika Kuoppala
[not found] ` <20200311162300.1838847-7-matthew.d.roper@intel.com>
2020-03-12 16:55 ` [Intel-gfx] [PATCH v2 6/6] drm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL and EHL Mika Kuoppala
2020-03-12 18:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Gen11 workarounds (rev5) Patchwork
[not found] ` <20200311162300.1838847-3-matthew.d.roper@intel.com>
2020-03-12 21:46 ` [Intel-gfx] [PATCH v2 2/6] drm/i915: Add Wa_1207131216:icl,ehl Souza, Jose
[not found] ` <20200311162300.1838847-5-matthew.d.roper@intel.com>
2020-03-12 22:07 ` [Intel-gfx] [PATCH v2 4/6] drm/i915: Add Wa_1406306137:icl,ehl Souza, Jose
2020-03-12 22:30 ` Souza, Jose
[not found] ` <20200311162300.1838847-4-matthew.d.roper@intel.com>
2020-03-12 22:38 ` [Intel-gfx] [PATCH v2 3/6] drm/i915: Add Wa_1604278689:icl,ehl Souza, Jose
2020-03-13 8:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for Gen11 workarounds (rev5) Patchwork
2020-03-13 16:05 ` Matt Roper
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