From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL and EHL
Date: Thu, 12 Mar 2020 18:55:48 +0200 [thread overview]
Message-ID: <877dzp1pij.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20200311162300.1838847-7-matthew.d.roper@intel.com>
Matt Roper <matthew.d.roper@intel.com> writes:
> This workaround appears under two different numbers (and with somewhat
> confused stepping applicability on ICL). Ultimately it appears we
> should just implement this for all stepping of ICL and EHL.
>
> Note that this is identical to Wa_1407928979:tgl that already exists in
> our driver too...yet another number referencing the same actual
> workaround.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index cbfc8d5ebb3e..5176ad1a3976 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1487,6 +1487,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> wa_write_or(wal,
> SUBSLICE_UNIT_LEVEL_CLKGATE,
> GWUNIT_CLKGATE_DIS);
> +
> + /*
> + * Wa_1408767742:icl[a2..forever],ehl[all]
> + * Wa_1605460711:icl[a0..c0]
> + */
> + wa_write_or(wal,
> + GEN7_FF_THREAD_MODE,
> + GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
The gen12 assignment is amusing artefact. But we learn these things
late sometimes. And when we do, we should try to proactively look one gen back.
This was supposed to be fixed in d0, then re-established.
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> }
>
> if (IS_GEN_RANGE(i915, 9, 12)) {
> --
> 2.24.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2020-03-12 16:57 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20200311162300.1838847-1-matthew.d.roper@intel.com>
2020-03-12 1:11 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Gen11 workarounds (rev2) Patchwork
2020-03-12 3:59 ` Matt Roper
2020-03-12 5:09 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Gen11 workarounds (rev3) Patchwork
2020-03-12 6:05 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Gen11 workarounds (rev4) Patchwork
[not found] ` <20200311162300.1838847-2-matthew.d.roper@intel.com>
2020-03-12 16:25 ` [Intel-gfx] [PATCH v2 1/6] drm/i915: Handle all MCR ranges Mika Kuoppala
[not found] ` <20200311162300.1838847-6-matthew.d.roper@intel.com>
2020-03-12 16:27 ` [Intel-gfx] [PATCH v2 5/6] drm/i915: Apply Wa_1406680159:icl, ehl as an engine workaround Mika Kuoppala
[not found] ` <20200311162300.1838847-7-matthew.d.roper@intel.com>
2020-03-12 16:55 ` Mika Kuoppala [this message]
2020-03-12 18:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Gen11 workarounds (rev5) Patchwork
[not found] ` <20200311162300.1838847-3-matthew.d.roper@intel.com>
2020-03-12 21:46 ` [Intel-gfx] [PATCH v2 2/6] drm/i915: Add Wa_1207131216:icl,ehl Souza, Jose
[not found] ` <20200311162300.1838847-5-matthew.d.roper@intel.com>
2020-03-12 22:07 ` [Intel-gfx] [PATCH v2 4/6] drm/i915: Add Wa_1406306137:icl,ehl Souza, Jose
2020-03-12 22:30 ` Souza, Jose
[not found] ` <20200311162300.1838847-4-matthew.d.roper@intel.com>
2020-03-12 22:38 ` [Intel-gfx] [PATCH v2 3/6] drm/i915: Add Wa_1604278689:icl,ehl Souza, Jose
2020-03-13 8:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for Gen11 workarounds (rev5) Patchwork
2020-03-13 16:05 ` Matt Roper
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