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* [PATCH v2 1/2] drm/i915: Fix audio power up sequence for gen10+ display
@ 2019-10-03  8:55 Kai Vehmanen
  2019-10-03  8:55 ` [PATCH v2 2/2] drm/i915: extend audio CDCLK>=2*BCLK constraint to more platforms Kai Vehmanen
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Kai Vehmanen @ 2019-10-03  8:55 UTC (permalink / raw)
  To: intel-gfx; +Cc: Jani Nikula, tiwai

On platfroms with gen10+ display, driver must set the enable bit of
AUDIO_PIN_BUF_CTL register before transactions with the HDA controller
can proceed. Add setting this bit to the audio power up sequence.

Failing to do this resulted in errors during display audio codec probe,
and failures during resume from suspend.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111214
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_audio.c | 5 +++++
 drivers/gpu/drm/i915/i915_reg.h            | 2 ++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 54638d99e021..e93776710abc 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -862,6 +862,11 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
 		/* Force CDCLK to 2*BCLK as long as we need audio powered. */
 		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
 			glk_force_audio_cdclk(dev_priv, true);
+
+		if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+			I915_WRITE(AUD_PIN_BUF_CTL,
+				   (I915_READ(AUD_PIN_BUF_CTL) |
+				    AUD_PIN_BUF_ENABLE));
 	}
 
 	return ret;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 058aa5ca8b73..18037d7803ad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9133,6 +9133,8 @@ enum {
 #define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
 
 #define AUD_FREQ_CNTRL			_MMIO(0x65900)
+#define AUD_PIN_BUF_CTL		_MMIO(0x48414)
+#define   AUD_PIN_BUF_ENABLE		REG_BIT(31)
 
 /*
  * HSW - ICL power wells
-- 
2.17.1

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^ permalink raw reply related	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2019-10-04 12:48 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-10-03  8:55 [PATCH v2 1/2] drm/i915: Fix audio power up sequence for gen10+ display Kai Vehmanen
2019-10-03  8:55 ` [PATCH v2 2/2] drm/i915: extend audio CDCLK>=2*BCLK constraint to more platforms Kai Vehmanen
2019-10-03 11:16 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915: Fix audio power up sequence for gen10+ display Patchwork
2019-10-03 18:26 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-10-04 12:48   ` Jani Nikula

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