[RFC 0/3] Link off between frames for edp

[RFC 0/3] Link off between frames for edp

[Animesh Manna]

Link Off Between Active Frames (LOBF) allows an eDP link to be turned Off and On
durning long VBLANK durations without enabling any of the PSR/PSR2/PR modes of operation.

Bspec: 71477

Note: This is a feature has dependency on ALPM, AS SDP. So the below changes
are done on top of the following patch series where review is ongoing. So
compilation issue expected from CI.
https://patchwork.freedesktop.org/series/129938/
https://patchwork.freedesktop.org/series/126829/

These patches are not tested, sending early for review feedback

Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Animesh Manna (3):
  drm/i915/alpm: Move alpm parameters from intel_psr
  drm/i915/alpm: Add compute config for lobf
  drm/i915/alpm: Enable lobf from source in ALPM_CTL

 .../drm/i915/display/intel_display_types.h    | 27 +++---
 drivers/gpu/drm/i915/display/intel_dp.c       |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 92 ++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_psr.h      |  3 +
 4 files changed, 89 insertions(+), 34 deletions(-)

-- 
2.29.0

[RFC 1/3] drm/i915/alpm: Move alpm parameters from intel_psr

[Animesh Manna]

ALPM can be enabled for non psr panel and currenly aplm-params are
encapsulated under intel_psr struct, so moving out to intel_dp struct.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../drm/i915/display/intel_display_types.h    | 23 +++++-----
 drivers/gpu/drm/i915/display/intel_psr.c      | 42 +++++++++----------
 2 files changed, 31 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index cc52693a0e58..d473d8dca90a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1715,18 +1715,6 @@ struct intel_psr {
 	bool psr2_sel_fetch_cff_enabled;
 	bool req_psr2_sdp_prior_scanline;
 	u8 sink_sync_latency;
-
-	struct {
-		u8 io_wake_lines;
-		u8 fast_wake_lines;
-
-		/* LNL and beyond */
-		u8 check_entry_lines;
-		u8 aux_less_wake_lines;
-		u8 silence_period_sym_clocks;
-		u8 lfps_half_cycle_num_of_syms;
-	} alpm_parameters;
-
 	ktime_t last_entry_attempt;
 	ktime_t last_exit;
 	bool sink_not_reliable;
@@ -1852,6 +1840,17 @@ struct intel_dp {
 	unsigned long last_oui_write;
 
 	bool colorimetry_support;
+
+	struct {
+		u8 io_wake_lines;
+		u8 fast_wake_lines;
+
+		/* LNL and beyond */
+		u8 check_entry_lines;
+		u8 aux_less_wake_lines;
+		u8 silence_period_sym_clocks;
+		u8 lfps_half_cycle_num_of_syms;
+	} alpm_parameters;
 };
 
 enum lspcon_vendor {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index ed5f62f89027..4adcddba69c1 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -779,8 +779,8 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
 
 static int psr2_block_count_lines(struct intel_dp *intel_dp)
 {
-	return intel_dp->psr.alpm_parameters.io_wake_lines < 9 &&
-		intel_dp->psr.alpm_parameters.fast_wake_lines < 9 ? 8 : 12;
+	return intel_dp->alpm_parameters.io_wake_lines < 9 &&
+		intel_dp->alpm_parameters.fast_wake_lines < 9 ? 8 : 12;
 }
 
 static int psr2_block_count(struct intel_dp *intel_dp)
@@ -817,7 +817,6 @@ static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	struct intel_psr *psr = &intel_dp->psr;
 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
 	u32 val = EDP_PSR2_ENABLE;
 	u32 psr_val = 0;
@@ -859,18 +858,18 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 		 */
 		int tmp;
 
-		tmp = map[psr->alpm_parameters.io_wake_lines -
+		tmp = map[intel_dp->alpm_parameters.io_wake_lines -
 			  TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
 		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(tmp + TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES);
 
-		tmp = map[psr->alpm_parameters.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
+		tmp = map[intel_dp->alpm_parameters.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
 		val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES);
 	} else if (DISPLAY_VER(dev_priv) >= 12) {
-		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines);
-		val |= TGL_EDP_PSR2_FAST_WAKE(psr->alpm_parameters.fast_wake_lines);
+		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines);
+		val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->alpm_parameters.fast_wake_lines);
 	} else if (DISPLAY_VER(dev_priv) >= 9) {
-		val |= EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines);
-		val |= EDP_PSR2_FAST_WAKE(psr->alpm_parameters.fast_wake_lines);
+		val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines);
+		val |= EDP_PSR2_FAST_WAKE(intel_dp->alpm_parameters.fast_wake_lines);
 	}
 
 	if (intel_dp->psr.req_psr2_sdp_prior_scanline)
@@ -1253,9 +1252,9 @@ static int _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
 	if (i915->display.params.psr_safest_params)
 		aux_less_wake_lines = 63;
 
-	intel_dp->psr.alpm_parameters.aux_less_wake_lines = aux_less_wake_lines;
-	intel_dp->psr.alpm_parameters.silence_period_sym_clocks = silence_period;
-	intel_dp->psr.alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle;
+	intel_dp->alpm_parameters.aux_less_wake_lines = aux_less_wake_lines;
+	intel_dp->alpm_parameters.silence_period_sym_clocks = silence_period;
+	intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle;
 
 	return true;
 }
@@ -1282,7 +1281,7 @@ static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,
 	if (i915->display.params.psr_safest_params)
 		check_entry_lines = 15;
 
-	intel_dp->psr.alpm_parameters.check_entry_lines = check_entry_lines;
+	intel_dp->alpm_parameters.check_entry_lines = check_entry_lines;
 
 	return true;
 }
@@ -1326,8 +1325,8 @@ static bool _compute_alpm_params(struct intel_dp *intel_dp,
 		io_wake_lines = fast_wake_lines = max_wake_lines;
 
 	/* According to Bspec lower limit should be set as 7 lines. */
-	intel_dp->psr.alpm_parameters.io_wake_lines = max(io_wake_lines, 7);
-	intel_dp->psr.alpm_parameters.fast_wake_lines = max(fast_wake_lines, 7);
+	intel_dp->alpm_parameters.io_wake_lines = max(io_wake_lines, 7);
+	intel_dp->alpm_parameters.fast_wake_lines = max(fast_wake_lines, 7);
 
 	return true;
 }
@@ -1695,7 +1694,6 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
-	struct intel_psr *psr = &intel_dp->psr;
 	u32 alpm_ctl;
 
 	if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.psr2_enabled &&
@@ -1712,22 +1710,22 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp)
 			       PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
 			       PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
 			       PORT_ALPM_CTL_SILENCE_PERIOD(
-				       psr->alpm_parameters.silence_period_sym_clocks));
+				       intel_dp->alpm_parameters.silence_period_sym_clocks));
 
 		intel_de_write(dev_priv, PORT_ALPM_LFPS_CTL(cpu_transcoder),
 			       PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
 			       PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
-				       psr->alpm_parameters.lfps_half_cycle_num_of_syms) |
+				       intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
 			       PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
-				       psr->alpm_parameters.lfps_half_cycle_num_of_syms) |
+				       intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
 			       PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
-				       psr->alpm_parameters.lfps_half_cycle_num_of_syms));
+				       intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms));
 	} else {
 		alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
-			ALPM_CTL_EXTENDED_FAST_WAKE_TIME(psr->alpm_parameters.fast_wake_lines);
+			ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines);
 	}
 
-	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(psr->alpm_parameters.check_entry_lines);
+	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines);
 
 	intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder), alpm_ctl);
 }
-- 
2.29.0

[RFC 2/3] drm/i915/alpm: Add compute config for lobf

[Animesh Manna]

Link Off Between Active Frames, is a new feature for eDP
that allows the panel to go to lower power state after
transmission of data. This is a feature on top of ALPM, AS SDP.
Add compute config during atomic-check phase.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  3 ++
 drivers/gpu/drm/i915/display/intel_dp.c       |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 45 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_psr.h      |  3 ++
 4 files changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d473d8dca90a..4d2161eeb686 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1851,6 +1851,9 @@ struct intel_dp {
 		u8 silence_period_sym_clocks;
 		u8 lfps_half_cycle_num_of_syms;
 	} alpm_parameters;
+
+	/* LOBF flags*/
+	bool lobf_supported;
 };
 
 enum lspcon_vendor {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8304ef912767..e34b70d88b9a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2979,6 +2979,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	intel_vrr_compute_config(pipe_config, conn_state);
 	intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state);
 	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
+	intel_psr_lobf_compute_config(intel_dp, pipe_config, conn_state);
 	intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
 	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
 	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4adcddba69c1..c08bffc2921a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -436,6 +436,16 @@ static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
 	return alpm_caps & DP_ALPM_CAP;
 }
 
+static bool intel_dp_get_aux_less_alpm_status(struct intel_dp *intel_dp)
+{
+	u8 alpm_caps = 0;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
+			      &alpm_caps) != 1)
+		return false;
+	return alpm_caps & DP_ALPM_AUX_LESS_CAP;
+}
+
 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1569,6 +1579,41 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
 }
 
+void intel_psr_lobf_compute_config(struct intel_dp *intel_dp,
+			       struct intel_crtc_state *crtc_state,
+			       struct drm_connector_state *conn_state)
+{
+	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	int waketime_in_lines, first_sdp_position;
+	int context_latency, guardband;
+	bool auxless_alpm;
+
+	intel_dp->lobf_supported = false;
+
+	if (!intel_dp_is_edp(intel_dp))
+		return;
+
+	if (!intel_dp_as_sdp_supported(intel_dp))
+		return;
+
+	if (CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))
+		return;
+
+	if (_compute_alpm_params(intel_dp, crtc_state)) {
+		context_latency = adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
+		guardband = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - context_latency;
+		first_sdp_position = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
+		auxless_alpm = intel_dp_get_aux_less_alpm_status(intel_dp);
+		if (auxless_alpm)
+			waketime_in_lines = intel_dp->alpm_parameters.io_wake_lines;
+		else
+			waketime_in_lines = intel_dp->alpm_parameters.aux_less_wake_lines;
+
+		if ((context_latency + guardband) > (first_sdp_position + waketime_in_lines))
+			intel_dp->lobf_supported = true;
+	}
+}
+
 void intel_psr_get_config(struct intel_encoder *encoder,
 			  struct intel_crtc_state *pipe_config)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index cde781df84d5..4bb77295288f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -40,6 +40,9 @@ void intel_psr_init(struct intel_dp *intel_dp);
 void intel_psr_compute_config(struct intel_dp *intel_dp,
 			      struct intel_crtc_state *crtc_state,
 			      struct drm_connector_state *conn_state);
+void intel_psr_lobf_compute_config(struct intel_dp *intel_dp,
+				   struct intel_crtc_state *crtc_state,
+				   struct drm_connector_state *conn_state);
 void intel_psr_get_config(struct intel_encoder *encoder,
 			  struct intel_crtc_state *pipe_config);
 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
-- 
2.29.0

[RFC 3/3] drm/i915/alpm: Enable lobf from source in ALPM_CTL

[Animesh Manna]

Set the Link Off Between Frames Enable bit in ALPM_CTL register.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
 drivers/gpu/drm/i915/display/intel_psr.c           | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 4d2161eeb686..c8e7a65df45d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1854,6 +1854,7 @@ struct intel_dp {
 
 	/* LOBF flags*/
 	bool lobf_supported;
+	bool lobf_enabled;
 };
 
 enum lspcon_vendor {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c08bffc2921a..a9f8f2982b50 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1770,6 +1770,11 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp)
 			ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines);
 	}
 
+	if (intel_dp->lobf_supported) {
+		alpm_ctl |= ALPM_CTL_LOBF_ENABLE;
+		intel_dp->lobf_enabled = true;
+	}
+
 	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines);
 
 	intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder), alpm_ctl);
-- 
2.29.0

Re: [RFC 2/3] drm/i915/alpm: Add compute config for lobf

[Jani Nikula]

On Mon, 04 Mar 2024, Animesh Manna <animesh.manna@intel.com> wrote:
> Link Off Between Active Frames, is a new feature for eDP
> that allows the panel to go to lower power state after
> transmission of data. This is a feature on top of ALPM, AS SDP.
> Add compute config during atomic-check phase.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  3 ++
>  drivers/gpu/drm/i915/display/intel_dp.c       |  1 +
>  drivers/gpu/drm/i915/display/intel_psr.c      | 45 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_psr.h      |  3 ++
>  4 files changed, 52 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d473d8dca90a..4d2161eeb686 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1851,6 +1851,9 @@ struct intel_dp {
>  		u8 silence_period_sym_clocks;
>  		u8 lfps_half_cycle_num_of_syms;
>  	} alpm_parameters;
> +
> +	/* LOBF flags*/
> +	bool lobf_supported;
>  };
>  
>  enum lspcon_vendor {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8304ef912767..e34b70d88b9a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2979,6 +2979,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  	intel_vrr_compute_config(pipe_config, conn_state);
>  	intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state);
>  	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> +	intel_psr_lobf_compute_config(intel_dp, pipe_config, conn_state);
>  	intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
>  	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
>  	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4adcddba69c1..c08bffc2921a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -436,6 +436,16 @@ static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
>  	return alpm_caps & DP_ALPM_CAP;
>  }
>  
> +static bool intel_dp_get_aux_less_alpm_status(struct intel_dp *intel_dp)
> +{
> +	u8 alpm_caps = 0;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
> +			      &alpm_caps) != 1)

The compute config path must not access the hardware.

BR,
Jani.

> +		return false;
> +	return alpm_caps & DP_ALPM_AUX_LESS_CAP;
> +}
> +
>  static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> @@ -1569,6 +1579,41 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  	crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
>  }
>  
> +void intel_psr_lobf_compute_config(struct intel_dp *intel_dp,
> +			       struct intel_crtc_state *crtc_state,
> +			       struct drm_connector_state *conn_state)
> +{
> +	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +	int waketime_in_lines, first_sdp_position;
> +	int context_latency, guardband;
> +	bool auxless_alpm;
> +
> +	intel_dp->lobf_supported = false;
> +
> +	if (!intel_dp_is_edp(intel_dp))
> +		return;
> +
> +	if (!intel_dp_as_sdp_supported(intel_dp))
> +		return;
> +
> +	if (CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))
> +		return;
> +
> +	if (_compute_alpm_params(intel_dp, crtc_state)) {
> +		context_latency = adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
> +		guardband = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - context_latency;
> +		first_sdp_position = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
> +		auxless_alpm = intel_dp_get_aux_less_alpm_status(intel_dp);
> +		if (auxless_alpm)
> +			waketime_in_lines = intel_dp->alpm_parameters.io_wake_lines;
> +		else
> +			waketime_in_lines = intel_dp->alpm_parameters.aux_less_wake_lines;
> +
> +		if ((context_latency + guardband) > (first_sdp_position + waketime_in_lines))
> +			intel_dp->lobf_supported = true;
> +	}
> +}
> +
>  void intel_psr_get_config(struct intel_encoder *encoder,
>  			  struct intel_crtc_state *pipe_config)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index cde781df84d5..4bb77295288f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -40,6 +40,9 @@ void intel_psr_init(struct intel_dp *intel_dp);
>  void intel_psr_compute_config(struct intel_dp *intel_dp,
>  			      struct intel_crtc_state *crtc_state,
>  			      struct drm_connector_state *conn_state);
> +void intel_psr_lobf_compute_config(struct intel_dp *intel_dp,
> +				   struct intel_crtc_state *crtc_state,
> +				   struct drm_connector_state *conn_state);
>  void intel_psr_get_config(struct intel_encoder *encoder,
>  			  struct intel_crtc_state *pipe_config);
>  void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);

-- 
Jani Nikula, Intel

✗ Fi.CI.BUILD: failure for Link off between frames for edp

[Patchwork]

== Series Details ==

Series: Link off between frames for edp
URL   : https://patchwork.freedesktop.org/series/130650/
State : failure

== Summary ==

Error: patch https://patchwork.freedesktop.org/api/1.0/series/130650/revisions/1/mbox/ not applied
Applying: drm/i915/alpm: Move alpm parameters from intel_psr
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_display_types.h).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915/alpm: Move alpm parameters from intel_psr
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced

RE: [RFC 2/3] drm/i915/alpm: Add compute config for lobf

[Manna, Animesh]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Monday, March 4, 2024 11:03 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Hogander, Jouni <jouni.hogander@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Manna, Animesh <animesh.manna@intel.com>
> Subject: Re: [RFC 2/3] drm/i915/alpm: Add compute config for lobf
> 
> On Mon, 04 Mar 2024, Animesh Manna <animesh.manna@intel.com>
> wrote:
> > Link Off Between Active Frames, is a new feature for eDP that allows
> > the panel to go to lower power state after transmission of data. This
> > is a feature on top of ALPM, AS SDP.
> > Add compute config during atomic-check phase.
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_types.h    |  3 ++
> >  drivers/gpu/drm/i915/display/intel_dp.c       |  1 +
> >  drivers/gpu/drm/i915/display/intel_psr.c      | 45 +++++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_psr.h      |  3 ++
> >  4 files changed, 52 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index d473d8dca90a..4d2161eeb686 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1851,6 +1851,9 @@ struct intel_dp {
> >  		u8 silence_period_sym_clocks;
> >  		u8 lfps_half_cycle_num_of_syms;
> >  	} alpm_parameters;
> > +
> > +	/* LOBF flags*/
> > +	bool lobf_supported;
> >  };
> >
> >  enum lspcon_vendor {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 8304ef912767..e34b70d88b9a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2979,6 +2979,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
> >  	intel_vrr_compute_config(pipe_config, conn_state);
> >  	intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state);
> >  	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> > +	intel_psr_lobf_compute_config(intel_dp, pipe_config, conn_state);
> >  	intel_dp_drrs_compute_config(connector, pipe_config,
> link_bpp_x16);
> >  	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> >  	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp,
> pipe_config,
> > conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 4adcddba69c1..c08bffc2921a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -436,6 +436,16 @@ static bool intel_dp_get_alpm_status(struct
> intel_dp *intel_dp)
> >  	return alpm_caps & DP_ALPM_CAP;
> >  }
> >
> > +static bool intel_dp_get_aux_less_alpm_status(struct intel_dp
> > +*intel_dp) {
> > +	u8 alpm_caps = 0;
> > +
> > +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
> > +			      &alpm_caps) != 1)
> 
> The compute config path must not access the hardware.

Sure, will put in init_connector() and store in a variable.

Regards,
Animesh

> 
> BR,
> Jani.
> 
> > +		return false;
> > +	return alpm_caps & DP_ALPM_AUX_LESS_CAP; }
> > +
> >  static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
> > {
> >  	struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -1569,6
> > +1579,41 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> >  	crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
> > crtc_state);  }
> >
> > +void intel_psr_lobf_compute_config(struct intel_dp *intel_dp,
> > +			       struct intel_crtc_state *crtc_state,
> > +			       struct drm_connector_state *conn_state) {
> > +	struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> > +	int waketime_in_lines, first_sdp_position;
> > +	int context_latency, guardband;
> > +	bool auxless_alpm;
> > +
> > +	intel_dp->lobf_supported = false;
> > +
> > +	if (!intel_dp_is_edp(intel_dp))
> > +		return;
> > +
> > +	if (!intel_dp_as_sdp_supported(intel_dp))
> > +		return;
> > +
> > +	if (CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))
> > +		return;
> > +
> > +	if (_compute_alpm_params(intel_dp, crtc_state)) {
> > +		context_latency = adjusted_mode->crtc_vblank_start -
> adjusted_mode->crtc_vdisplay;
> > +		guardband = adjusted_mode->crtc_vtotal - adjusted_mode-
> >crtc_vdisplay - context_latency;
> > +		first_sdp_position = adjusted_mode->crtc_vtotal -
> adjusted_mode->crtc_vsync_start;
> > +		auxless_alpm =
> intel_dp_get_aux_less_alpm_status(intel_dp);
> > +		if (auxless_alpm)
> > +			waketime_in_lines = intel_dp-
> >alpm_parameters.io_wake_lines;
> > +		else
> > +			waketime_in_lines = intel_dp-
> >alpm_parameters.aux_less_wake_lines;
> > +
> > +		if ((context_latency + guardband) > (first_sdp_position +
> waketime_in_lines))
> > +			intel_dp->lobf_supported = true;
> > +	}
> > +}
> > +
> >  void intel_psr_get_config(struct intel_encoder *encoder,
> >  			  struct intel_crtc_state *pipe_config)  { diff --git
> > a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index cde781df84d5..4bb77295288f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -40,6 +40,9 @@ void intel_psr_init(struct intel_dp *intel_dp);
> > void intel_psr_compute_config(struct intel_dp *intel_dp,
> >  			      struct intel_crtc_state *crtc_state,
> >  			      struct drm_connector_state *conn_state);
> > +void intel_psr_lobf_compute_config(struct intel_dp *intel_dp,
> > +				   struct intel_crtc_state *crtc_state,
> > +				   struct drm_connector_state *conn_state);
> >  void intel_psr_get_config(struct intel_encoder *encoder,
> >  			  struct intel_crtc_state *pipe_config);  void
> > intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
> 
> --
> Jani Nikula, Intel

Re: [RFC 2/3] drm/i915/alpm: Add compute config for lobf

[Hogander, Jouni]

On Mon, 2024-03-04 at 13:13 +0530, Animesh Manna wrote:
> Link Off Between Active Frames, is a new feature for eDP
> that allows the panel to go to lower power state after
> transmission of data. This is a feature on top of ALPM, AS SDP.
> Add compute config during atomic-check phase.
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  3 ++
>  drivers/gpu/drm/i915/display/intel_dp.c       |  1 +
>  drivers/gpu/drm/i915/display/intel_psr.c      | 45
> +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_psr.h      |  3 ++
>  4 files changed, 52 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d473d8dca90a..4d2161eeb686 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1851,6 +1851,9 @@ struct intel_dp {
>                 u8 silence_period_sym_clocks;
>                 u8 lfps_half_cycle_num_of_syms;
>         } alpm_parameters;
> +
> +       /* LOBF flags*/
> +       bool lobf_supported;
>  };
>  
>  enum lspcon_vendor {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8304ef912767..e34b70d88b9a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2979,6 +2979,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
>         intel_vrr_compute_config(pipe_config, conn_state);
>         intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state);
>         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> +       intel_psr_lobf_compute_config(intel_dp, pipe_config,
> conn_state);
>         intel_dp_drrs_compute_config(connector, pipe_config,
> link_bpp_x16);
>         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
>         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp,
> pipe_config, conn_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4adcddba69c1..c08bffc2921a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -436,6 +436,16 @@ static bool intel_dp_get_alpm_status(struct
> intel_dp *intel_dp)
>         return alpm_caps & DP_ALPM_CAP;
>  }
>  
> +static bool intel_dp_get_aux_less_alpm_status(struct intel_dp
> *intel_dp)
> +{
> +       u8 alpm_caps = 0;
> +
> +       if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
> +                             &alpm_caps) != 1)
> +               return false;
> +       return alpm_caps & DP_ALPM_AUX_LESS_CAP;
> +}
> +
>  static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
>  {
>         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> @@ -1569,6 +1579,41 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>         crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
> crtc_state);
>  }
>  
> +void intel_psr_lobf_compute_config(struct intel_dp *intel_dp,
> +                              struct intel_crtc_state *crtc_state,
> +                              struct drm_connector_state

I think this could rather be intel_alpm_compute_config which would
compute alpm parameters including enable for alpm, aux less and lobf.

> *conn_state)
> +{
> +       struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> +       int waketime_in_lines, first_sdp_position;
> +       int context_latency, guardband;
> +       bool auxless_alpm;
> +
> +       intel_dp->lobf_supported = false;
> +
> +       if (!intel_dp_is_edp(intel_dp))
> +               return;
> +
> +       if (!intel_dp_as_sdp_supported(intel_dp))
> +               return;
> +
> +       if (CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))
> +               return;

Maybe this should check crtc_state->has_psr2 and crtc_state-
>has_panel_replay ?

BR,

Jouni Högander

> +
> +       if (_compute_alpm_params(intel_dp, crtc_state)) {
> +               context_latency = adjusted_mode->crtc_vblank_start -
> adjusted_mode->crtc_vdisplay;
> +               guardband = adjusted_mode->crtc_vtotal -
> adjusted_mode->crtc_vdisplay - context_latency;
> +               first_sdp_position = adjusted_mode->crtc_vtotal -
> adjusted_mode->crtc_vsync_start;
> +               auxless_alpm =
> intel_dp_get_aux_less_alpm_status(intel_dp);
> +               if (auxless_alpm)
> +                       waketime_in_lines = intel_dp-
> >alpm_parameters.io_wake_lines;
> +               else
> +                       waketime_in_lines = intel_dp-
> >alpm_parameters.aux_less_wake_lines;
> +
> +               if ((context_latency + guardband) >
> (first_sdp_position + waketime_in_lines))
> +                       intel_dp->lobf_supported = true;
> +       }
> +}
> +
>  void intel_psr_get_config(struct intel_encoder *encoder,
>                           struct intel_crtc_state *pipe_config)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index cde781df84d5..4bb77295288f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -40,6 +40,9 @@ void intel_psr_init(struct intel_dp *intel_dp);
>  void intel_psr_compute_config(struct intel_dp *intel_dp,
>                               struct intel_crtc_state *crtc_state,
>                               struct drm_connector_state
> *conn_state);
> +void intel_psr_lobf_compute_config(struct intel_dp *intel_dp,
> +                                  struct intel_crtc_state
> *crtc_state,
> +                                  struct drm_connector_state
> *conn_state);
>  void intel_psr_get_config(struct intel_encoder *encoder,
>                           struct intel_crtc_state *pipe_config);
>  void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);