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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 3/4] drm/i915/mst: Clear ACT just before triggering payload allocation
Date: Mon, 30 Oct 2023 14:44:36 +0200	[thread overview]
Message-ID: <87edhc5lfv.fsf@intel.com> (raw)
In-Reply-To: <20231018154123.5479-4-ville.syrjala@linux.intel.com>

On Wed, 18 Oct 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Follow the bspec sequqnece more closely and clear ACT sent just
                   ^ sequence

> before triggering the allocation. Can't see why we'd want to
> deviate from the spec sequence here.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 57eb581b8a50..3c66a3e3cc5e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -791,8 +791,6 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
>  
>  	drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
>  
> -	clear_act_sent(encoder, pipe_config);
> -
>  	if (intel_dp_is_uhbr(pipe_config)) {
>  		const struct drm_display_mode *adjusted_mode =
>  			&pipe_config->hw.adjusted_mode;
> @@ -806,6 +804,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
>  
>  	intel_ddi_enable_transcoder_func(encoder, pipe_config);
>  
> +	clear_act_sent(encoder, pipe_config);
> +
>  	intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
>  		     TRANS_DDI_DP_VC_PAYLOAD_ALLOC);

-- 
Jani Nikula, Intel

  parent reply	other threads:[~2023-10-30 12:44 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-18 15:41 [Intel-gfx] [PATCH 0/4] drm/i915/mst: MST modeset sequence fixes Ville Syrjala
2023-10-18 15:41 ` [Intel-gfx] [PATCH 1/4] drm/i915/mst: Swap TRANSCONF vs. FECSTALL_DIS_DPTSTREAM_DPTTG disable Ville Syrjala
2023-10-30 12:38   ` Jani Nikula
2023-10-18 15:41 ` [Intel-gfx] [PATCH 2/4] drm/i915/mst: Disable transcoder before deleting the payload Ville Syrjala
2023-10-30 12:42   ` Jani Nikula
2023-11-01 10:27   ` Ville Syrjälä
2023-10-18 15:41 ` [Intel-gfx] [PATCH 3/4] drm/i915/mst: Clear ACT just before triggering payload allocation Ville Syrjala
2023-10-30 12:44   ` Jani Nikula
2023-10-30 12:44   ` Jani Nikula [this message]
2023-10-18 15:41 ` [Intel-gfx] [PATCH 4/4] drm/i915/mst: Always write CHICKEN_TRANS Ville Syrjala
2023-10-30 12:45   ` Jani Nikula
2023-10-18 23:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mst: MST modeset sequence fixes Patchwork
2023-10-18 23:42 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-10-24 13:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mst: MST modeset sequence fixes (rev2) Patchwork
2023-10-24 13:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-24 22:57 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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