[Intel-gfx] [PATCH] drm/i915/backlight: split out backlight registers to a separate file

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* [Intel-gfx] [PATCH] drm/i915/backlight: split out backlight registers to a separate file
@ 2022-08-15  9:48 Jani Nikula
  2022-08-15 10:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
                   ` (3 more replies)
  0 siblings, 4 replies; 6+ messages in thread
From: Jani Nikula @ 2022-08-15  9:48 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Declutter i915_reg.h by splitting backlight registers to a separate
file. Also include the utility pin definitions, even though they are
used for non-backlight things too.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        |   1 +
 .../gpu/drm/i915/display/intel_backlight.c    |   1 +
 .../drm/i915/display/intel_backlight_regs.h   | 124 ++++++++++++++++++
 .../drm/i915/display/intel_display_power.c    |   1 +
 .../i915/display/intel_display_power_well.c   |   1 +
 drivers/gpu/drm/i915/i915_reg.h               | 112 ----------------
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |   1 +
 7 files changed, 129 insertions(+), 112 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_backlight_regs.h

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 5dcfa7feffa9..c182253196f3 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -33,6 +33,7 @@
 #include "icl_dsi_regs.h"
 #include "intel_atomic.h"
 #include "intel_backlight.h"
+#include "intel_backlight_regs.h"
 #include "intel_combo_phy.h"
 #include "intel_combo_phy_regs.h"
 #include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index 110fc98ec280..262b2fda37e5 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -9,6 +9,7 @@
 #include <linux/string_helpers.h>
 
 #include "intel_backlight.h"
+#include "intel_backlight_regs.h"
 #include "intel_connector.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/display/intel_backlight_regs.h b/drivers/gpu/drm/i915/display/intel_backlight_regs.h
new file mode 100644
index 000000000000..50c1210f6d5d
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_backlight_regs.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_BACKLIGHT_REGS_H__
+#define __INTEL_BACKLIGHT_REGS_H__
+
+#include "i915_reg_defs.h"
+
+#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
+#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
+#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
+					 _VLV_BLC_PWM_CTL2_B)
+
+#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
+#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
+#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
+					_VLV_BLC_PWM_CTL_B)
+
+#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
+#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
+#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
+					 _VLV_BLC_HIST_CTL_B)
+
+/* Backlight control */
+#define BLC_PWM_CTL2	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
+#define   BLM_PWM_ENABLE		(1 << 31)
+#define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
+#define   BLM_PIPE_SELECT		(1 << 29)
+#define   BLM_PIPE_SELECT_IVB		(3 << 29)
+#define   BLM_PIPE_A			(0 << 29)
+#define   BLM_PIPE_B			(1 << 29)
+#define   BLM_PIPE_C			(2 << 29) /* ivb + */
+#define   BLM_TRANSCODER_A		BLM_PIPE_A /* hsw */
+#define   BLM_TRANSCODER_B		BLM_PIPE_B
+#define   BLM_TRANSCODER_C		BLM_PIPE_C
+#define   BLM_TRANSCODER_EDP		(3 << 29)
+#define   BLM_PIPE(pipe)		((pipe) << 29)
+#define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
+#define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
+#define   BLM_PHASE_IN_ENABLE		(1 << 25)
+#define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
+#define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
+#define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
+#define   BLM_PHASE_IN_COUNT_SHIFT	(8)
+#define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
+#define   BLM_PHASE_IN_INCR_SHIFT	(0)
+#define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
+#define BLC_PWM_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
+/*
+ * This is the most significant 15 bits of the number of backlight cycles in a
+ * complete cycle of the modulated backlight control.
+ *
+ * The actual value is this field multiplied by two.
+ */
+#define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
+#define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
+#define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
+/*
+ * This is the number of cycles out of the backlight modulation cycle for which
+ * the backlight is on.
+ *
+ * This field must be no greater than the number of cycles in the complete
+ * backlight modulation cycle.
+ */
+#define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
+#define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
+#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
+#define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
+
+#define BLC_HIST_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
+#define  BLM_HISTOGRAM_ENABLE			(1 << 31)
+
+/* New registers for PCH-split platforms. Safe where new bits show up, the
+ * register layout machtes with gen4 BLC_PWM_CTL[12]. */
+#define BLC_PWM_CPU_CTL2	_MMIO(0x48250)
+#define BLC_PWM_CPU_CTL		_MMIO(0x48254)
+
+#define HSW_BLC_PWM2_CTL	_MMIO(0x48350)
+
+/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
+ * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
+#define BLC_PWM_PCH_CTL1	_MMIO(0xc8250)
+#define   BLM_PCH_PWM_ENABLE			(1 << 31)
+#define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
+#define   BLM_PCH_POLARITY			(1 << 29)
+#define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
+
+/* BXT backlight register definition. */
+#define _BXT_BLC_PWM_CTL1			0xC8250
+#define   BXT_BLC_PWM_ENABLE			(1 << 31)
+#define   BXT_BLC_PWM_POLARITY			(1 << 29)
+#define _BXT_BLC_PWM_FREQ1			0xC8254
+#define _BXT_BLC_PWM_DUTY1			0xC8258
+
+#define _BXT_BLC_PWM_CTL2			0xC8350
+#define _BXT_BLC_PWM_FREQ2			0xC8354
+#define _BXT_BLC_PWM_DUTY2			0xC8358
+
+#define BXT_BLC_PWM_CTL(controller)    _MMIO_PIPE(controller,		\
+					_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
+#define BXT_BLC_PWM_FREQ(controller)   _MMIO_PIPE(controller, \
+					_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
+#define BXT_BLC_PWM_DUTY(controller)   _MMIO_PIPE(controller, \
+					_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
+
+/* Utility pin */
+#define UTIL_PIN_CTL			_MMIO(0x48400)
+#define   UTIL_PIN_ENABLE		(1 << 31)
+#define   UTIL_PIN_PIPE_MASK		(3 << 29)
+#define   UTIL_PIN_PIPE(x)		((x) << 29)
+#define   UTIL_PIN_MODE_MASK		(0xf << 24)
+#define   UTIL_PIN_MODE_DATA		(0 << 24)
+#define   UTIL_PIN_MODE_PWM		(1 << 24)
+#define   UTIL_PIN_MODE_VBLANK		(4 << 24)
+#define   UTIL_PIN_MODE_VSYNC		(5 << 24)
+#define   UTIL_PIN_MODE_EYE_LEVEL	(8 << 24)
+#define   UTIL_PIN_OUTPUT_DATA		(1 << 23)
+#define   UTIL_PIN_POLARITY		(1 << 22)
+#define   UTIL_PIN_DIRECTION_INPUT	(1 << 19)
+#define   UTIL_PIN_INPUT_DATA		(1 << 16)
+
+#endif /* __INTEL_BACKLIGHT_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 3f84af6beff3..1d8f2935ed98 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -7,6 +7,7 @@
 
 #include "i915_drv.h"
 #include "i915_irq.h"
+#include "intel_backlight_regs.h"
 #include "intel_cdclk.h"
 #include "intel_combo_phy.h"
 #include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 91cfd5890f46..7044016d4d98 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -5,6 +5,7 @@
 
 #include "i915_drv.h"
 #include "i915_irq.h"
+#include "intel_backlight_regs.h"
 #include "intel_combo_phy.h"
 #include "intel_combo_phy_regs.h"
 #include "intel_crt.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ad2c441aceca..50d7bfd541ad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2925,118 +2925,6 @@
 
 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
 
-#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
-#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
-#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
-					 _VLV_BLC_PWM_CTL2_B)
-
-#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
-#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
-#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
-					_VLV_BLC_PWM_CTL_B)
-
-#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
-#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
-#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
-					 _VLV_BLC_HIST_CTL_B)
-
-/* Backlight control */
-#define BLC_PWM_CTL2	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
-#define   BLM_PWM_ENABLE		(1 << 31)
-#define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
-#define   BLM_PIPE_SELECT		(1 << 29)
-#define   BLM_PIPE_SELECT_IVB		(3 << 29)
-#define   BLM_PIPE_A			(0 << 29)
-#define   BLM_PIPE_B			(1 << 29)
-#define   BLM_PIPE_C			(2 << 29) /* ivb + */
-#define   BLM_TRANSCODER_A		BLM_PIPE_A /* hsw */
-#define   BLM_TRANSCODER_B		BLM_PIPE_B
-#define   BLM_TRANSCODER_C		BLM_PIPE_C
-#define   BLM_TRANSCODER_EDP		(3 << 29)
-#define   BLM_PIPE(pipe)		((pipe) << 29)
-#define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
-#define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
-#define   BLM_PHASE_IN_ENABLE		(1 << 25)
-#define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
-#define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
-#define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
-#define   BLM_PHASE_IN_COUNT_SHIFT	(8)
-#define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
-#define   BLM_PHASE_IN_INCR_SHIFT	(0)
-#define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
-#define BLC_PWM_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
-/*
- * This is the most significant 15 bits of the number of backlight cycles in a
- * complete cycle of the modulated backlight control.
- *
- * The actual value is this field multiplied by two.
- */
-#define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
-#define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
-#define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
-/*
- * This is the number of cycles out of the backlight modulation cycle for which
- * the backlight is on.
- *
- * This field must be no greater than the number of cycles in the complete
- * backlight modulation cycle.
- */
-#define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
-#define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
-#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
-#define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
-
-#define BLC_HIST_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
-#define  BLM_HISTOGRAM_ENABLE			(1 << 31)
-
-/* New registers for PCH-split platforms. Safe where new bits show up, the
- * register layout machtes with gen4 BLC_PWM_CTL[12]. */
-#define BLC_PWM_CPU_CTL2	_MMIO(0x48250)
-#define BLC_PWM_CPU_CTL		_MMIO(0x48254)
-
-#define HSW_BLC_PWM2_CTL	_MMIO(0x48350)
-
-/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
- * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
-#define BLC_PWM_PCH_CTL1	_MMIO(0xc8250)
-#define   BLM_PCH_PWM_ENABLE			(1 << 31)
-#define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
-#define   BLM_PCH_POLARITY			(1 << 29)
-#define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
-
-#define UTIL_PIN_CTL			_MMIO(0x48400)
-#define   UTIL_PIN_ENABLE		(1 << 31)
-#define   UTIL_PIN_PIPE_MASK		(3 << 29)
-#define   UTIL_PIN_PIPE(x)		((x) << 29)
-#define   UTIL_PIN_MODE_MASK		(0xf << 24)
-#define   UTIL_PIN_MODE_DATA		(0 << 24)
-#define   UTIL_PIN_MODE_PWM		(1 << 24)
-#define   UTIL_PIN_MODE_VBLANK		(4 << 24)
-#define   UTIL_PIN_MODE_VSYNC		(5 << 24)
-#define   UTIL_PIN_MODE_EYE_LEVEL	(8 << 24)
-#define   UTIL_PIN_OUTPUT_DATA		(1 << 23)
-#define   UTIL_PIN_POLARITY		(1 << 22)
-#define   UTIL_PIN_DIRECTION_INPUT	(1 << 19)
-#define   UTIL_PIN_INPUT_DATA		(1 << 16)
-
-/* BXT backlight register definition. */
-#define _BXT_BLC_PWM_CTL1			0xC8250
-#define   BXT_BLC_PWM_ENABLE			(1 << 31)
-#define   BXT_BLC_PWM_POLARITY			(1 << 29)
-#define _BXT_BLC_PWM_FREQ1			0xC8254
-#define _BXT_BLC_PWM_DUTY1			0xC8258
-
-#define _BXT_BLC_PWM_CTL2			0xC8350
-#define _BXT_BLC_PWM_FREQ2			0xC8354
-#define _BXT_BLC_PWM_DUTY2			0xC8358
-
-#define BXT_BLC_PWM_CTL(controller)    _MMIO_PIPE(controller,		\
-					_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
-#define BXT_BLC_PWM_FREQ(controller)   _MMIO_PIPE(controller, \
-					_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
-#define BXT_BLC_PWM_DUTY(controller)   _MMIO_PIPE(controller, \
-					_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
-
 #define PCH_GTC_CTL		_MMIO(0xe7000)
 #define   PCH_GTC_ENABLE	(1 << 31)
 
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 157e166672d7..e015bc91a26f 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -4,6 +4,7 @@
  */
 
 #include "display/intel_audio_regs.h"
+#include "display/intel_backlight_regs.h"
 #include "display/intel_dmc_regs.h"
 #include "display/vlv_dsi_pll_regs.h"
 #include "gt/intel_gt_regs.h"
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/backlight: split out backlight registers to a separate file
  2022-08-15  9:48 [Intel-gfx] [PATCH] drm/i915/backlight: split out backlight registers to a separate file Jani Nikula
@ 2022-08-15 10:14 ` Patchwork
  2022-08-15 10:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2022-08-15 10:14 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/backlight: split out backlight registers to a separate file
URL   : https://patchwork.freedesktop.org/series/107270/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.



^ permalink raw reply	[flat|nested] 6+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/backlight: split out backlight registers to a separate file
  2022-08-15  9:48 [Intel-gfx] [PATCH] drm/i915/backlight: split out backlight registers to a separate file Jani Nikula
  2022-08-15 10:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
@ 2022-08-15 10:33 ` Patchwork
  2022-08-15 15:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  2022-08-16  4:18 ` [Intel-gfx] [PATCH] " Murthy, Arun R
  3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2022-08-15 10:33 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 4369 bytes --]

== Series Details ==

Series: drm/i915/backlight: split out backlight registers to a separate file
URL   : https://patchwork.freedesktop.org/series/107270/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11988 -> Patchwork_107270v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/index.html

Participating hosts (28 -> 28)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_107270v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-hsw-g3258:       NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#111827])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/fi-hsw-g3258/igt@kms_chamelium@common-hpd-after-suspend.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - fi-cfl-8109u:       [DMESG-FAIL][2] ([i915#62]) -> [PASS][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@gt_pm:
    - {fi-jsl-1}:         [DMESG-FAIL][4] ([i915#1886]) -> [PASS][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/fi-jsl-1/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-g3258:       [INCOMPLETE][6] ([i915#3303] / [i915#4785]) -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@ring_submission:
    - fi-cfl-8109u:       [DMESG-WARN][8] ([i915#5904]) -> [PASS][9] +30 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - fi-cfl-8109u:       [DMESG-WARN][10] ([i915#5904] / [i915#62]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-cfl-8109u:       [DMESG-WARN][12] ([i915#62]) -> [PASS][13] +12 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#5904]: https://gitlab.freedesktop.org/drm/intel/issues/5904
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62


Build changes
-------------

  * Linux: CI_DRM_11988 -> Patchwork_107270v1

  CI-20190529: 20190529
  CI_DRM_11988: a707ffeb65d1883ae1c1aec2b5ed447187781ad1 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6625: d47beef9b01595f721c584070940c95be1cf11e8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_107270v1: a707ffeb65d1883ae1c1aec2b5ed447187781ad1 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

a9ad31ce8100 drm/i915/backlight: split out backlight registers to a separate file

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/index.html

[-- Attachment #2: Type: text/html, Size: 5336 bytes --]

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/backlight: split out backlight registers to a separate file
  2022-08-15  9:48 [Intel-gfx] [PATCH] drm/i915/backlight: split out backlight registers to a separate file Jani Nikula
  2022-08-15 10:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
  2022-08-15 10:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-08-15 15:48 ` Patchwork
  2022-08-16  4:18 ` [Intel-gfx] [PATCH] " Murthy, Arun R
  3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2022-08-15 15:48 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 35916 bytes --]

== Series Details ==

Series: drm/i915/backlight: split out backlight registers to a separate file
URL   : https://patchwork.freedesktop.org/series/107270/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11988_full -> Patchwork_107270v1_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_107270v1_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_107270v1_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 12)
------------------------------

  Missing    (1): shard-rkl 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_107270v1_full:

### IGT changes ###

#### Warnings ####

  * igt@gem_ctx_persistence@many-contexts:
    - shard-tglb:         [FAIL][1] ([i915#2410]) -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-tglb2/igt@gem_ctx_persistence@many-contexts.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@gem_ctx_persistence@many-contexts.html

  
Known issues
------------

  Here are the changes found in Patchwork_107270v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ccs@block-copy-compressed:
    - shard-tglb:         NOTRUN -> [SKIP][3] ([i915#3555] / [i915#5325])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
    - shard-iclb:         [PASS][4] -> [SKIP][5] ([i915#4525]) +2 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-iclb1/igt@gem_exec_balancer@parallel-keep-in-fence.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-iclb8/igt@gem_exec_balancer@parallel-keep-in-fence.html

  * igt@gem_exec_fair@basic-none@rcs0:
    - shard-kbl:          [PASS][6] -> [FAIL][7] ([i915#2842]) +2 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-kbl4/igt@gem_exec_fair@basic-none@rcs0.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl7/igt@gem_exec_fair@basic-none@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-glk:          NOTRUN -> [FAIL][8] ([i915#2842]) +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-glk7/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [PASS][9] -> [SKIP][10] ([i915#2190])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-tglb5/igt@gem_huc_copy@huc-copy.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb7/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@heavy-verify-random-ccs:
    - shard-tglb:         NOTRUN -> [SKIP][11] ([i915#4613])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@gem_lmem_swapping@heavy-verify-random-ccs.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - shard-kbl:          NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl7/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-glk:          [PASS][13] -> [FAIL][14] ([i915#644])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-glk3/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-glk2/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_pxp@reject-modify-context-protection-on:
    - shard-tglb:         NOTRUN -> [SKIP][15] ([i915#4270])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@gem_pxp@reject-modify-context-protection-on.html

  * igt@gem_softpin@evict-single-offset:
    - shard-tglb:         [PASS][16] -> [FAIL][17] ([i915#4171])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-tglb3/igt@gem_softpin@evict-single-offset.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@gem_softpin@evict-single-offset.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-tglb:         NOTRUN -> [SKIP][18] ([fdo#110542])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-kbl:          NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3323])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl7/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-snb:          NOTRUN -> [FAIL][20] ([i915#2724])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-snb6/igt@gem_userptr_blits@vma-merge.html

  * igt@gen3_render_linear_blits:
    - shard-tglb:         NOTRUN -> [SKIP][21] ([fdo#109289]) +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@gen3_render_linear_blits.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-apl:          [PASS][22] -> [DMESG-WARN][23] ([i915#5566] / [i915#716])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-apl6/igt@gen9_exec_parse@allowed-single.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-apl7/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [PASS][24] -> [FAIL][25] ([i915#454])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-iclb3/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
    - shard-tglb:         NOTRUN -> [SKIP][26] ([fdo#111615])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html

  * igt@kms_ccs@pipe-a-random-ccs-data-4_tiled_dg2_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][27] ([i915#6095]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@kms_ccs@pipe-a-random-ccs-data-4_tiled_dg2_mc_ccs.html

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3886])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-skl9/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-bad-pixel-format-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][29] ([fdo#111615] / [i915#3689])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@kms_ccs@pipe-d-bad-pixel-format-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][30] ([i915#3689]) +2 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-audio-edid:
    - shard-snb:          NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-snb6/igt@kms_chamelium@dp-audio-edid.html

  * igt@kms_chamelium@hdmi-hpd-for-each-pipe:
    - shard-tglb:         NOTRUN -> [SKIP][32] ([fdo#109284] / [fdo#111827])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html

  * igt@kms_chamelium@vga-hpd-fast:
    - shard-kbl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl7/igt@kms_chamelium@vga-hpd-fast.html

  * igt@kms_flip@2x-plain-flip:
    - shard-tglb:         NOTRUN -> [SKIP][34] ([fdo#109274] / [fdo#111825] / [i915#3637])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-skl:          [PASS][35] -> [FAIL][36] ([i915#79])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
    - shard-apl:          [PASS][37] -> [DMESG-WARN][38] ([i915#180]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_flip@flip-vs-suspend@a-dp1:
    - shard-kbl:          [PASS][39] -> [DMESG-WARN][40] ([i915#180]) +9 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-kbl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl4/igt@kms_flip@flip-vs-suspend@a-dp1.html

  * igt@kms_flip@flip-vs-suspend@b-edp1:
    - shard-skl:          [PASS][41] -> [INCOMPLETE][42] ([i915#4839])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-skl6/igt@kms_flip@flip-vs-suspend@b-edp1.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-skl10/igt@kms_flip@flip-vs-suspend@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][43] ([i915#3555])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][44] ([i915#2672]) +10 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-tglb:         NOTRUN -> [SKIP][45] ([i915#2672])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][46] ([i915#2672] / [i915#3555])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt:
    - shard-tglb:         NOTRUN -> [SKIP][47] ([fdo#109280] / [fdo#111825]) +9 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-tglb:         [PASS][48] -> [DMESG-WARN][49] ([i915#2411] / [i915#2867])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render:
    - shard-tglb:         NOTRUN -> [SKIP][50] ([i915#6497]) +2 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
    - shard-skl:          NOTRUN -> [SKIP][51] ([fdo#109271]) +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-skl9/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:
    - shard-kbl:          [PASS][52] -> [FAIL][53] ([i915#1188])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-kbl4/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl7/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][54] -> [FAIL][55] ([fdo#108145] / [i915#265])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-c-edp-1:
    - shard-tglb:         NOTRUN -> [SKIP][56] ([i915#5176]) +3 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-c-edp-1.html

  * igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-b-vga-1:
    - shard-snb:          NOTRUN -> [SKIP][57] ([fdo#109271]) +22 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-snb6/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-b-vga-1.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
    - shard-iclb:         [PASS][58] -> [SKIP][59] ([i915#5235]) +2 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-iclb6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-glk:          NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#658])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-glk7/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-tglb:         NOTRUN -> [FAIL][61] ([i915#132] / [i915#3467])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [PASS][62] -> [SKIP][63] ([fdo#109441]) +2 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-iclb7/igt@kms_psr@psr2_primary_page_flip.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-tglb:         [PASS][64] -> [SKIP][65] ([i915#5519])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-tglb7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb3/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@nouveau_crc@pipe-c-ctx-flip-detection:
    - shard-tglb:         NOTRUN -> [SKIP][66] ([i915#2530])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@nouveau_crc@pipe-c-ctx-flip-detection.html

  * igt@nouveau_crc@pipe-d-ctx-flip-detection:
    - shard-glk:          NOTRUN -> [SKIP][67] ([fdo#109271]) +25 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-glk7/igt@nouveau_crc@pipe-d-ctx-flip-detection.html

  * igt@prime_nv_test@nv_write_i915_cpu_mmap_read:
    - shard-tglb:         NOTRUN -> [SKIP][68] ([fdo#109291]) +1 similar issue
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@prime_nv_test@nv_write_i915_cpu_mmap_read.html

  * igt@sysfs_clients@sema-10:
    - shard-tglb:         NOTRUN -> [SKIP][69] ([i915#2994])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@sysfs_clients@sema-10.html

  * igt@sysfs_clients@split-25:
    - shard-kbl:          NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#2994]) +1 similar issue
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl7/igt@sysfs_clients@split-25.html

  * igt@tools_test@sysfs_l3_parity:
    - shard-kbl:          NOTRUN -> [SKIP][71] ([fdo#109271]) +49 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl7/igt@tools_test@sysfs_l3_parity.html

  
#### Possible fixes ####

  * igt@gem_busy@close-race:
    - shard-snb:          [TIMEOUT][72] ([i915#5748]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-snb2/igt@gem_busy@close-race.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-snb6/igt@gem_busy@close-race.html

  * igt@gem_ctx_persistence@legacy-engines-hang@blt:
    - {shard-dg1}:        [FAIL][74] ([i915#4883]) -> [PASS][75] +1 similar issue
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-dg1-14/igt@gem_ctx_persistence@legacy-engines-hang@blt.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-dg1-17/igt@gem_ctx_persistence@legacy-engines-hang@blt.html

  * igt@gem_eio@kms:
    - shard-tglb:         [FAIL][76] ([i915#5784]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-tglb5/igt@gem_eio@kms.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb7/igt@gem_eio@kms.html

  * igt@gem_eio@unwedge-stress:
    - shard-iclb:         [TIMEOUT][78] ([i915#3070]) -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-iclb4/igt@gem_eio@unwedge-stress.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-iclb3/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-bb-first:
    - shard-iclb:         [SKIP][80] ([i915#4525]) -> [PASS][81] +1 similar issue
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-iclb8/igt@gem_exec_balancer@parallel-bb-first.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-iclb1/igt@gem_exec_balancer@parallel-bb-first.html

  * igt@gem_exec_fair@basic-none@vecs0:
    - shard-glk:          [FAIL][82] ([i915#2842]) -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-glk1/igt@gem_exec_fair@basic-none@vecs0.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-glk1/igt@gem_exec_fair@basic-none@vecs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [FAIL][84] ([i915#2842]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-kbl:          [SKIP][86] ([fdo#109271]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs0.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-kbl:          [FAIL][88] ([i915#2842]) -> [PASS][89] +1 similar issue
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_whisper@basic-fds-priority-all:
    - shard-tglb:         [INCOMPLETE][90] -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-tglb7/igt@gem_exec_whisper@basic-fds-priority-all.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-tglb2/igt@gem_exec_whisper@basic-fds-priority-all.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-kbl:          [DMESG-WARN][92] ([i915#180]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-kbl4/igt@gem_workarounds@suspend-resume-context.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl7/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [FAIL][94] ([i915#454]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-iclb7/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress:
    - {shard-dg1}:        [SKIP][96] ([i915#1397]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-dg1-18/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-dg1-15/igt@i915_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
    - shard-skl:          [FAIL][98] ([i915#2521]) -> [PASS][99] +1 similar issue
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-skl6/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-skl:          [FAIL][100] ([i915#79]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
    - shard-kbl:          [FAIL][102] ([i915#1188]) -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-kbl7/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl4/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-vs-premult-vs-constant:
    - shard-iclb:         [FAIL][104] -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-iclb1/igt@kms_plane_alpha_blend@pipe-c-coverage-vs-premult-vs-constant.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-iclb8/igt@kms_plane_alpha_blend@pipe-c-coverage-vs-premult-vs-constant.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [SKIP][106] ([fdo#109441]) -> [PASS][107] +1 similar issue
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-iclb6/igt@kms_psr@psr2_no_drrs.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-iclb2/igt@kms_psr@psr2_no_drrs.html

  * igt@perf@stress-open-close:
    - shard-glk:          [INCOMPLETE][108] ([i915#5213]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-glk9/igt@perf@stress-open-close.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-glk7/igt@perf@stress-open-close.html

  * igt@perf_pmu@busy-double-start@rcs0:
    - {shard-dg1}:        [FAIL][110] ([i915#4349]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-dg1-16/igt@perf_pmu@busy-double-start@rcs0.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-dg1-16/igt@perf_pmu@busy-double-start@rcs0.html

  
#### Warnings ####

  * igt@gem_pxp@create-protected-buffer:
    - shard-glk:          [SKIP][112] ([fdo#109271] / [i915#1888]) -> [SKIP][113] ([fdo#109271])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-glk6/igt@gem_pxp@create-protected-buffer.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-glk9/igt@gem_pxp@create-protected-buffer.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-kbl:          [INCOMPLETE][114] ([i915#180] / [i915#4939]) -> [FAIL][115] ([i915#4767])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
    - shard-apl:          [FAIL][116] ([i915#1188]) -> [DMESG-FAIL][117] ([i915#180])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-apl2/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-apl2/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html

  * igt@kms_psr2_sf@cursor-plane-update-sf:
    - shard-iclb:         [SKIP][118] ([fdo#111068] / [i915#658]) -> [SKIP][119] ([i915#2920])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-iclb8/igt@kms_psr2_sf@cursor-plane-update-sf.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
    - shard-iclb:         [SKIP][120] ([i915#2920]) -> [SKIP][121] ([i915#658])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-iclb4/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
    - shard-iclb:         [SKIP][122] ([i915#2920]) -> [SKIP][123] ([fdo#111068] / [i915#658]) +1 similar issue
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-iclb7/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html

  * igt@kms_vblank@pipe-d-wait-forked-hang:
    - shard-skl:          [SKIP][124] ([fdo#109271] / [i915#1888]) -> [SKIP][125] ([fdo#109271]) +1 similar issue
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-skl10/igt@kms_vblank@pipe-d-wait-forked-hang.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-skl7/igt@kms_vblank@pipe-d-wait-forked-hang.html

  * igt@runner@aborted:
    - shard-apl:          ([FAIL][126], [FAIL][127], [FAIL][128]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-apl1/igt@runner@aborted.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-apl6/igt@runner@aborted.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-apl6/igt@runner@aborted.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-apl2/igt@runner@aborted.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-apl3/igt@runner@aborted.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-apl7/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-apl1/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-apl1/igt@runner@aborted.html
    - shard-kbl:          ([FAIL][134], [FAIL][135], [FAIL][136]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#92]) -> ([FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-kbl4/igt@runner@aborted.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-kbl4/igt@runner@aborted.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11988/shard-kbl1/igt@runner@aborted.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl4/igt@runner@aborted.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl4/igt@runner@aborted.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl4/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl4/igt@runner@aborted.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/shard-kbl1/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
  [i915#4839]: https://gitlab.freedesktop.org/drm/intel/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
  [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
  [i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883
  [i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
  [i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
  [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#5748]: https://gitlab.freedesktop.org/drm/intel/issues/5748
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92


Build changes
-------------

  * Linux: CI_DRM_11988 -> Patchwork_107270v1

  CI-20190529: 20190529
  CI_DRM_11988: a707ffeb65d1883ae1c1aec2b5ed447187781ad1 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6625: d47beef9b01595f721c584070940c95be1cf11e8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_107270v1: a707ffeb65d1883ae1c1aec2b5ed447187781ad1 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107270v1/index.html

[-- Attachment #2: Type: text/html, Size: 41413 bytes --]

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/backlight: split out backlight registers to a separate file
  2022-08-15  9:48 [Intel-gfx] [PATCH] drm/i915/backlight: split out backlight registers to a separate file Jani Nikula
                   ` (2 preceding siblings ...)
  2022-08-15 15:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2022-08-16  4:18 ` Murthy, Arun R
  2022-08-17 11:34   ` Jani Nikula
  3 siblings, 1 reply; 6+ messages in thread
From: Murthy, Arun R @ 2022-08-16  4:18 UTC (permalink / raw)
  To: Nikula, Jani, intel-gfx@lists.freedesktop.org; +Cc: Nikula, Jani

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Monday, August 15, 2022 3:19 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [Intel-gfx] [PATCH] drm/i915/backlight: split out backlight registers to
> a separate file
> 
> Declutter i915_reg.h by splitting backlight registers to a separate file. Also
> include the utility pin definitions, even though they are used for non-
> backlight things too.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---	

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>  drivers/gpu/drm/i915/display/icl_dsi.c        |   1 +
>  .../gpu/drm/i915/display/intel_backlight.c    |   1 +
>  .../drm/i915/display/intel_backlight_regs.h   | 124 ++++++++++++++++++
>  .../drm/i915/display/intel_display_power.c    |   1 +
>  .../i915/display/intel_display_power_well.c   |   1 +
>  drivers/gpu/drm/i915/i915_reg.h               | 112 ----------------
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |   1 +
>  7 files changed, 129 insertions(+), 112 deletions(-)  create mode 100644
> drivers/gpu/drm/i915/display/intel_backlight_regs.h
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 5dcfa7feffa9..c182253196f3 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -33,6 +33,7 @@
>  #include "icl_dsi_regs.h"
>  #include "intel_atomic.h"
>  #include "intel_backlight.h"
> +#include "intel_backlight_regs.h"
>  #include "intel_combo_phy.h"
>  #include "intel_combo_phy_regs.h"
>  #include "intel_connector.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
> b/drivers/gpu/drm/i915/display/intel_backlight.c
> index 110fc98ec280..262b2fda37e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_backlight.c
> @@ -9,6 +9,7 @@
>  #include <linux/string_helpers.h>
> 
>  #include "intel_backlight.h"
> +#include "intel_backlight_regs.h"
>  #include "intel_connector.h"
>  #include "intel_de.h"
>  #include "intel_display_types.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_backlight_regs.h
> b/drivers/gpu/drm/i915/display/intel_backlight_regs.h
> new file mode 100644
> index 000000000000..50c1210f6d5d
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_backlight_regs.h
> @@ -0,0 +1,124 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __INTEL_BACKLIGHT_REGS_H__
> +#define __INTEL_BACKLIGHT_REGS_H__
> +
> +#include "i915_reg_defs.h"
> +
> +#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) +
> 0x61250)
> +#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) +
> 0x61350)
> +#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe,
> _VLV_BLC_PWM_CTL2_A, \
> +					 _VLV_BLC_PWM_CTL2_B)
> +
> +#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) +
> 0x61254)
> +#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) +
> 0x61354)
> +#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe,
> _VLV_BLC_PWM_CTL_A, \
> +					_VLV_BLC_PWM_CTL_B)
> +
> +#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
> +#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
> +#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe,
> _VLV_BLC_HIST_CTL_A, \
> +					 _VLV_BLC_HIST_CTL_B)
> +
> +/* Backlight control */
> +#define BLC_PWM_CTL2	_MMIO(DISPLAY_MMIO_BASE(dev_priv) +
> 0x61250) /* 965+ only */
> +#define   BLM_PWM_ENABLE		(1 << 31)
> +#define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
> +#define   BLM_PIPE_SELECT		(1 << 29)
> +#define   BLM_PIPE_SELECT_IVB		(3 << 29)
> +#define   BLM_PIPE_A			(0 << 29)
> +#define   BLM_PIPE_B			(1 << 29)
> +#define   BLM_PIPE_C			(2 << 29) /* ivb + */
> +#define   BLM_TRANSCODER_A		BLM_PIPE_A /* hsw */
> +#define   BLM_TRANSCODER_B		BLM_PIPE_B
> +#define   BLM_TRANSCODER_C		BLM_PIPE_C
> +#define   BLM_TRANSCODER_EDP		(3 << 29)
> +#define   BLM_PIPE(pipe)		((pipe) << 29)
> +#define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
> +#define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
> +#define   BLM_PHASE_IN_ENABLE		(1 << 25)
> +#define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
> +#define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
> +#define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
> +#define   BLM_PHASE_IN_COUNT_SHIFT	(8)
> +#define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
> +#define   BLM_PHASE_IN_INCR_SHIFT	(0)
> +#define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
> +#define BLC_PWM_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) +
> 0x61254)
> +/*
> + * This is the most significant 15 bits of the number of backlight
> +cycles in a
> + * complete cycle of the modulated backlight control.
> + *
> + * The actual value is this field multiplied by two.
> + */
> +#define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
> +#define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
> +#define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
> +/*
> + * This is the number of cycles out of the backlight modulation cycle
> +for which
> + * the backlight is on.
> + *
> + * This field must be no greater than the number of cycles in the
> +complete
> + * backlight modulation cycle.
> + */
> +#define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
> +#define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
> +#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
> +#define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
> +
> +#define BLC_HIST_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
> +#define  BLM_HISTOGRAM_ENABLE			(1 << 31)
> +
> +/* New registers for PCH-split platforms. Safe where new bits show up,
> +the
> + * register layout machtes with gen4 BLC_PWM_CTL[12]. */
> +#define BLC_PWM_CPU_CTL2	_MMIO(0x48250)
> +#define BLC_PWM_CPU_CTL		_MMIO(0x48254)
> +
> +#define HSW_BLC_PWM2_CTL	_MMIO(0x48350)
> +
> +/* PCH CTL1 is totally different, all but the below bits are reserved.
> +CTL2 is
> + * like the normal CTL from gen4 and earlier. Hooray for confusing naming.
> */
> +#define BLC_PWM_PCH_CTL1	_MMIO(0xc8250)
> +#define   BLM_PCH_PWM_ENABLE			(1 << 31)
> +#define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
> +#define   BLM_PCH_POLARITY			(1 << 29)
> +#define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
> +
> +/* BXT backlight register definition. */
> +#define _BXT_BLC_PWM_CTL1			0xC8250
> +#define   BXT_BLC_PWM_ENABLE			(1 << 31)
> +#define   BXT_BLC_PWM_POLARITY			(1 << 29)
> +#define _BXT_BLC_PWM_FREQ1			0xC8254
> +#define _BXT_BLC_PWM_DUTY1			0xC8258
> +
> +#define _BXT_BLC_PWM_CTL2			0xC8350
> +#define _BXT_BLC_PWM_FREQ2			0xC8354
> +#define _BXT_BLC_PWM_DUTY2			0xC8358
> +
> +#define BXT_BLC_PWM_CTL(controller)    _MMIO_PIPE(controller,
> 	\
> +					_BXT_BLC_PWM_CTL1,
> _BXT_BLC_PWM_CTL2)
> +#define BXT_BLC_PWM_FREQ(controller)   _MMIO_PIPE(controller, \
> +					_BXT_BLC_PWM_FREQ1,
> _BXT_BLC_PWM_FREQ2)
> +#define BXT_BLC_PWM_DUTY(controller)   _MMIO_PIPE(controller, \
> +					_BXT_BLC_PWM_DUTY1,
> _BXT_BLC_PWM_DUTY2)
> +
> +/* Utility pin */
> +#define UTIL_PIN_CTL			_MMIO(0x48400)
> +#define   UTIL_PIN_ENABLE		(1 << 31)
> +#define   UTIL_PIN_PIPE_MASK		(3 << 29)
> +#define   UTIL_PIN_PIPE(x)		((x) << 29)
> +#define   UTIL_PIN_MODE_MASK		(0xf << 24)
> +#define   UTIL_PIN_MODE_DATA		(0 << 24)
> +#define   UTIL_PIN_MODE_PWM		(1 << 24)
> +#define   UTIL_PIN_MODE_VBLANK		(4 << 24)
> +#define   UTIL_PIN_MODE_VSYNC		(5 << 24)
> +#define   UTIL_PIN_MODE_EYE_LEVEL	(8 << 24)
> +#define   UTIL_PIN_OUTPUT_DATA		(1 << 23)
> +#define   UTIL_PIN_POLARITY		(1 << 22)
> +#define   UTIL_PIN_DIRECTION_INPUT	(1 << 19)
> +#define   UTIL_PIN_INPUT_DATA		(1 << 16)
> +
> +#endif /* __INTEL_BACKLIGHT_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 3f84af6beff3..1d8f2935ed98 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -7,6 +7,7 @@
> 
>  #include "i915_drv.h"
>  #include "i915_irq.h"
> +#include "intel_backlight_regs.h"
>  #include "intel_cdclk.h"
>  #include "intel_combo_phy.h"
>  #include "intel_de.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 91cfd5890f46..7044016d4d98 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -5,6 +5,7 @@
> 
>  #include "i915_drv.h"
>  #include "i915_irq.h"
> +#include "intel_backlight_regs.h"
>  #include "intel_combo_phy.h"
>  #include "intel_combo_phy_regs.h"
>  #include "intel_crt.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index ad2c441aceca..50d7bfd541ad
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2925,118 +2925,6 @@
> 
>  #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
> 0x61238)
> 
> -#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) +
> 0x61250) -#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv)
> + 0x61350) -#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe,
> _VLV_BLC_PWM_CTL2_A, \
> -					 _VLV_BLC_PWM_CTL2_B)
> -
> -#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) +
> 0x61254) -#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv)
> + 0x61354) -#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe,
> _VLV_BLC_PWM_CTL_A, \
> -					_VLV_BLC_PWM_CTL_B)
> -
> -#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
> -#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
> -#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe,
> _VLV_BLC_HIST_CTL_A, \
> -					 _VLV_BLC_HIST_CTL_B)
> -
> -/* Backlight control */
> -#define BLC_PWM_CTL2	_MMIO(DISPLAY_MMIO_BASE(dev_priv) +
> 0x61250) /* 965+ only */
> -#define   BLM_PWM_ENABLE		(1 << 31)
> -#define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
> -#define   BLM_PIPE_SELECT		(1 << 29)
> -#define   BLM_PIPE_SELECT_IVB		(3 << 29)
> -#define   BLM_PIPE_A			(0 << 29)
> -#define   BLM_PIPE_B			(1 << 29)
> -#define   BLM_PIPE_C			(2 << 29) /* ivb + */
> -#define   BLM_TRANSCODER_A		BLM_PIPE_A /* hsw */
> -#define   BLM_TRANSCODER_B		BLM_PIPE_B
> -#define   BLM_TRANSCODER_C		BLM_PIPE_C
> -#define   BLM_TRANSCODER_EDP		(3 << 29)
> -#define   BLM_PIPE(pipe)		((pipe) << 29)
> -#define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
> -#define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
> -#define   BLM_PHASE_IN_ENABLE		(1 << 25)
> -#define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
> -#define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
> -#define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
> -#define   BLM_PHASE_IN_COUNT_SHIFT	(8)
> -#define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
> -#define   BLM_PHASE_IN_INCR_SHIFT	(0)
> -#define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
> -#define BLC_PWM_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) +
> 0x61254)
> -/*
> - * This is the most significant 15 bits of the number of backlight cycles in a
> - * complete cycle of the modulated backlight control.
> - *
> - * The actual value is this field multiplied by two.
> - */
> -#define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
> -#define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
> -#define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
> -/*
> - * This is the number of cycles out of the backlight modulation cycle for
> which
> - * the backlight is on.
> - *
> - * This field must be no greater than the number of cycles in the complete
> - * backlight modulation cycle.
> - */
> -#define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
> -#define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
> -#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
> -#define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
> -
> -#define BLC_HIST_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
> -#define  BLM_HISTOGRAM_ENABLE			(1 << 31)
> -
> -/* New registers for PCH-split platforms. Safe where new bits show up, the
> - * register layout machtes with gen4 BLC_PWM_CTL[12]. */
> -#define BLC_PWM_CPU_CTL2	_MMIO(0x48250)
> -#define BLC_PWM_CPU_CTL		_MMIO(0x48254)
> -
> -#define HSW_BLC_PWM2_CTL	_MMIO(0x48350)
> -
> -/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
> - * like the normal CTL from gen4 and earlier. Hooray for confusing naming.
> */
> -#define BLC_PWM_PCH_CTL1	_MMIO(0xc8250)
> -#define   BLM_PCH_PWM_ENABLE			(1 << 31)
> -#define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
> -#define   BLM_PCH_POLARITY			(1 << 29)
> -#define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
> -
> -#define UTIL_PIN_CTL			_MMIO(0x48400)
> -#define   UTIL_PIN_ENABLE		(1 << 31)
> -#define   UTIL_PIN_PIPE_MASK		(3 << 29)
> -#define   UTIL_PIN_PIPE(x)		((x) << 29)
> -#define   UTIL_PIN_MODE_MASK		(0xf << 24)
> -#define   UTIL_PIN_MODE_DATA		(0 << 24)
> -#define   UTIL_PIN_MODE_PWM		(1 << 24)
> -#define   UTIL_PIN_MODE_VBLANK		(4 << 24)
> -#define   UTIL_PIN_MODE_VSYNC		(5 << 24)
> -#define   UTIL_PIN_MODE_EYE_LEVEL	(8 << 24)
> -#define   UTIL_PIN_OUTPUT_DATA		(1 << 23)
> -#define   UTIL_PIN_POLARITY		(1 << 22)
> -#define   UTIL_PIN_DIRECTION_INPUT	(1 << 19)
> -#define   UTIL_PIN_INPUT_DATA		(1 << 16)
> -
> -/* BXT backlight register definition. */
> -#define _BXT_BLC_PWM_CTL1			0xC8250
> -#define   BXT_BLC_PWM_ENABLE			(1 << 31)
> -#define   BXT_BLC_PWM_POLARITY			(1 << 29)
> -#define _BXT_BLC_PWM_FREQ1			0xC8254
> -#define _BXT_BLC_PWM_DUTY1			0xC8258
> -
> -#define _BXT_BLC_PWM_CTL2			0xC8350
> -#define _BXT_BLC_PWM_FREQ2			0xC8354
> -#define _BXT_BLC_PWM_DUTY2			0xC8358
> -
> -#define BXT_BLC_PWM_CTL(controller)    _MMIO_PIPE(controller,
> 	\
> -					_BXT_BLC_PWM_CTL1,
> _BXT_BLC_PWM_CTL2)
> -#define BXT_BLC_PWM_FREQ(controller)   _MMIO_PIPE(controller, \
> -					_BXT_BLC_PWM_FREQ1,
> _BXT_BLC_PWM_FREQ2)
> -#define BXT_BLC_PWM_DUTY(controller)   _MMIO_PIPE(controller, \
> -					_BXT_BLC_PWM_DUTY1,
> _BXT_BLC_PWM_DUTY2)
> -
>  #define PCH_GTC_CTL		_MMIO(0xe7000)
>  #define   PCH_GTC_ENABLE	(1 << 31)
> 
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 157e166672d7..e015bc91a26f 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -4,6 +4,7 @@
>   */
> 
>  #include "display/intel_audio_regs.h"
> +#include "display/intel_backlight_regs.h"
>  #include "display/intel_dmc_regs.h"
>  #include "display/vlv_dsi_pll_regs.h"
>  #include "gt/intel_gt_regs.h"
> --
> 2.34.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/backlight: split out backlight registers to a separate file
  2022-08-16  4:18 ` [Intel-gfx] [PATCH] " Murthy, Arun R
@ 2022-08-17 11:34   ` Jani Nikula
  0 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2022-08-17 11:34 UTC (permalink / raw)
  To: Murthy, Arun R, intel-gfx@lists.freedesktop.org

On Tue, 16 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
>> Nikula
>> Sent: Monday, August 15, 2022 3:19 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>
>> Subject: [Intel-gfx] [PATCH] drm/i915/backlight: split out backlight registers to
>> a separate file
>>
>> Declutter i915_reg.h by splitting backlight registers to a separate file. Also
>> include the utility pin definitions, even though they are used for non-
>> backlight things too.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>
> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks for the review, pushed to drm-intel-next.

BR,
Jani.

>
> Thanks and Regards,
> Arun R Murthy
> --------------------
>
>>  drivers/gpu/drm/i915/display/icl_dsi.c        |   1 +
>>  .../gpu/drm/i915/display/intel_backlight.c    |   1 +
>>  .../drm/i915/display/intel_backlight_regs.h   | 124 ++++++++++++++++++
>>  .../drm/i915/display/intel_display_power.c    |   1 +
>>  .../i915/display/intel_display_power_well.c   |   1 +
>>  drivers/gpu/drm/i915/i915_reg.h               | 112 ----------------
>>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |   1 +
>>  7 files changed, 129 insertions(+), 112 deletions(-)  create mode 100644
>> drivers/gpu/drm/i915/display/intel_backlight_regs.h
>>
>> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>> b/drivers/gpu/drm/i915/display/icl_dsi.c
>> index 5dcfa7feffa9..c182253196f3 100644
>> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> @@ -33,6 +33,7 @@
>>  #include "icl_dsi_regs.h"
>>  #include "intel_atomic.h"
>>  #include "intel_backlight.h"
>> +#include "intel_backlight_regs.h"
>>  #include "intel_combo_phy.h"
>>  #include "intel_combo_phy_regs.h"
>>  #include "intel_connector.h"
>> diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
>> b/drivers/gpu/drm/i915/display/intel_backlight.c
>> index 110fc98ec280..262b2fda37e5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_backlight.c
>> +++ b/drivers/gpu/drm/i915/display/intel_backlight.c
>> @@ -9,6 +9,7 @@
>>  #include <linux/string_helpers.h>
>>
>>  #include "intel_backlight.h"
>> +#include "intel_backlight_regs.h"
>>  #include "intel_connector.h"
>>  #include "intel_de.h"
>>  #include "intel_display_types.h"
>> diff --git a/drivers/gpu/drm/i915/display/intel_backlight_regs.h
>> b/drivers/gpu/drm/i915/display/intel_backlight_regs.h
>> new file mode 100644
>> index 000000000000..50c1210f6d5d
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_backlight_regs.h
>> @@ -0,0 +1,124 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2022 Intel Corporation
>> + */
>> +
>> +#ifndef __INTEL_BACKLIGHT_REGS_H__
>> +#define __INTEL_BACKLIGHT_REGS_H__
>> +
>> +#include "i915_reg_defs.h"
>> +
>> +#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) +
>> 0x61250)
>> +#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) +
>> 0x61350)
>> +#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe,
>> _VLV_BLC_PWM_CTL2_A, \
>> +                                      _VLV_BLC_PWM_CTL2_B)
>> +
>> +#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) +
>> 0x61254)
>> +#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) +
>> 0x61354)
>> +#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe,
>> _VLV_BLC_PWM_CTL_A, \
>> +                                     _VLV_BLC_PWM_CTL_B)
>> +
>> +#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
>> +#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
>> +#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe,
>> _VLV_BLC_HIST_CTL_A, \
>> +                                      _VLV_BLC_HIST_CTL_B)
>> +
>> +/* Backlight control */
>> +#define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
>> 0x61250) /* 965+ only */
>> +#define   BLM_PWM_ENABLE             (1 << 31)
>> +#define   BLM_COMBINATION_MODE               (1 << 30) /* gen4 only */
>> +#define   BLM_PIPE_SELECT            (1 << 29)
>> +#define   BLM_PIPE_SELECT_IVB                (3 << 29)
>> +#define   BLM_PIPE_A                 (0 << 29)
>> +#define   BLM_PIPE_B                 (1 << 29)
>> +#define   BLM_PIPE_C                 (2 << 29) /* ivb + */
>> +#define   BLM_TRANSCODER_A           BLM_PIPE_A /* hsw */
>> +#define   BLM_TRANSCODER_B           BLM_PIPE_B
>> +#define   BLM_TRANSCODER_C           BLM_PIPE_C
>> +#define   BLM_TRANSCODER_EDP         (3 << 29)
>> +#define   BLM_PIPE(pipe)             ((pipe) << 29)
>> +#define   BLM_POLARITY_I965          (1 << 28) /* gen4 only */
>> +#define   BLM_PHASE_IN_INTERUPT_STATUS       (1 << 26)
>> +#define   BLM_PHASE_IN_ENABLE                (1 << 25)
>> +#define   BLM_PHASE_IN_INTERUPT_ENABL        (1 << 24)
>> +#define   BLM_PHASE_IN_TIME_BASE_SHIFT       (16)
>> +#define   BLM_PHASE_IN_TIME_BASE_MASK        (0xff << 16)
>> +#define   BLM_PHASE_IN_COUNT_SHIFT   (8)
>> +#define   BLM_PHASE_IN_COUNT_MASK    (0xff << 8)
>> +#define   BLM_PHASE_IN_INCR_SHIFT    (0)
>> +#define   BLM_PHASE_IN_INCR_MASK     (0xff << 0)
>> +#define BLC_PWM_CTL  _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
>> 0x61254)
>> +/*
>> + * This is the most significant 15 bits of the number of backlight
>> +cycles in a
>> + * complete cycle of the modulated backlight control.
>> + *
>> + * The actual value is this field multiplied by two.
>> + */
>> +#define   BACKLIGHT_MODULATION_FREQ_SHIFT    (17)
>> +#define   BACKLIGHT_MODULATION_FREQ_MASK     (0x7fff << 17)
>> +#define   BLM_LEGACY_MODE                    (1 << 16) /* gen2 only */
>> +/*
>> + * This is the number of cycles out of the backlight modulation cycle
>> +for which
>> + * the backlight is on.
>> + *
>> + * This field must be no greater than the number of cycles in the
>> +complete
>> + * backlight modulation cycle.
>> + */
>> +#define   BACKLIGHT_DUTY_CYCLE_SHIFT         (0)
>> +#define   BACKLIGHT_DUTY_CYCLE_MASK          (0xffff)
>> +#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV              (0xfffe)
>> +#define   BLM_POLARITY_PNV                   (1 << 0) /* pnv only */
>> +
>> +#define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
>> +#define  BLM_HISTOGRAM_ENABLE                        (1 << 31)
>> +
>> +/* New registers for PCH-split platforms. Safe where new bits show up,
>> +the
>> + * register layout machtes with gen4 BLC_PWM_CTL[12]. */
>> +#define BLC_PWM_CPU_CTL2     _MMIO(0x48250)
>> +#define BLC_PWM_CPU_CTL              _MMIO(0x48254)
>> +
>> +#define HSW_BLC_PWM2_CTL     _MMIO(0x48350)
>> +
>> +/* PCH CTL1 is totally different, all but the below bits are reserved.
>> +CTL2 is
>> + * like the normal CTL from gen4 and earlier. Hooray for confusing naming.
>> */
>> +#define BLC_PWM_PCH_CTL1     _MMIO(0xc8250)
>> +#define   BLM_PCH_PWM_ENABLE                 (1 << 31)
>> +#define   BLM_PCH_OVERRIDE_ENABLE            (1 << 30)
>> +#define   BLM_PCH_POLARITY                   (1 << 29)
>> +#define BLC_PWM_PCH_CTL2     _MMIO(0xc8254)
>> +
>> +/* BXT backlight register definition. */
>> +#define _BXT_BLC_PWM_CTL1                    0xC8250
>> +#define   BXT_BLC_PWM_ENABLE                 (1 << 31)
>> +#define   BXT_BLC_PWM_POLARITY                       (1 << 29)
>> +#define _BXT_BLC_PWM_FREQ1                   0xC8254
>> +#define _BXT_BLC_PWM_DUTY1                   0xC8258
>> +
>> +#define _BXT_BLC_PWM_CTL2                    0xC8350
>> +#define _BXT_BLC_PWM_FREQ2                   0xC8354
>> +#define _BXT_BLC_PWM_DUTY2                   0xC8358
>> +
>> +#define BXT_BLC_PWM_CTL(controller)    _MMIO_PIPE(controller,
>>       \
>> +                                     _BXT_BLC_PWM_CTL1,
>> _BXT_BLC_PWM_CTL2)
>> +#define BXT_BLC_PWM_FREQ(controller)   _MMIO_PIPE(controller, \
>> +                                     _BXT_BLC_PWM_FREQ1,
>> _BXT_BLC_PWM_FREQ2)
>> +#define BXT_BLC_PWM_DUTY(controller)   _MMIO_PIPE(controller, \
>> +                                     _BXT_BLC_PWM_DUTY1,
>> _BXT_BLC_PWM_DUTY2)
>> +
>> +/* Utility pin */
>> +#define UTIL_PIN_CTL                 _MMIO(0x48400)
>> +#define   UTIL_PIN_ENABLE            (1 << 31)
>> +#define   UTIL_PIN_PIPE_MASK         (3 << 29)
>> +#define   UTIL_PIN_PIPE(x)           ((x) << 29)
>> +#define   UTIL_PIN_MODE_MASK         (0xf << 24)
>> +#define   UTIL_PIN_MODE_DATA         (0 << 24)
>> +#define   UTIL_PIN_MODE_PWM          (1 << 24)
>> +#define   UTIL_PIN_MODE_VBLANK               (4 << 24)
>> +#define   UTIL_PIN_MODE_VSYNC                (5 << 24)
>> +#define   UTIL_PIN_MODE_EYE_LEVEL    (8 << 24)
>> +#define   UTIL_PIN_OUTPUT_DATA               (1 << 23)
>> +#define   UTIL_PIN_POLARITY          (1 << 22)
>> +#define   UTIL_PIN_DIRECTION_INPUT   (1 << 19)
>> +#define   UTIL_PIN_INPUT_DATA                (1 << 16)
>> +
>> +#endif /* __INTEL_BACKLIGHT_REGS_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>> b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 3f84af6beff3..1d8f2935ed98 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -7,6 +7,7 @@
>>
>>  #include "i915_drv.h"
>>  #include "i915_irq.h"
>> +#include "intel_backlight_regs.h"
>>  #include "intel_cdclk.h"
>>  #include "intel_combo_phy.h"
>>  #include "intel_de.h"
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> index 91cfd5890f46..7044016d4d98 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> @@ -5,6 +5,7 @@
>>
>>  #include "i915_drv.h"
>>  #include "i915_irq.h"
>> +#include "intel_backlight_regs.h"
>>  #include "intel_combo_phy.h"
>>  #include "intel_combo_phy_regs.h"
>>  #include "intel_crt.h"
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index ad2c441aceca..50d7bfd541ad
>> 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2925,118 +2925,6 @@
>>
>>  #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
>> 0x61238)
>>
>> -#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) +
>> 0x61250) -#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv)
>> + 0x61350) -#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe,
>> _VLV_BLC_PWM_CTL2_A, \
>> -                                      _VLV_BLC_PWM_CTL2_B)
>> -
>> -#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) +
>> 0x61254) -#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv)
>> + 0x61354) -#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe,
>> _VLV_BLC_PWM_CTL_A, \
>> -                                     _VLV_BLC_PWM_CTL_B)
>> -
>> -#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
>> -#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
>> -#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe,
>> _VLV_BLC_HIST_CTL_A, \
>> -                                      _VLV_BLC_HIST_CTL_B)
>> -
>> -/* Backlight control */
>> -#define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
>> 0x61250) /* 965+ only */
>> -#define   BLM_PWM_ENABLE             (1 << 31)
>> -#define   BLM_COMBINATION_MODE               (1 << 30) /* gen4 only */
>> -#define   BLM_PIPE_SELECT            (1 << 29)
>> -#define   BLM_PIPE_SELECT_IVB                (3 << 29)
>> -#define   BLM_PIPE_A                 (0 << 29)
>> -#define   BLM_PIPE_B                 (1 << 29)
>> -#define   BLM_PIPE_C                 (2 << 29) /* ivb + */
>> -#define   BLM_TRANSCODER_A           BLM_PIPE_A /* hsw */
>> -#define   BLM_TRANSCODER_B           BLM_PIPE_B
>> -#define   BLM_TRANSCODER_C           BLM_PIPE_C
>> -#define   BLM_TRANSCODER_EDP         (3 << 29)
>> -#define   BLM_PIPE(pipe)             ((pipe) << 29)
>> -#define   BLM_POLARITY_I965          (1 << 28) /* gen4 only */
>> -#define   BLM_PHASE_IN_INTERUPT_STATUS       (1 << 26)
>> -#define   BLM_PHASE_IN_ENABLE                (1 << 25)
>> -#define   BLM_PHASE_IN_INTERUPT_ENABL        (1 << 24)
>> -#define   BLM_PHASE_IN_TIME_BASE_SHIFT       (16)
>> -#define   BLM_PHASE_IN_TIME_BASE_MASK        (0xff << 16)
>> -#define   BLM_PHASE_IN_COUNT_SHIFT   (8)
>> -#define   BLM_PHASE_IN_COUNT_MASK    (0xff << 8)
>> -#define   BLM_PHASE_IN_INCR_SHIFT    (0)
>> -#define   BLM_PHASE_IN_INCR_MASK     (0xff << 0)
>> -#define BLC_PWM_CTL  _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
>> 0x61254)
>> -/*
>> - * This is the most significant 15 bits of the number of backlight cycles in a
>> - * complete cycle of the modulated backlight control.
>> - *
>> - * The actual value is this field multiplied by two.
>> - */
>> -#define   BACKLIGHT_MODULATION_FREQ_SHIFT    (17)
>> -#define   BACKLIGHT_MODULATION_FREQ_MASK     (0x7fff << 17)
>> -#define   BLM_LEGACY_MODE                    (1 << 16) /* gen2 only */
>> -/*
>> - * This is the number of cycles out of the backlight modulation cycle for
>> which
>> - * the backlight is on.
>> - *
>> - * This field must be no greater than the number of cycles in the complete
>> - * backlight modulation cycle.
>> - */
>> -#define   BACKLIGHT_DUTY_CYCLE_SHIFT         (0)
>> -#define   BACKLIGHT_DUTY_CYCLE_MASK          (0xffff)
>> -#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV              (0xfffe)
>> -#define   BLM_POLARITY_PNV                   (1 << 0) /* pnv only */
>> -
>> -#define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
>> -#define  BLM_HISTOGRAM_ENABLE                        (1 << 31)
>> -
>> -/* New registers for PCH-split platforms. Safe where new bits show up, the
>> - * register layout machtes with gen4 BLC_PWM_CTL[12]. */
>> -#define BLC_PWM_CPU_CTL2     _MMIO(0x48250)
>> -#define BLC_PWM_CPU_CTL              _MMIO(0x48254)
>> -
>> -#define HSW_BLC_PWM2_CTL     _MMIO(0x48350)
>> -
>> -/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
>> - * like the normal CTL from gen4 and earlier. Hooray for confusing naming.
>> */
>> -#define BLC_PWM_PCH_CTL1     _MMIO(0xc8250)
>> -#define   BLM_PCH_PWM_ENABLE                 (1 << 31)
>> -#define   BLM_PCH_OVERRIDE_ENABLE            (1 << 30)
>> -#define   BLM_PCH_POLARITY                   (1 << 29)
>> -#define BLC_PWM_PCH_CTL2     _MMIO(0xc8254)
>> -
>> -#define UTIL_PIN_CTL                 _MMIO(0x48400)
>> -#define   UTIL_PIN_ENABLE            (1 << 31)
>> -#define   UTIL_PIN_PIPE_MASK         (3 << 29)
>> -#define   UTIL_PIN_PIPE(x)           ((x) << 29)
>> -#define   UTIL_PIN_MODE_MASK         (0xf << 24)
>> -#define   UTIL_PIN_MODE_DATA         (0 << 24)
>> -#define   UTIL_PIN_MODE_PWM          (1 << 24)
>> -#define   UTIL_PIN_MODE_VBLANK               (4 << 24)
>> -#define   UTIL_PIN_MODE_VSYNC                (5 << 24)
>> -#define   UTIL_PIN_MODE_EYE_LEVEL    (8 << 24)
>> -#define   UTIL_PIN_OUTPUT_DATA               (1 << 23)
>> -#define   UTIL_PIN_POLARITY          (1 << 22)
>> -#define   UTIL_PIN_DIRECTION_INPUT   (1 << 19)
>> -#define   UTIL_PIN_INPUT_DATA                (1 << 16)
>> -
>> -/* BXT backlight register definition. */
>> -#define _BXT_BLC_PWM_CTL1                    0xC8250
>> -#define   BXT_BLC_PWM_ENABLE                 (1 << 31)
>> -#define   BXT_BLC_PWM_POLARITY                       (1 << 29)
>> -#define _BXT_BLC_PWM_FREQ1                   0xC8254
>> -#define _BXT_BLC_PWM_DUTY1                   0xC8258
>> -
>> -#define _BXT_BLC_PWM_CTL2                    0xC8350
>> -#define _BXT_BLC_PWM_FREQ2                   0xC8354
>> -#define _BXT_BLC_PWM_DUTY2                   0xC8358
>> -
>> -#define BXT_BLC_PWM_CTL(controller)    _MMIO_PIPE(controller,
>>       \
>> -                                     _BXT_BLC_PWM_CTL1,
>> _BXT_BLC_PWM_CTL2)
>> -#define BXT_BLC_PWM_FREQ(controller)   _MMIO_PIPE(controller, \
>> -                                     _BXT_BLC_PWM_FREQ1,
>> _BXT_BLC_PWM_FREQ2)
>> -#define BXT_BLC_PWM_DUTY(controller)   _MMIO_PIPE(controller, \
>> -                                     _BXT_BLC_PWM_DUTY1,
>> _BXT_BLC_PWM_DUTY2)
>> -
>>  #define PCH_GTC_CTL          _MMIO(0xe7000)
>>  #define   PCH_GTC_ENABLE     (1 << 31)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
>> b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
>> index 157e166672d7..e015bc91a26f 100644
>> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
>> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
>> @@ -4,6 +4,7 @@
>>   */
>>
>>  #include "display/intel_audio_regs.h"
>> +#include "display/intel_backlight_regs.h"
>>  #include "display/intel_dmc_regs.h"
>>  #include "display/vlv_dsi_pll_regs.h"
>>  #include "gt/intel_gt_regs.h"
>> --
>> 2.34.1
>

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2022-08-24 17:39 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-08-15  9:48 [Intel-gfx] [PATCH] drm/i915/backlight: split out backlight registers to a separate file Jani Nikula
2022-08-15 10:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
2022-08-15 10:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-08-15 15:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-08-16  4:18 ` [Intel-gfx] [PATCH] " Murthy, Arun R
2022-08-17 11:34   ` Jani Nikula

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