* [Intel-gfx] [PATCH v2 1/6] drm/i915/display: Move display device info to header under display/
2023-05-22 20:23 [Intel-gfx] [PATCH v2 0/6] i915: Move display identification/probing under display/ Matt Roper
@ 2023-05-22 20:23 ` Matt Roper
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 2/6] drm/i915: Convert INTEL_INFO()->display to a pointer Matt Roper
` (9 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Matt Roper @ 2023-05-22 20:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Matt Roper, intel-xe, Andrzej Hajda
Moving display-specific substructure definitions will help keep display
more self-contained and make it easier to re-use in other drivers (i.e.,
Xe) in the future.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../drm/i915/display/intel_display_device.h | 60 +++++++++++++++++++
drivers/gpu/drm/i915/intel_device_info.h | 49 +--------------
2 files changed, 62 insertions(+), 47 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.h
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
new file mode 100644
index 000000000000..c689d582dbf1
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __INTEL_DISPLAY_DEVICE_H__
+#define __INTEL_DISPLAY_DEVICE_H__
+
+#include <linux/types.h>
+
+#include "display/intel_display_limits.h"
+
+#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
+ /* Keep in alphabetical order */ \
+ func(cursor_needs_physical); \
+ func(has_cdclk_crawl); \
+ func(has_cdclk_squash); \
+ func(has_ddi); \
+ func(has_dp_mst); \
+ func(has_dsb); \
+ func(has_fpga_dbg); \
+ func(has_gmch); \
+ func(has_hotplug); \
+ func(has_hti); \
+ func(has_ipc); \
+ func(has_overlay); \
+ func(has_psr); \
+ func(has_psr_hw_tracking); \
+ func(overlay_needs_physical); \
+ func(supports_tv);
+
+struct intel_display_device_info {
+ u8 abox_mask;
+
+ struct {
+ u16 size; /* in blocks */
+ u8 slice_mask;
+ } dbuf;
+
+#define DEFINE_FLAG(name) u8 name:1
+ DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
+#undef DEFINE_FLAG
+
+ /* Global register offset for the display engine */
+ u32 mmio_offset;
+
+ /* Register offsets for the various display pipes and transcoders */
+ u32 pipe_offsets[I915_MAX_TRANSCODERS];
+ u32 trans_offsets[I915_MAX_TRANSCODERS];
+ u32 cursor_offsets[I915_MAX_PIPES];
+
+ struct {
+ u32 degamma_lut_size;
+ u32 gamma_lut_size;
+ u32 degamma_lut_tests;
+ u32 gamma_lut_tests;
+ } color;
+};
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 959a4080840c..96f6bdb04b1b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -29,7 +29,7 @@
#include "intel_step.h"
-#include "display/intel_display_limits.h"
+#include "display/intel_display_device.h"
#include "gt/intel_engine_types.h"
#include "gt/intel_context_types.h"
@@ -182,25 +182,6 @@ enum intel_ppgtt_type {
func(unfenced_needs_alignment); \
func(hws_needs_physical);
-#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
- /* Keep in alphabetical order */ \
- func(cursor_needs_physical); \
- func(has_cdclk_crawl); \
- func(has_cdclk_squash); \
- func(has_ddi); \
- func(has_dp_mst); \
- func(has_dsb); \
- func(has_fpga_dbg); \
- func(has_gmch); \
- func(has_hotplug); \
- func(has_hti); \
- func(has_ipc); \
- func(has_overlay); \
- func(has_psr); \
- func(has_psr_hw_tracking); \
- func(overlay_needs_physical); \
- func(supports_tv);
-
struct intel_ip_version {
u8 ver;
u8 rel;
@@ -278,33 +259,7 @@ struct intel_device_info {
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
- struct {
- u8 abox_mask;
-
- struct {
- u16 size; /* in blocks */
- u8 slice_mask;
- } dbuf;
-
-#define DEFINE_FLAG(name) u8 name:1
- DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
-#undef DEFINE_FLAG
-
- /* Global register offset for the display engine */
- u32 mmio_offset;
-
- /* Register offsets for the various display pipes and transcoders */
- u32 pipe_offsets[I915_MAX_TRANSCODERS];
- u32 trans_offsets[I915_MAX_TRANSCODERS];
- u32 cursor_offsets[I915_MAX_PIPES];
-
- struct {
- u32 degamma_lut_size;
- u32 gamma_lut_size;
- u32 degamma_lut_tests;
- u32 gamma_lut_tests;
- } color;
- } display;
+ struct intel_display_device_info display;
/*
* Initial runtime info. Do not access outside of i915_driver_create().
--
2.40.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Intel-gfx] [PATCH v2 2/6] drm/i915: Convert INTEL_INFO()->display to a pointer
2023-05-22 20:23 [Intel-gfx] [PATCH v2 0/6] i915: Move display identification/probing under display/ Matt Roper
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 1/6] drm/i915/display: Move display device info to header " Matt Roper
@ 2023-05-22 20:23 ` Matt Roper
2023-05-23 7:45 ` Andrzej Hajda
2023-05-23 12:47 ` [Intel-gfx] [Intel-xe] " Jani Nikula
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 3/6] drm/i915/display: Move display runtime info to display structure Matt Roper
` (8 subsequent siblings)
10 siblings, 2 replies; 22+ messages in thread
From: Matt Roper @ 2023-05-22 20:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Matt Roper, intel-xe, Andrzej Hajda
Rather than embeddeding the display's device info within the main device
info structure, just provide a pointer to the display-specific
structure. This is in preparation for moving the display device info
definitions into the display code itself and for eventually allowing the
pointer to be assigned at runtime on platforms that use GMD_ID for
device identification.
In the future, this will also eventually allow the same display device
info structures to be used outside the current i915 code (e.g., from the
Xe driver).
v2:
- Move introduction of DISPLAY_INFO() to this patch. (Andrzej)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 31 +-
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
.../drm/i915/display/intel_display_power.c | 6 +-
.../drm/i915/display/intel_display_reg_defs.h | 14 +-
drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +-
drivers/gpu/drm/i915/display/intel_hti.c | 2 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 29 +-
drivers/gpu/drm/i915/i915_pci.c | 579 ++++++++++++------
drivers/gpu/drm/i915/intel_device_info.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
12 files changed, 452 insertions(+), 231 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 07f1afe1d406..744b3a4ec99a 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1824,14 +1824,14 @@ static u32 intel_gamma_lut_tests(const struct intel_crtc_state *crtc_state)
if (lut_is_legacy(gamma_lut))
return 0;
- return INTEL_INFO(i915)->display.color.gamma_lut_tests;
+ return DISPLAY_INFO(i915)->color.gamma_lut_tests;
}
static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- return INTEL_INFO(i915)->display.color.degamma_lut_tests;
+ return DISPLAY_INFO(i915)->color.degamma_lut_tests;
}
static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
@@ -1842,14 +1842,14 @@ static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
if (lut_is_legacy(gamma_lut))
return LEGACY_LUT_LENGTH;
- return INTEL_INFO(i915)->display.color.gamma_lut_size;
+ return DISPLAY_INFO(i915)->color.gamma_lut_size;
}
static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- return INTEL_INFO(i915)->display.color.degamma_lut_size;
+ return DISPLAY_INFO(i915)->color.degamma_lut_size;
}
static int check_lut_size(const struct drm_property_blob *lut, int expected)
@@ -2321,7 +2321,7 @@ static int glk_assign_luts(struct intel_crtc_state *crtc_state)
struct drm_property_blob *gamma_lut;
gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut,
- INTEL_INFO(i915)->display.color.degamma_lut_size,
+ DISPLAY_INFO(i915)->color.degamma_lut_size,
false);
if (IS_ERR(gamma_lut))
return PTR_ERR(gamma_lut);
@@ -2855,7 +2855,7 @@ static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
+ u32 lut_size = DISPLAY_INFO(dev_priv)->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -2904,7 +2904,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
+ int i, lut_size = DISPLAY_INFO(dev_priv)->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -2954,7 +2954,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
+ int i, lut_size = DISPLAY_INFO(dev_priv)->color.degamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -2980,7 +2980,7 @@ static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc)
static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
+ int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -3044,7 +3044,7 @@ static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
+ int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -3228,7 +3228,7 @@ static void bdw_read_luts(struct intel_crtc_state *crtc_state)
static struct drm_property_blob *glk_read_degamma_lut(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
+ int i, lut_size = DISPLAY_INFO(dev_priv)->color.degamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -3293,7 +3293,7 @@ static struct drm_property_blob *
icl_read_lut_multi_segment(struct intel_crtc *crtc)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
+ int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -3471,8 +3471,8 @@ void intel_color_crtc_init(struct intel_crtc *crtc)
drm_mode_crtc_set_gamma_size(&crtc->base, 256);
- gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
- degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size;
+ gamma_lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;
+ degamma_lut_size = DISPLAY_INFO(i915)->color.degamma_lut_size;
has_ctm = degamma_lut_size != 0;
/*
@@ -3497,7 +3497,8 @@ int intel_color_init(struct drm_i915_private *i915)
if (DISPLAY_VER(i915) != 10)
return 0;
- blob = create_linear_lut(i915, INTEL_INFO(i915)->display.color.degamma_lut_size);
+ blob = create_linear_lut(i915,
+ DISPLAY_INFO(i915)->color.degamma_lut_size);
if (IS_ERR(blob))
return PTR_ERR(blob);
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 31bef0427377..3864da5f5c17 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -36,7 +36,7 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
u32 base;
- if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
+ if (DISPLAY_INFO(dev_priv)->cursor_needs_physical)
base = sg_dma_address(obj->mm.pages->sgl);
else
base = intel_plane_ggtt_offset(plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 205b3929b861..aa3a21ccd7fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -113,7 +113,7 @@ enum i9xx_plane_id {
#define for_each_dbuf_slice(__dev_priv, __slice) \
for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
- for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice))
+ for_each_if(INTEL_INFO(__dev_priv)->display->dbuf.slice_mask & BIT(__slice))
#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
for_each_dbuf_slice((__dev_priv), (__slice)) \
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 6ed2ece89c3f..9c9a809c71f1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1053,7 +1053,7 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
- u8 slice_mask = INTEL_INFO(dev_priv)->display.dbuf.slice_mask;
+ u8 slice_mask = DISPLAY_INFO(dev_priv)->dbuf.slice_mask;
enum dbuf_slice slice;
drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
@@ -1113,7 +1113,7 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
static void icl_mbus_init(struct drm_i915_private *dev_priv)
{
- unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask;
+ unsigned long abox_regs = DISPLAY_INFO(dev_priv)->abox_mask;
u32 mask, val, i;
if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
@@ -1568,7 +1568,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
enum intel_dram_type type = dev_priv->dram_info.type;
u8 num_channels = dev_priv->dram_info.num_channels;
const struct buddy_page_mask *table;
- unsigned long abox_mask = INTEL_INFO(dev_priv)->display.abox_mask;
+ unsigned long abox_mask = DISPLAY_INFO(dev_priv)->abox_mask;
int config, i;
/* BW_BUDDY registers are not used on dgpu's beyond DG1 */
diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
index 755c1ea8225c..e0f82f28d8b3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
@@ -8,7 +8,7 @@
#include "i915_reg_defs.h"
-#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display.mmio_offset)
+#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display->mmio_offset)
#define VLV_DISPLAY_BASE 0x180000
@@ -36,14 +36,14 @@
* Device info offset array based helpers for groups of registers with unevenly
* spaced base offsets.
*/
-#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \
- INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \
+#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display->pipe_offsets[(pipe)] - \
+ INTEL_INFO(dev_priv)->display->pipe_offsets[PIPE_A] + \
DISPLAY_MMIO_BASE(dev_priv) + (reg))
-#define _MMIO_TRANS2(tran, reg) _MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
- INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
+#define _MMIO_TRANS2(tran, reg) _MMIO(INTEL_INFO(dev_priv)->display->trans_offsets[(tran)] - \
+ INTEL_INFO(dev_priv)->display->trans_offsets[TRANSCODER_A] + \
DISPLAY_MMIO_BASE(dev_priv) + (reg))
-#define _MMIO_CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
- INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
+#define _MMIO_CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display->cursor_offsets[(pipe)] - \
+ INTEL_INFO(dev_priv)->display->cursor_offsets[PIPE_A] + \
DISPLAY_MMIO_BASE(dev_priv) + (reg))
#endif /* __INTEL_DISPLAY_REG_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 1aca7552a85d..fffd568070d4 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -243,7 +243,7 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state)
struct i915_vma *vma;
bool phys_cursor =
plane->id == PLANE_CURSOR &&
- INTEL_INFO(dev_priv)->display.cursor_needs_physical;
+ DISPLAY_INFO(dev_priv)->cursor_needs_physical;
if (!intel_fb_uses_dpt(fb)) {
vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
diff --git a/drivers/gpu/drm/i915/display/intel_hti.c b/drivers/gpu/drm/i915/display/intel_hti.c
index c518efebdf77..a92d008d4e6e 100644
--- a/drivers/gpu/drm/i915/display/intel_hti.c
+++ b/drivers/gpu/drm/i915/display/intel_hti.c
@@ -15,7 +15,7 @@ void intel_hti_init(struct drm_i915_private *i915)
* If the platform has HTI, we need to find out whether it has reserved
* any display resources before we create our display outputs.
*/
- if (INTEL_INFO(i915)->display.has_hti)
+ if (DISPLAY_INFO(i915)->has_hti)
i915->display.hti.state = intel_de_read(i915, HDPORT_STATE);
}
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 1c7e6468f3e3..d1245c847f1c 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -507,8 +507,8 @@ static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
static int intel_dbuf_slice_size(struct drm_i915_private *i915)
{
- return INTEL_INFO(i915)->display.dbuf.size /
- hweight8(INTEL_INFO(i915)->display.dbuf.slice_mask);
+ return DISPLAY_INFO(i915)->dbuf.size /
+ hweight8(DISPLAY_INFO(i915)->dbuf.slice_mask);
}
static void
@@ -527,7 +527,7 @@ skl_ddb_entry_for_slices(struct drm_i915_private *i915, u8 slice_mask,
ddb->end = fls(slice_mask) * slice_size;
WARN_ON(ddb->start >= ddb->end);
- WARN_ON(ddb->end > INTEL_INFO(i915)->display.dbuf.size);
+ WARN_ON(ddb->end > DISPLAY_INFO(i915)->dbuf.size);
}
static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask)
@@ -2625,7 +2625,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
"Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
old_dbuf_state->enabled_slices,
new_dbuf_state->enabled_slices,
- INTEL_INFO(i915)->display.dbuf.slice_mask,
+ DISPLAY_INFO(i915)->dbuf.slice_mask,
str_yes_no(old_dbuf_state->joined_mbus),
str_yes_no(new_dbuf_state->joined_mbus));
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 14c5338c96a6..9612c2ac4b00 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -408,6 +408,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
#define INTEL_INFO(i915) (&(i915)->__info)
+#define DISPLAY_INFO(i915) (INTEL_INFO(i915)->display)
#define RUNTIME_INFO(i915) (&(i915)->__runtime)
#define DRIVER_CAPS(i915) (&(i915)->caps)
@@ -782,9 +783,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
})
-#define HAS_OVERLAY(i915) (INTEL_INFO(i915)->display.has_overlay)
+#define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(i915) \
- (INTEL_INFO(i915)->display.overlay_needs_physical)
+ (DISPLAY_INFO(i915)->overlay_needs_physical)
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915))
@@ -806,8 +807,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
*/
#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
!(IS_I915G(i915) || IS_I915GM(i915)))
-#define SUPPORTS_TV(i915) (INTEL_INFO(i915)->display.supports_tv)
-#define I915_HAS_HOTPLUG(i915) (INTEL_INFO(i915)->display.has_hotplug)
+#define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv)
+#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
#define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2)
#define HAS_FBC(i915) (RUNTIME_INFO(i915)->fbc_mask != 0)
@@ -817,18 +818,18 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_IPS(i915) (IS_HSW_ULT(i915) || IS_BROADWELL(i915))
-#define HAS_DP_MST(i915) (INTEL_INFO(i915)->display.has_dp_mst)
+#define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst)
#define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
#define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
-#define HAS_CDCLK_CRAWL(i915) (INTEL_INFO(i915)->display.has_cdclk_crawl)
-#define HAS_CDCLK_SQUASH(i915) (INTEL_INFO(i915)->display.has_cdclk_squash)
-#define HAS_DDI(i915) (INTEL_INFO(i915)->display.has_ddi)
-#define HAS_FPGA_DBG_UNCLAIMED(i915) (INTEL_INFO(i915)->display.has_fpga_dbg)
-#define HAS_PSR(i915) (INTEL_INFO(i915)->display.has_psr)
+#define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl)
+#define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash)
+#define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi)
+#define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg)
+#define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr)
#define HAS_PSR_HW_TRACKING(i915) \
- (INTEL_INFO(i915)->display.has_psr_hw_tracking)
+ (DISPLAY_INFO(i915)->has_psr_hw_tracking)
#define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12)
#define HAS_TRANSCODER(i915, trans) ((RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
@@ -839,7 +840,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
#define HAS_DMC(i915) (RUNTIME_INFO(i915)->has_dmc)
-#define HAS_DSB(i915) (INTEL_INFO(i915)->display.has_dsb)
+#define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb)
#define HAS_DSC(__i915) (RUNTIME_INFO(__i915)->has_dsc)
#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
@@ -869,7 +870,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
*/
#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
-#define HAS_IPC(i915) (INTEL_INFO(i915)->display.has_ipc)
+#define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
#define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
@@ -889,7 +890,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
-#define HAS_GMCH(i915) (INTEL_INFO(i915)->display.has_gmch)
+#define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch)
#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e4a19161afce..dd874a4db604 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -47,43 +47,43 @@
#define NO_DISPLAY .__runtime.pipe_mask = 0
#define I845_PIPE_OFFSETS \
- .display.pipe_offsets = { \
+ .pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
}, \
- .display.trans_offsets = { \
+ .trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
}
#define I9XX_PIPE_OFFSETS \
- .display.pipe_offsets = { \
+ .pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
}, \
- .display.trans_offsets = { \
+ .trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
}
#define IVB_PIPE_OFFSETS \
- .display.pipe_offsets = { \
+ .pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
[TRANSCODER_C] = PIPE_C_OFFSET, \
}, \
- .display.trans_offsets = { \
+ .trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
}
#define HSW_PIPE_OFFSETS \
- .display.pipe_offsets = { \
+ .pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
[TRANSCODER_C] = PIPE_C_OFFSET, \
[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
}, \
- .display.trans_offsets = { \
+ .trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -91,44 +91,44 @@
}
#define CHV_PIPE_OFFSETS \
- .display.pipe_offsets = { \
+ .pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
}, \
- .display.trans_offsets = { \
+ .trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
}
#define I845_CURSOR_OFFSETS \
- .display.cursor_offsets = { \
+ .cursor_offsets = { \
[PIPE_A] = CURSOR_A_OFFSET, \
}
#define I9XX_CURSOR_OFFSETS \
- .display.cursor_offsets = { \
+ .cursor_offsets = { \
[PIPE_A] = CURSOR_A_OFFSET, \
[PIPE_B] = CURSOR_B_OFFSET, \
}
#define CHV_CURSOR_OFFSETS \
- .display.cursor_offsets = { \
+ .cursor_offsets = { \
[PIPE_A] = CURSOR_A_OFFSET, \
[PIPE_B] = CURSOR_B_OFFSET, \
[PIPE_C] = CHV_CURSOR_C_OFFSET, \
}
#define IVB_CURSOR_OFFSETS \
- .display.cursor_offsets = { \
+ .cursor_offsets = { \
[PIPE_A] = CURSOR_A_OFFSET, \
[PIPE_B] = IVB_CURSOR_B_OFFSET, \
[PIPE_C] = IVB_CURSOR_C_OFFSET, \
}
#define TGL_CURSOR_OFFSETS \
- .display.cursor_offsets = { \
+ .cursor_offsets = { \
[PIPE_A] = CURSOR_A_OFFSET, \
[PIPE_B] = IVB_CURSOR_B_OFFSET, \
[PIPE_C] = IVB_CURSOR_C_OFFSET, \
@@ -136,29 +136,29 @@
}
#define I845_COLORS \
- .display.color = { .gamma_lut_size = 256 }
+ .color = { .gamma_lut_size = 256 }
#define I9XX_COLORS \
- .display.color = { .gamma_lut_size = 129, \
+ .color = { .gamma_lut_size = 129, \
.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
}
#define ILK_COLORS \
- .display.color = { .gamma_lut_size = 1024 }
+ .color = { .gamma_lut_size = 1024 }
#define IVB_COLORS \
- .display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
+ .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
#define CHV_COLORS \
- .display.color = { \
+ .color = { \
.degamma_lut_size = 65, .gamma_lut_size = 257, \
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
}
#define GLK_COLORS \
- .display.color = { \
+ .color = { \
.degamma_lut_size = 33, .gamma_lut_size = 1024, \
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
DRM_COLOR_LUT_EQUAL_CHANNELS, \
}
#define ICL_COLORS \
- .display.color = { \
+ .color = { \
.degamma_lut_size = 33, .gamma_lut_size = 262145, \
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
DRM_COLOR_LUT_EQUAL_CHANNELS, \
@@ -205,15 +205,24 @@
#define GEN_DEFAULT_REGIONS \
.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
+#define I830_DISPLAY \
+ .has_overlay = 1, \
+ .cursor_needs_physical = 1, \
+ .overlay_needs_physical = 1, \
+ .has_gmch = 1, \
+ I9XX_PIPE_OFFSETS, \
+ I9XX_CURSOR_OFFSETS, \
+ I9XX_COLORS
+
+static const struct intel_display_device_info i830_display = {
+ I830_DISPLAY,
+};
+
#define I830_FEATURES \
GEN(2), \
.is_mobile = 1, \
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
- .display.has_overlay = 1, \
- .display.cursor_needs_physical = 1, \
- .display.overlay_needs_physical = 1, \
- .display.has_gmch = 1, \
.gpu_reset_clobbers_display = true, \
.has_3d_pipeline = 1, \
.hws_needs_physical = 1, \
@@ -223,20 +232,26 @@
.has_coherent_ggtt = false, \
.dma_mask_size = 32, \
.max_pat_index = 3, \
- I9XX_PIPE_OFFSETS, \
- I9XX_CURSOR_OFFSETS, \
- I9XX_COLORS, \
GEN_DEFAULT_PAGE_SIZES, \
GEN_DEFAULT_REGIONS, \
LEGACY_CACHELEVEL
+#define I845_DISPLAY \
+ .has_overlay = 1, \
+ .overlay_needs_physical = 1, \
+ .has_gmch = 1, \
+ I845_PIPE_OFFSETS, \
+ I845_CURSOR_OFFSETS, \
+ I845_COLORS
+
+static const struct intel_display_device_info i845_display = {
+ I845_DISPLAY,
+};
+
#define I845_FEATURES \
GEN(2), \
.__runtime.pipe_mask = BIT(PIPE_A), \
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \
- .display.has_overlay = 1, \
- .display.overlay_needs_physical = 1, \
- .display.has_gmch = 1, \
.has_3d_pipeline = 1, \
.gpu_reset_clobbers_display = true, \
.hws_needs_physical = 1, \
@@ -246,9 +261,6 @@
.has_coherent_ggtt = false, \
.dma_mask_size = 32, \
.max_pat_index = 3, \
- I845_PIPE_OFFSETS, \
- I845_CURSOR_OFFSETS, \
- I845_COLORS, \
GEN_DEFAULT_PAGE_SIZES, \
GEN_DEFAULT_REGIONS, \
LEGACY_CACHELEVEL
@@ -256,30 +268,81 @@
static const struct intel_device_info i830_info = {
I830_FEATURES,
PLATFORM(INTEL_I830),
+ .display = &i830_display,
};
static const struct intel_device_info i845g_info = {
I845_FEATURES,
PLATFORM(INTEL_I845G),
+ .display = &i845_display,
+};
+
+static const struct intel_display_device_info i85x_display = {
+ I830_DISPLAY,
};
static const struct intel_device_info i85x_info = {
I830_FEATURES,
PLATFORM(INTEL_I85X),
+ .display = &i85x_display,
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
};
+static const struct intel_display_device_info i865g_display = {
+ I845_DISPLAY,
+};
+
static const struct intel_device_info i865g_info = {
I845_FEATURES,
PLATFORM(INTEL_I865G),
+ .display = &i865g_display,
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
};
+#define GEN3_DISPLAY \
+ .has_gmch = 1, \
+ .has_overlay = 1, \
+ I9XX_PIPE_OFFSETS, \
+ I9XX_CURSOR_OFFSETS, \
+ I9XX_COLORS
+
+static const struct intel_display_device_info i915g_display = {
+ GEN3_DISPLAY,
+ .cursor_needs_physical = 1,
+ .overlay_needs_physical = 1,
+};
+
+static const struct intel_display_device_info i915gm_display = {
+ GEN3_DISPLAY,
+ .cursor_needs_physical = 1,
+ .overlay_needs_physical = 1,
+ .supports_tv = 1,
+};
+
+static const struct intel_display_device_info i945g_display = {
+ GEN3_DISPLAY,
+ .has_hotplug = 1,
+ .cursor_needs_physical = 1,
+ .overlay_needs_physical = 1,
+};
+
+static const struct intel_display_device_info i945gm_display = {
+ GEN3_DISPLAY,
+ .has_hotplug = 1,
+ .cursor_needs_physical = 1,
+ .overlay_needs_physical = 1,
+ .supports_tv = 1,
+};
+
+static const struct intel_display_device_info g33_display = {
+ GEN3_DISPLAY,
+ .has_hotplug = 1,
+};
+
#define GEN3_FEATURES \
GEN(3), \
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
- .display.has_gmch = 1, \
.gpu_reset_clobbers_display = true, \
.__runtime.platform_engine_mask = BIT(RCS0), \
.has_3d_pipeline = 1, \
@@ -287,9 +350,6 @@ static const struct intel_device_info i865g_info = {
.has_coherent_ggtt = true, \
.dma_mask_size = 32, \
.max_pat_index = 3, \
- I9XX_PIPE_OFFSETS, \
- I9XX_CURSOR_OFFSETS, \
- I9XX_COLORS, \
GEN_DEFAULT_PAGE_SIZES, \
GEN_DEFAULT_REGIONS, \
LEGACY_CACHELEVEL
@@ -297,10 +357,8 @@ static const struct intel_device_info i865g_info = {
static const struct intel_device_info i915g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I915G),
+ .display = &i915g_display,
.has_coherent_ggtt = false,
- .display.cursor_needs_physical = 1,
- .display.has_overlay = 1,
- .display.overlay_needs_physical = 1,
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -308,11 +366,8 @@ static const struct intel_device_info i915g_info = {
static const struct intel_device_info i915gm_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I915GM),
+ .display = &i915gm_display,
.is_mobile = 1,
- .display.cursor_needs_physical = 1,
- .display.has_overlay = 1,
- .display.overlay_needs_physical = 1,
- .display.supports_tv = 1,
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
@@ -321,10 +376,7 @@ static const struct intel_device_info i915gm_info = {
static const struct intel_device_info i945g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I945G),
- .display.has_hotplug = 1,
- .display.cursor_needs_physical = 1,
- .display.has_overlay = 1,
- .display.overlay_needs_physical = 1,
+ .display = &i945g_display,
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -332,12 +384,8 @@ static const struct intel_device_info i945g_info = {
static const struct intel_device_info i945gm_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I945GM),
+ .display = &i945gm_display,
.is_mobile = 1,
- .display.has_hotplug = 1,
- .display.cursor_needs_physical = 1,
- .display.has_overlay = 1,
- .display.overlay_needs_physical = 1,
- .display.supports_tv = 1,
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
@@ -346,16 +394,14 @@ static const struct intel_device_info i945gm_info = {
static const struct intel_device_info g33_info = {
GEN3_FEATURES,
PLATFORM(INTEL_G33),
- .display.has_hotplug = 1,
- .display.has_overlay = 1,
+ .display = &g33_display,
.dma_mask_size = 36,
};
static const struct intel_device_info pnv_g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_PINEVIEW),
- .display.has_hotplug = 1,
- .display.has_overlay = 1,
+ .display = &g33_display,
.dma_mask_size = 36,
};
@@ -363,17 +409,41 @@ static const struct intel_device_info pnv_m_info = {
GEN3_FEATURES,
PLATFORM(INTEL_PINEVIEW),
.is_mobile = 1,
- .display.has_hotplug = 1,
- .display.has_overlay = 1,
+ .display = &g33_display,
.dma_mask_size = 36,
};
+#define GEN4_DISPLAY \
+ .has_hotplug = 1, \
+ .has_gmch = 1, \
+ I9XX_PIPE_OFFSETS, \
+ I9XX_CURSOR_OFFSETS, \
+ I9XX_COLORS
+
+static const struct intel_display_device_info i965g_display = {
+ GEN4_DISPLAY,
+ .has_overlay = 1,
+};
+
+static const struct intel_display_device_info i965gm_display = {
+ GEN4_DISPLAY,
+ .has_overlay = 1,
+ .supports_tv = 1,
+};
+
+static const struct intel_display_device_info g45_display = {
+ GEN4_DISPLAY,
+};
+
+static const struct intel_display_device_info gm45_display = {
+ GEN4_DISPLAY,
+ .supports_tv = 1,
+};
+
#define GEN4_FEATURES \
GEN(4), \
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
- .display.has_hotplug = 1, \
- .display.has_gmch = 1, \
.gpu_reset_clobbers_display = true, \
.__runtime.platform_engine_mask = BIT(RCS0), \
.has_3d_pipeline = 1, \
@@ -381,9 +451,6 @@ static const struct intel_device_info pnv_m_info = {
.has_coherent_ggtt = true, \
.dma_mask_size = 36, \
.max_pat_index = 3, \
- I9XX_PIPE_OFFSETS, \
- I9XX_CURSOR_OFFSETS, \
- I9XX_COLORS, \
GEN_DEFAULT_PAGE_SIZES, \
GEN_DEFAULT_REGIONS, \
LEGACY_CACHELEVEL
@@ -391,7 +458,7 @@ static const struct intel_device_info pnv_m_info = {
static const struct intel_device_info i965g_info = {
GEN4_FEATURES,
PLATFORM(INTEL_I965G),
- .display.has_overlay = 1,
+ .display = &i965g_display,
.hws_needs_physical = 1,
.has_snoop = false,
};
@@ -399,10 +466,9 @@ static const struct intel_device_info i965g_info = {
static const struct intel_device_info i965gm_info = {
GEN4_FEATURES,
PLATFORM(INTEL_I965GM),
+ .display = &i965gm_display,
.is_mobile = 1,
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
- .display.has_overlay = 1,
- .display.supports_tv = 1,
.hws_needs_physical = 1,
.has_snoop = false,
};
@@ -411,6 +477,7 @@ static const struct intel_device_info g45_info = {
GEN4_FEATURES,
PLATFORM(INTEL_G45),
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
+ .display = &g45_display,
.gpu_reset_clobbers_display = false,
};
@@ -419,8 +486,8 @@ static const struct intel_device_info gm45_info = {
PLATFORM(INTEL_GM45),
.is_mobile = 1,
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
- .display.supports_tv = 1,
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
+ .display = &gm45_display,
.gpu_reset_clobbers_display = false,
};
@@ -428,7 +495,6 @@ static const struct intel_device_info gm45_info = {
GEN(5), \
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
- .display.has_hotplug = 1, \
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
.has_3d_pipeline = 1, \
.has_snoop = true, \
@@ -437,21 +503,34 @@ static const struct intel_device_info gm45_info = {
.has_rc6 = 0, \
.dma_mask_size = 36, \
.max_pat_index = 3, \
- I9XX_PIPE_OFFSETS, \
- I9XX_CURSOR_OFFSETS, \
- ILK_COLORS, \
GEN_DEFAULT_PAGE_SIZES, \
GEN_DEFAULT_REGIONS, \
LEGACY_CACHELEVEL
+#define ILK_DISPLAY \
+ .has_hotplug = 1, \
+ I9XX_PIPE_OFFSETS, \
+ I9XX_CURSOR_OFFSETS, \
+ ILK_COLORS
+
+static const struct intel_display_device_info ilk_d_display = {
+ ILK_DISPLAY,
+};
+
static const struct intel_device_info ilk_d_info = {
GEN5_FEATURES,
PLATFORM(INTEL_IRONLAKE),
+ .display = &ilk_d_display,
+};
+
+static const struct intel_display_device_info ilk_m_display = {
+ ILK_DISPLAY,
};
static const struct intel_device_info ilk_m_info = {
GEN5_FEATURES,
PLATFORM(INTEL_IRONLAKE),
+ .display = &ilk_m_display,
.is_mobile = 1,
.has_rps = true,
.__runtime.fbc_mask = BIT(INTEL_FBC_A),
@@ -461,7 +540,6 @@ static const struct intel_device_info ilk_m_info = {
GEN(6), \
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
- .display.has_hotplug = 1, \
.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_3d_pipeline = 1, \
@@ -475,24 +553,30 @@ static const struct intel_device_info ilk_m_info = {
.max_pat_index = 3, \
.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
.__runtime.ppgtt_size = 31, \
- I9XX_PIPE_OFFSETS, \
- I9XX_CURSOR_OFFSETS, \
- ILK_COLORS, \
GEN_DEFAULT_PAGE_SIZES, \
GEN_DEFAULT_REGIONS, \
LEGACY_CACHELEVEL
+static const struct intel_display_device_info snb_display = {
+ .has_hotplug = 1,
+ I9XX_PIPE_OFFSETS,
+ I9XX_CURSOR_OFFSETS,
+ ILK_COLORS,
+};
+
#define SNB_D_PLATFORM \
GEN6_FEATURES, \
PLATFORM(INTEL_SANDYBRIDGE)
static const struct intel_device_info snb_d_gt1_info = {
SNB_D_PLATFORM,
+ .display = &snb_display,
.gt = 1,
};
static const struct intel_device_info snb_d_gt2_info = {
SNB_D_PLATFORM,
+ .display = &snb_display,
.gt = 2,
};
@@ -504,11 +588,13 @@ static const struct intel_device_info snb_d_gt2_info = {
static const struct intel_device_info snb_m_gt1_info = {
SNB_M_PLATFORM,
+ .display = &snb_display,
.gt = 1,
};
static const struct intel_device_info snb_m_gt2_info = {
SNB_M_PLATFORM,
+ .display = &snb_display,
.gt = 2,
};
@@ -516,7 +602,6 @@ static const struct intel_device_info snb_m_gt2_info = {
GEN(7), \
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
- .display.has_hotplug = 1, \
.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_3d_pipeline = 1, \
@@ -530,9 +615,6 @@ static const struct intel_device_info snb_m_gt2_info = {
.max_pat_index = 3, \
.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
.__runtime.ppgtt_size = 31, \
- IVB_PIPE_OFFSETS, \
- IVB_CURSOR_OFFSETS, \
- IVB_COLORS, \
GEN_DEFAULT_PAGE_SIZES, \
GEN_DEFAULT_REGIONS, \
LEGACY_CACHELEVEL
@@ -542,13 +624,22 @@ static const struct intel_device_info snb_m_gt2_info = {
PLATFORM(INTEL_IVYBRIDGE), \
.has_l3_dpf = 1
+static const struct intel_display_device_info ivb_display = {
+ .has_hotplug = 1,
+ IVB_PIPE_OFFSETS,
+ IVB_CURSOR_OFFSETS,
+ IVB_COLORS,
+};
+
static const struct intel_device_info ivb_d_gt1_info = {
IVB_D_PLATFORM,
+ .display = &ivb_display,
.gt = 1,
};
static const struct intel_device_info ivb_d_gt2_info = {
IVB_D_PLATFORM,
+ .display = &ivb_display,
.gt = 2,
};
@@ -560,11 +651,13 @@ static const struct intel_device_info ivb_d_gt2_info = {
static const struct intel_device_info ivb_m_gt1_info = {
IVB_M_PLATFORM,
+ .display = &ivb_display,
.gt = 1,
};
static const struct intel_device_info ivb_m_gt2_info = {
IVB_M_PLATFORM,
+ .display = &ivb_display,
.gt = 2,
};
@@ -576,18 +669,26 @@ static const struct intel_device_info ivb_q_info = {
.has_l3_dpf = 1,
};
+static const struct intel_display_device_info vlv_display = {
+ .has_gmch = 1,
+ .has_hotplug = 1,
+ .mmio_offset = VLV_DISPLAY_BASE,
+ I9XX_PIPE_OFFSETS,
+ I9XX_CURSOR_OFFSETS,
+ I9XX_COLORS,
+};
+
static const struct intel_device_info vlv_info = {
PLATFORM(INTEL_VALLEYVIEW),
GEN(7),
.is_lp = 1,
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
+ .display = &vlv_display,
.has_runtime_pm = 1,
.has_rc6 = 1,
.has_reset_engine = true,
.has_rps = true,
- .display.has_gmch = 1,
- .display.has_hotplug = 1,
.dma_mask_size = 40,
.max_pat_index = 3,
.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
@@ -595,10 +696,6 @@ static const struct intel_device_info vlv_info = {
.has_snoop = true,
.has_coherent_ggtt = false,
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
- .display.mmio_offset = VLV_DISPLAY_BASE,
- I9XX_PIPE_OFFSETS,
- I9XX_CURSOR_OFFSETS,
- I9XX_COLORS,
GEN_DEFAULT_PAGE_SIZES,
GEN_DEFAULT_REGIONS,
LEGACY_CACHELEVEL,
@@ -609,11 +706,7 @@ static const struct intel_device_info vlv_info = {
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
- .display.has_ddi = 1, \
- .display.has_fpga_dbg = 1, \
- .display.has_dp_mst = 1, \
.has_rc6p = 0 /* RC6p removed-by HSW */, \
- HSW_PIPE_OFFSETS, \
.has_runtime_pm = 1
#define HSW_PLATFORM \
@@ -621,18 +714,31 @@ static const struct intel_device_info vlv_info = {
PLATFORM(INTEL_HASWELL), \
.has_l3_dpf = 1
+static const struct intel_display_device_info hsw_display = {
+ .has_ddi = 1,
+ .has_dp_mst = 1,
+ .has_fpga_dbg = 1,
+ .has_hotplug = 1,
+ HSW_PIPE_OFFSETS,
+ IVB_CURSOR_OFFSETS,
+ IVB_COLORS,
+};
+
static const struct intel_device_info hsw_gt1_info = {
HSW_PLATFORM,
+ .display = &hsw_display,
.gt = 1,
};
static const struct intel_device_info hsw_gt2_info = {
HSW_PLATFORM,
+ .display = &hsw_display,
.gt = 2,
};
static const struct intel_device_info hsw_gt3_info = {
HSW_PLATFORM,
+ .display = &hsw_display,
.gt = 3,
};
@@ -645,22 +751,35 @@ static const struct intel_device_info hsw_gt3_info = {
.__runtime.ppgtt_size = 48, \
.has_64bit_reloc = 1
+static const struct intel_display_device_info bdw_display = {
+ .has_ddi = 1,
+ .has_dp_mst = 1,
+ .has_fpga_dbg = 1,
+ .has_hotplug = 1,
+ HSW_PIPE_OFFSETS,
+ IVB_CURSOR_OFFSETS,
+ IVB_COLORS,
+};
+
#define BDW_PLATFORM \
GEN8_FEATURES, \
PLATFORM(INTEL_BROADWELL)
static const struct intel_device_info bdw_gt1_info = {
BDW_PLATFORM,
+ .display = &bdw_display,
.gt = 1,
};
static const struct intel_device_info bdw_gt2_info = {
BDW_PLATFORM,
+ .display = &bdw_display,
.gt = 2,
};
static const struct intel_device_info bdw_rsvd_info = {
BDW_PLATFORM,
+ .display = &bdw_display,
.gt = 3,
/* According to the device ID those devices are GT3, they were
* previously treated as not GT3, keep it like that.
@@ -669,17 +788,27 @@ static const struct intel_device_info bdw_rsvd_info = {
static const struct intel_device_info bdw_gt3_info = {
BDW_PLATFORM,
+ .display = &bdw_display,
.gt = 3,
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
};
+static const struct intel_display_device_info chv_display = {
+ .has_hotplug = 1,
+ .has_gmch = 1,
+ .mmio_offset = VLV_DISPLAY_BASE,
+ CHV_PIPE_OFFSETS,
+ CHV_CURSOR_OFFSETS,
+ CHV_COLORS,
+};
+
static const struct intel_device_info chv_info = {
PLATFORM(INTEL_CHERRYVIEW),
GEN(8),
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
- .display.has_hotplug = 1,
+ .display = &chv_display,
.is_lp = 1,
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
.has_64bit_reloc = 1,
@@ -687,7 +816,6 @@ static const struct intel_device_info chv_info = {
.has_rc6 = 1,
.has_rps = true,
.has_logical_ring_contexts = 1,
- .display.has_gmch = 1,
.dma_mask_size = 39,
.max_pat_index = 3,
.__runtime.ppgtt_type = INTEL_PPGTT_FULL,
@@ -695,10 +823,6 @@ static const struct intel_device_info chv_info = {
.has_reset_engine = 1,
.has_snoop = true,
.has_coherent_ggtt = false,
- .display.mmio_offset = VLV_DISPLAY_BASE,
- CHV_PIPE_OFFSETS,
- CHV_CURSOR_OFFSETS,
- CHV_COLORS,
GEN_DEFAULT_PAGE_SIZES,
GEN_DEFAULT_REGIONS,
LEGACY_CACHELEVEL,
@@ -714,12 +838,22 @@ static const struct intel_device_info chv_info = {
GEN9_DEFAULT_PAGE_SIZES, \
.__runtime.has_dmc = 1, \
.has_gt_uc = 1, \
- .__runtime.has_hdcp = 1, \
- .display.has_ipc = 1, \
- .display.has_psr = 1, \
- .display.has_psr_hw_tracking = 1, \
- .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
- .display.dbuf.slice_mask = BIT(DBUF_S1)
+ .__runtime.has_hdcp = 1
+
+static const struct intel_display_device_info skl_display = {
+ .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
+ .dbuf.slice_mask = BIT(DBUF_S1),
+ .has_ddi = 1,
+ .has_dp_mst = 1,
+ .has_fpga_dbg = 1,
+ .has_hotplug = 1,
+ .has_ipc = 1,
+ .has_psr = 1,
+ .has_psr_hw_tracking = 1,
+ HSW_PIPE_OFFSETS,
+ IVB_CURSOR_OFFSETS,
+ IVB_COLORS,
+};
#define SKL_PLATFORM \
GEN9_FEATURES, \
@@ -727,11 +861,13 @@ static const struct intel_device_info chv_info = {
static const struct intel_device_info skl_gt1_info = {
SKL_PLATFORM,
+ .display = &skl_display,
.gt = 1,
};
static const struct intel_device_info skl_gt2_info = {
SKL_PLATFORM,
+ .display = &skl_display,
.gt = 2,
};
@@ -743,19 +879,19 @@ static const struct intel_device_info skl_gt2_info = {
static const struct intel_device_info skl_gt3_info = {
SKL_GT3_PLUS_PLATFORM,
+ .display = &skl_display,
.gt = 3,
};
static const struct intel_device_info skl_gt4_info = {
SKL_GT3_PLUS_PLATFORM,
+ .display = &skl_display,
.gt = 4,
};
#define GEN9_LP_FEATURES \
GEN(9), \
.is_lp = 1, \
- .display.dbuf.slice_mask = BIT(DBUF_S1), \
- .display.has_hotplug = 1, \
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
@@ -763,17 +899,12 @@ static const struct intel_device_info skl_gt4_info = {
BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
.has_3d_pipeline = 1, \
.has_64bit_reloc = 1, \
- .display.has_ddi = 1, \
- .display.has_fpga_dbg = 1, \
.__runtime.fbc_mask = BIT(INTEL_FBC_A), \
.__runtime.has_hdcp = 1, \
- .display.has_psr = 1, \
- .display.has_psr_hw_tracking = 1, \
.has_runtime_pm = 1, \
.__runtime.has_dmc = 1, \
.has_rc6 = 1, \
.has_rps = true, \
- .display.has_dp_mst = 1, \
.has_logical_ring_contexts = 1, \
.has_gt_uc = 1, \
.dma_mask_size = 39, \
@@ -782,27 +913,46 @@ static const struct intel_device_info skl_gt4_info = {
.has_reset_engine = 1, \
.has_snoop = true, \
.has_coherent_ggtt = false, \
- .display.has_ipc = 1, \
.max_pat_index = 3, \
- HSW_PIPE_OFFSETS, \
- IVB_CURSOR_OFFSETS, \
- IVB_COLORS, \
GEN9_DEFAULT_PAGE_SIZES, \
GEN_DEFAULT_REGIONS, \
LEGACY_CACHELEVEL
+#define GEN9_LP_DISPLAY \
+ .dbuf.slice_mask = BIT(DBUF_S1), \
+ .has_dp_mst = 1, \
+ .has_ddi = 1, \
+ .has_fpga_dbg = 1, \
+ .has_hotplug = 1, \
+ .has_ipc = 1, \
+ .has_psr = 1, \
+ .has_psr_hw_tracking = 1, \
+ HSW_PIPE_OFFSETS, \
+ IVB_CURSOR_OFFSETS, \
+ IVB_COLORS
+
+static const struct intel_display_device_info bxt_display = {
+ GEN9_LP_DISPLAY,
+ .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
+};
+
static const struct intel_device_info bxt_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_BROXTON),
- .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
+ .display = &bxt_display,
+};
+
+static const struct intel_display_device_info glk_display = {
+ GEN9_LP_DISPLAY,
+ .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
+ GLK_COLORS,
};
static const struct intel_device_info glk_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_GEMINILAKE),
.__runtime.display.ip.ver = 10,
- .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
- GLK_COLORS,
+ .display = &glk_display,
};
#define KBL_PLATFORM \
@@ -811,16 +961,19 @@ static const struct intel_device_info glk_info = {
static const struct intel_device_info kbl_gt1_info = {
KBL_PLATFORM,
+ .display = &skl_display,
.gt = 1,
};
static const struct intel_device_info kbl_gt2_info = {
KBL_PLATFORM,
+ .display = &skl_display,
.gt = 2,
};
static const struct intel_device_info kbl_gt3_info = {
KBL_PLATFORM,
+ .display = &skl_display,
.gt = 3,
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
@@ -832,16 +985,19 @@ static const struct intel_device_info kbl_gt3_info = {
static const struct intel_device_info cfl_gt1_info = {
CFL_PLATFORM,
+ .display = &skl_display,
.gt = 1,
};
static const struct intel_device_info cfl_gt2_info = {
CFL_PLATFORM,
+ .display = &skl_display,
.gt = 2,
};
static const struct intel_device_info cfl_gt3_info = {
CFL_PLATFORM,
+ .display = &skl_display,
.gt = 3,
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
@@ -853,11 +1009,13 @@ static const struct intel_device_info cfl_gt3_info = {
static const struct intel_device_info cml_gt1_info = {
CML_PLATFORM,
+ .display = &skl_display,
.gt = 1,
};
static const struct intel_device_info cml_gt2_info = {
CML_PLATFORM,
+ .display = &skl_display,
.gt = 2,
};
@@ -869,39 +1027,51 @@ static const struct intel_device_info cml_gt2_info = {
#define GEN11_FEATURES \
GEN9_FEATURES, \
GEN11_DEFAULT_PAGE_SIZES, \
- .display.abox_mask = BIT(0), \
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
- .display.pipe_offsets = { \
- [TRANSCODER_A] = PIPE_A_OFFSET, \
- [TRANSCODER_B] = PIPE_B_OFFSET, \
- [TRANSCODER_C] = PIPE_C_OFFSET, \
- [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
- [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
- [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
- }, \
- .display.trans_offsets = { \
- [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
- [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
- [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
- [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
- }, \
GEN(11), \
- ICL_COLORS, \
- .display.dbuf.size = 2048, \
- .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
.__runtime.has_dsc = 1, \
.has_coherent_ggtt = false, \
.has_logical_ring_elsq = 1
+static const struct intel_display_device_info gen11_display = {
+ .abox_mask = BIT(0),
+ .dbuf.size = 2048,
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2),
+ .has_ddi = 1,
+ .has_dp_mst = 1,
+ .has_fpga_dbg = 1,
+ .has_hotplug = 1,
+ .has_ipc = 1,
+ .has_psr = 1,
+ .has_psr_hw_tracking = 1,
+ .pipe_offsets = {
+ [TRANSCODER_A] = PIPE_A_OFFSET,
+ [TRANSCODER_B] = PIPE_B_OFFSET,
+ [TRANSCODER_C] = PIPE_C_OFFSET,
+ [TRANSCODER_EDP] = PIPE_EDP_OFFSET,
+ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
+ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
+ },
+ .trans_offsets = {
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET,
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET,
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET,
+ [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET,
+ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
+ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
+ },
+ IVB_CURSOR_OFFSETS,
+ ICL_COLORS,
+};
+
static const struct intel_device_info icl_info = {
GEN11_FEATURES,
PLATFORM(INTEL_ICELAKE),
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+ .display = &gen11_display,
};
static const struct intel_device_info ehl_info = {
@@ -909,6 +1079,7 @@ static const struct intel_device_info ehl_info = {
PLATFORM(INTEL_ELKHARTLAKE),
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
.__runtime.ppgtt_size = 36,
+ .display = &gen11_display,
};
static const struct intel_device_info jsl_info = {
@@ -916,17 +1087,34 @@ static const struct intel_device_info jsl_info = {
PLATFORM(INTEL_JASPERLAKE),
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
.__runtime.ppgtt_size = 36,
+ .display = &gen11_display,
};
#define GEN12_FEATURES \
GEN11_FEATURES, \
GEN(12), \
- .display.abox_mask = GENMASK(2, 1), \
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
- .display.pipe_offsets = { \
+ TGL_CACHELEVEL, \
+ .has_global_mocs = 1, \
+ .has_pxp = 1, \
+ .max_pat_index = 3
+
+#define XE_D_DISPLAY \
+ .abox_mask = GENMASK(2, 1), \
+ .dbuf.size = 2048, \
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
+ .has_ddi = 1, \
+ .has_dp_mst = 1, \
+ .has_dsb = 1, \
+ .has_fpga_dbg = 1, \
+ .has_hotplug = 1, \
+ .has_ipc = 1, \
+ .has_psr = 1, \
+ .has_psr_hw_tracking = 1, \
+ .pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
[TRANSCODER_C] = PIPE_C_OFFSET, \
@@ -934,7 +1122,7 @@ static const struct intel_device_info jsl_info = {
[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
}, \
- .display.trans_offsets = { \
+ .trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -943,30 +1131,36 @@ static const struct intel_device_info jsl_info = {
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
TGL_CURSOR_OFFSETS, \
- TGL_CACHELEVEL, \
- .has_global_mocs = 1, \
- .has_pxp = 1, \
- .display.has_dsb = 1, \
- .max_pat_index = 3
+ ICL_COLORS
+
+static const struct intel_display_device_info tgl_display = {
+ XE_D_DISPLAY,
+};
static const struct intel_device_info tgl_info = {
GEN12_FEATURES,
PLATFORM(INTEL_TIGERLAKE),
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+ .display = &tgl_display,
+};
+
+static const struct intel_display_device_info rkl_display = {
+ XE_D_DISPLAY,
+ .abox_mask = BIT(0),
+ .has_hti = 1,
+ .has_psr_hw_tracking = 0,
};
static const struct intel_device_info rkl_info = {
GEN12_FEATURES,
PLATFORM(INTEL_ROCKETLAKE),
- .display.abox_mask = BIT(0),
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C),
- .display.has_hti = 1,
- .display.has_psr_hw_tracking = 0,
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
+ .display = &rkl_display,
};
#define DGFX_FEATURES \
@@ -989,43 +1183,43 @@ static const struct intel_device_info dg1_info = {
BIT(VCS0) | BIT(VCS2),
/* Wa_16011227922 */
.__runtime.ppgtt_size = 47,
+ .display = &tgl_display,
+};
+
+static const struct intel_display_device_info adl_s_display = {
+ XE_D_DISPLAY,
+ .has_hti = 1,
+ .has_psr_hw_tracking = 0,
};
static const struct intel_device_info adl_s_info = {
GEN12_FEATURES,
PLATFORM(INTEL_ALDERLAKE_S),
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
- .display.has_hti = 1,
- .display.has_psr_hw_tracking = 0,
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.dma_mask_size = 39,
+ .display = &adl_s_display,
};
#define XE_LPD_FEATURES \
- .display.abox_mask = GENMASK(1, 0), \
- .display.color = { \
+ .abox_mask = GENMASK(1, 0), \
+ .color = { \
.degamma_lut_size = 129, .gamma_lut_size = 1024, \
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
- DRM_COLOR_LUT_EQUAL_CHANNELS, \
+ DRM_COLOR_LUT_EQUAL_CHANNELS, \
}, \
- .display.dbuf.size = 4096, \
- .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
+ .dbuf.size = 4096, \
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
BIT(DBUF_S4), \
- .display.has_ddi = 1, \
- .__runtime.has_dmc = 1, \
- .display.has_dp_mst = 1, \
- .display.has_dsb = 1, \
- .__runtime.has_dsc = 1, \
- .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
- .display.has_fpga_dbg = 1, \
- .__runtime.has_hdcp = 1, \
- .display.has_hotplug = 1, \
- .display.has_ipc = 1, \
- .display.has_psr = 1, \
- .__runtime.display.ip.ver = 13, \
- .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
- .display.pipe_offsets = { \
+ .has_ddi = 1, \
+ .has_dp_mst = 1, \
+ .has_dsb = 1, \
+ .has_fpga_dbg = 1, \
+ .has_hotplug = 1, \
+ .has_ipc = 1, \
+ .has_psr = 1, \
+ .pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
[TRANSCODER_C] = PIPE_C_OFFSET, \
@@ -1033,7 +1227,7 @@ static const struct intel_device_info adl_s_info = {
[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
}, \
- .display.trans_offsets = { \
+ .trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -1043,18 +1237,31 @@ static const struct intel_device_info adl_s_info = {
}, \
TGL_CURSOR_OFFSETS
+#define XE_LPD_RUNTIME \
+ .__runtime.has_dmc = 1, \
+ .__runtime.has_dsc = 1, \
+ .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
+ .__runtime.has_hdcp = 1, \
+ .__runtime.display.ip.ver = 13, \
+ .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
+
+static const struct intel_display_device_info xe_lpd_display = {
+ XE_LPD_FEATURES,
+ .has_cdclk_crawl = 1,
+ .has_psr_hw_tracking = 0,
+};
+
static const struct intel_device_info adl_p_info = {
GEN12_FEATURES,
- XE_LPD_FEATURES,
+ XE_LPD_RUNTIME,
PLATFORM(INTEL_ALDERLAKE_P),
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
- .display.has_cdclk_crawl = 1,
- .display.has_psr_hw_tracking = 0,
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.__runtime.ppgtt_size = 48,
+ .display = &xe_lpd_display,
.dma_mask_size = 39,
};
@@ -1125,18 +1332,23 @@ static const struct intel_device_info xehpsdv_info = {
.has_guc_deprivilege = 1, \
.has_heci_pxp = 1, \
.has_media_ratio_mode = 1, \
- .display.has_cdclk_squash = 1, \
.__runtime.platform_engine_mask = \
BIT(RCS0) | BIT(BCS0) | \
BIT(VECS0) | BIT(VECS1) | \
BIT(VCS0) | BIT(VCS2) | \
BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
+static const struct intel_display_device_info xe_hpd_display = {
+ XE_LPD_FEATURES,
+ .has_cdclk_squash = 1,
+};
+
static const struct intel_device_info dg2_info = {
DG2_FEATURES,
- XE_LPD_FEATURES,
+ XE_LPD_RUNTIME,
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+ .display = &xe_hpd_display,
};
static const struct intel_device_info ats_m_info = {
@@ -1174,11 +1386,9 @@ static const struct intel_device_info pvc_info = {
PVC_CACHELEVEL,
};
-#define XE_LPDP_FEATURES \
- XE_LPD_FEATURES, \
+#define XE_LPDP_RUNTIME \
+ XE_LPD_RUNTIME, \
.__runtime.display.ip.ver = 14, \
- .display.has_cdclk_crawl = 1, \
- .display.has_cdclk_squash = 1, \
.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
static const struct intel_gt_definition xelpmp_extra_gt[] = {
@@ -1191,9 +1401,15 @@ static const struct intel_gt_definition xelpmp_extra_gt[] = {
{}
};
+static const struct intel_display_device_info xe_lpdp_display = {
+ XE_LPD_FEATURES,
+ .has_cdclk_crawl = 1,
+ .has_cdclk_squash = 1,
+};
+
static const struct intel_device_info mtl_info = {
XE_HP_FEATURES,
- XE_LPDP_FEATURES,
+ XE_LPDP_RUNTIME,
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
/*
@@ -1204,6 +1420,7 @@ static const struct intel_device_info mtl_info = {
.__runtime.graphics.ip.rel = 70,
.__runtime.media.ip.ver = 13,
PLATFORM(INTEL_METEORLAKE),
+ .display = &xe_lpdp_display,
.extra_gt_list = xelpmp_extra_gt,
.has_flat_ccs = 0,
.has_gmd_id = 1,
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 4e23be2995bf..d0bf626d0360 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -138,7 +138,7 @@ void intel_device_info_print(const struct intel_device_info *info,
drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
-#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name))
+#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display->name))
DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
#undef PRINT_FLAG
@@ -388,6 +388,8 @@ mkwrite_device_info(struct drm_i915_private *i915)
return (struct intel_device_info *)INTEL_INFO(i915);
}
+static const struct intel_display_device_info no_display = { 0 };
+
/**
* intel_device_info_runtime_init - initialize runtime info
* @dev_priv: the i915 device
@@ -538,7 +540,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv)) {
dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
DRIVER_ATOMIC);
- memset(&info->display, 0, sizeof(info->display));
+ info->display = &no_display;
runtime->cpu_transcoder_mask = 0;
memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 96f6bdb04b1b..f212e02e6582 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -259,7 +259,7 @@ struct intel_device_info {
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
- struct intel_display_device_info display;
+ const struct intel_display_device_info *display;
/*
* Initial runtime info. Do not access outside of i915_driver_create().
--
2.40.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: Convert INTEL_INFO()->display to a pointer
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 2/6] drm/i915: Convert INTEL_INFO()->display to a pointer Matt Roper
@ 2023-05-23 7:45 ` Andrzej Hajda
2023-05-23 12:47 ` [Intel-gfx] [Intel-xe] " Jani Nikula
1 sibling, 0 replies; 22+ messages in thread
From: Andrzej Hajda @ 2023-05-23 7:45 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: Lucas De Marchi, intel-xe
On 22.05.2023 22:23, Matt Roper wrote:
> Rather than embeddeding the display's device info within the main device
> info structure, just provide a pointer to the display-specific
> structure. This is in preparation for moving the display device info
> definitions into the display code itself and for eventually allowing the
> pointer to be assigned at runtime on platforms that use GMD_ID for
> device identification.
>
> In the future, this will also eventually allow the same display device
> info structures to be used outside the current i915 code (e.g., from the
> Xe driver).
>
> v2:
> - Move introduction of DISPLAY_INFO() to this patch. (Andrzej)
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 31 +-
> drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
> .../drm/i915/display/intel_display_power.c | 6 +-
> .../drm/i915/display/intel_display_reg_defs.h | 14 +-
> drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hti.c | 2 +-
> drivers/gpu/drm/i915/display/skl_watermark.c | 8 +-
> drivers/gpu/drm/i915/i915_drv.h | 29 +-
> drivers/gpu/drm/i915/i915_pci.c | 579 ++++++++++++------
> drivers/gpu/drm/i915/intel_device_info.c | 6 +-
> drivers/gpu/drm/i915/intel_device_info.h | 2 +-
> 12 files changed, 452 insertions(+), 231 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 07f1afe1d406..744b3a4ec99a 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1824,14 +1824,14 @@ static u32 intel_gamma_lut_tests(const struct intel_crtc_state *crtc_state)
> if (lut_is_legacy(gamma_lut))
> return 0;
>
> - return INTEL_INFO(i915)->display.color.gamma_lut_tests;
> + return DISPLAY_INFO(i915)->color.gamma_lut_tests;
> }
>
> static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>
> - return INTEL_INFO(i915)->display.color.degamma_lut_tests;
> + return DISPLAY_INFO(i915)->color.degamma_lut_tests;
> }
>
> static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
> @@ -1842,14 +1842,14 @@ static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
> if (lut_is_legacy(gamma_lut))
> return LEGACY_LUT_LENGTH;
>
> - return INTEL_INFO(i915)->display.color.gamma_lut_size;
> + return DISPLAY_INFO(i915)->color.gamma_lut_size;
> }
>
> static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>
> - return INTEL_INFO(i915)->display.color.degamma_lut_size;
> + return DISPLAY_INFO(i915)->color.degamma_lut_size;
> }
>
> static int check_lut_size(const struct drm_property_blob *lut, int expected)
> @@ -2321,7 +2321,7 @@ static int glk_assign_luts(struct intel_crtc_state *crtc_state)
> struct drm_property_blob *gamma_lut;
>
> gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut,
> - INTEL_INFO(i915)->display.color.degamma_lut_size,
> + DISPLAY_INFO(i915)->color.degamma_lut_size,
> false);
> if (IS_ERR(gamma_lut))
> return PTR_ERR(gamma_lut);
> @@ -2855,7 +2855,7 @@ static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
> static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - u32 lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
> + u32 lut_size = DISPLAY_INFO(dev_priv)->color.gamma_lut_size;
> enum pipe pipe = crtc->pipe;
> struct drm_property_blob *blob;
> struct drm_color_lut *lut;
> @@ -2904,7 +2904,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
> static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
> + int i, lut_size = DISPLAY_INFO(dev_priv)->color.gamma_lut_size;
> enum pipe pipe = crtc->pipe;
> struct drm_property_blob *blob;
> struct drm_color_lut *lut;
> @@ -2954,7 +2954,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
> static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
> + int i, lut_size = DISPLAY_INFO(dev_priv)->color.degamma_lut_size;
> enum pipe pipe = crtc->pipe;
> struct drm_property_blob *blob;
> struct drm_color_lut *lut;
> @@ -2980,7 +2980,7 @@ static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc)
> static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
> {
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> - int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
> + int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;
> enum pipe pipe = crtc->pipe;
> struct drm_property_blob *blob;
> struct drm_color_lut *lut;
> @@ -3044,7 +3044,7 @@ static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
> static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
> {
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> - int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
> + int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;
> enum pipe pipe = crtc->pipe;
> struct drm_property_blob *blob;
> struct drm_color_lut *lut;
> @@ -3228,7 +3228,7 @@ static void bdw_read_luts(struct intel_crtc_state *crtc_state)
> static struct drm_property_blob *glk_read_degamma_lut(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
> + int i, lut_size = DISPLAY_INFO(dev_priv)->color.degamma_lut_size;
> enum pipe pipe = crtc->pipe;
> struct drm_property_blob *blob;
> struct drm_color_lut *lut;
> @@ -3293,7 +3293,7 @@ static struct drm_property_blob *
> icl_read_lut_multi_segment(struct intel_crtc *crtc)
> {
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> - int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
> + int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;
> enum pipe pipe = crtc->pipe;
> struct drm_property_blob *blob;
> struct drm_color_lut *lut;
> @@ -3471,8 +3471,8 @@ void intel_color_crtc_init(struct intel_crtc *crtc)
>
> drm_mode_crtc_set_gamma_size(&crtc->base, 256);
>
> - gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
> - degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size;
> + gamma_lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;
> + degamma_lut_size = DISPLAY_INFO(i915)->color.degamma_lut_size;
> has_ctm = degamma_lut_size != 0;
>
> /*
> @@ -3497,7 +3497,8 @@ int intel_color_init(struct drm_i915_private *i915)
> if (DISPLAY_VER(i915) != 10)
> return 0;
>
> - blob = create_linear_lut(i915, INTEL_INFO(i915)->display.color.degamma_lut_size);
> + blob = create_linear_lut(i915,
> + DISPLAY_INFO(i915)->color.degamma_lut_size);
> if (IS_ERR(blob))
> return PTR_ERR(blob);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index 31bef0427377..3864da5f5c17 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -36,7 +36,7 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
> const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> u32 base;
>
> - if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
> + if (DISPLAY_INFO(dev_priv)->cursor_needs_physical)
> base = sg_dma_address(obj->mm.pages->sgl);
> else
> base = intel_plane_ggtt_offset(plane_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 205b3929b861..aa3a21ccd7fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -113,7 +113,7 @@ enum i9xx_plane_id {
>
> #define for_each_dbuf_slice(__dev_priv, __slice) \
> for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
> - for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice))
> + for_each_if(INTEL_INFO(__dev_priv)->display->dbuf.slice_mask & BIT(__slice))
>
> #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
> for_each_dbuf_slice((__dev_priv), (__slice)) \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 6ed2ece89c3f..9c9a809c71f1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1053,7 +1053,7 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
> u8 req_slices)
> {
> struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
> - u8 slice_mask = INTEL_INFO(dev_priv)->display.dbuf.slice_mask;
> + u8 slice_mask = DISPLAY_INFO(dev_priv)->dbuf.slice_mask;
> enum dbuf_slice slice;
>
> drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
> @@ -1113,7 +1113,7 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
>
> static void icl_mbus_init(struct drm_i915_private *dev_priv)
> {
> - unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask;
> + unsigned long abox_regs = DISPLAY_INFO(dev_priv)->abox_mask;
> u32 mask, val, i;
>
> if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
> @@ -1568,7 +1568,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> enum intel_dram_type type = dev_priv->dram_info.type;
> u8 num_channels = dev_priv->dram_info.num_channels;
> const struct buddy_page_mask *table;
> - unsigned long abox_mask = INTEL_INFO(dev_priv)->display.abox_mask;
> + unsigned long abox_mask = DISPLAY_INFO(dev_priv)->abox_mask;
> int config, i;
>
> /* BW_BUDDY registers are not used on dgpu's beyond DG1 */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> index 755c1ea8225c..e0f82f28d8b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> @@ -8,7 +8,7 @@
>
> #include "i915_reg_defs.h"
>
> -#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display.mmio_offset)
> +#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display->mmio_offset)
Why not DISPLAY_INFO here and below?
intel_display_reg_defs.h does not include header defining neither
DISPLAY_INFO neither INTEL_INFO, so no big difference in terms of
correctness/self-containment :)
I do not know what is ultimate goal of the conversion.
If part of it is to make INTEL_INFO/DISPLAY_INFO driver (i915/xe)
agnostic then it is probably fine, otherwise maybe it would be good to
add include i915_drv.h.
r-b is valid anyway.
Regards
Andrzej
>
> #define VLV_DISPLAY_BASE 0x180000
>
> @@ -36,14 +36,14 @@
> * Device info offset array based helpers for groups of registers with unevenly
> * spaced base offsets.
> */
> -#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \
> - INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \
> +#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display->pipe_offsets[(pipe)] - \
> + INTEL_INFO(dev_priv)->display->pipe_offsets[PIPE_A] + \
> DISPLAY_MMIO_BASE(dev_priv) + (reg))
> -#define _MMIO_TRANS2(tran, reg) _MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
> - INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
> +#define _MMIO_TRANS2(tran, reg) _MMIO(INTEL_INFO(dev_priv)->display->trans_offsets[(tran)] - \
> + INTEL_INFO(dev_priv)->display->trans_offsets[TRANSCODER_A] + \
> DISPLAY_MMIO_BASE(dev_priv) + (reg))
> -#define _MMIO_CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
> - INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
> +#define _MMIO_CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display->cursor_offsets[(pipe)] - \
> + INTEL_INFO(dev_priv)->display->cursor_offsets[PIPE_A] + \
> DISPLAY_MMIO_BASE(dev_priv) + (reg))
>
> #endif /* __INTEL_DISPLAY_REG_DEFS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c
> index 1aca7552a85d..fffd568070d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
> @@ -243,7 +243,7 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state)
> struct i915_vma *vma;
> bool phys_cursor =
> plane->id == PLANE_CURSOR &&
> - INTEL_INFO(dev_priv)->display.cursor_needs_physical;
> + DISPLAY_INFO(dev_priv)->cursor_needs_physical;
>
> if (!intel_fb_uses_dpt(fb)) {
> vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
> diff --git a/drivers/gpu/drm/i915/display/intel_hti.c b/drivers/gpu/drm/i915/display/intel_hti.c
> index c518efebdf77..a92d008d4e6e 100644
> --- a/drivers/gpu/drm/i915/display/intel_hti.c
> +++ b/drivers/gpu/drm/i915/display/intel_hti.c
> @@ -15,7 +15,7 @@ void intel_hti_init(struct drm_i915_private *i915)
> * If the platform has HTI, we need to find out whether it has reserved
> * any display resources before we create our display outputs.
> */
> - if (INTEL_INFO(i915)->display.has_hti)
> + if (DISPLAY_INFO(i915)->has_hti)
> i915->display.hti.state = intel_de_read(i915, HDPORT_STATE);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 1c7e6468f3e3..d1245c847f1c 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -507,8 +507,8 @@ static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
>
> static int intel_dbuf_slice_size(struct drm_i915_private *i915)
> {
> - return INTEL_INFO(i915)->display.dbuf.size /
> - hweight8(INTEL_INFO(i915)->display.dbuf.slice_mask);
> + return DISPLAY_INFO(i915)->dbuf.size /
> + hweight8(DISPLAY_INFO(i915)->dbuf.slice_mask);
> }
>
> static void
> @@ -527,7 +527,7 @@ skl_ddb_entry_for_slices(struct drm_i915_private *i915, u8 slice_mask,
> ddb->end = fls(slice_mask) * slice_size;
>
> WARN_ON(ddb->start >= ddb->end);
> - WARN_ON(ddb->end > INTEL_INFO(i915)->display.dbuf.size);
> + WARN_ON(ddb->end > DISPLAY_INFO(i915)->dbuf.size);
> }
>
> static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask)
> @@ -2625,7 +2625,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
> "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
> old_dbuf_state->enabled_slices,
> new_dbuf_state->enabled_slices,
> - INTEL_INFO(i915)->display.dbuf.slice_mask,
> + DISPLAY_INFO(i915)->dbuf.slice_mask,
> str_yes_no(old_dbuf_state->joined_mbus),
> str_yes_no(new_dbuf_state->joined_mbus));
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 14c5338c96a6..9612c2ac4b00 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -408,6 +408,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
> (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
>
> #define INTEL_INFO(i915) (&(i915)->__info)
> +#define DISPLAY_INFO(i915) (INTEL_INFO(i915)->display)
> #define RUNTIME_INFO(i915) (&(i915)->__runtime)
> #define DRIVER_CAPS(i915) (&(i915)->caps)
>
> @@ -782,9 +783,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
> })
>
> -#define HAS_OVERLAY(i915) (INTEL_INFO(i915)->display.has_overlay)
> +#define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay)
> #define OVERLAY_NEEDS_PHYSICAL(i915) \
> - (INTEL_INFO(i915)->display.overlay_needs_physical)
> + (DISPLAY_INFO(i915)->overlay_needs_physical)
>
> /* Early gen2 have a totally busted CS tlb and require pinned batches. */
> #define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915))
> @@ -806,8 +807,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> */
> #define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
> !(IS_I915G(i915) || IS_I915GM(i915)))
> -#define SUPPORTS_TV(i915) (INTEL_INFO(i915)->display.supports_tv)
> -#define I915_HAS_HOTPLUG(i915) (INTEL_INFO(i915)->display.has_hotplug)
> +#define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv)
> +#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
>
> #define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2)
> #define HAS_FBC(i915) (RUNTIME_INFO(i915)->fbc_mask != 0)
> @@ -817,18 +818,18 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_IPS(i915) (IS_HSW_ULT(i915) || IS_BROADWELL(i915))
>
> -#define HAS_DP_MST(i915) (INTEL_INFO(i915)->display.has_dp_mst)
> +#define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst)
> #define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
>
> #define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
>
> -#define HAS_CDCLK_CRAWL(i915) (INTEL_INFO(i915)->display.has_cdclk_crawl)
> -#define HAS_CDCLK_SQUASH(i915) (INTEL_INFO(i915)->display.has_cdclk_squash)
> -#define HAS_DDI(i915) (INTEL_INFO(i915)->display.has_ddi)
> -#define HAS_FPGA_DBG_UNCLAIMED(i915) (INTEL_INFO(i915)->display.has_fpga_dbg)
> -#define HAS_PSR(i915) (INTEL_INFO(i915)->display.has_psr)
> +#define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl)
> +#define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash)
> +#define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi)
> +#define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg)
> +#define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr)
> #define HAS_PSR_HW_TRACKING(i915) \
> - (INTEL_INFO(i915)->display.has_psr_hw_tracking)
> + (DISPLAY_INFO(i915)->has_psr_hw_tracking)
> #define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12)
> #define HAS_TRANSCODER(i915, trans) ((RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
>
> @@ -839,7 +840,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
>
> #define HAS_DMC(i915) (RUNTIME_INFO(i915)->has_dmc)
> -#define HAS_DSB(i915) (INTEL_INFO(i915)->display.has_dsb)
> +#define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb)
> #define HAS_DSC(__i915) (RUNTIME_INFO(__i915)->has_dsc)
> #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
>
> @@ -869,7 +870,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> */
> #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
>
> -#define HAS_IPC(i915) (INTEL_INFO(i915)->display.has_ipc)
> +#define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
> #define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
>
> #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
> @@ -889,7 +890,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
>
> -#define HAS_GMCH(i915) (INTEL_INFO(i915)->display.has_gmch)
> +#define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch)
>
> #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index e4a19161afce..dd874a4db604 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -47,43 +47,43 @@
> #define NO_DISPLAY .__runtime.pipe_mask = 0
>
> #define I845_PIPE_OFFSETS \
> - .display.pipe_offsets = { \
> + .pipe_offsets = { \
> [TRANSCODER_A] = PIPE_A_OFFSET, \
> }, \
> - .display.trans_offsets = { \
> + .trans_offsets = { \
> [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> }
>
> #define I9XX_PIPE_OFFSETS \
> - .display.pipe_offsets = { \
> + .pipe_offsets = { \
> [TRANSCODER_A] = PIPE_A_OFFSET, \
> [TRANSCODER_B] = PIPE_B_OFFSET, \
> }, \
> - .display.trans_offsets = { \
> + .trans_offsets = { \
> [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> }
>
> #define IVB_PIPE_OFFSETS \
> - .display.pipe_offsets = { \
> + .pipe_offsets = { \
> [TRANSCODER_A] = PIPE_A_OFFSET, \
> [TRANSCODER_B] = PIPE_B_OFFSET, \
> [TRANSCODER_C] = PIPE_C_OFFSET, \
> }, \
> - .display.trans_offsets = { \
> + .trans_offsets = { \
> [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> }
>
> #define HSW_PIPE_OFFSETS \
> - .display.pipe_offsets = { \
> + .pipe_offsets = { \
> [TRANSCODER_A] = PIPE_A_OFFSET, \
> [TRANSCODER_B] = PIPE_B_OFFSET, \
> [TRANSCODER_C] = PIPE_C_OFFSET, \
> [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
> }, \
> - .display.trans_offsets = { \
> + .trans_offsets = { \
> [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> @@ -91,44 +91,44 @@
> }
>
> #define CHV_PIPE_OFFSETS \
> - .display.pipe_offsets = { \
> + .pipe_offsets = { \
> [TRANSCODER_A] = PIPE_A_OFFSET, \
> [TRANSCODER_B] = PIPE_B_OFFSET, \
> [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
> }, \
> - .display.trans_offsets = { \
> + .trans_offsets = { \
> [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
> }
>
> #define I845_CURSOR_OFFSETS \
> - .display.cursor_offsets = { \
> + .cursor_offsets = { \
> [PIPE_A] = CURSOR_A_OFFSET, \
> }
>
> #define I9XX_CURSOR_OFFSETS \
> - .display.cursor_offsets = { \
> + .cursor_offsets = { \
> [PIPE_A] = CURSOR_A_OFFSET, \
> [PIPE_B] = CURSOR_B_OFFSET, \
> }
>
> #define CHV_CURSOR_OFFSETS \
> - .display.cursor_offsets = { \
> + .cursor_offsets = { \
> [PIPE_A] = CURSOR_A_OFFSET, \
> [PIPE_B] = CURSOR_B_OFFSET, \
> [PIPE_C] = CHV_CURSOR_C_OFFSET, \
> }
>
> #define IVB_CURSOR_OFFSETS \
> - .display.cursor_offsets = { \
> + .cursor_offsets = { \
> [PIPE_A] = CURSOR_A_OFFSET, \
> [PIPE_B] = IVB_CURSOR_B_OFFSET, \
> [PIPE_C] = IVB_CURSOR_C_OFFSET, \
> }
>
> #define TGL_CURSOR_OFFSETS \
> - .display.cursor_offsets = { \
> + .cursor_offsets = { \
> [PIPE_A] = CURSOR_A_OFFSET, \
> [PIPE_B] = IVB_CURSOR_B_OFFSET, \
> [PIPE_C] = IVB_CURSOR_C_OFFSET, \
> @@ -136,29 +136,29 @@
> }
>
> #define I845_COLORS \
> - .display.color = { .gamma_lut_size = 256 }
> + .color = { .gamma_lut_size = 256 }
> #define I9XX_COLORS \
> - .display.color = { .gamma_lut_size = 129, \
> + .color = { .gamma_lut_size = 129, \
> .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> }
> #define ILK_COLORS \
> - .display.color = { .gamma_lut_size = 1024 }
> + .color = { .gamma_lut_size = 1024 }
> #define IVB_COLORS \
> - .display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
> + .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
> #define CHV_COLORS \
> - .display.color = { \
> + .color = { \
> .degamma_lut_size = 65, .gamma_lut_size = 257, \
> .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> }
> #define GLK_COLORS \
> - .display.color = { \
> + .color = { \
> .degamma_lut_size = 33, .gamma_lut_size = 1024, \
> .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> DRM_COLOR_LUT_EQUAL_CHANNELS, \
> }
> #define ICL_COLORS \
> - .display.color = { \
> + .color = { \
> .degamma_lut_size = 33, .gamma_lut_size = 262145, \
> .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> DRM_COLOR_LUT_EQUAL_CHANNELS, \
> @@ -205,15 +205,24 @@
> #define GEN_DEFAULT_REGIONS \
> .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
>
> +#define I830_DISPLAY \
> + .has_overlay = 1, \
> + .cursor_needs_physical = 1, \
> + .overlay_needs_physical = 1, \
> + .has_gmch = 1, \
> + I9XX_PIPE_OFFSETS, \
> + I9XX_CURSOR_OFFSETS, \
> + I9XX_COLORS
> +
> +static const struct intel_display_device_info i830_display = {
> + I830_DISPLAY,
> +};
> +
> #define I830_FEATURES \
> GEN(2), \
> .is_mobile = 1, \
> .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> - .display.has_overlay = 1, \
> - .display.cursor_needs_physical = 1, \
> - .display.overlay_needs_physical = 1, \
> - .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> .has_3d_pipeline = 1, \
> .hws_needs_physical = 1, \
> @@ -223,20 +232,26 @@
> .has_coherent_ggtt = false, \
> .dma_mask_size = 32, \
> .max_pat_index = 3, \
> - I9XX_PIPE_OFFSETS, \
> - I9XX_CURSOR_OFFSETS, \
> - I9XX_COLORS, \
> GEN_DEFAULT_PAGE_SIZES, \
> GEN_DEFAULT_REGIONS, \
> LEGACY_CACHELEVEL
>
> +#define I845_DISPLAY \
> + .has_overlay = 1, \
> + .overlay_needs_physical = 1, \
> + .has_gmch = 1, \
> + I845_PIPE_OFFSETS, \
> + I845_CURSOR_OFFSETS, \
> + I845_COLORS
> +
> +static const struct intel_display_device_info i845_display = {
> + I845_DISPLAY,
> +};
> +
> #define I845_FEATURES \
> GEN(2), \
> .__runtime.pipe_mask = BIT(PIPE_A), \
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \
> - .display.has_overlay = 1, \
> - .display.overlay_needs_physical = 1, \
> - .display.has_gmch = 1, \
> .has_3d_pipeline = 1, \
> .gpu_reset_clobbers_display = true, \
> .hws_needs_physical = 1, \
> @@ -246,9 +261,6 @@
> .has_coherent_ggtt = false, \
> .dma_mask_size = 32, \
> .max_pat_index = 3, \
> - I845_PIPE_OFFSETS, \
> - I845_CURSOR_OFFSETS, \
> - I845_COLORS, \
> GEN_DEFAULT_PAGE_SIZES, \
> GEN_DEFAULT_REGIONS, \
> LEGACY_CACHELEVEL
> @@ -256,30 +268,81 @@
> static const struct intel_device_info i830_info = {
> I830_FEATURES,
> PLATFORM(INTEL_I830),
> + .display = &i830_display,
> };
>
> static const struct intel_device_info i845g_info = {
> I845_FEATURES,
> PLATFORM(INTEL_I845G),
> + .display = &i845_display,
> +};
> +
> +static const struct intel_display_device_info i85x_display = {
> + I830_DISPLAY,
> };
>
> static const struct intel_device_info i85x_info = {
> I830_FEATURES,
> PLATFORM(INTEL_I85X),
> + .display = &i85x_display,
> .__runtime.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> +static const struct intel_display_device_info i865g_display = {
> + I845_DISPLAY,
> +};
> +
> static const struct intel_device_info i865g_info = {
> I845_FEATURES,
> PLATFORM(INTEL_I865G),
> + .display = &i865g_display,
> .__runtime.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> +#define GEN3_DISPLAY \
> + .has_gmch = 1, \
> + .has_overlay = 1, \
> + I9XX_PIPE_OFFSETS, \
> + I9XX_CURSOR_OFFSETS, \
> + I9XX_COLORS
> +
> +static const struct intel_display_device_info i915g_display = {
> + GEN3_DISPLAY,
> + .cursor_needs_physical = 1,
> + .overlay_needs_physical = 1,
> +};
> +
> +static const struct intel_display_device_info i915gm_display = {
> + GEN3_DISPLAY,
> + .cursor_needs_physical = 1,
> + .overlay_needs_physical = 1,
> + .supports_tv = 1,
> +};
> +
> +static const struct intel_display_device_info i945g_display = {
> + GEN3_DISPLAY,
> + .has_hotplug = 1,
> + .cursor_needs_physical = 1,
> + .overlay_needs_physical = 1,
> +};
> +
> +static const struct intel_display_device_info i945gm_display = {
> + GEN3_DISPLAY,
> + .has_hotplug = 1,
> + .cursor_needs_physical = 1,
> + .overlay_needs_physical = 1,
> + .supports_tv = 1,
> +};
> +
> +static const struct intel_display_device_info g33_display = {
> + GEN3_DISPLAY,
> + .has_hotplug = 1,
> +};
> +
> #define GEN3_FEATURES \
> GEN(3), \
> .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> - .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> .__runtime.platform_engine_mask = BIT(RCS0), \
> .has_3d_pipeline = 1, \
> @@ -287,9 +350,6 @@ static const struct intel_device_info i865g_info = {
> .has_coherent_ggtt = true, \
> .dma_mask_size = 32, \
> .max_pat_index = 3, \
> - I9XX_PIPE_OFFSETS, \
> - I9XX_CURSOR_OFFSETS, \
> - I9XX_COLORS, \
> GEN_DEFAULT_PAGE_SIZES, \
> GEN_DEFAULT_REGIONS, \
> LEGACY_CACHELEVEL
> @@ -297,10 +357,8 @@ static const struct intel_device_info i865g_info = {
> static const struct intel_device_info i915g_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_I915G),
> + .display = &i915g_display,
> .has_coherent_ggtt = false,
> - .display.cursor_needs_physical = 1,
> - .display.has_overlay = 1,
> - .display.overlay_needs_physical = 1,
> .hws_needs_physical = 1,
> .unfenced_needs_alignment = 1,
> };
> @@ -308,11 +366,8 @@ static const struct intel_device_info i915g_info = {
> static const struct intel_device_info i915gm_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_I915GM),
> + .display = &i915gm_display,
> .is_mobile = 1,
> - .display.cursor_needs_physical = 1,
> - .display.has_overlay = 1,
> - .display.overlay_needs_physical = 1,
> - .display.supports_tv = 1,
> .__runtime.fbc_mask = BIT(INTEL_FBC_A),
> .hws_needs_physical = 1,
> .unfenced_needs_alignment = 1,
> @@ -321,10 +376,7 @@ static const struct intel_device_info i915gm_info = {
> static const struct intel_device_info i945g_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_I945G),
> - .display.has_hotplug = 1,
> - .display.cursor_needs_physical = 1,
> - .display.has_overlay = 1,
> - .display.overlay_needs_physical = 1,
> + .display = &i945g_display,
> .hws_needs_physical = 1,
> .unfenced_needs_alignment = 1,
> };
> @@ -332,12 +384,8 @@ static const struct intel_device_info i945g_info = {
> static const struct intel_device_info i945gm_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_I945GM),
> + .display = &i945gm_display,
> .is_mobile = 1,
> - .display.has_hotplug = 1,
> - .display.cursor_needs_physical = 1,
> - .display.has_overlay = 1,
> - .display.overlay_needs_physical = 1,
> - .display.supports_tv = 1,
> .__runtime.fbc_mask = BIT(INTEL_FBC_A),
> .hws_needs_physical = 1,
> .unfenced_needs_alignment = 1,
> @@ -346,16 +394,14 @@ static const struct intel_device_info i945gm_info = {
> static const struct intel_device_info g33_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_G33),
> - .display.has_hotplug = 1,
> - .display.has_overlay = 1,
> + .display = &g33_display,
> .dma_mask_size = 36,
> };
>
> static const struct intel_device_info pnv_g_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_PINEVIEW),
> - .display.has_hotplug = 1,
> - .display.has_overlay = 1,
> + .display = &g33_display,
> .dma_mask_size = 36,
> };
>
> @@ -363,17 +409,41 @@ static const struct intel_device_info pnv_m_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_PINEVIEW),
> .is_mobile = 1,
> - .display.has_hotplug = 1,
> - .display.has_overlay = 1,
> + .display = &g33_display,
> .dma_mask_size = 36,
> };
>
> +#define GEN4_DISPLAY \
> + .has_hotplug = 1, \
> + .has_gmch = 1, \
> + I9XX_PIPE_OFFSETS, \
> + I9XX_CURSOR_OFFSETS, \
> + I9XX_COLORS
> +
> +static const struct intel_display_device_info i965g_display = {
> + GEN4_DISPLAY,
> + .has_overlay = 1,
> +};
> +
> +static const struct intel_display_device_info i965gm_display = {
> + GEN4_DISPLAY,
> + .has_overlay = 1,
> + .supports_tv = 1,
> +};
> +
> +static const struct intel_display_device_info g45_display = {
> + GEN4_DISPLAY,
> +};
> +
> +static const struct intel_display_device_info gm45_display = {
> + GEN4_DISPLAY,
> + .supports_tv = 1,
> +};
> +
> #define GEN4_FEATURES \
> GEN(4), \
> .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> - .display.has_hotplug = 1, \
> - .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> .__runtime.platform_engine_mask = BIT(RCS0), \
> .has_3d_pipeline = 1, \
> @@ -381,9 +451,6 @@ static const struct intel_device_info pnv_m_info = {
> .has_coherent_ggtt = true, \
> .dma_mask_size = 36, \
> .max_pat_index = 3, \
> - I9XX_PIPE_OFFSETS, \
> - I9XX_CURSOR_OFFSETS, \
> - I9XX_COLORS, \
> GEN_DEFAULT_PAGE_SIZES, \
> GEN_DEFAULT_REGIONS, \
> LEGACY_CACHELEVEL
> @@ -391,7 +458,7 @@ static const struct intel_device_info pnv_m_info = {
> static const struct intel_device_info i965g_info = {
> GEN4_FEATURES,
> PLATFORM(INTEL_I965G),
> - .display.has_overlay = 1,
> + .display = &i965g_display,
> .hws_needs_physical = 1,
> .has_snoop = false,
> };
> @@ -399,10 +466,9 @@ static const struct intel_device_info i965g_info = {
> static const struct intel_device_info i965gm_info = {
> GEN4_FEATURES,
> PLATFORM(INTEL_I965GM),
> + .display = &i965gm_display,
> .is_mobile = 1,
> .__runtime.fbc_mask = BIT(INTEL_FBC_A),
> - .display.has_overlay = 1,
> - .display.supports_tv = 1,
> .hws_needs_physical = 1,
> .has_snoop = false,
> };
> @@ -411,6 +477,7 @@ static const struct intel_device_info g45_info = {
> GEN4_FEATURES,
> PLATFORM(INTEL_G45),
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
> + .display = &g45_display,
> .gpu_reset_clobbers_display = false,
> };
>
> @@ -419,8 +486,8 @@ static const struct intel_device_info gm45_info = {
> PLATFORM(INTEL_GM45),
> .is_mobile = 1,
> .__runtime.fbc_mask = BIT(INTEL_FBC_A),
> - .display.supports_tv = 1,
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
> + .display = &gm45_display,
> .gpu_reset_clobbers_display = false,
> };
>
> @@ -428,7 +495,6 @@ static const struct intel_device_info gm45_info = {
> GEN(5), \
> .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> - .display.has_hotplug = 1, \
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
> .has_3d_pipeline = 1, \
> .has_snoop = true, \
> @@ -437,21 +503,34 @@ static const struct intel_device_info gm45_info = {
> .has_rc6 = 0, \
> .dma_mask_size = 36, \
> .max_pat_index = 3, \
> - I9XX_PIPE_OFFSETS, \
> - I9XX_CURSOR_OFFSETS, \
> - ILK_COLORS, \
> GEN_DEFAULT_PAGE_SIZES, \
> GEN_DEFAULT_REGIONS, \
> LEGACY_CACHELEVEL
>
> +#define ILK_DISPLAY \
> + .has_hotplug = 1, \
> + I9XX_PIPE_OFFSETS, \
> + I9XX_CURSOR_OFFSETS, \
> + ILK_COLORS
> +
> +static const struct intel_display_device_info ilk_d_display = {
> + ILK_DISPLAY,
> +};
> +
> static const struct intel_device_info ilk_d_info = {
> GEN5_FEATURES,
> PLATFORM(INTEL_IRONLAKE),
> + .display = &ilk_d_display,
> +};
> +
> +static const struct intel_display_device_info ilk_m_display = {
> + ILK_DISPLAY,
> };
>
> static const struct intel_device_info ilk_m_info = {
> GEN5_FEATURES,
> PLATFORM(INTEL_IRONLAKE),
> + .display = &ilk_m_display,
> .is_mobile = 1,
> .has_rps = true,
> .__runtime.fbc_mask = BIT(INTEL_FBC_A),
> @@ -461,7 +540,6 @@ static const struct intel_device_info ilk_m_info = {
> GEN(6), \
> .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> - .display.has_hotplug = 1, \
> .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> .has_3d_pipeline = 1, \
> @@ -475,24 +553,30 @@ static const struct intel_device_info ilk_m_info = {
> .max_pat_index = 3, \
> .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
> .__runtime.ppgtt_size = 31, \
> - I9XX_PIPE_OFFSETS, \
> - I9XX_CURSOR_OFFSETS, \
> - ILK_COLORS, \
> GEN_DEFAULT_PAGE_SIZES, \
> GEN_DEFAULT_REGIONS, \
> LEGACY_CACHELEVEL
>
> +static const struct intel_display_device_info snb_display = {
> + .has_hotplug = 1,
> + I9XX_PIPE_OFFSETS,
> + I9XX_CURSOR_OFFSETS,
> + ILK_COLORS,
> +};
> +
> #define SNB_D_PLATFORM \
> GEN6_FEATURES, \
> PLATFORM(INTEL_SANDYBRIDGE)
>
> static const struct intel_device_info snb_d_gt1_info = {
> SNB_D_PLATFORM,
> + .display = &snb_display,
> .gt = 1,
> };
>
> static const struct intel_device_info snb_d_gt2_info = {
> SNB_D_PLATFORM,
> + .display = &snb_display,
> .gt = 2,
> };
>
> @@ -504,11 +588,13 @@ static const struct intel_device_info snb_d_gt2_info = {
>
> static const struct intel_device_info snb_m_gt1_info = {
> SNB_M_PLATFORM,
> + .display = &snb_display,
> .gt = 1,
> };
>
> static const struct intel_device_info snb_m_gt2_info = {
> SNB_M_PLATFORM,
> + .display = &snb_display,
> .gt = 2,
> };
>
> @@ -516,7 +602,6 @@ static const struct intel_device_info snb_m_gt2_info = {
> GEN(7), \
> .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
> - .display.has_hotplug = 1, \
> .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> .has_3d_pipeline = 1, \
> @@ -530,9 +615,6 @@ static const struct intel_device_info snb_m_gt2_info = {
> .max_pat_index = 3, \
> .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
> .__runtime.ppgtt_size = 31, \
> - IVB_PIPE_OFFSETS, \
> - IVB_CURSOR_OFFSETS, \
> - IVB_COLORS, \
> GEN_DEFAULT_PAGE_SIZES, \
> GEN_DEFAULT_REGIONS, \
> LEGACY_CACHELEVEL
> @@ -542,13 +624,22 @@ static const struct intel_device_info snb_m_gt2_info = {
> PLATFORM(INTEL_IVYBRIDGE), \
> .has_l3_dpf = 1
>
> +static const struct intel_display_device_info ivb_display = {
> + .has_hotplug = 1,
> + IVB_PIPE_OFFSETS,
> + IVB_CURSOR_OFFSETS,
> + IVB_COLORS,
> +};
> +
> static const struct intel_device_info ivb_d_gt1_info = {
> IVB_D_PLATFORM,
> + .display = &ivb_display,
> .gt = 1,
> };
>
> static const struct intel_device_info ivb_d_gt2_info = {
> IVB_D_PLATFORM,
> + .display = &ivb_display,
> .gt = 2,
> };
>
> @@ -560,11 +651,13 @@ static const struct intel_device_info ivb_d_gt2_info = {
>
> static const struct intel_device_info ivb_m_gt1_info = {
> IVB_M_PLATFORM,
> + .display = &ivb_display,
> .gt = 1,
> };
>
> static const struct intel_device_info ivb_m_gt2_info = {
> IVB_M_PLATFORM,
> + .display = &ivb_display,
> .gt = 2,
> };
>
> @@ -576,18 +669,26 @@ static const struct intel_device_info ivb_q_info = {
> .has_l3_dpf = 1,
> };
>
> +static const struct intel_display_device_info vlv_display = {
> + .has_gmch = 1,
> + .has_hotplug = 1,
> + .mmio_offset = VLV_DISPLAY_BASE,
> + I9XX_PIPE_OFFSETS,
> + I9XX_CURSOR_OFFSETS,
> + I9XX_COLORS,
> +};
> +
> static const struct intel_device_info vlv_info = {
> PLATFORM(INTEL_VALLEYVIEW),
> GEN(7),
> .is_lp = 1,
> .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> + .display = &vlv_display,
> .has_runtime_pm = 1,
> .has_rc6 = 1,
> .has_reset_engine = true,
> .has_rps = true,
> - .display.has_gmch = 1,
> - .display.has_hotplug = 1,
> .dma_mask_size = 40,
> .max_pat_index = 3,
> .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
> @@ -595,10 +696,6 @@ static const struct intel_device_info vlv_info = {
> .has_snoop = true,
> .has_coherent_ggtt = false,
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
> - .display.mmio_offset = VLV_DISPLAY_BASE,
> - I9XX_PIPE_OFFSETS,
> - I9XX_CURSOR_OFFSETS,
> - I9XX_COLORS,
> GEN_DEFAULT_PAGE_SIZES,
> GEN_DEFAULT_REGIONS,
> LEGACY_CACHELEVEL,
> @@ -609,11 +706,7 @@ static const struct intel_device_info vlv_info = {
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
> - .display.has_ddi = 1, \
> - .display.has_fpga_dbg = 1, \
> - .display.has_dp_mst = 1, \
> .has_rc6p = 0 /* RC6p removed-by HSW */, \
> - HSW_PIPE_OFFSETS, \
> .has_runtime_pm = 1
>
> #define HSW_PLATFORM \
> @@ -621,18 +714,31 @@ static const struct intel_device_info vlv_info = {
> PLATFORM(INTEL_HASWELL), \
> .has_l3_dpf = 1
>
> +static const struct intel_display_device_info hsw_display = {
> + .has_ddi = 1,
> + .has_dp_mst = 1,
> + .has_fpga_dbg = 1,
> + .has_hotplug = 1,
> + HSW_PIPE_OFFSETS,
> + IVB_CURSOR_OFFSETS,
> + IVB_COLORS,
> +};
> +
> static const struct intel_device_info hsw_gt1_info = {
> HSW_PLATFORM,
> + .display = &hsw_display,
> .gt = 1,
> };
>
> static const struct intel_device_info hsw_gt2_info = {
> HSW_PLATFORM,
> + .display = &hsw_display,
> .gt = 2,
> };
>
> static const struct intel_device_info hsw_gt3_info = {
> HSW_PLATFORM,
> + .display = &hsw_display,
> .gt = 3,
> };
>
> @@ -645,22 +751,35 @@ static const struct intel_device_info hsw_gt3_info = {
> .__runtime.ppgtt_size = 48, \
> .has_64bit_reloc = 1
>
> +static const struct intel_display_device_info bdw_display = {
> + .has_ddi = 1,
> + .has_dp_mst = 1,
> + .has_fpga_dbg = 1,
> + .has_hotplug = 1,
> + HSW_PIPE_OFFSETS,
> + IVB_CURSOR_OFFSETS,
> + IVB_COLORS,
> +};
> +
> #define BDW_PLATFORM \
> GEN8_FEATURES, \
> PLATFORM(INTEL_BROADWELL)
>
> static const struct intel_device_info bdw_gt1_info = {
> BDW_PLATFORM,
> + .display = &bdw_display,
> .gt = 1,
> };
>
> static const struct intel_device_info bdw_gt2_info = {
> BDW_PLATFORM,
> + .display = &bdw_display,
> .gt = 2,
> };
>
> static const struct intel_device_info bdw_rsvd_info = {
> BDW_PLATFORM,
> + .display = &bdw_display,
> .gt = 3,
> /* According to the device ID those devices are GT3, they were
> * previously treated as not GT3, keep it like that.
> @@ -669,17 +788,27 @@ static const struct intel_device_info bdw_rsvd_info = {
>
> static const struct intel_device_info bdw_gt3_info = {
> BDW_PLATFORM,
> + .display = &bdw_display,
> .gt = 3,
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> };
>
> +static const struct intel_display_device_info chv_display = {
> + .has_hotplug = 1,
> + .has_gmch = 1,
> + .mmio_offset = VLV_DISPLAY_BASE,
> + CHV_PIPE_OFFSETS,
> + CHV_CURSOR_OFFSETS,
> + CHV_COLORS,
> +};
> +
> static const struct intel_device_info chv_info = {
> PLATFORM(INTEL_CHERRYVIEW),
> GEN(8),
> .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
> - .display.has_hotplug = 1,
> + .display = &chv_display,
> .is_lp = 1,
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
> .has_64bit_reloc = 1,
> @@ -687,7 +816,6 @@ static const struct intel_device_info chv_info = {
> .has_rc6 = 1,
> .has_rps = true,
> .has_logical_ring_contexts = 1,
> - .display.has_gmch = 1,
> .dma_mask_size = 39,
> .max_pat_index = 3,
> .__runtime.ppgtt_type = INTEL_PPGTT_FULL,
> @@ -695,10 +823,6 @@ static const struct intel_device_info chv_info = {
> .has_reset_engine = 1,
> .has_snoop = true,
> .has_coherent_ggtt = false,
> - .display.mmio_offset = VLV_DISPLAY_BASE,
> - CHV_PIPE_OFFSETS,
> - CHV_CURSOR_OFFSETS,
> - CHV_COLORS,
> GEN_DEFAULT_PAGE_SIZES,
> GEN_DEFAULT_REGIONS,
> LEGACY_CACHELEVEL,
> @@ -714,12 +838,22 @@ static const struct intel_device_info chv_info = {
> GEN9_DEFAULT_PAGE_SIZES, \
> .__runtime.has_dmc = 1, \
> .has_gt_uc = 1, \
> - .__runtime.has_hdcp = 1, \
> - .display.has_ipc = 1, \
> - .display.has_psr = 1, \
> - .display.has_psr_hw_tracking = 1, \
> - .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
> - .display.dbuf.slice_mask = BIT(DBUF_S1)
> + .__runtime.has_hdcp = 1
> +
> +static const struct intel_display_device_info skl_display = {
> + .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
> + .dbuf.slice_mask = BIT(DBUF_S1),
> + .has_ddi = 1,
> + .has_dp_mst = 1,
> + .has_fpga_dbg = 1,
> + .has_hotplug = 1,
> + .has_ipc = 1,
> + .has_psr = 1,
> + .has_psr_hw_tracking = 1,
> + HSW_PIPE_OFFSETS,
> + IVB_CURSOR_OFFSETS,
> + IVB_COLORS,
> +};
>
> #define SKL_PLATFORM \
> GEN9_FEATURES, \
> @@ -727,11 +861,13 @@ static const struct intel_device_info chv_info = {
>
> static const struct intel_device_info skl_gt1_info = {
> SKL_PLATFORM,
> + .display = &skl_display,
> .gt = 1,
> };
>
> static const struct intel_device_info skl_gt2_info = {
> SKL_PLATFORM,
> + .display = &skl_display,
> .gt = 2,
> };
>
> @@ -743,19 +879,19 @@ static const struct intel_device_info skl_gt2_info = {
>
> static const struct intel_device_info skl_gt3_info = {
> SKL_GT3_PLUS_PLATFORM,
> + .display = &skl_display,
> .gt = 3,
> };
>
> static const struct intel_device_info skl_gt4_info = {
> SKL_GT3_PLUS_PLATFORM,
> + .display = &skl_display,
> .gt = 4,
> };
>
> #define GEN9_LP_FEATURES \
> GEN(9), \
> .is_lp = 1, \
> - .display.dbuf.slice_mask = BIT(DBUF_S1), \
> - .display.has_hotplug = 1, \
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
> .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> @@ -763,17 +899,12 @@ static const struct intel_device_info skl_gt4_info = {
> BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
> .has_3d_pipeline = 1, \
> .has_64bit_reloc = 1, \
> - .display.has_ddi = 1, \
> - .display.has_fpga_dbg = 1, \
> .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
> .__runtime.has_hdcp = 1, \
> - .display.has_psr = 1, \
> - .display.has_psr_hw_tracking = 1, \
> .has_runtime_pm = 1, \
> .__runtime.has_dmc = 1, \
> .has_rc6 = 1, \
> .has_rps = true, \
> - .display.has_dp_mst = 1, \
> .has_logical_ring_contexts = 1, \
> .has_gt_uc = 1, \
> .dma_mask_size = 39, \
> @@ -782,27 +913,46 @@ static const struct intel_device_info skl_gt4_info = {
> .has_reset_engine = 1, \
> .has_snoop = true, \
> .has_coherent_ggtt = false, \
> - .display.has_ipc = 1, \
> .max_pat_index = 3, \
> - HSW_PIPE_OFFSETS, \
> - IVB_CURSOR_OFFSETS, \
> - IVB_COLORS, \
> GEN9_DEFAULT_PAGE_SIZES, \
> GEN_DEFAULT_REGIONS, \
> LEGACY_CACHELEVEL
>
> +#define GEN9_LP_DISPLAY \
> + .dbuf.slice_mask = BIT(DBUF_S1), \
> + .has_dp_mst = 1, \
> + .has_ddi = 1, \
> + .has_fpga_dbg = 1, \
> + .has_hotplug = 1, \
> + .has_ipc = 1, \
> + .has_psr = 1, \
> + .has_psr_hw_tracking = 1, \
> + HSW_PIPE_OFFSETS, \
> + IVB_CURSOR_OFFSETS, \
> + IVB_COLORS
> +
> +static const struct intel_display_device_info bxt_display = {
> + GEN9_LP_DISPLAY,
> + .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
> +};
> +
> static const struct intel_device_info bxt_info = {
> GEN9_LP_FEATURES,
> PLATFORM(INTEL_BROXTON),
> - .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
> + .display = &bxt_display,
> +};
> +
> +static const struct intel_display_device_info glk_display = {
> + GEN9_LP_DISPLAY,
> + .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
> + GLK_COLORS,
> };
>
> static const struct intel_device_info glk_info = {
> GEN9_LP_FEATURES,
> PLATFORM(INTEL_GEMINILAKE),
> .__runtime.display.ip.ver = 10,
> - .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
> - GLK_COLORS,
> + .display = &glk_display,
> };
>
> #define KBL_PLATFORM \
> @@ -811,16 +961,19 @@ static const struct intel_device_info glk_info = {
>
> static const struct intel_device_info kbl_gt1_info = {
> KBL_PLATFORM,
> + .display = &skl_display,
> .gt = 1,
> };
>
> static const struct intel_device_info kbl_gt2_info = {
> KBL_PLATFORM,
> + .display = &skl_display,
> .gt = 2,
> };
>
> static const struct intel_device_info kbl_gt3_info = {
> KBL_PLATFORM,
> + .display = &skl_display,
> .gt = 3,
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> @@ -832,16 +985,19 @@ static const struct intel_device_info kbl_gt3_info = {
>
> static const struct intel_device_info cfl_gt1_info = {
> CFL_PLATFORM,
> + .display = &skl_display,
> .gt = 1,
> };
>
> static const struct intel_device_info cfl_gt2_info = {
> CFL_PLATFORM,
> + .display = &skl_display,
> .gt = 2,
> };
>
> static const struct intel_device_info cfl_gt3_info = {
> CFL_PLATFORM,
> + .display = &skl_display,
> .gt = 3,
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> @@ -853,11 +1009,13 @@ static const struct intel_device_info cfl_gt3_info = {
>
> static const struct intel_device_info cml_gt1_info = {
> CML_PLATFORM,
> + .display = &skl_display,
> .gt = 1,
> };
>
> static const struct intel_device_info cml_gt2_info = {
> CML_PLATFORM,
> + .display = &skl_display,
> .gt = 2,
> };
>
> @@ -869,39 +1027,51 @@ static const struct intel_device_info cml_gt2_info = {
> #define GEN11_FEATURES \
> GEN9_FEATURES, \
> GEN11_DEFAULT_PAGE_SIZES, \
> - .display.abox_mask = BIT(0), \
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
> BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> - .display.pipe_offsets = { \
> - [TRANSCODER_A] = PIPE_A_OFFSET, \
> - [TRANSCODER_B] = PIPE_B_OFFSET, \
> - [TRANSCODER_C] = PIPE_C_OFFSET, \
> - [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
> - [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> - [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> - }, \
> - .display.trans_offsets = { \
> - [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> - [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> - [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> - [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
> - [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> - [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> - }, \
> GEN(11), \
> - ICL_COLORS, \
> - .display.dbuf.size = 2048, \
> - .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
> .__runtime.has_dsc = 1, \
> .has_coherent_ggtt = false, \
> .has_logical_ring_elsq = 1
>
> +static const struct intel_display_device_info gen11_display = {
> + .abox_mask = BIT(0),
> + .dbuf.size = 2048,
> + .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2),
> + .has_ddi = 1,
> + .has_dp_mst = 1,
> + .has_fpga_dbg = 1,
> + .has_hotplug = 1,
> + .has_ipc = 1,
> + .has_psr = 1,
> + .has_psr_hw_tracking = 1,
> + .pipe_offsets = {
> + [TRANSCODER_A] = PIPE_A_OFFSET,
> + [TRANSCODER_B] = PIPE_B_OFFSET,
> + [TRANSCODER_C] = PIPE_C_OFFSET,
> + [TRANSCODER_EDP] = PIPE_EDP_OFFSET,
> + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
> + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
> + },
> + .trans_offsets = {
> + [TRANSCODER_A] = TRANSCODER_A_OFFSET,
> + [TRANSCODER_B] = TRANSCODER_B_OFFSET,
> + [TRANSCODER_C] = TRANSCODER_C_OFFSET,
> + [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET,
> + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
> + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
> + },
> + IVB_CURSOR_OFFSETS,
> + ICL_COLORS,
> +};
> +
> static const struct intel_device_info icl_info = {
> GEN11_FEATURES,
> PLATFORM(INTEL_ICELAKE),
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> + .display = &gen11_display,
> };
>
> static const struct intel_device_info ehl_info = {
> @@ -909,6 +1079,7 @@ static const struct intel_device_info ehl_info = {
> PLATFORM(INTEL_ELKHARTLAKE),
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> .__runtime.ppgtt_size = 36,
> + .display = &gen11_display,
> };
>
> static const struct intel_device_info jsl_info = {
> @@ -916,17 +1087,34 @@ static const struct intel_device_info jsl_info = {
> PLATFORM(INTEL_JASPERLAKE),
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> .__runtime.ppgtt_size = 36,
> + .display = &gen11_display,
> };
>
> #define GEN12_FEATURES \
> GEN11_FEATURES, \
> GEN(12), \
> - .display.abox_mask = GENMASK(2, 1), \
> .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
> BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> - .display.pipe_offsets = { \
> + TGL_CACHELEVEL, \
> + .has_global_mocs = 1, \
> + .has_pxp = 1, \
> + .max_pat_index = 3
> +
> +#define XE_D_DISPLAY \
> + .abox_mask = GENMASK(2, 1), \
> + .dbuf.size = 2048, \
> + .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
> + .has_ddi = 1, \
> + .has_dp_mst = 1, \
> + .has_dsb = 1, \
> + .has_fpga_dbg = 1, \
> + .has_hotplug = 1, \
> + .has_ipc = 1, \
> + .has_psr = 1, \
> + .has_psr_hw_tracking = 1, \
> + .pipe_offsets = { \
> [TRANSCODER_A] = PIPE_A_OFFSET, \
> [TRANSCODER_B] = PIPE_B_OFFSET, \
> [TRANSCODER_C] = PIPE_C_OFFSET, \
> @@ -934,7 +1122,7 @@ static const struct intel_device_info jsl_info = {
> [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> }, \
> - .display.trans_offsets = { \
> + .trans_offsets = { \
> [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> @@ -943,30 +1131,36 @@ static const struct intel_device_info jsl_info = {
> [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> }, \
> TGL_CURSOR_OFFSETS, \
> - TGL_CACHELEVEL, \
> - .has_global_mocs = 1, \
> - .has_pxp = 1, \
> - .display.has_dsb = 1, \
> - .max_pat_index = 3
> + ICL_COLORS
> +
> +static const struct intel_display_device_info tgl_display = {
> + XE_D_DISPLAY,
> +};
>
> static const struct intel_device_info tgl_info = {
> GEN12_FEATURES,
> PLATFORM(INTEL_TIGERLAKE),
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> + .display = &tgl_display,
> +};
> +
> +static const struct intel_display_device_info rkl_display = {
> + XE_D_DISPLAY,
> + .abox_mask = BIT(0),
> + .has_hti = 1,
> + .has_psr_hw_tracking = 0,
> };
>
> static const struct intel_device_info rkl_info = {
> GEN12_FEATURES,
> PLATFORM(INTEL_ROCKETLAKE),
> - .display.abox_mask = BIT(0),
> .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> BIT(TRANSCODER_C),
> - .display.has_hti = 1,
> - .display.has_psr_hw_tracking = 0,
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
> + .display = &rkl_display,
> };
>
> #define DGFX_FEATURES \
> @@ -989,43 +1183,43 @@ static const struct intel_device_info dg1_info = {
> BIT(VCS0) | BIT(VCS2),
> /* Wa_16011227922 */
> .__runtime.ppgtt_size = 47,
> + .display = &tgl_display,
> +};
> +
> +static const struct intel_display_device_info adl_s_display = {
> + XE_D_DISPLAY,
> + .has_hti = 1,
> + .has_psr_hw_tracking = 0,
> };
>
> static const struct intel_device_info adl_s_info = {
> GEN12_FEATURES,
> PLATFORM(INTEL_ALDERLAKE_S),
> .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> - .display.has_hti = 1,
> - .display.has_psr_hw_tracking = 0,
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> .dma_mask_size = 39,
> + .display = &adl_s_display,
> };
>
> #define XE_LPD_FEATURES \
> - .display.abox_mask = GENMASK(1, 0), \
> - .display.color = { \
> + .abox_mask = GENMASK(1, 0), \
> + .color = { \
> .degamma_lut_size = 129, .gamma_lut_size = 1024, \
> .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> - DRM_COLOR_LUT_EQUAL_CHANNELS, \
> + DRM_COLOR_LUT_EQUAL_CHANNELS, \
> }, \
> - .display.dbuf.size = 4096, \
> - .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
> + .dbuf.size = 4096, \
> + .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
> BIT(DBUF_S4), \
> - .display.has_ddi = 1, \
> - .__runtime.has_dmc = 1, \
> - .display.has_dp_mst = 1, \
> - .display.has_dsb = 1, \
> - .__runtime.has_dsc = 1, \
> - .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
> - .display.has_fpga_dbg = 1, \
> - .__runtime.has_hdcp = 1, \
> - .display.has_hotplug = 1, \
> - .display.has_ipc = 1, \
> - .display.has_psr = 1, \
> - .__runtime.display.ip.ver = 13, \
> - .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> - .display.pipe_offsets = { \
> + .has_ddi = 1, \
> + .has_dp_mst = 1, \
> + .has_dsb = 1, \
> + .has_fpga_dbg = 1, \
> + .has_hotplug = 1, \
> + .has_ipc = 1, \
> + .has_psr = 1, \
> + .pipe_offsets = { \
> [TRANSCODER_A] = PIPE_A_OFFSET, \
> [TRANSCODER_B] = PIPE_B_OFFSET, \
> [TRANSCODER_C] = PIPE_C_OFFSET, \
> @@ -1033,7 +1227,7 @@ static const struct intel_device_info adl_s_info = {
> [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> }, \
> - .display.trans_offsets = { \
> + .trans_offsets = { \
> [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> @@ -1043,18 +1237,31 @@ static const struct intel_device_info adl_s_info = {
> }, \
> TGL_CURSOR_OFFSETS
>
> +#define XE_LPD_RUNTIME \
> + .__runtime.has_dmc = 1, \
> + .__runtime.has_dsc = 1, \
> + .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
> + .__runtime.has_hdcp = 1, \
> + .__runtime.display.ip.ver = 13, \
> + .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
> +
> +static const struct intel_display_device_info xe_lpd_display = {
> + XE_LPD_FEATURES,
> + .has_cdclk_crawl = 1,
> + .has_psr_hw_tracking = 0,
> +};
> +
> static const struct intel_device_info adl_p_info = {
> GEN12_FEATURES,
> - XE_LPD_FEATURES,
> + XE_LPD_RUNTIME,
> PLATFORM(INTEL_ALDERLAKE_P),
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
> BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> - .display.has_cdclk_crawl = 1,
> - .display.has_psr_hw_tracking = 0,
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> .__runtime.ppgtt_size = 48,
> + .display = &xe_lpd_display,
> .dma_mask_size = 39,
> };
>
> @@ -1125,18 +1332,23 @@ static const struct intel_device_info xehpsdv_info = {
> .has_guc_deprivilege = 1, \
> .has_heci_pxp = 1, \
> .has_media_ratio_mode = 1, \
> - .display.has_cdclk_squash = 1, \
> .__runtime.platform_engine_mask = \
> BIT(RCS0) | BIT(BCS0) | \
> BIT(VECS0) | BIT(VECS1) | \
> BIT(VCS0) | BIT(VCS2) | \
> BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
>
> +static const struct intel_display_device_info xe_hpd_display = {
> + XE_LPD_FEATURES,
> + .has_cdclk_squash = 1,
> +};
> +
> static const struct intel_device_info dg2_info = {
> DG2_FEATURES,
> - XE_LPD_FEATURES,
> + XE_LPD_RUNTIME,
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> + .display = &xe_hpd_display,
> };
>
> static const struct intel_device_info ats_m_info = {
> @@ -1174,11 +1386,9 @@ static const struct intel_device_info pvc_info = {
> PVC_CACHELEVEL,
> };
>
> -#define XE_LPDP_FEATURES \
> - XE_LPD_FEATURES, \
> +#define XE_LPDP_RUNTIME \
> + XE_LPD_RUNTIME, \
> .__runtime.display.ip.ver = 14, \
> - .display.has_cdclk_crawl = 1, \
> - .display.has_cdclk_squash = 1, \
> .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
>
> static const struct intel_gt_definition xelpmp_extra_gt[] = {
> @@ -1191,9 +1401,15 @@ static const struct intel_gt_definition xelpmp_extra_gt[] = {
> {}
> };
>
> +static const struct intel_display_device_info xe_lpdp_display = {
> + XE_LPD_FEATURES,
> + .has_cdclk_crawl = 1,
> + .has_cdclk_squash = 1,
> +};
> +
> static const struct intel_device_info mtl_info = {
> XE_HP_FEATURES,
> - XE_LPDP_FEATURES,
> + XE_LPDP_RUNTIME,
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> /*
> @@ -1204,6 +1420,7 @@ static const struct intel_device_info mtl_info = {
> .__runtime.graphics.ip.rel = 70,
> .__runtime.media.ip.ver = 13,
> PLATFORM(INTEL_METEORLAKE),
> + .display = &xe_lpdp_display,
> .extra_gt_list = xelpmp_extra_gt,
> .has_flat_ccs = 0,
> .has_gmd_id = 1,
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 4e23be2995bf..d0bf626d0360 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -138,7 +138,7 @@ void intel_device_info_print(const struct intel_device_info *info,
>
> drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
>
> -#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name))
> +#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display->name))
> DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
> #undef PRINT_FLAG
>
> @@ -388,6 +388,8 @@ mkwrite_device_info(struct drm_i915_private *i915)
> return (struct intel_device_info *)INTEL_INFO(i915);
> }
>
> +static const struct intel_display_device_info no_display = { 0 };
> +
> /**
> * intel_device_info_runtime_init - initialize runtime info
> * @dev_priv: the i915 device
> @@ -538,7 +540,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv)) {
> dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
> DRIVER_ATOMIC);
> - memset(&info->display, 0, sizeof(info->display));
> + info->display = &no_display;
>
> runtime->cpu_transcoder_mask = 0;
> memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 96f6bdb04b1b..f212e02e6582 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -259,7 +259,7 @@ struct intel_device_info {
> DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
> #undef DEFINE_FLAG
>
> - struct intel_display_device_info display;
> + const struct intel_display_device_info *display;
>
> /*
> * Initial runtime info. Do not access outside of i915_driver_create().
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [Intel-xe] [PATCH v2 2/6] drm/i915: Convert INTEL_INFO()->display to a pointer
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 2/6] drm/i915: Convert INTEL_INFO()->display to a pointer Matt Roper
2023-05-23 7:45 ` Andrzej Hajda
@ 2023-05-23 12:47 ` Jani Nikula
1 sibling, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2023-05-23 12:47 UTC (permalink / raw)
To: Matt Roper, intel-gfx
Cc: Matt Roper, Lucas De Marchi, intel-xe, Andrzej Hajda
On Mon, 22 May 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 4e23be2995bf..d0bf626d0360 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -138,7 +138,7 @@ void intel_device_info_print(const struct intel_device_info *info,
>
> drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
>
> -#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name))
> +#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display->name))
> DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
> #undef PRINT_FLAG
>
> @@ -388,6 +388,8 @@ mkwrite_device_info(struct drm_i915_private *i915)
> return (struct intel_device_info *)INTEL_INFO(i915);
> }
>
> +static const struct intel_display_device_info no_display = { 0 };
I think {} is preferred. Can be fixed afterwards if there's no other
reason to do a respin.
> +
> /**
> * intel_device_info_runtime_init - initialize runtime info
> * @dev_priv: the i915 device
> @@ -538,7 +540,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv)) {
> dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
> DRIVER_ATOMIC);
> - memset(&info->display, 0, sizeof(info->display));
> + info->display = &no_display;
Nice!
Acked-by: Jani Nikula <jani.nikula@intel.com>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v2 3/6] drm/i915/display: Move display runtime info to display structure
2023-05-22 20:23 [Intel-gfx] [PATCH v2 0/6] i915: Move display identification/probing under display/ Matt Roper
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 1/6] drm/i915/display: Move display device info to header " Matt Roper
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 2/6] drm/i915: Convert INTEL_INFO()->display to a pointer Matt Roper
@ 2023-05-22 20:23 ` Matt Roper
2023-05-23 7:50 ` Andrzej Hajda
2023-05-23 12:45 ` Jani Nikula
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 4/6] drm/i915/display: Make display responsible for probing its own IP Matt Roper
` (7 subsequent siblings)
10 siblings, 2 replies; 22+ messages in thread
From: Matt Roper @ 2023-05-22 20:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, intel-xe, Andrzej Hajda
Move the runtime info specific to display into display-specific
structures as has already been done with the constant display info.
v2:
- Rename __runtime to __runtime_defaults for more clarity on the
purpose. (Andrzej)
- Move introduction of DISPLAY_INFO() to previous patch. (Andrzej)
- Drop NO_DISPLAY macro. (Andrzej)
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 8 +-
.../drm/i915/display/intel_display_device.h | 23 ++
drivers/gpu/drm/i915/display/intel_fbc.c | 6 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
.../drm/i915/display/skl_universal_plane.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 16 +-
drivers/gpu/drm/i915/i915_pci.c | 252 +++++++++++-------
drivers/gpu/drm/i915/intel_device_info.c | 101 +++----
drivers/gpu/drm/i915/intel_device_info.h | 18 --
drivers/gpu/drm/i915/intel_step.c | 8 +-
13 files changed, 267 insertions(+), 175 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 93c3226b98c9..182c6dd64f47 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -306,7 +306,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
return PTR_ERR(crtc);
crtc->pipe = pipe;
- crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
+ crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe];
if (DISPLAY_VER(dev_priv) >= 9)
primary = skl_universal_plane_create(dev_priv, pipe,
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 3864da5f5c17..b342fad180ca 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -814,7 +814,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
DRM_MODE_ROTATE_0 |
DRM_MODE_ROTATE_180);
- zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
+ zpos = DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
if (DISPLAY_VER(dev_priv) >= 12)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0490c6412ab5..e477e16ea58e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3366,7 +3366,7 @@ static u8 bigjoiner_pipes(struct drm_i915_private *i915)
else
pipes = 0;
- return pipes & RUNTIME_INFO(i915)->pipe_mask;
+ return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
}
static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index aa3a21ccd7fe..c744c021af23 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -105,7 +105,7 @@ enum i9xx_plane_id {
};
#define plane_name(p) ((p) + 'A')
-#define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
+#define sprite_name(p, s) ((p) * DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
#define for_each_plane_id_on_crtc(__crtc, __p) \
for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
@@ -221,7 +221,7 @@ enum phy_fia {
#define for_each_pipe(__dev_priv, __p) \
for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
- for_each_if(RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
+ for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
#define for_each_pipe_masked(__dev_priv, __p, __mask) \
for_each_pipe(__dev_priv, __p) \
@@ -229,7 +229,7 @@ enum phy_fia {
#define for_each_cpu_transcoder(__dev_priv, __t) \
for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
- for_each_if (RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
+ for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
for_each_cpu_transcoder(__dev_priv, __t) \
@@ -237,7 +237,7 @@ enum phy_fia {
#define for_each_sprite(__dev_priv, __p, __s) \
for ((__s) = 0; \
- (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
+ (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
(__s)++)
#define for_each_port(__port) \
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index c689d582dbf1..613607fad5af 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -29,7 +29,30 @@
func(overlay_needs_physical); \
func(supports_tv);
+struct intel_display_runtime_info {
+ struct {
+ u16 ver;
+ u16 rel;
+ u16 step;
+ } ip;
+
+ u8 pipe_mask;
+ u8 cpu_transcoder_mask;
+
+ u8 num_sprites[I915_MAX_PIPES];
+ u8 num_scalers[I915_MAX_PIPES];
+
+ u8 fbc_mask;
+
+ bool has_hdcp;
+ bool has_dmc;
+ bool has_dsc;
+};
+
struct intel_display_device_info {
+ /* Initial runtime info. */
+ const struct intel_display_runtime_info __runtime_defaults;
+
u8 abox_mask;
struct {
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 11bb8cf9c9d0..1966f9396201 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -56,7 +56,7 @@
#define for_each_fbc_id(__dev_priv, __fbc_id) \
for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
- for_each_if(RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
+ for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
#define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
for_each_fbc_id((__dev_priv), (__fbc_id)) \
@@ -1708,10 +1708,10 @@ void intel_fbc_init(struct drm_i915_private *i915)
enum intel_fbc_id fbc_id;
if (!drm_mm_initialized(&i915->mm.stolen))
- RUNTIME_INFO(i915)->fbc_mask = 0;
+ DISPLAY_RUNTIME_INFO(i915)->fbc_mask = 0;
if (need_fbc_vtd_wa(i915))
- RUNTIME_INFO(i915)->fbc_mask = 0;
+ DISPLAY_RUNTIME_INFO(i915)->fbc_mask = 0;
i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index dd539106ee5a..1f96d1fa68e0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1103,7 +1103,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
{
- return RUNTIME_INFO(dev_priv)->has_hdcp &&
+ return DISPLAY_RUNTIME_INFO(dev_priv)->has_hdcp &&
(DISPLAY_VER(dev_priv) >= 12 || port < PORT_E);
}
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 110401aab038..36070d86550f 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1944,7 +1944,7 @@ static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe)
static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
enum intel_fbc_id fbc_id, enum plane_id plane_id)
{
- if ((RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0)
+ if ((DISPLAY_RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0)
return false;
return plane_id == PLANE_PRIMARY;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9612c2ac4b00..7a8a12d12790 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -205,6 +205,7 @@ struct drm_i915_private {
const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
+ struct intel_display_runtime_info __display_runtime; /* Access with DISPLAY_RUNTIME_INFO() */
struct intel_driver_caps caps;
struct i915_dsm dsm;
@@ -410,6 +411,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
#define INTEL_INFO(i915) (&(i915)->__info)
#define DISPLAY_INFO(i915) (INTEL_INFO(i915)->display)
#define RUNTIME_INFO(i915) (&(i915)->__runtime)
+#define DISPLAY_RUNTIME_INFO(i915) (&(i915)->__display_runtime)
#define DRIVER_CAPS(i915) (&(i915)->caps)
#define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id)
@@ -428,7 +430,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
#define IS_MEDIA_VER(i915, from, until) \
(MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
-#define DISPLAY_VER(i915) (RUNTIME_INFO(i915)->display.ip.ver)
+#define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver)
#define IS_DISPLAY_VER(i915, from, until) \
(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
@@ -811,7 +813,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
#define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2)
-#define HAS_FBC(i915) (RUNTIME_INFO(i915)->fbc_mask != 0)
+#define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
#define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
#define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13)
@@ -831,7 +833,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_PSR_HW_TRACKING(i915) \
(DISPLAY_INFO(i915)->has_psr_hw_tracking)
#define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12)
-#define HAS_TRANSCODER(i915, trans) ((RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
+#define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
#define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
#define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
@@ -839,9 +841,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
-#define HAS_DMC(i915) (RUNTIME_INFO(i915)->has_dmc)
+#define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc)
#define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb)
-#define HAS_DSC(__i915) (RUNTIME_INFO(__i915)->has_dsc)
+#define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
#define HAS_HECI_PXP(i915) \
@@ -903,9 +905,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \
2 : HAS_L3_DPF(i915))
-#define INTEL_NUM_PIPES(i915) (hweight8(RUNTIME_INFO(i915)->pipe_mask))
+#define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
-#define HAS_DISPLAY(i915) (RUNTIME_INFO(i915)->pipe_mask != 0)
+#define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index dd874a4db604..9c781b703c7b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -41,10 +41,9 @@
#define PLATFORM(x) .platform = (x)
#define GEN(x) \
.__runtime.graphics.ip.ver = (x), \
- .__runtime.media.ip.ver = (x), \
- .__runtime.display.ip.ver = (x)
+ .__runtime.media.ip.ver = (x)
-#define NO_DISPLAY .__runtime.pipe_mask = 0
+static const struct intel_display_device_info no_display = { 0 };
#define I845_PIPE_OFFSETS \
.pipe_offsets = { \
@@ -212,7 +211,12 @@
.has_gmch = 1, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
- I9XX_COLORS
+ I9XX_COLORS, \
+ \
+ .__runtime_defaults.ip.ver = 2, \
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+ .__runtime_defaults.cpu_transcoder_mask = \
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
static const struct intel_display_device_info i830_display = {
I830_DISPLAY,
@@ -221,8 +225,6 @@ static const struct intel_display_device_info i830_display = {
#define I830_FEATURES \
GEN(2), \
.is_mobile = 1, \
- .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.gpu_reset_clobbers_display = true, \
.has_3d_pipeline = 1, \
.hws_needs_physical = 1, \
@@ -242,7 +244,11 @@ static const struct intel_display_device_info i830_display = {
.has_gmch = 1, \
I845_PIPE_OFFSETS, \
I845_CURSOR_OFFSETS, \
- I845_COLORS
+ I845_COLORS, \
+ \
+ .__runtime_defaults.ip.ver = 2, \
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
+ .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
static const struct intel_display_device_info i845_display = {
I845_DISPLAY,
@@ -250,8 +256,6 @@ static const struct intel_display_device_info i845_display = {
#define I845_FEATURES \
GEN(2), \
- .__runtime.pipe_mask = BIT(PIPE_A), \
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \
.has_3d_pipeline = 1, \
.gpu_reset_clobbers_display = true, \
.hws_needs_physical = 1, \
@@ -279,24 +283,26 @@ static const struct intel_device_info i845g_info = {
static const struct intel_display_device_info i85x_display = {
I830_DISPLAY,
+
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
static const struct intel_device_info i85x_info = {
I830_FEATURES,
PLATFORM(INTEL_I85X),
.display = &i85x_display,
- .__runtime.fbc_mask = BIT(INTEL_FBC_A),
};
static const struct intel_display_device_info i865g_display = {
I845_DISPLAY,
+
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
static const struct intel_device_info i865g_info = {
I845_FEATURES,
PLATFORM(INTEL_I865G),
.display = &i865g_display,
- .__runtime.fbc_mask = BIT(INTEL_FBC_A),
};
#define GEN3_DISPLAY \
@@ -304,7 +310,12 @@ static const struct intel_device_info i865g_info = {
.has_overlay = 1, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
- I9XX_COLORS
+ I9XX_COLORS, \
+ \
+ .__runtime_defaults.ip.ver = 3, \
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+ .__runtime_defaults.cpu_transcoder_mask = \
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
static const struct intel_display_device_info i915g_display = {
GEN3_DISPLAY,
@@ -317,6 +328,8 @@ static const struct intel_display_device_info i915gm_display = {
.cursor_needs_physical = 1,
.overlay_needs_physical = 1,
.supports_tv = 1,
+
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
static const struct intel_display_device_info i945g_display = {
@@ -332,6 +345,8 @@ static const struct intel_display_device_info i945gm_display = {
.cursor_needs_physical = 1,
.overlay_needs_physical = 1,
.supports_tv = 1,
+
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
static const struct intel_display_device_info g33_display = {
@@ -341,8 +356,6 @@ static const struct intel_display_device_info g33_display = {
#define GEN3_FEATURES \
GEN(3), \
- .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.gpu_reset_clobbers_display = true, \
.__runtime.platform_engine_mask = BIT(RCS0), \
.has_3d_pipeline = 1, \
@@ -368,7 +381,6 @@ static const struct intel_device_info i915gm_info = {
PLATFORM(INTEL_I915GM),
.display = &i915gm_display,
.is_mobile = 1,
- .__runtime.fbc_mask = BIT(INTEL_FBC_A),
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -386,7 +398,6 @@ static const struct intel_device_info i945gm_info = {
PLATFORM(INTEL_I945GM),
.display = &i945gm_display,
.is_mobile = 1,
- .__runtime.fbc_mask = BIT(INTEL_FBC_A),
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -418,7 +429,12 @@ static const struct intel_device_info pnv_m_info = {
.has_gmch = 1, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
- I9XX_COLORS
+ I9XX_COLORS, \
+ \
+ .__runtime_defaults.ip.ver = 4, \
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+ .__runtime_defaults.cpu_transcoder_mask = \
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
static const struct intel_display_device_info i965g_display = {
GEN4_DISPLAY,
@@ -429,6 +445,8 @@ static const struct intel_display_device_info i965gm_display = {
GEN4_DISPLAY,
.has_overlay = 1,
.supports_tv = 1,
+
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
static const struct intel_display_device_info g45_display = {
@@ -438,12 +456,12 @@ static const struct intel_display_device_info g45_display = {
static const struct intel_display_device_info gm45_display = {
GEN4_DISPLAY,
.supports_tv = 1,
+
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
#define GEN4_FEATURES \
GEN(4), \
- .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.gpu_reset_clobbers_display = true, \
.__runtime.platform_engine_mask = BIT(RCS0), \
.has_3d_pipeline = 1, \
@@ -468,7 +486,6 @@ static const struct intel_device_info i965gm_info = {
PLATFORM(INTEL_I965GM),
.display = &i965gm_display,
.is_mobile = 1,
- .__runtime.fbc_mask = BIT(INTEL_FBC_A),
.hws_needs_physical = 1,
.has_snoop = false,
};
@@ -485,7 +502,6 @@ static const struct intel_device_info gm45_info = {
GEN4_FEATURES,
PLATFORM(INTEL_GM45),
.is_mobile = 1,
- .__runtime.fbc_mask = BIT(INTEL_FBC_A),
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
.display = &gm45_display,
.gpu_reset_clobbers_display = false,
@@ -493,8 +509,6 @@ static const struct intel_device_info gm45_info = {
#define GEN5_FEATURES \
GEN(5), \
- .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
.has_3d_pipeline = 1, \
.has_snoop = true, \
@@ -511,7 +525,12 @@ static const struct intel_device_info gm45_info = {
.has_hotplug = 1, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
- ILK_COLORS
+ ILK_COLORS, \
+ \
+ .__runtime_defaults.ip.ver = 5, \
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+ .__runtime_defaults.cpu_transcoder_mask = \
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
static const struct intel_display_device_info ilk_d_display = {
ILK_DISPLAY,
@@ -525,6 +544,8 @@ static const struct intel_device_info ilk_d_info = {
static const struct intel_display_device_info ilk_m_display = {
ILK_DISPLAY,
+
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
static const struct intel_device_info ilk_m_info = {
@@ -533,14 +554,10 @@ static const struct intel_device_info ilk_m_info = {
.display = &ilk_m_display,
.is_mobile = 1,
.has_rps = true,
- .__runtime.fbc_mask = BIT(INTEL_FBC_A),
};
#define GEN6_FEATURES \
GEN(6), \
- .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
- .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_3d_pipeline = 1, \
.has_coherent_ggtt = true, \
@@ -562,6 +579,12 @@ static const struct intel_display_device_info snb_display = {
I9XX_PIPE_OFFSETS,
I9XX_CURSOR_OFFSETS,
ILK_COLORS,
+
+ .__runtime_defaults.ip.ver = 6,
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
#define SNB_D_PLATFORM \
@@ -600,9 +623,6 @@ static const struct intel_device_info snb_m_gt2_info = {
#define GEN7_FEATURES \
GEN(7), \
- .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
- .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_3d_pipeline = 1, \
.has_coherent_ggtt = true, \
@@ -629,6 +649,12 @@ static const struct intel_display_device_info ivb_display = {
IVB_PIPE_OFFSETS,
IVB_CURSOR_OFFSETS,
IVB_COLORS,
+
+ .__runtime_defaults.ip.ver = 7,
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
static const struct intel_device_info ivb_d_gt1_info = {
@@ -664,7 +690,7 @@ static const struct intel_device_info ivb_m_gt2_info = {
static const struct intel_device_info ivb_q_info = {
GEN7_FEATURES,
PLATFORM(INTEL_IVYBRIDGE),
- NO_DISPLAY,
+ .display = &no_display,
.gt = 2,
.has_l3_dpf = 1,
};
@@ -676,14 +702,17 @@ static const struct intel_display_device_info vlv_display = {
I9XX_PIPE_OFFSETS,
I9XX_CURSOR_OFFSETS,
I9XX_COLORS,
+
+ .__runtime_defaults.ip.ver = 7,
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
};
static const struct intel_device_info vlv_info = {
PLATFORM(INTEL_VALLEYVIEW),
GEN(7),
.is_lp = 1,
- .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
.display = &vlv_display,
.has_runtime_pm = 1,
.has_rc6 = 1,
@@ -704,8 +733,6 @@ static const struct intel_device_info vlv_info = {
#define G75_FEATURES \
GEN7_FEATURES, \
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
- BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
.has_rc6p = 0 /* RC6p removed-by HSW */, \
.has_runtime_pm = 1
@@ -722,6 +749,13 @@ static const struct intel_display_device_info hsw_display = {
HSW_PIPE_OFFSETS,
IVB_CURSOR_OFFSETS,
IVB_COLORS,
+
+ .__runtime_defaults.ip.ver = 7,
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
static const struct intel_device_info hsw_gt1_info = {
@@ -759,6 +793,13 @@ static const struct intel_display_device_info bdw_display = {
HSW_PIPE_OFFSETS,
IVB_CURSOR_OFFSETS,
IVB_COLORS,
+
+ .__runtime_defaults.ip.ver = 8,
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
#define BDW_PLATFORM \
@@ -801,13 +842,16 @@ static const struct intel_display_device_info chv_display = {
CHV_PIPE_OFFSETS,
CHV_CURSOR_OFFSETS,
CHV_COLORS,
+
+ .__runtime_defaults.ip.ver = 8,
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
};
static const struct intel_device_info chv_info = {
PLATFORM(INTEL_CHERRYVIEW),
GEN(8),
- .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
.display = &chv_display,
.is_lp = 1,
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
@@ -836,9 +880,7 @@ static const struct intel_device_info chv_info = {
GEN8_FEATURES, \
GEN(9), \
GEN9_DEFAULT_PAGE_SIZES, \
- .__runtime.has_dmc = 1, \
- .has_gt_uc = 1, \
- .__runtime.has_hdcp = 1
+ .has_gt_uc = 1
static const struct intel_display_device_info skl_display = {
.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
@@ -853,6 +895,15 @@ static const struct intel_display_device_info skl_display = {
HSW_PIPE_OFFSETS,
IVB_CURSOR_OFFSETS,
IVB_COLORS,
+
+ .__runtime_defaults.ip.ver = 9,
+ .__runtime_defaults.has_dmc = 1,
+ .__runtime_defaults.has_hdcp = 1,
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
#define SKL_PLATFORM \
@@ -893,16 +944,9 @@ static const struct intel_device_info skl_gt4_info = {
GEN(9), \
.is_lp = 1, \
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
- .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
- BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
- BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
.has_3d_pipeline = 1, \
.has_64bit_reloc = 1, \
- .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
- .__runtime.has_hdcp = 1, \
.has_runtime_pm = 1, \
- .__runtime.has_dmc = 1, \
.has_rc6 = 1, \
.has_rps = true, \
.has_logical_ring_contexts = 1, \
@@ -929,11 +973,22 @@ static const struct intel_device_info skl_gt4_info = {
.has_psr_hw_tracking = 1, \
HSW_PIPE_OFFSETS, \
IVB_CURSOR_OFFSETS, \
- IVB_COLORS
+ IVB_COLORS, \
+ \
+ .__runtime_defaults.has_dmc = 1, \
+ .__runtime_defaults.has_hdcp = 1, \
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
+ .__runtime_defaults.cpu_transcoder_mask = \
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
+ BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C)
static const struct intel_display_device_info bxt_display = {
GEN9_LP_DISPLAY,
.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
+
+ .__runtime_defaults.ip.ver = 9,
};
static const struct intel_device_info bxt_info = {
@@ -946,12 +1001,13 @@ static const struct intel_display_device_info glk_display = {
GEN9_LP_DISPLAY,
.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
GLK_COLORS,
+
+ .__runtime_defaults.ip.ver = 10,
};
static const struct intel_device_info glk_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_GEMINILAKE),
- .__runtime.display.ip.ver = 10,
.display = &glk_display,
};
@@ -1027,11 +1083,7 @@ static const struct intel_device_info cml_gt2_info = {
#define GEN11_FEATURES \
GEN9_FEATURES, \
GEN11_DEFAULT_PAGE_SIZES, \
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
- BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
- BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
GEN(11), \
- .__runtime.has_dsc = 1, \
.has_coherent_ggtt = false, \
.has_logical_ring_elsq = 1
@@ -1064,6 +1116,17 @@ static const struct intel_display_device_info gen11_display = {
},
IVB_CURSOR_OFFSETS,
ICL_COLORS,
+
+ .__runtime_defaults.ip.ver = 11,
+ .__runtime_defaults.has_dmc = 1,
+ .__runtime_defaults.has_dsc = 1, \
+ .__runtime_defaults.has_hdcp = 1,
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) |
+ BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
static const struct intel_device_info icl_info = {
@@ -1093,10 +1156,6 @@ static const struct intel_device_info jsl_info = {
#define GEN12_FEATURES \
GEN11_FEATURES, \
GEN(12), \
- .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
- BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
TGL_CACHELEVEL, \
.has_global_mocs = 1, \
.has_pxp = 1, \
@@ -1131,7 +1190,19 @@ static const struct intel_device_info jsl_info = {
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
TGL_CURSOR_OFFSETS, \
- ICL_COLORS
+ ICL_COLORS, \
+ \
+ .__runtime_defaults.ip.ver = 12, \
+ .__runtime_defaults.has_dmc = 1, \
+ .__runtime_defaults.has_dsc = 1, \
+ .__runtime_defaults.has_hdcp = 1, \
+ .__runtime_defaults.pipe_mask = \
+ BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+ .__runtime_defaults.cpu_transcoder_mask = \
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
+ BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
static const struct intel_display_device_info tgl_display = {
XE_D_DISPLAY,
@@ -1150,14 +1221,15 @@ static const struct intel_display_device_info rkl_display = {
.abox_mask = BIT(0),
.has_hti = 1,
.has_psr_hw_tracking = 0,
+
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
};
static const struct intel_device_info rkl_info = {
GEN12_FEATURES,
PLATFORM(INTEL_ROCKETLAKE),
- .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C),
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
.display = &rkl_display,
@@ -1176,7 +1248,6 @@ static const struct intel_device_info dg1_info = {
DGFX_FEATURES,
.__runtime.graphics.ip.rel = 10,
PLATFORM(INTEL_DG1),
- .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
.require_force_probe = 1,
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
@@ -1195,7 +1266,6 @@ static const struct intel_display_device_info adl_s_display = {
static const struct intel_device_info adl_s_info = {
GEN12_FEATURES,
PLATFORM(INTEL_ALDERLAKE_S),
- .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.dma_mask_size = 39,
@@ -1235,29 +1305,30 @@ static const struct intel_device_info adl_s_info = {
[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
- TGL_CURSOR_OFFSETS
-
-#define XE_LPD_RUNTIME \
- .__runtime.has_dmc = 1, \
- .__runtime.has_dsc = 1, \
- .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
- .__runtime.has_hdcp = 1, \
- .__runtime.display.ip.ver = 13, \
- .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
+ TGL_CURSOR_OFFSETS, \
+ \
+ .__runtime_defaults.ip.ver = 13, \
+ .__runtime_defaults.has_dmc = 1, \
+ .__runtime_defaults.has_dsc = 1, \
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
+ .__runtime_defaults.has_hdcp = 1, \
+ .__runtime_defaults.pipe_mask = \
+ BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
static const struct intel_display_device_info xe_lpd_display = {
XE_LPD_FEATURES,
.has_cdclk_crawl = 1,
.has_psr_hw_tracking = 0,
+
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
+ BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
};
static const struct intel_device_info adl_p_info = {
GEN12_FEATURES,
- XE_LPD_RUNTIME,
PLATFORM(INTEL_ALDERLAKE_P),
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
- BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.__runtime.ppgtt_size = 48,
@@ -1309,7 +1380,7 @@ static const struct intel_device_info xehpsdv_info = {
XE_HPM_FEATURES,
DGFX_FEATURES,
PLATFORM(INTEL_XEHPSDV),
- NO_DISPLAY,
+ .display = &no_display,
.has_64k_pages = 1,
.has_media_ratio_mode = 1,
.__runtime.platform_engine_mask =
@@ -1341,19 +1412,20 @@ static const struct intel_device_info xehpsdv_info = {
static const struct intel_display_device_info xe_hpd_display = {
XE_LPD_FEATURES,
.has_cdclk_squash = 1,
+
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
};
static const struct intel_device_info dg2_info = {
DG2_FEATURES,
- XE_LPD_RUNTIME,
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
.display = &xe_hpd_display,
};
static const struct intel_device_info ats_m_info = {
DG2_FEATURES,
- NO_DISPLAY,
+ .display = &no_display,
.require_force_probe = 1,
.tuning_thread_rr_after_dep = 1,
};
@@ -1375,7 +1447,7 @@ static const struct intel_device_info pvc_info = {
.__runtime.graphics.ip.rel = 60,
.__runtime.media.ip.rel = 60,
PLATFORM(INTEL_PONTEVECCHIO),
- NO_DISPLAY,
+ .display = &no_display,
.has_flat_ccs = 0,
.max_pat_index = 7,
.__runtime.platform_engine_mask =
@@ -1386,11 +1458,6 @@ static const struct intel_device_info pvc_info = {
PVC_CACHELEVEL,
};
-#define XE_LPDP_RUNTIME \
- XE_LPD_RUNTIME, \
- .__runtime.display.ip.ver = 14, \
- .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
-
static const struct intel_gt_definition xelpmp_extra_gt[] = {
{
.type = GT_MEDIA,
@@ -1405,13 +1472,16 @@ static const struct intel_display_device_info xe_lpdp_display = {
XE_LPD_FEATURES,
.has_cdclk_crawl = 1,
.has_cdclk_squash = 1,
+
+ .__runtime_defaults.ip.ver = 14,
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
};
static const struct intel_device_info mtl_info = {
XE_HP_FEATURES,
- XE_LPDP_RUNTIME,
- .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
/*
* Real graphics IP version will be obtained from hardware GMD_ID
* register. Value provided here is just for sanity checking.
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index d0bf626d0360..4d158927c78b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -95,6 +95,9 @@ void intel_device_info_print(const struct intel_device_info *info,
const struct intel_runtime_info *runtime,
struct drm_printer *p)
{
+ const struct intel_display_runtime_info *display_runtime =
+ &info->display->__runtime_defaults;
+
if (runtime->graphics.ip.rel)
drm_printf(p, "graphics version: %u.%02u\n",
runtime->graphics.ip.ver,
@@ -111,13 +114,13 @@ void intel_device_info_print(const struct intel_device_info *info,
drm_printf(p, "media version: %u\n",
runtime->media.ip.ver);
- if (runtime->display.ip.rel)
+ if (display_runtime->ip.rel)
drm_printf(p, "display version: %u.%02u\n",
- runtime->display.ip.ver,
- runtime->display.ip.rel);
+ display_runtime->ip.ver,
+ display_runtime->ip.rel);
else
drm_printf(p, "display version: %u\n",
- runtime->display.ip.ver);
+ display_runtime->ip.ver);
drm_printf(p, "graphics stepping: %s\n", intel_step_name(runtime->step.graphics_step));
drm_printf(p, "media stepping: %s\n", intel_step_name(runtime->step.media_step));
@@ -142,9 +145,9 @@ void intel_device_info_print(const struct intel_device_info *info,
DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
#undef PRINT_FLAG
- drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
- drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
- drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
+ drm_printf(p, "has_hdcp: %s\n", str_yes_no(display_runtime->has_hdcp));
+ drm_printf(p, "has_dmc: %s\n", str_yes_no(display_runtime->has_dmc));
+ drm_printf(p, "has_dsc: %s\n", str_yes_no(display_runtime->has_dsc));
drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
}
@@ -342,6 +345,7 @@ static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_
static void intel_ipver_early_init(struct drm_i915_private *i915)
{
struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
+ struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
if (!HAS_GMD_ID(i915)) {
drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
@@ -363,7 +367,7 @@ static void intel_ipver_early_init(struct drm_i915_private *i915)
RUNTIME_INFO(i915)->graphics.ip.rel = 70;
}
ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
- &runtime->display.ip);
+ (struct intel_ip_version *)&display_runtime->ip);
ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
&runtime->media.ip);
}
@@ -410,32 +414,34 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
{
struct intel_device_info *info = mkwrite_device_info(dev_priv);
struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
+ struct intel_display_runtime_info *display_runtime =
+ DISPLAY_RUNTIME_INFO(dev_priv);
enum pipe pipe;
/* Wa_14011765242: adl-s A0,A1 */
if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
for_each_pipe(dev_priv, pipe)
- runtime->num_scalers[pipe] = 0;
+ display_runtime->num_scalers[pipe] = 0;
else if (DISPLAY_VER(dev_priv) >= 11) {
for_each_pipe(dev_priv, pipe)
- runtime->num_scalers[pipe] = 2;
+ display_runtime->num_scalers[pipe] = 2;
} else if (DISPLAY_VER(dev_priv) >= 9) {
- runtime->num_scalers[PIPE_A] = 2;
- runtime->num_scalers[PIPE_B] = 2;
- runtime->num_scalers[PIPE_C] = 1;
+ display_runtime->num_scalers[PIPE_A] = 2;
+ display_runtime->num_scalers[PIPE_B] = 2;
+ display_runtime->num_scalers[PIPE_C] = 1;
}
BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
for_each_pipe(dev_priv, pipe)
- runtime->num_sprites[pipe] = 4;
+ display_runtime->num_sprites[pipe] = 4;
else if (DISPLAY_VER(dev_priv) >= 11)
for_each_pipe(dev_priv, pipe)
- runtime->num_sprites[pipe] = 6;
+ display_runtime->num_sprites[pipe] = 6;
else if (DISPLAY_VER(dev_priv) == 10)
for_each_pipe(dev_priv, pipe)
- runtime->num_sprites[pipe] = 3;
+ display_runtime->num_sprites[pipe] = 3;
else if (IS_BROXTON(dev_priv)) {
/*
* Skylake and Broxton currently don't expose the topmost plane as its
@@ -446,15 +452,15 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
* down the line.
*/
- runtime->num_sprites[PIPE_A] = 2;
- runtime->num_sprites[PIPE_B] = 2;
- runtime->num_sprites[PIPE_C] = 1;
+ display_runtime->num_sprites[PIPE_A] = 2;
+ display_runtime->num_sprites[PIPE_B] = 2;
+ display_runtime->num_sprites[PIPE_C] = 1;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
for_each_pipe(dev_priv, pipe)
- runtime->num_sprites[pipe] = 2;
+ display_runtime->num_sprites[pipe] = 2;
} else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
for_each_pipe(dev_priv, pipe)
- runtime->num_sprites[pipe] = 1;
+ display_runtime->num_sprites[pipe] = 1;
}
if (HAS_DISPLAY(dev_priv) &&
@@ -462,7 +468,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
!(intel_de_read(dev_priv, GU_CNTL_PROTECTED) & DEPRESENT)) {
drm_info(&dev_priv->drm, "Display not present, disabling\n");
- runtime->pipe_mask = 0;
+ display_runtime->pipe_mask = 0;
}
if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
@@ -485,47 +491,47 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
drm_info(&dev_priv->drm,
"Display fused off, disabling\n");
- runtime->pipe_mask = 0;
+ display_runtime->pipe_mask = 0;
} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
drm_info(&dev_priv->drm, "PipeC fused off\n");
- runtime->pipe_mask &= ~BIT(PIPE_C);
- runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
+ display_runtime->pipe_mask &= ~BIT(PIPE_C);
+ display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
}
} else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
- runtime->pipe_mask &= ~BIT(PIPE_A);
- runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
- runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
+ display_runtime->pipe_mask &= ~BIT(PIPE_A);
+ display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
+ display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
}
if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
- runtime->pipe_mask &= ~BIT(PIPE_B);
- runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
+ display_runtime->pipe_mask &= ~BIT(PIPE_B);
+ display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
}
if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
- runtime->pipe_mask &= ~BIT(PIPE_C);
- runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
+ display_runtime->pipe_mask &= ~BIT(PIPE_C);
+ display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
}
if (DISPLAY_VER(dev_priv) >= 12 &&
(dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
- runtime->pipe_mask &= ~BIT(PIPE_D);
- runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
+ display_runtime->pipe_mask &= ~BIT(PIPE_D);
+ display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
}
if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
- runtime->has_hdcp = 0;
+ display_runtime->has_hdcp = 0;
if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
- runtime->fbc_mask = 0;
+ display_runtime->fbc_mask = 0;
if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
- runtime->has_dmc = 0;
+ display_runtime->has_dmc = 0;
if (IS_DISPLAY_VER(dev_priv, 10, 12) &&
(dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
- runtime->has_dsc = 0;
+ display_runtime->has_dsc = 0;
}
if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {
@@ -542,13 +548,13 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
DRIVER_ATOMIC);
info->display = &no_display;
- runtime->cpu_transcoder_mask = 0;
- memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
- memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
- runtime->fbc_mask = 0;
- runtime->has_hdcp = false;
- runtime->has_dmc = false;
- runtime->has_dsc = false;
+ display_runtime->cpu_transcoder_mask = 0;
+ memset(display_runtime->num_sprites, 0, sizeof(display_runtime->num_sprites));
+ memset(display_runtime->num_scalers, 0, sizeof(display_runtime->num_scalers));
+ display_runtime->fbc_mask = 0;
+ display_runtime->has_hdcp = false;
+ display_runtime->has_dmc = false;
+ display_runtime->has_dsc = false;
}
/* Disable nuclear pageflip by default on pre-g4x */
@@ -568,6 +574,7 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
{
struct intel_device_info *info;
struct intel_runtime_info *runtime;
+ struct intel_display_runtime_info *display_runtime;
/* Setup the write-once "constant" device info */
info = mkwrite_device_info(i915);
@@ -576,6 +583,10 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
/* Initialize initial runtime info from static const data and pdev. */
runtime = RUNTIME_INFO(i915);
memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
+ display_runtime = DISPLAY_RUNTIME_INFO(i915);
+ memcpy(display_runtime, &DISPLAY_INFO(i915)->__runtime_defaults,
+ sizeof(*display_runtime));
+
runtime->device_id = device_id;
}
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index f212e02e6582..069291b3bd37 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -199,9 +199,6 @@ struct intel_runtime_info {
struct {
struct intel_ip_version ip;
} media;
- struct {
- struct intel_ip_version ip;
- } display;
/*
* Platform mask is used for optimizing or-ed IS_PLATFORM calls into
@@ -229,21 +226,6 @@ struct intel_runtime_info {
u32 memory_regions; /* regions supported by the HW */
bool has_pooled_eu;
-
- /* display */
- struct {
- u8 pipe_mask;
- u8 cpu_transcoder_mask;
-
- u8 num_sprites[I915_MAX_PIPES];
- u8 num_scalers[I915_MAX_PIPES];
-
- u8 fbc_mask;
-
- bool has_hdcp;
- bool has_dmc;
- bool has_dsc;
- };
};
struct intel_device_info {
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 84a6fe736a3b..8a9ff6227e53 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -166,8 +166,12 @@ void intel_step_init(struct drm_i915_private *i915)
&RUNTIME_INFO(i915)->graphics.ip);
step.media_step = gmd_to_intel_step(i915,
&RUNTIME_INFO(i915)->media.ip);
- step.display_step = gmd_to_intel_step(i915,
- &RUNTIME_INFO(i915)->display.ip);
+ step.display_step = STEP_A0 + DISPLAY_RUNTIME_INFO(i915)->ip.step;
+ if (step.display_step >= STEP_FUTURE) {
+ drm_dbg(&i915->drm, "Using future display steppings\n");
+ step.display_step = STEP_FUTURE;
+ }
+
RUNTIME_INFO(i915)->step = step;
return;
--
2.40.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH v2 3/6] drm/i915/display: Move display runtime info to display structure
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 3/6] drm/i915/display: Move display runtime info to display structure Matt Roper
@ 2023-05-23 7:50 ` Andrzej Hajda
2023-05-23 12:45 ` Jani Nikula
1 sibling, 0 replies; 22+ messages in thread
From: Andrzej Hajda @ 2023-05-23 7:50 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: intel-xe
On 22.05.2023 22:23, Matt Roper wrote:
> Move the runtime info specific to display into display-specific
> structures as has already been done with the constant display info.
>
> v2:
> - Rename __runtime to __runtime_defaults for more clarity on the
> purpose. (Andrzej)
> - Move introduction of DISPLAY_INFO() to previous patch. (Andrzej)
> - Drop NO_DISPLAY macro. (Andrzej)
>
> Cc: Andrzej Hajda <andrzej.hajda@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Regards
Andrzej
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
> drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.h | 8 +-
> .../drm/i915/display/intel_display_device.h | 23 ++
> drivers/gpu/drm/i915/display/intel_fbc.c | 6 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> .../drm/i915/display/skl_universal_plane.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 16 +-
> drivers/gpu/drm/i915/i915_pci.c | 252 +++++++++++-------
> drivers/gpu/drm/i915/intel_device_info.c | 101 +++----
> drivers/gpu/drm/i915/intel_device_info.h | 18 --
> drivers/gpu/drm/i915/intel_step.c | 8 +-
> 13 files changed, 267 insertions(+), 175 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 93c3226b98c9..182c6dd64f47 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -306,7 +306,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
> return PTR_ERR(crtc);
>
> crtc->pipe = pipe;
> - crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
> + crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe];
>
> if (DISPLAY_VER(dev_priv) >= 9)
> primary = skl_universal_plane_create(dev_priv, pipe,
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index 3864da5f5c17..b342fad180ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -814,7 +814,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> DRM_MODE_ROTATE_0 |
> DRM_MODE_ROTATE_180);
>
> - zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
> + zpos = DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
> drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
>
> if (DISPLAY_VER(dev_priv) >= 12)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0490c6412ab5..e477e16ea58e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3366,7 +3366,7 @@ static u8 bigjoiner_pipes(struct drm_i915_private *i915)
> else
> pipes = 0;
>
> - return pipes & RUNTIME_INFO(i915)->pipe_mask;
> + return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
> }
>
> static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index aa3a21ccd7fe..c744c021af23 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -105,7 +105,7 @@ enum i9xx_plane_id {
> };
>
> #define plane_name(p) ((p) + 'A')
> -#define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
> +#define sprite_name(p, s) ((p) * DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
>
> #define for_each_plane_id_on_crtc(__crtc, __p) \
> for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
> @@ -221,7 +221,7 @@ enum phy_fia {
>
> #define for_each_pipe(__dev_priv, __p) \
> for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
> - for_each_if(RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
> + for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
>
> #define for_each_pipe_masked(__dev_priv, __p, __mask) \
> for_each_pipe(__dev_priv, __p) \
> @@ -229,7 +229,7 @@ enum phy_fia {
>
> #define for_each_cpu_transcoder(__dev_priv, __t) \
> for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
> - for_each_if (RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
> + for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
>
> #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
> for_each_cpu_transcoder(__dev_priv, __t) \
> @@ -237,7 +237,7 @@ enum phy_fia {
>
> #define for_each_sprite(__dev_priv, __p, __s) \
> for ((__s) = 0; \
> - (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
> + (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
> (__s)++)
>
> #define for_each_port(__port) \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index c689d582dbf1..613607fad5af 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -29,7 +29,30 @@
> func(overlay_needs_physical); \
> func(supports_tv);
>
> +struct intel_display_runtime_info {
> + struct {
> + u16 ver;
> + u16 rel;
> + u16 step;
> + } ip;
> +
> + u8 pipe_mask;
> + u8 cpu_transcoder_mask;
> +
> + u8 num_sprites[I915_MAX_PIPES];
> + u8 num_scalers[I915_MAX_PIPES];
> +
> + u8 fbc_mask;
> +
> + bool has_hdcp;
> + bool has_dmc;
> + bool has_dsc;
> +};
> +
> struct intel_display_device_info {
> + /* Initial runtime info. */
> + const struct intel_display_runtime_info __runtime_defaults;
> +
> u8 abox_mask;
>
> struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 11bb8cf9c9d0..1966f9396201 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -56,7 +56,7 @@
>
> #define for_each_fbc_id(__dev_priv, __fbc_id) \
> for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
> - for_each_if(RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
> + for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
>
> #define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
> for_each_fbc_id((__dev_priv), (__fbc_id)) \
> @@ -1708,10 +1708,10 @@ void intel_fbc_init(struct drm_i915_private *i915)
> enum intel_fbc_id fbc_id;
>
> if (!drm_mm_initialized(&i915->mm.stolen))
> - RUNTIME_INFO(i915)->fbc_mask = 0;
> + DISPLAY_RUNTIME_INFO(i915)->fbc_mask = 0;
>
> if (need_fbc_vtd_wa(i915))
> - RUNTIME_INFO(i915)->fbc_mask = 0;
> + DISPLAY_RUNTIME_INFO(i915)->fbc_mask = 0;
>
> i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
> drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index dd539106ee5a..1f96d1fa68e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -1103,7 +1103,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
>
> bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
> {
> - return RUNTIME_INFO(dev_priv)->has_hdcp &&
> + return DISPLAY_RUNTIME_INFO(dev_priv)->has_hdcp &&
> (DISPLAY_VER(dev_priv) >= 12 || port < PORT_E);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 110401aab038..36070d86550f 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1944,7 +1944,7 @@ static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe)
> static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
> enum intel_fbc_id fbc_id, enum plane_id plane_id)
> {
> - if ((RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0)
> + if ((DISPLAY_RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0)
> return false;
>
> return plane_id == PLANE_PRIMARY;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9612c2ac4b00..7a8a12d12790 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -205,6 +205,7 @@ struct drm_i915_private {
>
> const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
> struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
> + struct intel_display_runtime_info __display_runtime; /* Access with DISPLAY_RUNTIME_INFO() */
> struct intel_driver_caps caps;
>
> struct i915_dsm dsm;
> @@ -410,6 +411,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
> #define INTEL_INFO(i915) (&(i915)->__info)
> #define DISPLAY_INFO(i915) (INTEL_INFO(i915)->display)
> #define RUNTIME_INFO(i915) (&(i915)->__runtime)
> +#define DISPLAY_RUNTIME_INFO(i915) (&(i915)->__display_runtime)
> #define DRIVER_CAPS(i915) (&(i915)->caps)
>
> #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id)
> @@ -428,7 +430,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
> #define IS_MEDIA_VER(i915, from, until) \
> (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
>
> -#define DISPLAY_VER(i915) (RUNTIME_INFO(i915)->display.ip.ver)
> +#define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver)
> #define IS_DISPLAY_VER(i915, from, until) \
> (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
>
> @@ -811,7 +813,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
>
> #define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2)
> -#define HAS_FBC(i915) (RUNTIME_INFO(i915)->fbc_mask != 0)
> +#define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
> #define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
>
> #define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13)
> @@ -831,7 +833,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_PSR_HW_TRACKING(i915) \
> (DISPLAY_INFO(i915)->has_psr_hw_tracking)
> #define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12)
> -#define HAS_TRANSCODER(i915, trans) ((RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
> +#define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
>
> #define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
> #define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
> @@ -839,9 +841,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
>
> -#define HAS_DMC(i915) (RUNTIME_INFO(i915)->has_dmc)
> +#define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc)
> #define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb)
> -#define HAS_DSC(__i915) (RUNTIME_INFO(__i915)->has_dsc)
> +#define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
> #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
>
> #define HAS_HECI_PXP(i915) \
> @@ -903,9 +905,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \
> 2 : HAS_L3_DPF(i915))
>
> -#define INTEL_NUM_PIPES(i915) (hweight8(RUNTIME_INFO(i915)->pipe_mask))
> +#define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
>
> -#define HAS_DISPLAY(i915) (RUNTIME_INFO(i915)->pipe_mask != 0)
> +#define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
>
> #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index dd874a4db604..9c781b703c7b 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -41,10 +41,9 @@
> #define PLATFORM(x) .platform = (x)
> #define GEN(x) \
> .__runtime.graphics.ip.ver = (x), \
> - .__runtime.media.ip.ver = (x), \
> - .__runtime.display.ip.ver = (x)
> + .__runtime.media.ip.ver = (x)
>
> -#define NO_DISPLAY .__runtime.pipe_mask = 0
> +static const struct intel_display_device_info no_display = { 0 };
>
> #define I845_PIPE_OFFSETS \
> .pipe_offsets = { \
> @@ -212,7 +211,12 @@
> .has_gmch = 1, \
> I9XX_PIPE_OFFSETS, \
> I9XX_CURSOR_OFFSETS, \
> - I9XX_COLORS
> + I9XX_COLORS, \
> + \
> + .__runtime_defaults.ip.ver = 2, \
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> + .__runtime_defaults.cpu_transcoder_mask = \
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
>
> static const struct intel_display_device_info i830_display = {
> I830_DISPLAY,
> @@ -221,8 +225,6 @@ static const struct intel_display_device_info i830_display = {
> #define I830_FEATURES \
> GEN(2), \
> .is_mobile = 1, \
> - .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> .gpu_reset_clobbers_display = true, \
> .has_3d_pipeline = 1, \
> .hws_needs_physical = 1, \
> @@ -242,7 +244,11 @@ static const struct intel_display_device_info i830_display = {
> .has_gmch = 1, \
> I845_PIPE_OFFSETS, \
> I845_CURSOR_OFFSETS, \
> - I845_COLORS
> + I845_COLORS, \
> + \
> + .__runtime_defaults.ip.ver = 2, \
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
> + .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
>
> static const struct intel_display_device_info i845_display = {
> I845_DISPLAY,
> @@ -250,8 +256,6 @@ static const struct intel_display_device_info i845_display = {
>
> #define I845_FEATURES \
> GEN(2), \
> - .__runtime.pipe_mask = BIT(PIPE_A), \
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \
> .has_3d_pipeline = 1, \
> .gpu_reset_clobbers_display = true, \
> .hws_needs_physical = 1, \
> @@ -279,24 +283,26 @@ static const struct intel_device_info i845g_info = {
>
> static const struct intel_display_device_info i85x_display = {
> I830_DISPLAY,
> +
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> static const struct intel_device_info i85x_info = {
> I830_FEATURES,
> PLATFORM(INTEL_I85X),
> .display = &i85x_display,
> - .__runtime.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> static const struct intel_display_device_info i865g_display = {
> I845_DISPLAY,
> +
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> static const struct intel_device_info i865g_info = {
> I845_FEATURES,
> PLATFORM(INTEL_I865G),
> .display = &i865g_display,
> - .__runtime.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> #define GEN3_DISPLAY \
> @@ -304,7 +310,12 @@ static const struct intel_device_info i865g_info = {
> .has_overlay = 1, \
> I9XX_PIPE_OFFSETS, \
> I9XX_CURSOR_OFFSETS, \
> - I9XX_COLORS
> + I9XX_COLORS, \
> + \
> + .__runtime_defaults.ip.ver = 3, \
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> + .__runtime_defaults.cpu_transcoder_mask = \
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
>
> static const struct intel_display_device_info i915g_display = {
> GEN3_DISPLAY,
> @@ -317,6 +328,8 @@ static const struct intel_display_device_info i915gm_display = {
> .cursor_needs_physical = 1,
> .overlay_needs_physical = 1,
> .supports_tv = 1,
> +
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> static const struct intel_display_device_info i945g_display = {
> @@ -332,6 +345,8 @@ static const struct intel_display_device_info i945gm_display = {
> .cursor_needs_physical = 1,
> .overlay_needs_physical = 1,
> .supports_tv = 1,
> +
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> static const struct intel_display_device_info g33_display = {
> @@ -341,8 +356,6 @@ static const struct intel_display_device_info g33_display = {
>
> #define GEN3_FEATURES \
> GEN(3), \
> - .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> .gpu_reset_clobbers_display = true, \
> .__runtime.platform_engine_mask = BIT(RCS0), \
> .has_3d_pipeline = 1, \
> @@ -368,7 +381,6 @@ static const struct intel_device_info i915gm_info = {
> PLATFORM(INTEL_I915GM),
> .display = &i915gm_display,
> .is_mobile = 1,
> - .__runtime.fbc_mask = BIT(INTEL_FBC_A),
> .hws_needs_physical = 1,
> .unfenced_needs_alignment = 1,
> };
> @@ -386,7 +398,6 @@ static const struct intel_device_info i945gm_info = {
> PLATFORM(INTEL_I945GM),
> .display = &i945gm_display,
> .is_mobile = 1,
> - .__runtime.fbc_mask = BIT(INTEL_FBC_A),
> .hws_needs_physical = 1,
> .unfenced_needs_alignment = 1,
> };
> @@ -418,7 +429,12 @@ static const struct intel_device_info pnv_m_info = {
> .has_gmch = 1, \
> I9XX_PIPE_OFFSETS, \
> I9XX_CURSOR_OFFSETS, \
> - I9XX_COLORS
> + I9XX_COLORS, \
> + \
> + .__runtime_defaults.ip.ver = 4, \
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> + .__runtime_defaults.cpu_transcoder_mask = \
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
>
> static const struct intel_display_device_info i965g_display = {
> GEN4_DISPLAY,
> @@ -429,6 +445,8 @@ static const struct intel_display_device_info i965gm_display = {
> GEN4_DISPLAY,
> .has_overlay = 1,
> .supports_tv = 1,
> +
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> static const struct intel_display_device_info g45_display = {
> @@ -438,12 +456,12 @@ static const struct intel_display_device_info g45_display = {
> static const struct intel_display_device_info gm45_display = {
> GEN4_DISPLAY,
> .supports_tv = 1,
> +
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> #define GEN4_FEATURES \
> GEN(4), \
> - .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> .gpu_reset_clobbers_display = true, \
> .__runtime.platform_engine_mask = BIT(RCS0), \
> .has_3d_pipeline = 1, \
> @@ -468,7 +486,6 @@ static const struct intel_device_info i965gm_info = {
> PLATFORM(INTEL_I965GM),
> .display = &i965gm_display,
> .is_mobile = 1,
> - .__runtime.fbc_mask = BIT(INTEL_FBC_A),
> .hws_needs_physical = 1,
> .has_snoop = false,
> };
> @@ -485,7 +502,6 @@ static const struct intel_device_info gm45_info = {
> GEN4_FEATURES,
> PLATFORM(INTEL_GM45),
> .is_mobile = 1,
> - .__runtime.fbc_mask = BIT(INTEL_FBC_A),
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
> .display = &gm45_display,
> .gpu_reset_clobbers_display = false,
> @@ -493,8 +509,6 @@ static const struct intel_device_info gm45_info = {
>
> #define GEN5_FEATURES \
> GEN(5), \
> - .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
> .has_3d_pipeline = 1, \
> .has_snoop = true, \
> @@ -511,7 +525,12 @@ static const struct intel_device_info gm45_info = {
> .has_hotplug = 1, \
> I9XX_PIPE_OFFSETS, \
> I9XX_CURSOR_OFFSETS, \
> - ILK_COLORS
> + ILK_COLORS, \
> + \
> + .__runtime_defaults.ip.ver = 5, \
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> + .__runtime_defaults.cpu_transcoder_mask = \
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
>
> static const struct intel_display_device_info ilk_d_display = {
> ILK_DISPLAY,
> @@ -525,6 +544,8 @@ static const struct intel_device_info ilk_d_info = {
>
> static const struct intel_display_device_info ilk_m_display = {
> ILK_DISPLAY,
> +
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> static const struct intel_device_info ilk_m_info = {
> @@ -533,14 +554,10 @@ static const struct intel_device_info ilk_m_info = {
> .display = &ilk_m_display,
> .is_mobile = 1,
> .has_rps = true,
> - .__runtime.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> #define GEN6_FEATURES \
> GEN(6), \
> - .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> - .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> .has_3d_pipeline = 1, \
> .has_coherent_ggtt = true, \
> @@ -562,6 +579,12 @@ static const struct intel_display_device_info snb_display = {
> I9XX_PIPE_OFFSETS,
> I9XX_CURSOR_OFFSETS,
> ILK_COLORS,
> +
> + .__runtime_defaults.ip.ver = 6,
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> #define SNB_D_PLATFORM \
> @@ -600,9 +623,6 @@ static const struct intel_device_info snb_m_gt2_info = {
>
> #define GEN7_FEATURES \
> GEN(7), \
> - .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
> - .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> .has_3d_pipeline = 1, \
> .has_coherent_ggtt = true, \
> @@ -629,6 +649,12 @@ static const struct intel_display_device_info ivb_display = {
> IVB_PIPE_OFFSETS,
> IVB_CURSOR_OFFSETS,
> IVB_COLORS,
> +
> + .__runtime_defaults.ip.ver = 7,
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> static const struct intel_device_info ivb_d_gt1_info = {
> @@ -664,7 +690,7 @@ static const struct intel_device_info ivb_m_gt2_info = {
> static const struct intel_device_info ivb_q_info = {
> GEN7_FEATURES,
> PLATFORM(INTEL_IVYBRIDGE),
> - NO_DISPLAY,
> + .display = &no_display,
> .gt = 2,
> .has_l3_dpf = 1,
> };
> @@ -676,14 +702,17 @@ static const struct intel_display_device_info vlv_display = {
> I9XX_PIPE_OFFSETS,
> I9XX_CURSOR_OFFSETS,
> I9XX_COLORS,
> +
> + .__runtime_defaults.ip.ver = 7,
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> };
>
> static const struct intel_device_info vlv_info = {
> PLATFORM(INTEL_VALLEYVIEW),
> GEN(7),
> .is_lp = 1,
> - .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> .display = &vlv_display,
> .has_runtime_pm = 1,
> .has_rc6 = 1,
> @@ -704,8 +733,6 @@ static const struct intel_device_info vlv_info = {
> #define G75_FEATURES \
> GEN7_FEATURES, \
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
> .has_rc6p = 0 /* RC6p removed-by HSW */, \
> .has_runtime_pm = 1
>
> @@ -722,6 +749,13 @@ static const struct intel_display_device_info hsw_display = {
> HSW_PIPE_OFFSETS,
> IVB_CURSOR_OFFSETS,
> IVB_COLORS,
> +
> + .__runtime_defaults.ip.ver = 7,
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> static const struct intel_device_info hsw_gt1_info = {
> @@ -759,6 +793,13 @@ static const struct intel_display_device_info bdw_display = {
> HSW_PIPE_OFFSETS,
> IVB_CURSOR_OFFSETS,
> IVB_COLORS,
> +
> + .__runtime_defaults.ip.ver = 8,
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> #define BDW_PLATFORM \
> @@ -801,13 +842,16 @@ static const struct intel_display_device_info chv_display = {
> CHV_PIPE_OFFSETS,
> CHV_CURSOR_OFFSETS,
> CHV_COLORS,
> +
> + .__runtime_defaults.ip.ver = 8,
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
> };
>
> static const struct intel_device_info chv_info = {
> PLATFORM(INTEL_CHERRYVIEW),
> GEN(8),
> - .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
> .display = &chv_display,
> .is_lp = 1,
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
> @@ -836,9 +880,7 @@ static const struct intel_device_info chv_info = {
> GEN8_FEATURES, \
> GEN(9), \
> GEN9_DEFAULT_PAGE_SIZES, \
> - .__runtime.has_dmc = 1, \
> - .has_gt_uc = 1, \
> - .__runtime.has_hdcp = 1
> + .has_gt_uc = 1
>
> static const struct intel_display_device_info skl_display = {
> .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
> @@ -853,6 +895,15 @@ static const struct intel_display_device_info skl_display = {
> HSW_PIPE_OFFSETS,
> IVB_CURSOR_OFFSETS,
> IVB_COLORS,
> +
> + .__runtime_defaults.ip.ver = 9,
> + .__runtime_defaults.has_dmc = 1,
> + .__runtime_defaults.has_hdcp = 1,
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> #define SKL_PLATFORM \
> @@ -893,16 +944,9 @@ static const struct intel_device_info skl_gt4_info = {
> GEN(9), \
> .is_lp = 1, \
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
> - .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
> - BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
> .has_3d_pipeline = 1, \
> .has_64bit_reloc = 1, \
> - .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
> - .__runtime.has_hdcp = 1, \
> .has_runtime_pm = 1, \
> - .__runtime.has_dmc = 1, \
> .has_rc6 = 1, \
> .has_rps = true, \
> .has_logical_ring_contexts = 1, \
> @@ -929,11 +973,22 @@ static const struct intel_device_info skl_gt4_info = {
> .has_psr_hw_tracking = 1, \
> HSW_PIPE_OFFSETS, \
> IVB_CURSOR_OFFSETS, \
> - IVB_COLORS
> + IVB_COLORS, \
> + \
> + .__runtime_defaults.has_dmc = 1, \
> + .__runtime_defaults.has_hdcp = 1, \
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> + .__runtime_defaults.cpu_transcoder_mask = \
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
> + BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C)
>
> static const struct intel_display_device_info bxt_display = {
> GEN9_LP_DISPLAY,
> .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
> +
> + .__runtime_defaults.ip.ver = 9,
> };
>
> static const struct intel_device_info bxt_info = {
> @@ -946,12 +1001,13 @@ static const struct intel_display_device_info glk_display = {
> GEN9_LP_DISPLAY,
> .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
> GLK_COLORS,
> +
> + .__runtime_defaults.ip.ver = 10,
> };
>
> static const struct intel_device_info glk_info = {
> GEN9_LP_FEATURES,
> PLATFORM(INTEL_GEMINILAKE),
> - .__runtime.display.ip.ver = 10,
> .display = &glk_display,
> };
>
> @@ -1027,11 +1083,7 @@ static const struct intel_device_info cml_gt2_info = {
> #define GEN11_FEATURES \
> GEN9_FEATURES, \
> GEN11_DEFAULT_PAGE_SIZES, \
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
> - BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> GEN(11), \
> - .__runtime.has_dsc = 1, \
> .has_coherent_ggtt = false, \
> .has_logical_ring_elsq = 1
>
> @@ -1064,6 +1116,17 @@ static const struct intel_display_device_info gen11_display = {
> },
> IVB_CURSOR_OFFSETS,
> ICL_COLORS,
> +
> + .__runtime_defaults.ip.ver = 11,
> + .__runtime_defaults.has_dmc = 1,
> + .__runtime_defaults.has_dsc = 1, \
> + .__runtime_defaults.has_hdcp = 1,
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) |
> + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> static const struct intel_device_info icl_info = {
> @@ -1093,10 +1156,6 @@ static const struct intel_device_info jsl_info = {
> #define GEN12_FEATURES \
> GEN11_FEATURES, \
> GEN(12), \
> - .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
> - BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> TGL_CACHELEVEL, \
> .has_global_mocs = 1, \
> .has_pxp = 1, \
> @@ -1131,7 +1190,19 @@ static const struct intel_device_info jsl_info = {
> [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> }, \
> TGL_CURSOR_OFFSETS, \
> - ICL_COLORS
> + ICL_COLORS, \
> + \
> + .__runtime_defaults.ip.ver = 12, \
> + .__runtime_defaults.has_dmc = 1, \
> + .__runtime_defaults.has_dsc = 1, \
> + .__runtime_defaults.has_hdcp = 1, \
> + .__runtime_defaults.pipe_mask = \
> + BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> + .__runtime_defaults.cpu_transcoder_mask = \
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
> + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
>
> static const struct intel_display_device_info tgl_display = {
> XE_D_DISPLAY,
> @@ -1150,14 +1221,15 @@ static const struct intel_display_device_info rkl_display = {
> .abox_mask = BIT(0),
> .has_hti = 1,
> .has_psr_hw_tracking = 0,
> +
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
> };
>
> static const struct intel_device_info rkl_info = {
> GEN12_FEATURES,
> PLATFORM(INTEL_ROCKETLAKE),
> - .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> - BIT(TRANSCODER_C),
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
> .display = &rkl_display,
> @@ -1176,7 +1248,6 @@ static const struct intel_device_info dg1_info = {
> DGFX_FEATURES,
> .__runtime.graphics.ip.rel = 10,
> PLATFORM(INTEL_DG1),
> - .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> .require_force_probe = 1,
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
> @@ -1195,7 +1266,6 @@ static const struct intel_display_device_info adl_s_display = {
> static const struct intel_device_info adl_s_info = {
> GEN12_FEATURES,
> PLATFORM(INTEL_ALDERLAKE_S),
> - .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> .dma_mask_size = 39,
> @@ -1235,29 +1305,30 @@ static const struct intel_device_info adl_s_info = {
> [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> }, \
> - TGL_CURSOR_OFFSETS
> -
> -#define XE_LPD_RUNTIME \
> - .__runtime.has_dmc = 1, \
> - .__runtime.has_dsc = 1, \
> - .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
> - .__runtime.has_hdcp = 1, \
> - .__runtime.display.ip.ver = 13, \
> - .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
> + TGL_CURSOR_OFFSETS, \
> + \
> + .__runtime_defaults.ip.ver = 13, \
> + .__runtime_defaults.has_dmc = 1, \
> + .__runtime_defaults.has_dsc = 1, \
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
> + .__runtime_defaults.has_hdcp = 1, \
> + .__runtime_defaults.pipe_mask = \
> + BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
>
> static const struct intel_display_device_info xe_lpd_display = {
> XE_LPD_FEATURES,
> .has_cdclk_crawl = 1,
> .has_psr_hw_tracking = 0,
> +
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
> + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> };
>
> static const struct intel_device_info adl_p_info = {
> GEN12_FEATURES,
> - XE_LPD_RUNTIME,
> PLATFORM(INTEL_ALDERLAKE_P),
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
> - BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> .__runtime.ppgtt_size = 48,
> @@ -1309,7 +1380,7 @@ static const struct intel_device_info xehpsdv_info = {
> XE_HPM_FEATURES,
> DGFX_FEATURES,
> PLATFORM(INTEL_XEHPSDV),
> - NO_DISPLAY,
> + .display = &no_display,
> .has_64k_pages = 1,
> .has_media_ratio_mode = 1,
> .__runtime.platform_engine_mask =
> @@ -1341,19 +1412,20 @@ static const struct intel_device_info xehpsdv_info = {
> static const struct intel_display_device_info xe_hpd_display = {
> XE_LPD_FEATURES,
> .has_cdclk_squash = 1,
> +
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> };
>
> static const struct intel_device_info dg2_info = {
> DG2_FEATURES,
> - XE_LPD_RUNTIME,
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> .display = &xe_hpd_display,
> };
>
> static const struct intel_device_info ats_m_info = {
> DG2_FEATURES,
> - NO_DISPLAY,
> + .display = &no_display,
> .require_force_probe = 1,
> .tuning_thread_rr_after_dep = 1,
> };
> @@ -1375,7 +1447,7 @@ static const struct intel_device_info pvc_info = {
> .__runtime.graphics.ip.rel = 60,
> .__runtime.media.ip.rel = 60,
> PLATFORM(INTEL_PONTEVECCHIO),
> - NO_DISPLAY,
> + .display = &no_display,
> .has_flat_ccs = 0,
> .max_pat_index = 7,
> .__runtime.platform_engine_mask =
> @@ -1386,11 +1458,6 @@ static const struct intel_device_info pvc_info = {
> PVC_CACHELEVEL,
> };
>
> -#define XE_LPDP_RUNTIME \
> - XE_LPD_RUNTIME, \
> - .__runtime.display.ip.ver = 14, \
> - .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
> -
> static const struct intel_gt_definition xelpmp_extra_gt[] = {
> {
> .type = GT_MEDIA,
> @@ -1405,13 +1472,16 @@ static const struct intel_display_device_info xe_lpdp_display = {
> XE_LPD_FEATURES,
> .has_cdclk_crawl = 1,
> .has_cdclk_squash = 1,
> +
> + .__runtime_defaults.ip.ver = 14,
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> };
>
> static const struct intel_device_info mtl_info = {
> XE_HP_FEATURES,
> - XE_LPDP_RUNTIME,
> - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> /*
> * Real graphics IP version will be obtained from hardware GMD_ID
> * register. Value provided here is just for sanity checking.
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index d0bf626d0360..4d158927c78b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -95,6 +95,9 @@ void intel_device_info_print(const struct intel_device_info *info,
> const struct intel_runtime_info *runtime,
> struct drm_printer *p)
> {
> + const struct intel_display_runtime_info *display_runtime =
> + &info->display->__runtime_defaults;
> +
> if (runtime->graphics.ip.rel)
> drm_printf(p, "graphics version: %u.%02u\n",
> runtime->graphics.ip.ver,
> @@ -111,13 +114,13 @@ void intel_device_info_print(const struct intel_device_info *info,
> drm_printf(p, "media version: %u\n",
> runtime->media.ip.ver);
>
> - if (runtime->display.ip.rel)
> + if (display_runtime->ip.rel)
> drm_printf(p, "display version: %u.%02u\n",
> - runtime->display.ip.ver,
> - runtime->display.ip.rel);
> + display_runtime->ip.ver,
> + display_runtime->ip.rel);
> else
> drm_printf(p, "display version: %u\n",
> - runtime->display.ip.ver);
> + display_runtime->ip.ver);
>
> drm_printf(p, "graphics stepping: %s\n", intel_step_name(runtime->step.graphics_step));
> drm_printf(p, "media stepping: %s\n", intel_step_name(runtime->step.media_step));
> @@ -142,9 +145,9 @@ void intel_device_info_print(const struct intel_device_info *info,
> DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
> #undef PRINT_FLAG
>
> - drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
> - drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
> - drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
> + drm_printf(p, "has_hdcp: %s\n", str_yes_no(display_runtime->has_hdcp));
> + drm_printf(p, "has_dmc: %s\n", str_yes_no(display_runtime->has_dmc));
> + drm_printf(p, "has_dsc: %s\n", str_yes_no(display_runtime->has_dsc));
>
> drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
> }
> @@ -342,6 +345,7 @@ static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_
> static void intel_ipver_early_init(struct drm_i915_private *i915)
> {
> struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
> + struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
>
> if (!HAS_GMD_ID(i915)) {
> drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
> @@ -363,7 +367,7 @@ static void intel_ipver_early_init(struct drm_i915_private *i915)
> RUNTIME_INFO(i915)->graphics.ip.rel = 70;
> }
> ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
> - &runtime->display.ip);
> + (struct intel_ip_version *)&display_runtime->ip);
> ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
> &runtime->media.ip);
> }
> @@ -410,32 +414,34 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> {
> struct intel_device_info *info = mkwrite_device_info(dev_priv);
> struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
> + struct intel_display_runtime_info *display_runtime =
> + DISPLAY_RUNTIME_INFO(dev_priv);
> enum pipe pipe;
>
> /* Wa_14011765242: adl-s A0,A1 */
> if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
> for_each_pipe(dev_priv, pipe)
> - runtime->num_scalers[pipe] = 0;
> + display_runtime->num_scalers[pipe] = 0;
> else if (DISPLAY_VER(dev_priv) >= 11) {
> for_each_pipe(dev_priv, pipe)
> - runtime->num_scalers[pipe] = 2;
> + display_runtime->num_scalers[pipe] = 2;
> } else if (DISPLAY_VER(dev_priv) >= 9) {
> - runtime->num_scalers[PIPE_A] = 2;
> - runtime->num_scalers[PIPE_B] = 2;
> - runtime->num_scalers[PIPE_C] = 1;
> + display_runtime->num_scalers[PIPE_A] = 2;
> + display_runtime->num_scalers[PIPE_B] = 2;
> + display_runtime->num_scalers[PIPE_C] = 1;
> }
>
> BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
>
> if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
> for_each_pipe(dev_priv, pipe)
> - runtime->num_sprites[pipe] = 4;
> + display_runtime->num_sprites[pipe] = 4;
> else if (DISPLAY_VER(dev_priv) >= 11)
> for_each_pipe(dev_priv, pipe)
> - runtime->num_sprites[pipe] = 6;
> + display_runtime->num_sprites[pipe] = 6;
> else if (DISPLAY_VER(dev_priv) == 10)
> for_each_pipe(dev_priv, pipe)
> - runtime->num_sprites[pipe] = 3;
> + display_runtime->num_sprites[pipe] = 3;
> else if (IS_BROXTON(dev_priv)) {
> /*
> * Skylake and Broxton currently don't expose the topmost plane as its
> @@ -446,15 +452,15 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> * down the line.
> */
>
> - runtime->num_sprites[PIPE_A] = 2;
> - runtime->num_sprites[PIPE_B] = 2;
> - runtime->num_sprites[PIPE_C] = 1;
> + display_runtime->num_sprites[PIPE_A] = 2;
> + display_runtime->num_sprites[PIPE_B] = 2;
> + display_runtime->num_sprites[PIPE_C] = 1;
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> for_each_pipe(dev_priv, pipe)
> - runtime->num_sprites[pipe] = 2;
> + display_runtime->num_sprites[pipe] = 2;
> } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
> for_each_pipe(dev_priv, pipe)
> - runtime->num_sprites[pipe] = 1;
> + display_runtime->num_sprites[pipe] = 1;
> }
>
> if (HAS_DISPLAY(dev_priv) &&
> @@ -462,7 +468,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> !(intel_de_read(dev_priv, GU_CNTL_PROTECTED) & DEPRESENT)) {
> drm_info(&dev_priv->drm, "Display not present, disabling\n");
>
> - runtime->pipe_mask = 0;
> + display_runtime->pipe_mask = 0;
> }
>
> if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
> @@ -485,47 +491,47 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
> drm_info(&dev_priv->drm,
> "Display fused off, disabling\n");
> - runtime->pipe_mask = 0;
> + display_runtime->pipe_mask = 0;
> } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
> drm_info(&dev_priv->drm, "PipeC fused off\n");
> - runtime->pipe_mask &= ~BIT(PIPE_C);
> - runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
> + display_runtime->pipe_mask &= ~BIT(PIPE_C);
> + display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
> }
> } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
> u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
>
> if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
> - runtime->pipe_mask &= ~BIT(PIPE_A);
> - runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
> - runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
> + display_runtime->pipe_mask &= ~BIT(PIPE_A);
> + display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
> + display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
> }
> if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
> - runtime->pipe_mask &= ~BIT(PIPE_B);
> - runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
> + display_runtime->pipe_mask &= ~BIT(PIPE_B);
> + display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
> }
> if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
> - runtime->pipe_mask &= ~BIT(PIPE_C);
> - runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
> + display_runtime->pipe_mask &= ~BIT(PIPE_C);
> + display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
> }
>
> if (DISPLAY_VER(dev_priv) >= 12 &&
> (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
> - runtime->pipe_mask &= ~BIT(PIPE_D);
> - runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
> + display_runtime->pipe_mask &= ~BIT(PIPE_D);
> + display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
> }
>
> if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> - runtime->has_hdcp = 0;
> + display_runtime->has_hdcp = 0;
>
> if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
> - runtime->fbc_mask = 0;
> + display_runtime->fbc_mask = 0;
>
> if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
> - runtime->has_dmc = 0;
> + display_runtime->has_dmc = 0;
>
> if (IS_DISPLAY_VER(dev_priv, 10, 12) &&
> (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
> - runtime->has_dsc = 0;
> + display_runtime->has_dsc = 0;
> }
>
> if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {
> @@ -542,13 +548,13 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> DRIVER_ATOMIC);
> info->display = &no_display;
>
> - runtime->cpu_transcoder_mask = 0;
> - memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
> - memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
> - runtime->fbc_mask = 0;
> - runtime->has_hdcp = false;
> - runtime->has_dmc = false;
> - runtime->has_dsc = false;
> + display_runtime->cpu_transcoder_mask = 0;
> + memset(display_runtime->num_sprites, 0, sizeof(display_runtime->num_sprites));
> + memset(display_runtime->num_scalers, 0, sizeof(display_runtime->num_scalers));
> + display_runtime->fbc_mask = 0;
> + display_runtime->has_hdcp = false;
> + display_runtime->has_dmc = false;
> + display_runtime->has_dsc = false;
> }
>
> /* Disable nuclear pageflip by default on pre-g4x */
> @@ -568,6 +574,7 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
> {
> struct intel_device_info *info;
> struct intel_runtime_info *runtime;
> + struct intel_display_runtime_info *display_runtime;
>
> /* Setup the write-once "constant" device info */
> info = mkwrite_device_info(i915);
> @@ -576,6 +583,10 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
> /* Initialize initial runtime info from static const data and pdev. */
> runtime = RUNTIME_INFO(i915);
> memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
> + display_runtime = DISPLAY_RUNTIME_INFO(i915);
> + memcpy(display_runtime, &DISPLAY_INFO(i915)->__runtime_defaults,
> + sizeof(*display_runtime));
> +
> runtime->device_id = device_id;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index f212e02e6582..069291b3bd37 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -199,9 +199,6 @@ struct intel_runtime_info {
> struct {
> struct intel_ip_version ip;
> } media;
> - struct {
> - struct intel_ip_version ip;
> - } display;
>
> /*
> * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
> @@ -229,21 +226,6 @@ struct intel_runtime_info {
> u32 memory_regions; /* regions supported by the HW */
>
> bool has_pooled_eu;
> -
> - /* display */
> - struct {
> - u8 pipe_mask;
> - u8 cpu_transcoder_mask;
> -
> - u8 num_sprites[I915_MAX_PIPES];
> - u8 num_scalers[I915_MAX_PIPES];
> -
> - u8 fbc_mask;
> -
> - bool has_hdcp;
> - bool has_dmc;
> - bool has_dsc;
> - };
> };
>
> struct intel_device_info {
> diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
> index 84a6fe736a3b..8a9ff6227e53 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -166,8 +166,12 @@ void intel_step_init(struct drm_i915_private *i915)
> &RUNTIME_INFO(i915)->graphics.ip);
> step.media_step = gmd_to_intel_step(i915,
> &RUNTIME_INFO(i915)->media.ip);
> - step.display_step = gmd_to_intel_step(i915,
> - &RUNTIME_INFO(i915)->display.ip);
> + step.display_step = STEP_A0 + DISPLAY_RUNTIME_INFO(i915)->ip.step;
> + if (step.display_step >= STEP_FUTURE) {
> + drm_dbg(&i915->drm, "Using future display steppings\n");
> + step.display_step = STEP_FUTURE;
> + }
> +
> RUNTIME_INFO(i915)->step = step;
>
> return;
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH v2 3/6] drm/i915/display: Move display runtime info to display structure
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 3/6] drm/i915/display: Move display runtime info to display structure Matt Roper
2023-05-23 7:50 ` Andrzej Hajda
@ 2023-05-23 12:45 ` Jani Nikula
1 sibling, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2023-05-23 12:45 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: Matt Roper, intel-xe, Andrzej Hajda
On Mon, 22 May 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9612c2ac4b00..7a8a12d12790 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -205,6 +205,7 @@ struct drm_i915_private {
>
> const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
> struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
> + struct intel_display_runtime_info __display_runtime; /* Access with DISPLAY_RUNTIME_INFO() */
This could now live as a member of struct intel_display, dropping
another display only member from struct drm_i915_private.
AFAICT this can be a trivial movement patch on top, since almost all
access is via DISPLAY_RUNTIME_INFO().
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index dd874a4db604..9c781b703c7b 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -41,10 +41,9 @@
> #define PLATFORM(x) .platform = (x)
> #define GEN(x) \
> .__runtime.graphics.ip.ver = (x), \
> - .__runtime.media.ip.ver = (x), \
> - .__runtime.display.ip.ver = (x)
> + .__runtime.media.ip.ver = (x)
>
> -#define NO_DISPLAY .__runtime.pipe_mask = 0
> +static const struct intel_display_device_info no_display = { 0 };
I think just {} is preferred for empty init, and dodges issues with some
verbose compiler warnings with sub-struct init. Can also be fixed
afterwards if there's no other need to do a respin.
Acked-by: Jani Nikula <jani.nikula@intel.com>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v2 4/6] drm/i915/display: Make display responsible for probing its own IP
2023-05-22 20:23 [Intel-gfx] [PATCH v2 0/6] i915: Move display identification/probing under display/ Matt Roper
` (2 preceding siblings ...)
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 3/6] drm/i915/display: Move display runtime info to display structure Matt Roper
@ 2023-05-22 20:23 ` Matt Roper
2023-05-23 7:51 ` Andrzej Hajda
2023-05-23 12:58 ` [Intel-gfx] [Intel-xe] " Jani Nikula
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 5/6] drm/i915/display: Handle GMD_ID identification in display code Matt Roper
` (6 subsequent siblings)
10 siblings, 2 replies; 22+ messages in thread
From: Matt Roper @ 2023-05-22 20:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, intel-xe, Andrzej Hajda
Rather than selecting the display IP and feature flags at the same time
the general PCI probing happens, move this step into the display code
itself so that it can be more easily re-used outside of i915 (i.e., by
the Xe driver).
v2:
- Make intel_display_device_probe() always return a non-NULL pointer
and simplify copying of runtime_defaults. (Andrzej)
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/Makefile | 2 +
.../drm/i915/display/intel_display_device.c | 710 ++++++++++++++++++
.../drm/i915/display/intel_display_device.h | 3 +
drivers/gpu/drm/i915/i915_pci.c | 665 ----------------
drivers/gpu/drm/i915/i915_reg.h | 33 -
drivers/gpu/drm/i915/intel_device_info.c | 8 +-
6 files changed, 719 insertions(+), 702 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index dd9ca69f4998..06374fc072d3 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -25,6 +25,7 @@ subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
# Fine grained warnings disable
CFLAGS_i915_pci.o = $(call cc-disable-warning, override-init)
+CFLAGS_display/intel_display_device.o = $(call cc-disable-warning, override-init)
CFLAGS_display/intel_fbdev.o = $(call cc-disable-warning, override-init)
subdir-ccflags-y += -I$(srctree)/$(src)
@@ -308,6 +309,7 @@ i915-y += \
display/intel_cx0_phy.o \
display/intel_ddi.o \
display/intel_ddi_buf_trans.o \
+ display/intel_display_device.o \
display/intel_display_trace.o \
display/intel_dkl_phy.o \
display/intel_dp.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
new file mode 100644
index 000000000000..3c5941c8788d
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -0,0 +1,710 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include <drm/i915_pciids.h>
+#include <drm/drm_color_mgmt.h>
+#include <linux/mod_devicetable.h>
+
+#include "intel_display_device.h"
+#include "intel_display_power.h"
+#include "intel_display_reg_defs.h"
+#include "intel_fbc.h"
+
+static const struct intel_display_device_info no_display = { 0 };
+
+#define PIPE_A_OFFSET 0x70000
+#define PIPE_B_OFFSET 0x71000
+#define PIPE_C_OFFSET 0x72000
+#define PIPE_D_OFFSET 0x73000
+#define CHV_PIPE_C_OFFSET 0x74000
+/*
+ * There's actually no pipe EDP. Some pipe registers have
+ * simply shifted from the pipe to the transcoder, while
+ * keeping their original offset. Thus we need PIPE_EDP_OFFSET
+ * to access such registers in transcoder EDP.
+ */
+#define PIPE_EDP_OFFSET 0x7f000
+
+/* ICL DSI 0 and 1 */
+#define PIPE_DSI0_OFFSET 0x7b000
+#define PIPE_DSI1_OFFSET 0x7b800
+
+#define TRANSCODER_A_OFFSET 0x60000
+#define TRANSCODER_B_OFFSET 0x61000
+#define TRANSCODER_C_OFFSET 0x62000
+#define CHV_TRANSCODER_C_OFFSET 0x63000
+#define TRANSCODER_D_OFFSET 0x63000
+#define TRANSCODER_EDP_OFFSET 0x6f000
+#define TRANSCODER_DSI0_OFFSET 0x6b000
+#define TRANSCODER_DSI1_OFFSET 0x6b800
+
+#define CURSOR_A_OFFSET 0x70080
+#define CURSOR_B_OFFSET 0x700c0
+#define CHV_CURSOR_C_OFFSET 0x700e0
+#define IVB_CURSOR_B_OFFSET 0x71080
+#define IVB_CURSOR_C_OFFSET 0x72080
+#define TGL_CURSOR_D_OFFSET 0x73080
+
+#define I845_PIPE_OFFSETS \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ }
+
+#define I9XX_PIPE_OFFSETS \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ }
+
+#define IVB_PIPE_OFFSETS \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ }
+
+#define HSW_PIPE_OFFSETS \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
+ }
+
+#define CHV_PIPE_OFFSETS \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
+ }
+
+#define I845_CURSOR_OFFSETS \
+ .cursor_offsets = { \
+ [PIPE_A] = CURSOR_A_OFFSET, \
+ }
+
+#define I9XX_CURSOR_OFFSETS \
+ .cursor_offsets = { \
+ [PIPE_A] = CURSOR_A_OFFSET, \
+ [PIPE_B] = CURSOR_B_OFFSET, \
+ }
+
+#define CHV_CURSOR_OFFSETS \
+ .cursor_offsets = { \
+ [PIPE_A] = CURSOR_A_OFFSET, \
+ [PIPE_B] = CURSOR_B_OFFSET, \
+ [PIPE_C] = CHV_CURSOR_C_OFFSET, \
+ }
+
+#define IVB_CURSOR_OFFSETS \
+ .cursor_offsets = { \
+ [PIPE_A] = CURSOR_A_OFFSET, \
+ [PIPE_B] = IVB_CURSOR_B_OFFSET, \
+ [PIPE_C] = IVB_CURSOR_C_OFFSET, \
+ }
+
+#define TGL_CURSOR_OFFSETS \
+ .cursor_offsets = { \
+ [PIPE_A] = CURSOR_A_OFFSET, \
+ [PIPE_B] = IVB_CURSOR_B_OFFSET, \
+ [PIPE_C] = IVB_CURSOR_C_OFFSET, \
+ [PIPE_D] = TGL_CURSOR_D_OFFSET, \
+ }
+
+#define I845_COLORS \
+ .color = { .gamma_lut_size = 256 }
+#define I9XX_COLORS \
+ .color = { .gamma_lut_size = 129, \
+ .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+ }
+#define ILK_COLORS \
+ .color = { .gamma_lut_size = 1024 }
+#define IVB_COLORS \
+ .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
+#define CHV_COLORS \
+ .color = { \
+ .degamma_lut_size = 65, .gamma_lut_size = 257, \
+ .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+ .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+ }
+#define GLK_COLORS \
+ .color = { \
+ .degamma_lut_size = 33, .gamma_lut_size = 1024, \
+ .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
+ DRM_COLOR_LUT_EQUAL_CHANNELS, \
+ }
+#define ICL_COLORS \
+ .color = { \
+ .degamma_lut_size = 33, .gamma_lut_size = 262145, \
+ .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
+ DRM_COLOR_LUT_EQUAL_CHANNELS, \
+ .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+ }
+
+#define I830_DISPLAY \
+ .has_overlay = 1, \
+ .cursor_needs_physical = 1, \
+ .overlay_needs_physical = 1, \
+ .has_gmch = 1, \
+ I9XX_PIPE_OFFSETS, \
+ I9XX_CURSOR_OFFSETS, \
+ I9XX_COLORS, \
+ \
+ .__runtime_defaults.ip.ver = 2, \
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+ .__runtime_defaults.cpu_transcoder_mask = \
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
+
+static const struct intel_display_device_info i830_display = {
+ I830_DISPLAY,
+};
+
+#define I845_DISPLAY \
+ .has_overlay = 1, \
+ .overlay_needs_physical = 1, \
+ .has_gmch = 1, \
+ I845_PIPE_OFFSETS, \
+ I845_CURSOR_OFFSETS, \
+ I845_COLORS, \
+ \
+ .__runtime_defaults.ip.ver = 2, \
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
+ .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
+
+static const struct intel_display_device_info i845_display = {
+ I845_DISPLAY,
+};
+
+static const struct intel_display_device_info i85x_display = {
+ I830_DISPLAY,
+
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info i865g_display = {
+ I845_DISPLAY,
+
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+#define GEN3_DISPLAY \
+ .has_gmch = 1, \
+ .has_overlay = 1, \
+ I9XX_PIPE_OFFSETS, \
+ I9XX_CURSOR_OFFSETS, \
+ I9XX_COLORS, \
+ \
+ .__runtime_defaults.ip.ver = 3, \
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+ .__runtime_defaults.cpu_transcoder_mask = \
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
+
+static const struct intel_display_device_info i915g_display = {
+ GEN3_DISPLAY,
+ .cursor_needs_physical = 1,
+ .overlay_needs_physical = 1,
+};
+
+static const struct intel_display_device_info i915gm_display = {
+ GEN3_DISPLAY,
+ .cursor_needs_physical = 1,
+ .overlay_needs_physical = 1,
+ .supports_tv = 1,
+
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info i945g_display = {
+ GEN3_DISPLAY,
+ .has_hotplug = 1,
+ .cursor_needs_physical = 1,
+ .overlay_needs_physical = 1,
+};
+
+static const struct intel_display_device_info i945gm_display = {
+ GEN3_DISPLAY,
+ .has_hotplug = 1,
+ .cursor_needs_physical = 1,
+ .overlay_needs_physical = 1,
+ .supports_tv = 1,
+
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info g33_display = {
+ GEN3_DISPLAY,
+ .has_hotplug = 1,
+};
+
+#define GEN4_DISPLAY \
+ .has_hotplug = 1, \
+ .has_gmch = 1, \
+ I9XX_PIPE_OFFSETS, \
+ I9XX_CURSOR_OFFSETS, \
+ I9XX_COLORS, \
+ \
+ .__runtime_defaults.ip.ver = 4, \
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+ .__runtime_defaults.cpu_transcoder_mask = \
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
+
+static const struct intel_display_device_info i965g_display = {
+ GEN4_DISPLAY,
+ .has_overlay = 1,
+};
+
+static const struct intel_display_device_info i965gm_display = {
+ GEN4_DISPLAY,
+ .has_overlay = 1,
+ .supports_tv = 1,
+
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info g45_display = {
+ GEN4_DISPLAY,
+};
+
+static const struct intel_display_device_info gm45_display = {
+ GEN4_DISPLAY,
+ .supports_tv = 1,
+
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+#define ILK_DISPLAY \
+ .has_hotplug = 1, \
+ I9XX_PIPE_OFFSETS, \
+ I9XX_CURSOR_OFFSETS, \
+ ILK_COLORS, \
+ \
+ .__runtime_defaults.ip.ver = 5, \
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+ .__runtime_defaults.cpu_transcoder_mask = \
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
+
+static const struct intel_display_device_info ilk_d_display = {
+ ILK_DISPLAY,
+};
+
+static const struct intel_display_device_info ilk_m_display = {
+ ILK_DISPLAY,
+
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info snb_display = {
+ .has_hotplug = 1,
+ I9XX_PIPE_OFFSETS,
+ I9XX_CURSOR_OFFSETS,
+ ILK_COLORS,
+
+ .__runtime_defaults.ip.ver = 6,
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info ivb_display = {
+ .has_hotplug = 1,
+ IVB_PIPE_OFFSETS,
+ IVB_CURSOR_OFFSETS,
+ IVB_COLORS,
+
+ .__runtime_defaults.ip.ver = 7,
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info vlv_display = {
+ .has_gmch = 1,
+ .has_hotplug = 1,
+ .mmio_offset = VLV_DISPLAY_BASE,
+ I9XX_PIPE_OFFSETS,
+ I9XX_CURSOR_OFFSETS,
+ I9XX_COLORS,
+
+ .__runtime_defaults.ip.ver = 7,
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
+};
+
+static const struct intel_display_device_info hsw_display = {
+ .has_ddi = 1,
+ .has_dp_mst = 1,
+ .has_fpga_dbg = 1,
+ .has_hotplug = 1,
+ HSW_PIPE_OFFSETS,
+ IVB_CURSOR_OFFSETS,
+ IVB_COLORS,
+
+ .__runtime_defaults.ip.ver = 7,
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info bdw_display = {
+ .has_ddi = 1,
+ .has_dp_mst = 1,
+ .has_fpga_dbg = 1,
+ .has_hotplug = 1,
+ HSW_PIPE_OFFSETS,
+ IVB_CURSOR_OFFSETS,
+ IVB_COLORS,
+
+ .__runtime_defaults.ip.ver = 8,
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+static const struct intel_display_device_info chv_display = {
+ .has_hotplug = 1,
+ .has_gmch = 1,
+ .mmio_offset = VLV_DISPLAY_BASE,
+ CHV_PIPE_OFFSETS,
+ CHV_CURSOR_OFFSETS,
+ CHV_COLORS,
+
+ .__runtime_defaults.ip.ver = 8,
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
+};
+
+static const struct intel_display_device_info skl_display = {
+ .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
+ .dbuf.slice_mask = BIT(DBUF_S1),
+ .has_ddi = 1,
+ .has_dp_mst = 1,
+ .has_fpga_dbg = 1,
+ .has_hotplug = 1,
+ .has_ipc = 1,
+ .has_psr = 1,
+ .has_psr_hw_tracking = 1,
+ HSW_PIPE_OFFSETS,
+ IVB_CURSOR_OFFSETS,
+ IVB_COLORS,
+
+ .__runtime_defaults.ip.ver = 9,
+ .__runtime_defaults.has_dmc = 1,
+ .__runtime_defaults.has_hdcp = 1,
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+#define GEN9_LP_DISPLAY \
+ .dbuf.slice_mask = BIT(DBUF_S1), \
+ .has_dp_mst = 1, \
+ .has_ddi = 1, \
+ .has_fpga_dbg = 1, \
+ .has_hotplug = 1, \
+ .has_ipc = 1, \
+ .has_psr = 1, \
+ .has_psr_hw_tracking = 1, \
+ HSW_PIPE_OFFSETS, \
+ IVB_CURSOR_OFFSETS, \
+ IVB_COLORS, \
+ \
+ .__runtime_defaults.has_dmc = 1, \
+ .__runtime_defaults.has_hdcp = 1, \
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
+ .__runtime_defaults.cpu_transcoder_mask = \
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
+ BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C)
+
+static const struct intel_display_device_info bxt_display = {
+ GEN9_LP_DISPLAY,
+ .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
+
+ .__runtime_defaults.ip.ver = 9,
+};
+
+static const struct intel_display_device_info glk_display = {
+ GEN9_LP_DISPLAY,
+ .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
+ GLK_COLORS,
+
+ .__runtime_defaults.ip.ver = 10,
+};
+
+static const struct intel_display_device_info gen11_display = {
+ .abox_mask = BIT(0),
+ .dbuf.size = 2048,
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2),
+ .has_ddi = 1,
+ .has_dp_mst = 1,
+ .has_fpga_dbg = 1,
+ .has_hotplug = 1,
+ .has_ipc = 1,
+ .has_psr = 1,
+ .has_psr_hw_tracking = 1,
+ .pipe_offsets = {
+ [TRANSCODER_A] = PIPE_A_OFFSET,
+ [TRANSCODER_B] = PIPE_B_OFFSET,
+ [TRANSCODER_C] = PIPE_C_OFFSET,
+ [TRANSCODER_EDP] = PIPE_EDP_OFFSET,
+ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
+ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
+ },
+ .trans_offsets = {
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET,
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET,
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET,
+ [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET,
+ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
+ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
+ },
+ IVB_CURSOR_OFFSETS,
+ ICL_COLORS,
+
+ .__runtime_defaults.ip.ver = 11,
+ .__runtime_defaults.has_dmc = 1,
+ .__runtime_defaults.has_dsc = 1, \
+ .__runtime_defaults.has_hdcp = 1,
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) |
+ BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+};
+
+#define XE_D_DISPLAY \
+ .abox_mask = GENMASK(2, 1), \
+ .dbuf.size = 2048, \
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
+ .has_ddi = 1, \
+ .has_dp_mst = 1, \
+ .has_dsb = 1, \
+ .has_fpga_dbg = 1, \
+ .has_hotplug = 1, \
+ .has_ipc = 1, \
+ .has_psr = 1, \
+ .has_psr_hw_tracking = 1, \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ [TRANSCODER_D] = PIPE_D_OFFSET, \
+ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
+ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
+ }, \
+ TGL_CURSOR_OFFSETS, \
+ ICL_COLORS, \
+ \
+ .__runtime_defaults.ip.ver = 12, \
+ .__runtime_defaults.has_dmc = 1, \
+ .__runtime_defaults.has_dsc = 1, \
+ .__runtime_defaults.has_hdcp = 1, \
+ .__runtime_defaults.pipe_mask = \
+ BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+ .__runtime_defaults.cpu_transcoder_mask = \
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
+ BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
+
+static const struct intel_display_device_info tgl_display = {
+ XE_D_DISPLAY,
+};
+
+static const struct intel_display_device_info rkl_display = {
+ XE_D_DISPLAY,
+ .abox_mask = BIT(0),
+ .has_hti = 1,
+ .has_psr_hw_tracking = 0,
+
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
+};
+
+static const struct intel_display_device_info adl_s_display = {
+ XE_D_DISPLAY,
+ .has_hti = 1,
+ .has_psr_hw_tracking = 0,
+};
+
+#define XE_LPD_FEATURES \
+ .abox_mask = GENMASK(1, 0), \
+ .color = { \
+ .degamma_lut_size = 129, .gamma_lut_size = 1024, \
+ .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
+ DRM_COLOR_LUT_EQUAL_CHANNELS, \
+ }, \
+ .dbuf.size = 4096, \
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
+ BIT(DBUF_S4), \
+ .has_ddi = 1, \
+ .has_dp_mst = 1, \
+ .has_dsb = 1, \
+ .has_fpga_dbg = 1, \
+ .has_hotplug = 1, \
+ .has_ipc = 1, \
+ .has_psr = 1, \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ [TRANSCODER_D] = PIPE_D_OFFSET, \
+ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
+ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
+ }, \
+ TGL_CURSOR_OFFSETS, \
+ \
+ .__runtime_defaults.ip.ver = 13, \
+ .__runtime_defaults.has_dmc = 1, \
+ .__runtime_defaults.has_dsc = 1, \
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
+ .__runtime_defaults.has_hdcp = 1, \
+ .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
+
+static const struct intel_display_device_info xe_lpd_display = {
+ XE_LPD_FEATURES,
+ .has_cdclk_crawl = 1,
+ .has_psr_hw_tracking = 0,
+
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
+ BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
+};
+
+static const struct intel_display_device_info xe_hpd_display = {
+ XE_LPD_FEATURES,
+ .has_cdclk_squash = 1,
+
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+};
+
+static const struct intel_display_device_info xe_lpdp_display = {
+ XE_LPD_FEATURES,
+ .has_cdclk_crawl = 1,
+ .has_cdclk_squash = 1,
+
+ .__runtime_defaults.ip.ver = 14,
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+};
+
+static const struct pci_device_id intel_display_ids[] = {
+ INTEL_I830_IDS(&i830_display),
+ INTEL_I845G_IDS(&i845_display),
+ INTEL_I85X_IDS(&i85x_display),
+ INTEL_I865G_IDS(&i865g_display),
+ INTEL_I915G_IDS(&i915g_display),
+ INTEL_I915GM_IDS(&i915gm_display),
+ INTEL_I945G_IDS(&i945g_display),
+ INTEL_I945GM_IDS(&i945gm_display),
+ INTEL_I965G_IDS(&i965g_display),
+ INTEL_G33_IDS(&g33_display),
+ INTEL_I965GM_IDS(&i965gm_display),
+ INTEL_GM45_IDS(&gm45_display),
+ INTEL_G45_IDS(&g45_display),
+ INTEL_PINEVIEW_G_IDS(&g33_display),
+ INTEL_PINEVIEW_M_IDS(&g33_display),
+ INTEL_IRONLAKE_D_IDS(&ilk_d_display),
+ INTEL_IRONLAKE_M_IDS(&ilk_m_display),
+ INTEL_SNB_D_IDS(&snb_display),
+ INTEL_SNB_M_IDS(&snb_display),
+ INTEL_IVB_Q_IDS(NULL), /* must be first IVB in list */
+ INTEL_IVB_M_IDS(&ivb_display),
+ INTEL_IVB_D_IDS(&ivb_display),
+ INTEL_HSW_IDS(&hsw_display),
+ INTEL_VLV_IDS(&vlv_display),
+ INTEL_BDW_IDS(&bdw_display),
+ INTEL_CHV_IDS(&chv_display),
+ INTEL_SKL_IDS(&skl_display),
+ INTEL_BXT_IDS(&bxt_display),
+ INTEL_GLK_IDS(&glk_display),
+ INTEL_KBL_IDS(&skl_display),
+ INTEL_CFL_IDS(&skl_display),
+ INTEL_ICL_11_IDS(&gen11_display),
+ INTEL_EHL_IDS(&gen11_display),
+ INTEL_JSL_IDS(&gen11_display),
+ INTEL_TGL_12_IDS(&tgl_display),
+ INTEL_DG1_IDS(&tgl_display),
+ INTEL_RKL_IDS(&rkl_display),
+ INTEL_ADLS_IDS(&adl_s_display),
+ INTEL_RPLS_IDS(&adl_s_display),
+ INTEL_ADLP_IDS(&xe_lpd_display),
+ INTEL_ADLN_IDS(&xe_lpd_display),
+ INTEL_RPLP_IDS(&xe_lpd_display),
+ INTEL_DG2_IDS(&xe_hpd_display),
+
+ /* FIXME: Replace this with a GMD_ID lookup */
+ INTEL_MTL_IDS(&xe_lpdp_display),
+};
+
+const struct intel_display_device_info *
+intel_display_device_probe(u16 pci_devid)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
+ if (intel_display_ids[i].device == pci_devid)
+ return (struct intel_display_device_info *)intel_display_ids[i].driver_data;
+ }
+
+ return &no_display;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 613607fad5af..1f7d08b3ad6b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -80,4 +80,7 @@ struct intel_display_device_info {
} color;
};
+const struct intel_display_device_info *
+intel_display_device_probe(u16 pci_devid);
+
#endif
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 9c781b703c7b..928975d5fe2f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -43,127 +43,6 @@
.__runtime.graphics.ip.ver = (x), \
.__runtime.media.ip.ver = (x)
-static const struct intel_display_device_info no_display = { 0 };
-
-#define I845_PIPE_OFFSETS \
- .pipe_offsets = { \
- [TRANSCODER_A] = PIPE_A_OFFSET, \
- }, \
- .trans_offsets = { \
- [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- }
-
-#define I9XX_PIPE_OFFSETS \
- .pipe_offsets = { \
- [TRANSCODER_A] = PIPE_A_OFFSET, \
- [TRANSCODER_B] = PIPE_B_OFFSET, \
- }, \
- .trans_offsets = { \
- [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- }
-
-#define IVB_PIPE_OFFSETS \
- .pipe_offsets = { \
- [TRANSCODER_A] = PIPE_A_OFFSET, \
- [TRANSCODER_B] = PIPE_B_OFFSET, \
- [TRANSCODER_C] = PIPE_C_OFFSET, \
- }, \
- .trans_offsets = { \
- [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
- }
-
-#define HSW_PIPE_OFFSETS \
- .pipe_offsets = { \
- [TRANSCODER_A] = PIPE_A_OFFSET, \
- [TRANSCODER_B] = PIPE_B_OFFSET, \
- [TRANSCODER_C] = PIPE_C_OFFSET, \
- [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
- }, \
- .trans_offsets = { \
- [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
- [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
- }
-
-#define CHV_PIPE_OFFSETS \
- .pipe_offsets = { \
- [TRANSCODER_A] = PIPE_A_OFFSET, \
- [TRANSCODER_B] = PIPE_B_OFFSET, \
- [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
- }, \
- .trans_offsets = { \
- [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
- }
-
-#define I845_CURSOR_OFFSETS \
- .cursor_offsets = { \
- [PIPE_A] = CURSOR_A_OFFSET, \
- }
-
-#define I9XX_CURSOR_OFFSETS \
- .cursor_offsets = { \
- [PIPE_A] = CURSOR_A_OFFSET, \
- [PIPE_B] = CURSOR_B_OFFSET, \
- }
-
-#define CHV_CURSOR_OFFSETS \
- .cursor_offsets = { \
- [PIPE_A] = CURSOR_A_OFFSET, \
- [PIPE_B] = CURSOR_B_OFFSET, \
- [PIPE_C] = CHV_CURSOR_C_OFFSET, \
- }
-
-#define IVB_CURSOR_OFFSETS \
- .cursor_offsets = { \
- [PIPE_A] = CURSOR_A_OFFSET, \
- [PIPE_B] = IVB_CURSOR_B_OFFSET, \
- [PIPE_C] = IVB_CURSOR_C_OFFSET, \
- }
-
-#define TGL_CURSOR_OFFSETS \
- .cursor_offsets = { \
- [PIPE_A] = CURSOR_A_OFFSET, \
- [PIPE_B] = IVB_CURSOR_B_OFFSET, \
- [PIPE_C] = IVB_CURSOR_C_OFFSET, \
- [PIPE_D] = TGL_CURSOR_D_OFFSET, \
- }
-
-#define I845_COLORS \
- .color = { .gamma_lut_size = 256 }
-#define I9XX_COLORS \
- .color = { .gamma_lut_size = 129, \
- .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- }
-#define ILK_COLORS \
- .color = { .gamma_lut_size = 1024 }
-#define IVB_COLORS \
- .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
-#define CHV_COLORS \
- .color = { \
- .degamma_lut_size = 65, .gamma_lut_size = 257, \
- .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- }
-#define GLK_COLORS \
- .color = { \
- .degamma_lut_size = 33, .gamma_lut_size = 1024, \
- .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
- DRM_COLOR_LUT_EQUAL_CHANNELS, \
- }
-#define ICL_COLORS \
- .color = { \
- .degamma_lut_size = 33, .gamma_lut_size = 262145, \
- .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
- DRM_COLOR_LUT_EQUAL_CHANNELS, \
- .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- }
-
#define LEGACY_CACHELEVEL \
.cachelevel_to_pat = { \
[I915_CACHE_NONE] = 0, \
@@ -204,24 +83,6 @@ static const struct intel_display_device_info no_display = { 0 };
#define GEN_DEFAULT_REGIONS \
.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
-#define I830_DISPLAY \
- .has_overlay = 1, \
- .cursor_needs_physical = 1, \
- .overlay_needs_physical = 1, \
- .has_gmch = 1, \
- I9XX_PIPE_OFFSETS, \
- I9XX_CURSOR_OFFSETS, \
- I9XX_COLORS, \
- \
- .__runtime_defaults.ip.ver = 2, \
- .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
- .__runtime_defaults.cpu_transcoder_mask = \
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
-
-static const struct intel_display_device_info i830_display = {
- I830_DISPLAY,
-};
-
#define I830_FEATURES \
GEN(2), \
.is_mobile = 1, \
@@ -238,22 +99,6 @@ static const struct intel_display_device_info i830_display = {
GEN_DEFAULT_REGIONS, \
LEGACY_CACHELEVEL
-#define I845_DISPLAY \
- .has_overlay = 1, \
- .overlay_needs_physical = 1, \
- .has_gmch = 1, \
- I845_PIPE_OFFSETS, \
- I845_CURSOR_OFFSETS, \
- I845_COLORS, \
- \
- .__runtime_defaults.ip.ver = 2, \
- .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
- .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
-
-static const struct intel_display_device_info i845_display = {
- I845_DISPLAY,
-};
-
#define I845_FEATURES \
GEN(2), \
.has_3d_pipeline = 1, \
@@ -272,86 +117,21 @@ static const struct intel_display_device_info i845_display = {
static const struct intel_device_info i830_info = {
I830_FEATURES,
PLATFORM(INTEL_I830),
- .display = &i830_display,
};
static const struct intel_device_info i845g_info = {
I845_FEATURES,
PLATFORM(INTEL_I845G),
- .display = &i845_display,
-};
-
-static const struct intel_display_device_info i85x_display = {
- I830_DISPLAY,
-
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
static const struct intel_device_info i85x_info = {
I830_FEATURES,
PLATFORM(INTEL_I85X),
- .display = &i85x_display,
-};
-
-static const struct intel_display_device_info i865g_display = {
- I845_DISPLAY,
-
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
static const struct intel_device_info i865g_info = {
I845_FEATURES,
PLATFORM(INTEL_I865G),
- .display = &i865g_display,
-};
-
-#define GEN3_DISPLAY \
- .has_gmch = 1, \
- .has_overlay = 1, \
- I9XX_PIPE_OFFSETS, \
- I9XX_CURSOR_OFFSETS, \
- I9XX_COLORS, \
- \
- .__runtime_defaults.ip.ver = 3, \
- .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
- .__runtime_defaults.cpu_transcoder_mask = \
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
-
-static const struct intel_display_device_info i915g_display = {
- GEN3_DISPLAY,
- .cursor_needs_physical = 1,
- .overlay_needs_physical = 1,
-};
-
-static const struct intel_display_device_info i915gm_display = {
- GEN3_DISPLAY,
- .cursor_needs_physical = 1,
- .overlay_needs_physical = 1,
- .supports_tv = 1,
-
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
-};
-
-static const struct intel_display_device_info i945g_display = {
- GEN3_DISPLAY,
- .has_hotplug = 1,
- .cursor_needs_physical = 1,
- .overlay_needs_physical = 1,
-};
-
-static const struct intel_display_device_info i945gm_display = {
- GEN3_DISPLAY,
- .has_hotplug = 1,
- .cursor_needs_physical = 1,
- .overlay_needs_physical = 1,
- .supports_tv = 1,
-
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
-};
-
-static const struct intel_display_device_info g33_display = {
- GEN3_DISPLAY,
- .has_hotplug = 1,
};
#define GEN3_FEATURES \
@@ -370,7 +150,6 @@ static const struct intel_display_device_info g33_display = {
static const struct intel_device_info i915g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I915G),
- .display = &i915g_display,
.has_coherent_ggtt = false,
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
@@ -379,7 +158,6 @@ static const struct intel_device_info i915g_info = {
static const struct intel_device_info i915gm_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I915GM),
- .display = &i915gm_display,
.is_mobile = 1,
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
@@ -388,7 +166,6 @@ static const struct intel_device_info i915gm_info = {
static const struct intel_device_info i945g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I945G),
- .display = &i945g_display,
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -396,7 +173,6 @@ static const struct intel_device_info i945g_info = {
static const struct intel_device_info i945gm_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I945GM),
- .display = &i945gm_display,
.is_mobile = 1,
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
@@ -405,14 +181,12 @@ static const struct intel_device_info i945gm_info = {
static const struct intel_device_info g33_info = {
GEN3_FEATURES,
PLATFORM(INTEL_G33),
- .display = &g33_display,
.dma_mask_size = 36,
};
static const struct intel_device_info pnv_g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_PINEVIEW),
- .display = &g33_display,
.dma_mask_size = 36,
};
@@ -420,46 +194,9 @@ static const struct intel_device_info pnv_m_info = {
GEN3_FEATURES,
PLATFORM(INTEL_PINEVIEW),
.is_mobile = 1,
- .display = &g33_display,
.dma_mask_size = 36,
};
-#define GEN4_DISPLAY \
- .has_hotplug = 1, \
- .has_gmch = 1, \
- I9XX_PIPE_OFFSETS, \
- I9XX_CURSOR_OFFSETS, \
- I9XX_COLORS, \
- \
- .__runtime_defaults.ip.ver = 4, \
- .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
- .__runtime_defaults.cpu_transcoder_mask = \
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
-
-static const struct intel_display_device_info i965g_display = {
- GEN4_DISPLAY,
- .has_overlay = 1,
-};
-
-static const struct intel_display_device_info i965gm_display = {
- GEN4_DISPLAY,
- .has_overlay = 1,
- .supports_tv = 1,
-
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
-};
-
-static const struct intel_display_device_info g45_display = {
- GEN4_DISPLAY,
-};
-
-static const struct intel_display_device_info gm45_display = {
- GEN4_DISPLAY,
- .supports_tv = 1,
-
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
-};
-
#define GEN4_FEATURES \
GEN(4), \
.gpu_reset_clobbers_display = true, \
@@ -476,7 +213,6 @@ static const struct intel_display_device_info gm45_display = {
static const struct intel_device_info i965g_info = {
GEN4_FEATURES,
PLATFORM(INTEL_I965G),
- .display = &i965g_display,
.hws_needs_physical = 1,
.has_snoop = false,
};
@@ -484,7 +220,6 @@ static const struct intel_device_info i965g_info = {
static const struct intel_device_info i965gm_info = {
GEN4_FEATURES,
PLATFORM(INTEL_I965GM),
- .display = &i965gm_display,
.is_mobile = 1,
.hws_needs_physical = 1,
.has_snoop = false,
@@ -494,7 +229,6 @@ static const struct intel_device_info g45_info = {
GEN4_FEATURES,
PLATFORM(INTEL_G45),
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
- .display = &g45_display,
.gpu_reset_clobbers_display = false,
};
@@ -503,7 +237,6 @@ static const struct intel_device_info gm45_info = {
PLATFORM(INTEL_GM45),
.is_mobile = 1,
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
- .display = &gm45_display,
.gpu_reset_clobbers_display = false,
};
@@ -521,37 +254,14 @@ static const struct intel_device_info gm45_info = {
GEN_DEFAULT_REGIONS, \
LEGACY_CACHELEVEL
-#define ILK_DISPLAY \
- .has_hotplug = 1, \
- I9XX_PIPE_OFFSETS, \
- I9XX_CURSOR_OFFSETS, \
- ILK_COLORS, \
- \
- .__runtime_defaults.ip.ver = 5, \
- .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
- .__runtime_defaults.cpu_transcoder_mask = \
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
-
-static const struct intel_display_device_info ilk_d_display = {
- ILK_DISPLAY,
-};
-
static const struct intel_device_info ilk_d_info = {
GEN5_FEATURES,
PLATFORM(INTEL_IRONLAKE),
- .display = &ilk_d_display,
-};
-
-static const struct intel_display_device_info ilk_m_display = {
- ILK_DISPLAY,
-
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
static const struct intel_device_info ilk_m_info = {
GEN5_FEATURES,
PLATFORM(INTEL_IRONLAKE),
- .display = &ilk_m_display,
.is_mobile = 1,
.has_rps = true,
};
@@ -574,32 +284,17 @@ static const struct intel_device_info ilk_m_info = {
GEN_DEFAULT_REGIONS, \
LEGACY_CACHELEVEL
-static const struct intel_display_device_info snb_display = {
- .has_hotplug = 1,
- I9XX_PIPE_OFFSETS,
- I9XX_CURSOR_OFFSETS,
- ILK_COLORS,
-
- .__runtime_defaults.ip.ver = 6,
- .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
- .__runtime_defaults.cpu_transcoder_mask =
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
-};
-
#define SNB_D_PLATFORM \
GEN6_FEATURES, \
PLATFORM(INTEL_SANDYBRIDGE)
static const struct intel_device_info snb_d_gt1_info = {
SNB_D_PLATFORM,
- .display = &snb_display,
.gt = 1,
};
static const struct intel_device_info snb_d_gt2_info = {
SNB_D_PLATFORM,
- .display = &snb_display,
.gt = 2,
};
@@ -611,13 +306,11 @@ static const struct intel_device_info snb_d_gt2_info = {
static const struct intel_device_info snb_m_gt1_info = {
SNB_M_PLATFORM,
- .display = &snb_display,
.gt = 1,
};
static const struct intel_device_info snb_m_gt2_info = {
SNB_M_PLATFORM,
- .display = &snb_display,
.gt = 2,
};
@@ -644,28 +337,13 @@ static const struct intel_device_info snb_m_gt2_info = {
PLATFORM(INTEL_IVYBRIDGE), \
.has_l3_dpf = 1
-static const struct intel_display_device_info ivb_display = {
- .has_hotplug = 1,
- IVB_PIPE_OFFSETS,
- IVB_CURSOR_OFFSETS,
- IVB_COLORS,
-
- .__runtime_defaults.ip.ver = 7,
- .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
- .__runtime_defaults.cpu_transcoder_mask =
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
-};
-
static const struct intel_device_info ivb_d_gt1_info = {
IVB_D_PLATFORM,
- .display = &ivb_display,
.gt = 1,
};
static const struct intel_device_info ivb_d_gt2_info = {
IVB_D_PLATFORM,
- .display = &ivb_display,
.gt = 2,
};
@@ -677,43 +355,25 @@ static const struct intel_device_info ivb_d_gt2_info = {
static const struct intel_device_info ivb_m_gt1_info = {
IVB_M_PLATFORM,
- .display = &ivb_display,
.gt = 1,
};
static const struct intel_device_info ivb_m_gt2_info = {
IVB_M_PLATFORM,
- .display = &ivb_display,
.gt = 2,
};
static const struct intel_device_info ivb_q_info = {
GEN7_FEATURES,
PLATFORM(INTEL_IVYBRIDGE),
- .display = &no_display,
.gt = 2,
.has_l3_dpf = 1,
};
-static const struct intel_display_device_info vlv_display = {
- .has_gmch = 1,
- .has_hotplug = 1,
- .mmio_offset = VLV_DISPLAY_BASE,
- I9XX_PIPE_OFFSETS,
- I9XX_CURSOR_OFFSETS,
- I9XX_COLORS,
-
- .__runtime_defaults.ip.ver = 7,
- .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
- .__runtime_defaults.cpu_transcoder_mask =
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
-};
-
static const struct intel_device_info vlv_info = {
PLATFORM(INTEL_VALLEYVIEW),
GEN(7),
.is_lp = 1,
- .display = &vlv_display,
.has_runtime_pm = 1,
.has_rc6 = 1,
.has_reset_engine = true,
@@ -741,38 +401,18 @@ static const struct intel_device_info vlv_info = {
PLATFORM(INTEL_HASWELL), \
.has_l3_dpf = 1
-static const struct intel_display_device_info hsw_display = {
- .has_ddi = 1,
- .has_dp_mst = 1,
- .has_fpga_dbg = 1,
- .has_hotplug = 1,
- HSW_PIPE_OFFSETS,
- IVB_CURSOR_OFFSETS,
- IVB_COLORS,
-
- .__runtime_defaults.ip.ver = 7,
- .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
- .__runtime_defaults.cpu_transcoder_mask =
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
-};
-
static const struct intel_device_info hsw_gt1_info = {
HSW_PLATFORM,
- .display = &hsw_display,
.gt = 1,
};
static const struct intel_device_info hsw_gt2_info = {
HSW_PLATFORM,
- .display = &hsw_display,
.gt = 2,
};
static const struct intel_device_info hsw_gt3_info = {
HSW_PLATFORM,
- .display = &hsw_display,
.gt = 3,
};
@@ -785,42 +425,22 @@ static const struct intel_device_info hsw_gt3_info = {
.__runtime.ppgtt_size = 48, \
.has_64bit_reloc = 1
-static const struct intel_display_device_info bdw_display = {
- .has_ddi = 1,
- .has_dp_mst = 1,
- .has_fpga_dbg = 1,
- .has_hotplug = 1,
- HSW_PIPE_OFFSETS,
- IVB_CURSOR_OFFSETS,
- IVB_COLORS,
-
- .__runtime_defaults.ip.ver = 8,
- .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
- .__runtime_defaults.cpu_transcoder_mask =
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
-};
-
#define BDW_PLATFORM \
GEN8_FEATURES, \
PLATFORM(INTEL_BROADWELL)
static const struct intel_device_info bdw_gt1_info = {
BDW_PLATFORM,
- .display = &bdw_display,
.gt = 1,
};
static const struct intel_device_info bdw_gt2_info = {
BDW_PLATFORM,
- .display = &bdw_display,
.gt = 2,
};
static const struct intel_device_info bdw_rsvd_info = {
BDW_PLATFORM,
- .display = &bdw_display,
.gt = 3,
/* According to the device ID those devices are GT3, they were
* previously treated as not GT3, keep it like that.
@@ -829,30 +449,14 @@ static const struct intel_device_info bdw_rsvd_info = {
static const struct intel_device_info bdw_gt3_info = {
BDW_PLATFORM,
- .display = &bdw_display,
.gt = 3,
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
};
-static const struct intel_display_device_info chv_display = {
- .has_hotplug = 1,
- .has_gmch = 1,
- .mmio_offset = VLV_DISPLAY_BASE,
- CHV_PIPE_OFFSETS,
- CHV_CURSOR_OFFSETS,
- CHV_COLORS,
-
- .__runtime_defaults.ip.ver = 8,
- .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
- .__runtime_defaults.cpu_transcoder_mask =
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
-};
-
static const struct intel_device_info chv_info = {
PLATFORM(INTEL_CHERRYVIEW),
GEN(8),
- .display = &chv_display,
.is_lp = 1,
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
.has_64bit_reloc = 1,
@@ -882,43 +486,17 @@ static const struct intel_device_info chv_info = {
GEN9_DEFAULT_PAGE_SIZES, \
.has_gt_uc = 1
-static const struct intel_display_device_info skl_display = {
- .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
- .dbuf.slice_mask = BIT(DBUF_S1),
- .has_ddi = 1,
- .has_dp_mst = 1,
- .has_fpga_dbg = 1,
- .has_hotplug = 1,
- .has_ipc = 1,
- .has_psr = 1,
- .has_psr_hw_tracking = 1,
- HSW_PIPE_OFFSETS,
- IVB_CURSOR_OFFSETS,
- IVB_COLORS,
-
- .__runtime_defaults.ip.ver = 9,
- .__runtime_defaults.has_dmc = 1,
- .__runtime_defaults.has_hdcp = 1,
- .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
- .__runtime_defaults.cpu_transcoder_mask =
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
-};
-
#define SKL_PLATFORM \
GEN9_FEATURES, \
PLATFORM(INTEL_SKYLAKE)
static const struct intel_device_info skl_gt1_info = {
SKL_PLATFORM,
- .display = &skl_display,
.gt = 1,
};
static const struct intel_device_info skl_gt2_info = {
SKL_PLATFORM,
- .display = &skl_display,
.gt = 2,
};
@@ -930,13 +508,11 @@ static const struct intel_device_info skl_gt2_info = {
static const struct intel_device_info skl_gt3_info = {
SKL_GT3_PLUS_PLATFORM,
- .display = &skl_display,
.gt = 3,
};
static const struct intel_device_info skl_gt4_info = {
SKL_GT3_PLUS_PLATFORM,
- .display = &skl_display,
.gt = 4,
};
@@ -962,53 +538,14 @@ static const struct intel_device_info skl_gt4_info = {
GEN_DEFAULT_REGIONS, \
LEGACY_CACHELEVEL
-#define GEN9_LP_DISPLAY \
- .dbuf.slice_mask = BIT(DBUF_S1), \
- .has_dp_mst = 1, \
- .has_ddi = 1, \
- .has_fpga_dbg = 1, \
- .has_hotplug = 1, \
- .has_ipc = 1, \
- .has_psr = 1, \
- .has_psr_hw_tracking = 1, \
- HSW_PIPE_OFFSETS, \
- IVB_CURSOR_OFFSETS, \
- IVB_COLORS, \
- \
- .__runtime_defaults.has_dmc = 1, \
- .__runtime_defaults.has_hdcp = 1, \
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
- .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
- .__runtime_defaults.cpu_transcoder_mask = \
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
- BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
- BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C)
-
-static const struct intel_display_device_info bxt_display = {
- GEN9_LP_DISPLAY,
- .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
-
- .__runtime_defaults.ip.ver = 9,
-};
-
static const struct intel_device_info bxt_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_BROXTON),
- .display = &bxt_display,
-};
-
-static const struct intel_display_device_info glk_display = {
- GEN9_LP_DISPLAY,
- .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
- GLK_COLORS,
-
- .__runtime_defaults.ip.ver = 10,
};
static const struct intel_device_info glk_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_GEMINILAKE),
- .display = &glk_display,
};
#define KBL_PLATFORM \
@@ -1017,19 +554,16 @@ static const struct intel_device_info glk_info = {
static const struct intel_device_info kbl_gt1_info = {
KBL_PLATFORM,
- .display = &skl_display,
.gt = 1,
};
static const struct intel_device_info kbl_gt2_info = {
KBL_PLATFORM,
- .display = &skl_display,
.gt = 2,
};
static const struct intel_device_info kbl_gt3_info = {
KBL_PLATFORM,
- .display = &skl_display,
.gt = 3,
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
@@ -1041,19 +575,16 @@ static const struct intel_device_info kbl_gt3_info = {
static const struct intel_device_info cfl_gt1_info = {
CFL_PLATFORM,
- .display = &skl_display,
.gt = 1,
};
static const struct intel_device_info cfl_gt2_info = {
CFL_PLATFORM,
- .display = &skl_display,
.gt = 2,
};
static const struct intel_device_info cfl_gt3_info = {
CFL_PLATFORM,
- .display = &skl_display,
.gt = 3,
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
@@ -1065,13 +596,11 @@ static const struct intel_device_info cfl_gt3_info = {
static const struct intel_device_info cml_gt1_info = {
CML_PLATFORM,
- .display = &skl_display,
.gt = 1,
};
static const struct intel_device_info cml_gt2_info = {
CML_PLATFORM,
- .display = &skl_display,
.gt = 2,
};
@@ -1087,54 +616,11 @@ static const struct intel_device_info cml_gt2_info = {
.has_coherent_ggtt = false, \
.has_logical_ring_elsq = 1
-static const struct intel_display_device_info gen11_display = {
- .abox_mask = BIT(0),
- .dbuf.size = 2048,
- .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2),
- .has_ddi = 1,
- .has_dp_mst = 1,
- .has_fpga_dbg = 1,
- .has_hotplug = 1,
- .has_ipc = 1,
- .has_psr = 1,
- .has_psr_hw_tracking = 1,
- .pipe_offsets = {
- [TRANSCODER_A] = PIPE_A_OFFSET,
- [TRANSCODER_B] = PIPE_B_OFFSET,
- [TRANSCODER_C] = PIPE_C_OFFSET,
- [TRANSCODER_EDP] = PIPE_EDP_OFFSET,
- [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
- [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
- },
- .trans_offsets = {
- [TRANSCODER_A] = TRANSCODER_A_OFFSET,
- [TRANSCODER_B] = TRANSCODER_B_OFFSET,
- [TRANSCODER_C] = TRANSCODER_C_OFFSET,
- [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET,
- [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
- [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
- },
- IVB_CURSOR_OFFSETS,
- ICL_COLORS,
-
- .__runtime_defaults.ip.ver = 11,
- .__runtime_defaults.has_dmc = 1,
- .__runtime_defaults.has_dsc = 1, \
- .__runtime_defaults.has_hdcp = 1,
- .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
- .__runtime_defaults.cpu_transcoder_mask =
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) |
- BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
-};
-
static const struct intel_device_info icl_info = {
GEN11_FEATURES,
PLATFORM(INTEL_ICELAKE),
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
- .display = &gen11_display,
};
static const struct intel_device_info ehl_info = {
@@ -1142,7 +628,6 @@ static const struct intel_device_info ehl_info = {
PLATFORM(INTEL_ELKHARTLAKE),
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
.__runtime.ppgtt_size = 36,
- .display = &gen11_display,
};
static const struct intel_device_info jsl_info = {
@@ -1150,7 +635,6 @@ static const struct intel_device_info jsl_info = {
PLATFORM(INTEL_JASPERLAKE),
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
.__runtime.ppgtt_size = 36,
- .display = &gen11_display,
};
#define GEN12_FEATURES \
@@ -1161,70 +645,11 @@ static const struct intel_device_info jsl_info = {
.has_pxp = 1, \
.max_pat_index = 3
-#define XE_D_DISPLAY \
- .abox_mask = GENMASK(2, 1), \
- .dbuf.size = 2048, \
- .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
- .has_ddi = 1, \
- .has_dp_mst = 1, \
- .has_dsb = 1, \
- .has_fpga_dbg = 1, \
- .has_hotplug = 1, \
- .has_ipc = 1, \
- .has_psr = 1, \
- .has_psr_hw_tracking = 1, \
- .pipe_offsets = { \
- [TRANSCODER_A] = PIPE_A_OFFSET, \
- [TRANSCODER_B] = PIPE_B_OFFSET, \
- [TRANSCODER_C] = PIPE_C_OFFSET, \
- [TRANSCODER_D] = PIPE_D_OFFSET, \
- [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
- [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
- }, \
- .trans_offsets = { \
- [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
- [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
- [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
- [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
- }, \
- TGL_CURSOR_OFFSETS, \
- ICL_COLORS, \
- \
- .__runtime_defaults.ip.ver = 12, \
- .__runtime_defaults.has_dmc = 1, \
- .__runtime_defaults.has_dsc = 1, \
- .__runtime_defaults.has_hdcp = 1, \
- .__runtime_defaults.pipe_mask = \
- BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
- .__runtime_defaults.cpu_transcoder_mask = \
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
- BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
-
-static const struct intel_display_device_info tgl_display = {
- XE_D_DISPLAY,
-};
-
static const struct intel_device_info tgl_info = {
GEN12_FEATURES,
PLATFORM(INTEL_TIGERLAKE),
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
- .display = &tgl_display,
-};
-
-static const struct intel_display_device_info rkl_display = {
- XE_D_DISPLAY,
- .abox_mask = BIT(0),
- .has_hti = 1,
- .has_psr_hw_tracking = 0,
-
- .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
- .__runtime_defaults.cpu_transcoder_mask =
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
};
static const struct intel_device_info rkl_info = {
@@ -1232,7 +657,6 @@ static const struct intel_device_info rkl_info = {
PLATFORM(INTEL_ROCKETLAKE),
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
- .display = &rkl_display,
};
#define DGFX_FEATURES \
@@ -1254,13 +678,6 @@ static const struct intel_device_info dg1_info = {
BIT(VCS0) | BIT(VCS2),
/* Wa_16011227922 */
.__runtime.ppgtt_size = 47,
- .display = &tgl_display,
-};
-
-static const struct intel_display_device_info adl_s_display = {
- XE_D_DISPLAY,
- .has_hti = 1,
- .has_psr_hw_tracking = 0,
};
static const struct intel_device_info adl_s_info = {
@@ -1269,61 +686,6 @@ static const struct intel_device_info adl_s_info = {
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.dma_mask_size = 39,
- .display = &adl_s_display,
-};
-
-#define XE_LPD_FEATURES \
- .abox_mask = GENMASK(1, 0), \
- .color = { \
- .degamma_lut_size = 129, .gamma_lut_size = 1024, \
- .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
- DRM_COLOR_LUT_EQUAL_CHANNELS, \
- }, \
- .dbuf.size = 4096, \
- .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
- BIT(DBUF_S4), \
- .has_ddi = 1, \
- .has_dp_mst = 1, \
- .has_dsb = 1, \
- .has_fpga_dbg = 1, \
- .has_hotplug = 1, \
- .has_ipc = 1, \
- .has_psr = 1, \
- .pipe_offsets = { \
- [TRANSCODER_A] = PIPE_A_OFFSET, \
- [TRANSCODER_B] = PIPE_B_OFFSET, \
- [TRANSCODER_C] = PIPE_C_OFFSET, \
- [TRANSCODER_D] = PIPE_D_OFFSET, \
- [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
- [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
- }, \
- .trans_offsets = { \
- [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
- [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
- [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
- [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
- }, \
- TGL_CURSOR_OFFSETS, \
- \
- .__runtime_defaults.ip.ver = 13, \
- .__runtime_defaults.has_dmc = 1, \
- .__runtime_defaults.has_dsc = 1, \
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
- .__runtime_defaults.has_hdcp = 1, \
- .__runtime_defaults.pipe_mask = \
- BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
-
-static const struct intel_display_device_info xe_lpd_display = {
- XE_LPD_FEATURES,
- .has_cdclk_crawl = 1,
- .has_psr_hw_tracking = 0,
-
- .__runtime_defaults.cpu_transcoder_mask =
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
- BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
};
static const struct intel_device_info adl_p_info = {
@@ -1332,7 +694,6 @@ static const struct intel_device_info adl_p_info = {
.__runtime.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.__runtime.ppgtt_size = 48,
- .display = &xe_lpd_display,
.dma_mask_size = 39,
};
@@ -1380,7 +741,6 @@ static const struct intel_device_info xehpsdv_info = {
XE_HPM_FEATURES,
DGFX_FEATURES,
PLATFORM(INTEL_XEHPSDV),
- .display = &no_display,
.has_64k_pages = 1,
.has_media_ratio_mode = 1,
.__runtime.platform_engine_mask =
@@ -1409,23 +769,12 @@ static const struct intel_device_info xehpsdv_info = {
BIT(VCS0) | BIT(VCS2) | \
BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
-static const struct intel_display_device_info xe_hpd_display = {
- XE_LPD_FEATURES,
- .has_cdclk_squash = 1,
-
- .__runtime_defaults.cpu_transcoder_mask =
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
-};
-
static const struct intel_device_info dg2_info = {
DG2_FEATURES,
- .display = &xe_hpd_display,
};
static const struct intel_device_info ats_m_info = {
DG2_FEATURES,
- .display = &no_display,
.require_force_probe = 1,
.tuning_thread_rr_after_dep = 1,
};
@@ -1447,7 +796,6 @@ static const struct intel_device_info pvc_info = {
.__runtime.graphics.ip.rel = 60,
.__runtime.media.ip.rel = 60,
PLATFORM(INTEL_PONTEVECCHIO),
- .display = &no_display,
.has_flat_ccs = 0,
.max_pat_index = 7,
.__runtime.platform_engine_mask =
@@ -1468,18 +816,6 @@ static const struct intel_gt_definition xelpmp_extra_gt[] = {
{}
};
-static const struct intel_display_device_info xe_lpdp_display = {
- XE_LPD_FEATURES,
- .has_cdclk_crawl = 1,
- .has_cdclk_squash = 1,
-
- .__runtime_defaults.ip.ver = 14,
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
- .__runtime_defaults.cpu_transcoder_mask =
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
-};
-
static const struct intel_device_info mtl_info = {
XE_HP_FEATURES,
/*
@@ -1490,7 +826,6 @@ static const struct intel_device_info mtl_info = {
.__runtime.graphics.ip.rel = 70,
.__runtime.media.ip.ver = 13,
PLATFORM(INTEL_METEORLAKE),
- .display = &xe_lpdp_display,
.extra_gt_list = xelpmp_extra_gt,
.has_flat_ccs = 0,
.has_gmd_id = 1,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2a9ab8de8421..f1ba1eae26ca 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1966,15 +1966,6 @@
#define _TRANS_VSYNC_DSI1 0x6b814
#define _TRANS_VSYNCSHIFT_DSI1 0x6b828
-#define TRANSCODER_A_OFFSET 0x60000
-#define TRANSCODER_B_OFFSET 0x61000
-#define TRANSCODER_C_OFFSET 0x62000
-#define CHV_TRANSCODER_C_OFFSET 0x63000
-#define TRANSCODER_D_OFFSET 0x63000
-#define TRANSCODER_EDP_OFFSET 0x6f000
-#define TRANSCODER_DSI0_OFFSET 0x6b000
-#define TRANSCODER_DSI1_OFFSET 0x6b800
-
#define TRANS_HTOTAL(trans) _MMIO_TRANS2((trans), _TRANS_HTOTAL_A)
#define TRANS_HBLANK(trans) _MMIO_TRANS2((trans), _TRANS_HBLANK_A)
#define TRANS_HSYNC(trans) _MMIO_TRANS2((trans), _TRANS_HSYNC_A)
@@ -2622,23 +2613,6 @@
#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
-#define PIPE_A_OFFSET 0x70000
-#define PIPE_B_OFFSET 0x71000
-#define PIPE_C_OFFSET 0x72000
-#define PIPE_D_OFFSET 0x73000
-#define CHV_PIPE_C_OFFSET 0x74000
-/*
- * There's actually no pipe EDP. Some pipe registers have
- * simply shifted from the pipe to the transcoder, while
- * keeping their original offset. Thus we need PIPE_EDP_OFFSET
- * to access such registers in transcoder EDP.
- */
-#define PIPE_EDP_OFFSET 0x7f000
-
-/* ICL DSI 0 and 1 */
-#define PIPE_DSI0_OFFSET 0x7b000
-#define PIPE_DSI1_OFFSET 0x7b800
-
#define TRANSCONF(trans) _MMIO_PIPE2((trans), _TRANSACONF)
#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
@@ -3099,13 +3073,6 @@
#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(pipe, _CUR_CHICKEN_A)
#define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE)
-#define CURSOR_A_OFFSET 0x70080
-#define CURSOR_B_OFFSET 0x700c0
-#define CHV_CURSOR_C_OFFSET 0x700e0
-#define IVB_CURSOR_B_OFFSET 0x71080
-#define IVB_CURSOR_C_OFFSET 0x72080
-#define TGL_CURSOR_D_OFFSET 0x73080
-
/* Display A control */
#define _DSPAADDR_VLV 0x7017C /* vlv/chv */
#define _DSPACNTR 0x70180
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 4d158927c78b..e1507ae59f2d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -574,7 +574,6 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
{
struct intel_device_info *info;
struct intel_runtime_info *runtime;
- struct intel_display_runtime_info *display_runtime;
/* Setup the write-once "constant" device info */
info = mkwrite_device_info(i915);
@@ -583,9 +582,10 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
/* Initialize initial runtime info from static const data and pdev. */
runtime = RUNTIME_INFO(i915);
memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
- display_runtime = DISPLAY_RUNTIME_INFO(i915);
- memcpy(display_runtime, &DISPLAY_INFO(i915)->__runtime_defaults,
- sizeof(*display_runtime));
+
+ /* Probe display support */
+ info->display = intel_display_device_probe(device_id);
+ *DISPLAY_RUNTIME_INFO(i915) = DISPLAY_INFO(i915)->__runtime_defaults;
runtime->device_id = device_id;
}
--
2.40.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH v2 4/6] drm/i915/display: Make display responsible for probing its own IP
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 4/6] drm/i915/display: Make display responsible for probing its own IP Matt Roper
@ 2023-05-23 7:51 ` Andrzej Hajda
2023-05-23 12:58 ` [Intel-gfx] [Intel-xe] " Jani Nikula
1 sibling, 0 replies; 22+ messages in thread
From: Andrzej Hajda @ 2023-05-23 7:51 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: intel-xe
On 22.05.2023 22:23, Matt Roper wrote:
> Rather than selecting the display IP and feature flags at the same time
> the general PCI probing happens, move this step into the display code
> itself so that it can be more easily re-used outside of i915 (i.e., by
> the Xe driver).
>
> v2:
> - Make intel_display_device_probe() always return a non-NULL pointer
> and simplify copying of runtime_defaults. (Andrzej)
>
> Cc: Andrzej Hajda <andrzej.hajda@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Regards
Andrzej
> ---
> drivers/gpu/drm/i915/Makefile | 2 +
> .../drm/i915/display/intel_display_device.c | 710 ++++++++++++++++++
> .../drm/i915/display/intel_display_device.h | 3 +
> drivers/gpu/drm/i915/i915_pci.c | 665 ----------------
> drivers/gpu/drm/i915/i915_reg.h | 33 -
> drivers/gpu/drm/i915/intel_device_info.c | 8 +-
> 6 files changed, 719 insertions(+), 702 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index dd9ca69f4998..06374fc072d3 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -25,6 +25,7 @@ subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
>
> # Fine grained warnings disable
> CFLAGS_i915_pci.o = $(call cc-disable-warning, override-init)
> +CFLAGS_display/intel_display_device.o = $(call cc-disable-warning, override-init)
> CFLAGS_display/intel_fbdev.o = $(call cc-disable-warning, override-init)
>
> subdir-ccflags-y += -I$(srctree)/$(src)
> @@ -308,6 +309,7 @@ i915-y += \
> display/intel_cx0_phy.o \
> display/intel_ddi.o \
> display/intel_ddi_buf_trans.o \
> + display/intel_display_device.o \
> display/intel_display_trace.o \
> display/intel_dkl_phy.o \
> display/intel_dp.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> new file mode 100644
> index 000000000000..3c5941c8788d
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -0,0 +1,710 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#include <drm/i915_pciids.h>
> +#include <drm/drm_color_mgmt.h>
> +#include <linux/mod_devicetable.h>
> +
> +#include "intel_display_device.h"
> +#include "intel_display_power.h"
> +#include "intel_display_reg_defs.h"
> +#include "intel_fbc.h"
> +
> +static const struct intel_display_device_info no_display = { 0 };
> +
> +#define PIPE_A_OFFSET 0x70000
> +#define PIPE_B_OFFSET 0x71000
> +#define PIPE_C_OFFSET 0x72000
> +#define PIPE_D_OFFSET 0x73000
> +#define CHV_PIPE_C_OFFSET 0x74000
> +/*
> + * There's actually no pipe EDP. Some pipe registers have
> + * simply shifted from the pipe to the transcoder, while
> + * keeping their original offset. Thus we need PIPE_EDP_OFFSET
> + * to access such registers in transcoder EDP.
> + */
> +#define PIPE_EDP_OFFSET 0x7f000
> +
> +/* ICL DSI 0 and 1 */
> +#define PIPE_DSI0_OFFSET 0x7b000
> +#define PIPE_DSI1_OFFSET 0x7b800
> +
> +#define TRANSCODER_A_OFFSET 0x60000
> +#define TRANSCODER_B_OFFSET 0x61000
> +#define TRANSCODER_C_OFFSET 0x62000
> +#define CHV_TRANSCODER_C_OFFSET 0x63000
> +#define TRANSCODER_D_OFFSET 0x63000
> +#define TRANSCODER_EDP_OFFSET 0x6f000
> +#define TRANSCODER_DSI0_OFFSET 0x6b000
> +#define TRANSCODER_DSI1_OFFSET 0x6b800
> +
> +#define CURSOR_A_OFFSET 0x70080
> +#define CURSOR_B_OFFSET 0x700c0
> +#define CHV_CURSOR_C_OFFSET 0x700e0
> +#define IVB_CURSOR_B_OFFSET 0x71080
> +#define IVB_CURSOR_C_OFFSET 0x72080
> +#define TGL_CURSOR_D_OFFSET 0x73080
> +
> +#define I845_PIPE_OFFSETS \
> + .pipe_offsets = { \
> + [TRANSCODER_A] = PIPE_A_OFFSET, \
> + }, \
> + .trans_offsets = { \
> + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> + }
> +
> +#define I9XX_PIPE_OFFSETS \
> + .pipe_offsets = { \
> + [TRANSCODER_A] = PIPE_A_OFFSET, \
> + [TRANSCODER_B] = PIPE_B_OFFSET, \
> + }, \
> + .trans_offsets = { \
> + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> + }
> +
> +#define IVB_PIPE_OFFSETS \
> + .pipe_offsets = { \
> + [TRANSCODER_A] = PIPE_A_OFFSET, \
> + [TRANSCODER_B] = PIPE_B_OFFSET, \
> + [TRANSCODER_C] = PIPE_C_OFFSET, \
> + }, \
> + .trans_offsets = { \
> + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> + [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> + }
> +
> +#define HSW_PIPE_OFFSETS \
> + .pipe_offsets = { \
> + [TRANSCODER_A] = PIPE_A_OFFSET, \
> + [TRANSCODER_B] = PIPE_B_OFFSET, \
> + [TRANSCODER_C] = PIPE_C_OFFSET, \
> + [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
> + }, \
> + .trans_offsets = { \
> + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> + [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> + [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
> + }
> +
> +#define CHV_PIPE_OFFSETS \
> + .pipe_offsets = { \
> + [TRANSCODER_A] = PIPE_A_OFFSET, \
> + [TRANSCODER_B] = PIPE_B_OFFSET, \
> + [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
> + }, \
> + .trans_offsets = { \
> + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> + [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
> + }
> +
> +#define I845_CURSOR_OFFSETS \
> + .cursor_offsets = { \
> + [PIPE_A] = CURSOR_A_OFFSET, \
> + }
> +
> +#define I9XX_CURSOR_OFFSETS \
> + .cursor_offsets = { \
> + [PIPE_A] = CURSOR_A_OFFSET, \
> + [PIPE_B] = CURSOR_B_OFFSET, \
> + }
> +
> +#define CHV_CURSOR_OFFSETS \
> + .cursor_offsets = { \
> + [PIPE_A] = CURSOR_A_OFFSET, \
> + [PIPE_B] = CURSOR_B_OFFSET, \
> + [PIPE_C] = CHV_CURSOR_C_OFFSET, \
> + }
> +
> +#define IVB_CURSOR_OFFSETS \
> + .cursor_offsets = { \
> + [PIPE_A] = CURSOR_A_OFFSET, \
> + [PIPE_B] = IVB_CURSOR_B_OFFSET, \
> + [PIPE_C] = IVB_CURSOR_C_OFFSET, \
> + }
> +
> +#define TGL_CURSOR_OFFSETS \
> + .cursor_offsets = { \
> + [PIPE_A] = CURSOR_A_OFFSET, \
> + [PIPE_B] = IVB_CURSOR_B_OFFSET, \
> + [PIPE_C] = IVB_CURSOR_C_OFFSET, \
> + [PIPE_D] = TGL_CURSOR_D_OFFSET, \
> + }
> +
> +#define I845_COLORS \
> + .color = { .gamma_lut_size = 256 }
> +#define I9XX_COLORS \
> + .color = { .gamma_lut_size = 129, \
> + .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> + }
> +#define ILK_COLORS \
> + .color = { .gamma_lut_size = 1024 }
> +#define IVB_COLORS \
> + .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
> +#define CHV_COLORS \
> + .color = { \
> + .degamma_lut_size = 65, .gamma_lut_size = 257, \
> + .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> + .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> + }
> +#define GLK_COLORS \
> + .color = { \
> + .degamma_lut_size = 33, .gamma_lut_size = 1024, \
> + .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> + DRM_COLOR_LUT_EQUAL_CHANNELS, \
> + }
> +#define ICL_COLORS \
> + .color = { \
> + .degamma_lut_size = 33, .gamma_lut_size = 262145, \
> + .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> + DRM_COLOR_LUT_EQUAL_CHANNELS, \
> + .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> + }
> +
> +#define I830_DISPLAY \
> + .has_overlay = 1, \
> + .cursor_needs_physical = 1, \
> + .overlay_needs_physical = 1, \
> + .has_gmch = 1, \
> + I9XX_PIPE_OFFSETS, \
> + I9XX_CURSOR_OFFSETS, \
> + I9XX_COLORS, \
> + \
> + .__runtime_defaults.ip.ver = 2, \
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> + .__runtime_defaults.cpu_transcoder_mask = \
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
> +
> +static const struct intel_display_device_info i830_display = {
> + I830_DISPLAY,
> +};
> +
> +#define I845_DISPLAY \
> + .has_overlay = 1, \
> + .overlay_needs_physical = 1, \
> + .has_gmch = 1, \
> + I845_PIPE_OFFSETS, \
> + I845_CURSOR_OFFSETS, \
> + I845_COLORS, \
> + \
> + .__runtime_defaults.ip.ver = 2, \
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
> + .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
> +
> +static const struct intel_display_device_info i845_display = {
> + I845_DISPLAY,
> +};
> +
> +static const struct intel_display_device_info i85x_display = {
> + I830_DISPLAY,
> +
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info i865g_display = {
> + I845_DISPLAY,
> +
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +#define GEN3_DISPLAY \
> + .has_gmch = 1, \
> + .has_overlay = 1, \
> + I9XX_PIPE_OFFSETS, \
> + I9XX_CURSOR_OFFSETS, \
> + I9XX_COLORS, \
> + \
> + .__runtime_defaults.ip.ver = 3, \
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> + .__runtime_defaults.cpu_transcoder_mask = \
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
> +
> +static const struct intel_display_device_info i915g_display = {
> + GEN3_DISPLAY,
> + .cursor_needs_physical = 1,
> + .overlay_needs_physical = 1,
> +};
> +
> +static const struct intel_display_device_info i915gm_display = {
> + GEN3_DISPLAY,
> + .cursor_needs_physical = 1,
> + .overlay_needs_physical = 1,
> + .supports_tv = 1,
> +
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info i945g_display = {
> + GEN3_DISPLAY,
> + .has_hotplug = 1,
> + .cursor_needs_physical = 1,
> + .overlay_needs_physical = 1,
> +};
> +
> +static const struct intel_display_device_info i945gm_display = {
> + GEN3_DISPLAY,
> + .has_hotplug = 1,
> + .cursor_needs_physical = 1,
> + .overlay_needs_physical = 1,
> + .supports_tv = 1,
> +
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info g33_display = {
> + GEN3_DISPLAY,
> + .has_hotplug = 1,
> +};
> +
> +#define GEN4_DISPLAY \
> + .has_hotplug = 1, \
> + .has_gmch = 1, \
> + I9XX_PIPE_OFFSETS, \
> + I9XX_CURSOR_OFFSETS, \
> + I9XX_COLORS, \
> + \
> + .__runtime_defaults.ip.ver = 4, \
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> + .__runtime_defaults.cpu_transcoder_mask = \
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
> +
> +static const struct intel_display_device_info i965g_display = {
> + GEN4_DISPLAY,
> + .has_overlay = 1,
> +};
> +
> +static const struct intel_display_device_info i965gm_display = {
> + GEN4_DISPLAY,
> + .has_overlay = 1,
> + .supports_tv = 1,
> +
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info g45_display = {
> + GEN4_DISPLAY,
> +};
> +
> +static const struct intel_display_device_info gm45_display = {
> + GEN4_DISPLAY,
> + .supports_tv = 1,
> +
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +#define ILK_DISPLAY \
> + .has_hotplug = 1, \
> + I9XX_PIPE_OFFSETS, \
> + I9XX_CURSOR_OFFSETS, \
> + ILK_COLORS, \
> + \
> + .__runtime_defaults.ip.ver = 5, \
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> + .__runtime_defaults.cpu_transcoder_mask = \
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
> +
> +static const struct intel_display_device_info ilk_d_display = {
> + ILK_DISPLAY,
> +};
> +
> +static const struct intel_display_device_info ilk_m_display = {
> + ILK_DISPLAY,
> +
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info snb_display = {
> + .has_hotplug = 1,
> + I9XX_PIPE_OFFSETS,
> + I9XX_CURSOR_OFFSETS,
> + ILK_COLORS,
> +
> + .__runtime_defaults.ip.ver = 6,
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info ivb_display = {
> + .has_hotplug = 1,
> + IVB_PIPE_OFFSETS,
> + IVB_CURSOR_OFFSETS,
> + IVB_COLORS,
> +
> + .__runtime_defaults.ip.ver = 7,
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info vlv_display = {
> + .has_gmch = 1,
> + .has_hotplug = 1,
> + .mmio_offset = VLV_DISPLAY_BASE,
> + I9XX_PIPE_OFFSETS,
> + I9XX_CURSOR_OFFSETS,
> + I9XX_COLORS,
> +
> + .__runtime_defaults.ip.ver = 7,
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> +};
> +
> +static const struct intel_display_device_info hsw_display = {
> + .has_ddi = 1,
> + .has_dp_mst = 1,
> + .has_fpga_dbg = 1,
> + .has_hotplug = 1,
> + HSW_PIPE_OFFSETS,
> + IVB_CURSOR_OFFSETS,
> + IVB_COLORS,
> +
> + .__runtime_defaults.ip.ver = 7,
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info bdw_display = {
> + .has_ddi = 1,
> + .has_dp_mst = 1,
> + .has_fpga_dbg = 1,
> + .has_hotplug = 1,
> + HSW_PIPE_OFFSETS,
> + IVB_CURSOR_OFFSETS,
> + IVB_COLORS,
> +
> + .__runtime_defaults.ip.ver = 8,
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +static const struct intel_display_device_info chv_display = {
> + .has_hotplug = 1,
> + .has_gmch = 1,
> + .mmio_offset = VLV_DISPLAY_BASE,
> + CHV_PIPE_OFFSETS,
> + CHV_CURSOR_OFFSETS,
> + CHV_COLORS,
> +
> + .__runtime_defaults.ip.ver = 8,
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
> +};
> +
> +static const struct intel_display_device_info skl_display = {
> + .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
> + .dbuf.slice_mask = BIT(DBUF_S1),
> + .has_ddi = 1,
> + .has_dp_mst = 1,
> + .has_fpga_dbg = 1,
> + .has_hotplug = 1,
> + .has_ipc = 1,
> + .has_psr = 1,
> + .has_psr_hw_tracking = 1,
> + HSW_PIPE_OFFSETS,
> + IVB_CURSOR_OFFSETS,
> + IVB_COLORS,
> +
> + .__runtime_defaults.ip.ver = 9,
> + .__runtime_defaults.has_dmc = 1,
> + .__runtime_defaults.has_hdcp = 1,
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +#define GEN9_LP_DISPLAY \
> + .dbuf.slice_mask = BIT(DBUF_S1), \
> + .has_dp_mst = 1, \
> + .has_ddi = 1, \
> + .has_fpga_dbg = 1, \
> + .has_hotplug = 1, \
> + .has_ipc = 1, \
> + .has_psr = 1, \
> + .has_psr_hw_tracking = 1, \
> + HSW_PIPE_OFFSETS, \
> + IVB_CURSOR_OFFSETS, \
> + IVB_COLORS, \
> + \
> + .__runtime_defaults.has_dmc = 1, \
> + .__runtime_defaults.has_hdcp = 1, \
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> + .__runtime_defaults.cpu_transcoder_mask = \
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
> + BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C)
> +
> +static const struct intel_display_device_info bxt_display = {
> + GEN9_LP_DISPLAY,
> + .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
> +
> + .__runtime_defaults.ip.ver = 9,
> +};
> +
> +static const struct intel_display_device_info glk_display = {
> + GEN9_LP_DISPLAY,
> + .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
> + GLK_COLORS,
> +
> + .__runtime_defaults.ip.ver = 10,
> +};
> +
> +static const struct intel_display_device_info gen11_display = {
> + .abox_mask = BIT(0),
> + .dbuf.size = 2048,
> + .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2),
> + .has_ddi = 1,
> + .has_dp_mst = 1,
> + .has_fpga_dbg = 1,
> + .has_hotplug = 1,
> + .has_ipc = 1,
> + .has_psr = 1,
> + .has_psr_hw_tracking = 1,
> + .pipe_offsets = {
> + [TRANSCODER_A] = PIPE_A_OFFSET,
> + [TRANSCODER_B] = PIPE_B_OFFSET,
> + [TRANSCODER_C] = PIPE_C_OFFSET,
> + [TRANSCODER_EDP] = PIPE_EDP_OFFSET,
> + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
> + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
> + },
> + .trans_offsets = {
> + [TRANSCODER_A] = TRANSCODER_A_OFFSET,
> + [TRANSCODER_B] = TRANSCODER_B_OFFSET,
> + [TRANSCODER_C] = TRANSCODER_C_OFFSET,
> + [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET,
> + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
> + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
> + },
> + IVB_CURSOR_OFFSETS,
> + ICL_COLORS,
> +
> + .__runtime_defaults.ip.ver = 11,
> + .__runtime_defaults.has_dmc = 1,
> + .__runtime_defaults.has_dsc = 1, \
> + .__runtime_defaults.has_hdcp = 1,
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) |
> + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> +};
> +
> +#define XE_D_DISPLAY \
> + .abox_mask = GENMASK(2, 1), \
> + .dbuf.size = 2048, \
> + .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
> + .has_ddi = 1, \
> + .has_dp_mst = 1, \
> + .has_dsb = 1, \
> + .has_fpga_dbg = 1, \
> + .has_hotplug = 1, \
> + .has_ipc = 1, \
> + .has_psr = 1, \
> + .has_psr_hw_tracking = 1, \
> + .pipe_offsets = { \
> + [TRANSCODER_A] = PIPE_A_OFFSET, \
> + [TRANSCODER_B] = PIPE_B_OFFSET, \
> + [TRANSCODER_C] = PIPE_C_OFFSET, \
> + [TRANSCODER_D] = PIPE_D_OFFSET, \
> + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> + }, \
> + .trans_offsets = { \
> + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> + [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> + [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
> + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> + }, \
> + TGL_CURSOR_OFFSETS, \
> + ICL_COLORS, \
> + \
> + .__runtime_defaults.ip.ver = 12, \
> + .__runtime_defaults.has_dmc = 1, \
> + .__runtime_defaults.has_dsc = 1, \
> + .__runtime_defaults.has_hdcp = 1, \
> + .__runtime_defaults.pipe_mask = \
> + BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> + .__runtime_defaults.cpu_transcoder_mask = \
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
> + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
> +
> +static const struct intel_display_device_info tgl_display = {
> + XE_D_DISPLAY,
> +};
> +
> +static const struct intel_display_device_info rkl_display = {
> + XE_D_DISPLAY,
> + .abox_mask = BIT(0),
> + .has_hti = 1,
> + .has_psr_hw_tracking = 0,
> +
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
> +};
> +
> +static const struct intel_display_device_info adl_s_display = {
> + XE_D_DISPLAY,
> + .has_hti = 1,
> + .has_psr_hw_tracking = 0,
> +};
> +
> +#define XE_LPD_FEATURES \
> + .abox_mask = GENMASK(1, 0), \
> + .color = { \
> + .degamma_lut_size = 129, .gamma_lut_size = 1024, \
> + .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> + DRM_COLOR_LUT_EQUAL_CHANNELS, \
> + }, \
> + .dbuf.size = 4096, \
> + .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
> + BIT(DBUF_S4), \
> + .has_ddi = 1, \
> + .has_dp_mst = 1, \
> + .has_dsb = 1, \
> + .has_fpga_dbg = 1, \
> + .has_hotplug = 1, \
> + .has_ipc = 1, \
> + .has_psr = 1, \
> + .pipe_offsets = { \
> + [TRANSCODER_A] = PIPE_A_OFFSET, \
> + [TRANSCODER_B] = PIPE_B_OFFSET, \
> + [TRANSCODER_C] = PIPE_C_OFFSET, \
> + [TRANSCODER_D] = PIPE_D_OFFSET, \
> + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> + }, \
> + .trans_offsets = { \
> + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> + [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> + [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
> + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> + }, \
> + TGL_CURSOR_OFFSETS, \
> + \
> + .__runtime_defaults.ip.ver = 13, \
> + .__runtime_defaults.has_dmc = 1, \
> + .__runtime_defaults.has_dsc = 1, \
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
> + .__runtime_defaults.has_hdcp = 1, \
> + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
> +
> +static const struct intel_display_device_info xe_lpd_display = {
> + XE_LPD_FEATURES,
> + .has_cdclk_crawl = 1,
> + .has_psr_hw_tracking = 0,
> +
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
> + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> +};
> +
> +static const struct intel_display_device_info xe_hpd_display = {
> + XE_LPD_FEATURES,
> + .has_cdclk_squash = 1,
> +
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> +};
> +
> +static const struct intel_display_device_info xe_lpdp_display = {
> + XE_LPD_FEATURES,
> + .has_cdclk_crawl = 1,
> + .has_cdclk_squash = 1,
> +
> + .__runtime_defaults.ip.ver = 14,
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> +};
> +
> +static const struct pci_device_id intel_display_ids[] = {
> + INTEL_I830_IDS(&i830_display),
> + INTEL_I845G_IDS(&i845_display),
> + INTEL_I85X_IDS(&i85x_display),
> + INTEL_I865G_IDS(&i865g_display),
> + INTEL_I915G_IDS(&i915g_display),
> + INTEL_I915GM_IDS(&i915gm_display),
> + INTEL_I945G_IDS(&i945g_display),
> + INTEL_I945GM_IDS(&i945gm_display),
> + INTEL_I965G_IDS(&i965g_display),
> + INTEL_G33_IDS(&g33_display),
> + INTEL_I965GM_IDS(&i965gm_display),
> + INTEL_GM45_IDS(&gm45_display),
> + INTEL_G45_IDS(&g45_display),
> + INTEL_PINEVIEW_G_IDS(&g33_display),
> + INTEL_PINEVIEW_M_IDS(&g33_display),
> + INTEL_IRONLAKE_D_IDS(&ilk_d_display),
> + INTEL_IRONLAKE_M_IDS(&ilk_m_display),
> + INTEL_SNB_D_IDS(&snb_display),
> + INTEL_SNB_M_IDS(&snb_display),
> + INTEL_IVB_Q_IDS(NULL), /* must be first IVB in list */
> + INTEL_IVB_M_IDS(&ivb_display),
> + INTEL_IVB_D_IDS(&ivb_display),
> + INTEL_HSW_IDS(&hsw_display),
> + INTEL_VLV_IDS(&vlv_display),
> + INTEL_BDW_IDS(&bdw_display),
> + INTEL_CHV_IDS(&chv_display),
> + INTEL_SKL_IDS(&skl_display),
> + INTEL_BXT_IDS(&bxt_display),
> + INTEL_GLK_IDS(&glk_display),
> + INTEL_KBL_IDS(&skl_display),
> + INTEL_CFL_IDS(&skl_display),
> + INTEL_ICL_11_IDS(&gen11_display),
> + INTEL_EHL_IDS(&gen11_display),
> + INTEL_JSL_IDS(&gen11_display),
> + INTEL_TGL_12_IDS(&tgl_display),
> + INTEL_DG1_IDS(&tgl_display),
> + INTEL_RKL_IDS(&rkl_display),
> + INTEL_ADLS_IDS(&adl_s_display),
> + INTEL_RPLS_IDS(&adl_s_display),
> + INTEL_ADLP_IDS(&xe_lpd_display),
> + INTEL_ADLN_IDS(&xe_lpd_display),
> + INTEL_RPLP_IDS(&xe_lpd_display),
> + INTEL_DG2_IDS(&xe_hpd_display),
> +
> + /* FIXME: Replace this with a GMD_ID lookup */
> + INTEL_MTL_IDS(&xe_lpdp_display),
> +};
> +
> +const struct intel_display_device_info *
> +intel_display_device_probe(u16 pci_devid)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
> + if (intel_display_ids[i].device == pci_devid)
> + return (struct intel_display_device_info *)intel_display_ids[i].driver_data;
> + }
> +
> + return &no_display;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 613607fad5af..1f7d08b3ad6b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -80,4 +80,7 @@ struct intel_display_device_info {
> } color;
> };
>
> +const struct intel_display_device_info *
> +intel_display_device_probe(u16 pci_devid);
> +
> #endif
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 9c781b703c7b..928975d5fe2f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -43,127 +43,6 @@
> .__runtime.graphics.ip.ver = (x), \
> .__runtime.media.ip.ver = (x)
>
> -static const struct intel_display_device_info no_display = { 0 };
> -
> -#define I845_PIPE_OFFSETS \
> - .pipe_offsets = { \
> - [TRANSCODER_A] = PIPE_A_OFFSET, \
> - }, \
> - .trans_offsets = { \
> - [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> - }
> -
> -#define I9XX_PIPE_OFFSETS \
> - .pipe_offsets = { \
> - [TRANSCODER_A] = PIPE_A_OFFSET, \
> - [TRANSCODER_B] = PIPE_B_OFFSET, \
> - }, \
> - .trans_offsets = { \
> - [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> - [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> - }
> -
> -#define IVB_PIPE_OFFSETS \
> - .pipe_offsets = { \
> - [TRANSCODER_A] = PIPE_A_OFFSET, \
> - [TRANSCODER_B] = PIPE_B_OFFSET, \
> - [TRANSCODER_C] = PIPE_C_OFFSET, \
> - }, \
> - .trans_offsets = { \
> - [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> - [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> - [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> - }
> -
> -#define HSW_PIPE_OFFSETS \
> - .pipe_offsets = { \
> - [TRANSCODER_A] = PIPE_A_OFFSET, \
> - [TRANSCODER_B] = PIPE_B_OFFSET, \
> - [TRANSCODER_C] = PIPE_C_OFFSET, \
> - [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
> - }, \
> - .trans_offsets = { \
> - [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> - [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> - [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> - [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
> - }
> -
> -#define CHV_PIPE_OFFSETS \
> - .pipe_offsets = { \
> - [TRANSCODER_A] = PIPE_A_OFFSET, \
> - [TRANSCODER_B] = PIPE_B_OFFSET, \
> - [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
> - }, \
> - .trans_offsets = { \
> - [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> - [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> - [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
> - }
> -
> -#define I845_CURSOR_OFFSETS \
> - .cursor_offsets = { \
> - [PIPE_A] = CURSOR_A_OFFSET, \
> - }
> -
> -#define I9XX_CURSOR_OFFSETS \
> - .cursor_offsets = { \
> - [PIPE_A] = CURSOR_A_OFFSET, \
> - [PIPE_B] = CURSOR_B_OFFSET, \
> - }
> -
> -#define CHV_CURSOR_OFFSETS \
> - .cursor_offsets = { \
> - [PIPE_A] = CURSOR_A_OFFSET, \
> - [PIPE_B] = CURSOR_B_OFFSET, \
> - [PIPE_C] = CHV_CURSOR_C_OFFSET, \
> - }
> -
> -#define IVB_CURSOR_OFFSETS \
> - .cursor_offsets = { \
> - [PIPE_A] = CURSOR_A_OFFSET, \
> - [PIPE_B] = IVB_CURSOR_B_OFFSET, \
> - [PIPE_C] = IVB_CURSOR_C_OFFSET, \
> - }
> -
> -#define TGL_CURSOR_OFFSETS \
> - .cursor_offsets = { \
> - [PIPE_A] = CURSOR_A_OFFSET, \
> - [PIPE_B] = IVB_CURSOR_B_OFFSET, \
> - [PIPE_C] = IVB_CURSOR_C_OFFSET, \
> - [PIPE_D] = TGL_CURSOR_D_OFFSET, \
> - }
> -
> -#define I845_COLORS \
> - .color = { .gamma_lut_size = 256 }
> -#define I9XX_COLORS \
> - .color = { .gamma_lut_size = 129, \
> - .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> - }
> -#define ILK_COLORS \
> - .color = { .gamma_lut_size = 1024 }
> -#define IVB_COLORS \
> - .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
> -#define CHV_COLORS \
> - .color = { \
> - .degamma_lut_size = 65, .gamma_lut_size = 257, \
> - .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> - .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> - }
> -#define GLK_COLORS \
> - .color = { \
> - .degamma_lut_size = 33, .gamma_lut_size = 1024, \
> - .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> - DRM_COLOR_LUT_EQUAL_CHANNELS, \
> - }
> -#define ICL_COLORS \
> - .color = { \
> - .degamma_lut_size = 33, .gamma_lut_size = 262145, \
> - .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> - DRM_COLOR_LUT_EQUAL_CHANNELS, \
> - .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
> - }
> -
> #define LEGACY_CACHELEVEL \
> .cachelevel_to_pat = { \
> [I915_CACHE_NONE] = 0, \
> @@ -204,24 +83,6 @@ static const struct intel_display_device_info no_display = { 0 };
> #define GEN_DEFAULT_REGIONS \
> .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
>
> -#define I830_DISPLAY \
> - .has_overlay = 1, \
> - .cursor_needs_physical = 1, \
> - .overlay_needs_physical = 1, \
> - .has_gmch = 1, \
> - I9XX_PIPE_OFFSETS, \
> - I9XX_CURSOR_OFFSETS, \
> - I9XX_COLORS, \
> - \
> - .__runtime_defaults.ip.ver = 2, \
> - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> - .__runtime_defaults.cpu_transcoder_mask = \
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
> -
> -static const struct intel_display_device_info i830_display = {
> - I830_DISPLAY,
> -};
> -
> #define I830_FEATURES \
> GEN(2), \
> .is_mobile = 1, \
> @@ -238,22 +99,6 @@ static const struct intel_display_device_info i830_display = {
> GEN_DEFAULT_REGIONS, \
> LEGACY_CACHELEVEL
>
> -#define I845_DISPLAY \
> - .has_overlay = 1, \
> - .overlay_needs_physical = 1, \
> - .has_gmch = 1, \
> - I845_PIPE_OFFSETS, \
> - I845_CURSOR_OFFSETS, \
> - I845_COLORS, \
> - \
> - .__runtime_defaults.ip.ver = 2, \
> - .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
> - .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
> -
> -static const struct intel_display_device_info i845_display = {
> - I845_DISPLAY,
> -};
> -
> #define I845_FEATURES \
> GEN(2), \
> .has_3d_pipeline = 1, \
> @@ -272,86 +117,21 @@ static const struct intel_display_device_info i845_display = {
> static const struct intel_device_info i830_info = {
> I830_FEATURES,
> PLATFORM(INTEL_I830),
> - .display = &i830_display,
> };
>
> static const struct intel_device_info i845g_info = {
> I845_FEATURES,
> PLATFORM(INTEL_I845G),
> - .display = &i845_display,
> -};
> -
> -static const struct intel_display_device_info i85x_display = {
> - I830_DISPLAY,
> -
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> static const struct intel_device_info i85x_info = {
> I830_FEATURES,
> PLATFORM(INTEL_I85X),
> - .display = &i85x_display,
> -};
> -
> -static const struct intel_display_device_info i865g_display = {
> - I845_DISPLAY,
> -
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> static const struct intel_device_info i865g_info = {
> I845_FEATURES,
> PLATFORM(INTEL_I865G),
> - .display = &i865g_display,
> -};
> -
> -#define GEN3_DISPLAY \
> - .has_gmch = 1, \
> - .has_overlay = 1, \
> - I9XX_PIPE_OFFSETS, \
> - I9XX_CURSOR_OFFSETS, \
> - I9XX_COLORS, \
> - \
> - .__runtime_defaults.ip.ver = 3, \
> - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> - .__runtime_defaults.cpu_transcoder_mask = \
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
> -
> -static const struct intel_display_device_info i915g_display = {
> - GEN3_DISPLAY,
> - .cursor_needs_physical = 1,
> - .overlay_needs_physical = 1,
> -};
> -
> -static const struct intel_display_device_info i915gm_display = {
> - GEN3_DISPLAY,
> - .cursor_needs_physical = 1,
> - .overlay_needs_physical = 1,
> - .supports_tv = 1,
> -
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
> -static const struct intel_display_device_info i945g_display = {
> - GEN3_DISPLAY,
> - .has_hotplug = 1,
> - .cursor_needs_physical = 1,
> - .overlay_needs_physical = 1,
> -};
> -
> -static const struct intel_display_device_info i945gm_display = {
> - GEN3_DISPLAY,
> - .has_hotplug = 1,
> - .cursor_needs_physical = 1,
> - .overlay_needs_physical = 1,
> - .supports_tv = 1,
> -
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
> -static const struct intel_display_device_info g33_display = {
> - GEN3_DISPLAY,
> - .has_hotplug = 1,
> };
>
> #define GEN3_FEATURES \
> @@ -370,7 +150,6 @@ static const struct intel_display_device_info g33_display = {
> static const struct intel_device_info i915g_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_I915G),
> - .display = &i915g_display,
> .has_coherent_ggtt = false,
> .hws_needs_physical = 1,
> .unfenced_needs_alignment = 1,
> @@ -379,7 +158,6 @@ static const struct intel_device_info i915g_info = {
> static const struct intel_device_info i915gm_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_I915GM),
> - .display = &i915gm_display,
> .is_mobile = 1,
> .hws_needs_physical = 1,
> .unfenced_needs_alignment = 1,
> @@ -388,7 +166,6 @@ static const struct intel_device_info i915gm_info = {
> static const struct intel_device_info i945g_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_I945G),
> - .display = &i945g_display,
> .hws_needs_physical = 1,
> .unfenced_needs_alignment = 1,
> };
> @@ -396,7 +173,6 @@ static const struct intel_device_info i945g_info = {
> static const struct intel_device_info i945gm_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_I945GM),
> - .display = &i945gm_display,
> .is_mobile = 1,
> .hws_needs_physical = 1,
> .unfenced_needs_alignment = 1,
> @@ -405,14 +181,12 @@ static const struct intel_device_info i945gm_info = {
> static const struct intel_device_info g33_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_G33),
> - .display = &g33_display,
> .dma_mask_size = 36,
> };
>
> static const struct intel_device_info pnv_g_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_PINEVIEW),
> - .display = &g33_display,
> .dma_mask_size = 36,
> };
>
> @@ -420,46 +194,9 @@ static const struct intel_device_info pnv_m_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_PINEVIEW),
> .is_mobile = 1,
> - .display = &g33_display,
> .dma_mask_size = 36,
> };
>
> -#define GEN4_DISPLAY \
> - .has_hotplug = 1, \
> - .has_gmch = 1, \
> - I9XX_PIPE_OFFSETS, \
> - I9XX_CURSOR_OFFSETS, \
> - I9XX_COLORS, \
> - \
> - .__runtime_defaults.ip.ver = 4, \
> - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> - .__runtime_defaults.cpu_transcoder_mask = \
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
> -
> -static const struct intel_display_device_info i965g_display = {
> - GEN4_DISPLAY,
> - .has_overlay = 1,
> -};
> -
> -static const struct intel_display_device_info i965gm_display = {
> - GEN4_DISPLAY,
> - .has_overlay = 1,
> - .supports_tv = 1,
> -
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
> -static const struct intel_display_device_info g45_display = {
> - GEN4_DISPLAY,
> -};
> -
> -static const struct intel_display_device_info gm45_display = {
> - GEN4_DISPLAY,
> - .supports_tv = 1,
> -
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
> #define GEN4_FEATURES \
> GEN(4), \
> .gpu_reset_clobbers_display = true, \
> @@ -476,7 +213,6 @@ static const struct intel_display_device_info gm45_display = {
> static const struct intel_device_info i965g_info = {
> GEN4_FEATURES,
> PLATFORM(INTEL_I965G),
> - .display = &i965g_display,
> .hws_needs_physical = 1,
> .has_snoop = false,
> };
> @@ -484,7 +220,6 @@ static const struct intel_device_info i965g_info = {
> static const struct intel_device_info i965gm_info = {
> GEN4_FEATURES,
> PLATFORM(INTEL_I965GM),
> - .display = &i965gm_display,
> .is_mobile = 1,
> .hws_needs_physical = 1,
> .has_snoop = false,
> @@ -494,7 +229,6 @@ static const struct intel_device_info g45_info = {
> GEN4_FEATURES,
> PLATFORM(INTEL_G45),
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
> - .display = &g45_display,
> .gpu_reset_clobbers_display = false,
> };
>
> @@ -503,7 +237,6 @@ static const struct intel_device_info gm45_info = {
> PLATFORM(INTEL_GM45),
> .is_mobile = 1,
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
> - .display = &gm45_display,
> .gpu_reset_clobbers_display = false,
> };
>
> @@ -521,37 +254,14 @@ static const struct intel_device_info gm45_info = {
> GEN_DEFAULT_REGIONS, \
> LEGACY_CACHELEVEL
>
> -#define ILK_DISPLAY \
> - .has_hotplug = 1, \
> - I9XX_PIPE_OFFSETS, \
> - I9XX_CURSOR_OFFSETS, \
> - ILK_COLORS, \
> - \
> - .__runtime_defaults.ip.ver = 5, \
> - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> - .__runtime_defaults.cpu_transcoder_mask = \
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
> -
> -static const struct intel_display_device_info ilk_d_display = {
> - ILK_DISPLAY,
> -};
> -
> static const struct intel_device_info ilk_d_info = {
> GEN5_FEATURES,
> PLATFORM(INTEL_IRONLAKE),
> - .display = &ilk_d_display,
> -};
> -
> -static const struct intel_display_device_info ilk_m_display = {
> - ILK_DISPLAY,
> -
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> static const struct intel_device_info ilk_m_info = {
> GEN5_FEATURES,
> PLATFORM(INTEL_IRONLAKE),
> - .display = &ilk_m_display,
> .is_mobile = 1,
> .has_rps = true,
> };
> @@ -574,32 +284,17 @@ static const struct intel_device_info ilk_m_info = {
> GEN_DEFAULT_REGIONS, \
> LEGACY_CACHELEVEL
>
> -static const struct intel_display_device_info snb_display = {
> - .has_hotplug = 1,
> - I9XX_PIPE_OFFSETS,
> - I9XX_CURSOR_OFFSETS,
> - ILK_COLORS,
> -
> - .__runtime_defaults.ip.ver = 6,
> - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> - .__runtime_defaults.cpu_transcoder_mask =
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
> #define SNB_D_PLATFORM \
> GEN6_FEATURES, \
> PLATFORM(INTEL_SANDYBRIDGE)
>
> static const struct intel_device_info snb_d_gt1_info = {
> SNB_D_PLATFORM,
> - .display = &snb_display,
> .gt = 1,
> };
>
> static const struct intel_device_info snb_d_gt2_info = {
> SNB_D_PLATFORM,
> - .display = &snb_display,
> .gt = 2,
> };
>
> @@ -611,13 +306,11 @@ static const struct intel_device_info snb_d_gt2_info = {
>
> static const struct intel_device_info snb_m_gt1_info = {
> SNB_M_PLATFORM,
> - .display = &snb_display,
> .gt = 1,
> };
>
> static const struct intel_device_info snb_m_gt2_info = {
> SNB_M_PLATFORM,
> - .display = &snb_display,
> .gt = 2,
> };
>
> @@ -644,28 +337,13 @@ static const struct intel_device_info snb_m_gt2_info = {
> PLATFORM(INTEL_IVYBRIDGE), \
> .has_l3_dpf = 1
>
> -static const struct intel_display_device_info ivb_display = {
> - .has_hotplug = 1,
> - IVB_PIPE_OFFSETS,
> - IVB_CURSOR_OFFSETS,
> - IVB_COLORS,
> -
> - .__runtime_defaults.ip.ver = 7,
> - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> - .__runtime_defaults.cpu_transcoder_mask =
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
> static const struct intel_device_info ivb_d_gt1_info = {
> IVB_D_PLATFORM,
> - .display = &ivb_display,
> .gt = 1,
> };
>
> static const struct intel_device_info ivb_d_gt2_info = {
> IVB_D_PLATFORM,
> - .display = &ivb_display,
> .gt = 2,
> };
>
> @@ -677,43 +355,25 @@ static const struct intel_device_info ivb_d_gt2_info = {
>
> static const struct intel_device_info ivb_m_gt1_info = {
> IVB_M_PLATFORM,
> - .display = &ivb_display,
> .gt = 1,
> };
>
> static const struct intel_device_info ivb_m_gt2_info = {
> IVB_M_PLATFORM,
> - .display = &ivb_display,
> .gt = 2,
> };
>
> static const struct intel_device_info ivb_q_info = {
> GEN7_FEATURES,
> PLATFORM(INTEL_IVYBRIDGE),
> - .display = &no_display,
> .gt = 2,
> .has_l3_dpf = 1,
> };
>
> -static const struct intel_display_device_info vlv_display = {
> - .has_gmch = 1,
> - .has_hotplug = 1,
> - .mmio_offset = VLV_DISPLAY_BASE,
> - I9XX_PIPE_OFFSETS,
> - I9XX_CURSOR_OFFSETS,
> - I9XX_COLORS,
> -
> - .__runtime_defaults.ip.ver = 7,
> - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> - .__runtime_defaults.cpu_transcoder_mask =
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> -};
> -
> static const struct intel_device_info vlv_info = {
> PLATFORM(INTEL_VALLEYVIEW),
> GEN(7),
> .is_lp = 1,
> - .display = &vlv_display,
> .has_runtime_pm = 1,
> .has_rc6 = 1,
> .has_reset_engine = true,
> @@ -741,38 +401,18 @@ static const struct intel_device_info vlv_info = {
> PLATFORM(INTEL_HASWELL), \
> .has_l3_dpf = 1
>
> -static const struct intel_display_device_info hsw_display = {
> - .has_ddi = 1,
> - .has_dp_mst = 1,
> - .has_fpga_dbg = 1,
> - .has_hotplug = 1,
> - HSW_PIPE_OFFSETS,
> - IVB_CURSOR_OFFSETS,
> - IVB_COLORS,
> -
> - .__runtime_defaults.ip.ver = 7,
> - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> - .__runtime_defaults.cpu_transcoder_mask =
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
> static const struct intel_device_info hsw_gt1_info = {
> HSW_PLATFORM,
> - .display = &hsw_display,
> .gt = 1,
> };
>
> static const struct intel_device_info hsw_gt2_info = {
> HSW_PLATFORM,
> - .display = &hsw_display,
> .gt = 2,
> };
>
> static const struct intel_device_info hsw_gt3_info = {
> HSW_PLATFORM,
> - .display = &hsw_display,
> .gt = 3,
> };
>
> @@ -785,42 +425,22 @@ static const struct intel_device_info hsw_gt3_info = {
> .__runtime.ppgtt_size = 48, \
> .has_64bit_reloc = 1
>
> -static const struct intel_display_device_info bdw_display = {
> - .has_ddi = 1,
> - .has_dp_mst = 1,
> - .has_fpga_dbg = 1,
> - .has_hotplug = 1,
> - HSW_PIPE_OFFSETS,
> - IVB_CURSOR_OFFSETS,
> - IVB_COLORS,
> -
> - .__runtime_defaults.ip.ver = 8,
> - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> - .__runtime_defaults.cpu_transcoder_mask =
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
> #define BDW_PLATFORM \
> GEN8_FEATURES, \
> PLATFORM(INTEL_BROADWELL)
>
> static const struct intel_device_info bdw_gt1_info = {
> BDW_PLATFORM,
> - .display = &bdw_display,
> .gt = 1,
> };
>
> static const struct intel_device_info bdw_gt2_info = {
> BDW_PLATFORM,
> - .display = &bdw_display,
> .gt = 2,
> };
>
> static const struct intel_device_info bdw_rsvd_info = {
> BDW_PLATFORM,
> - .display = &bdw_display,
> .gt = 3,
> /* According to the device ID those devices are GT3, they were
> * previously treated as not GT3, keep it like that.
> @@ -829,30 +449,14 @@ static const struct intel_device_info bdw_rsvd_info = {
>
> static const struct intel_device_info bdw_gt3_info = {
> BDW_PLATFORM,
> - .display = &bdw_display,
> .gt = 3,
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> };
>
> -static const struct intel_display_device_info chv_display = {
> - .has_hotplug = 1,
> - .has_gmch = 1,
> - .mmio_offset = VLV_DISPLAY_BASE,
> - CHV_PIPE_OFFSETS,
> - CHV_CURSOR_OFFSETS,
> - CHV_COLORS,
> -
> - .__runtime_defaults.ip.ver = 8,
> - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> - .__runtime_defaults.cpu_transcoder_mask =
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
> -};
> -
> static const struct intel_device_info chv_info = {
> PLATFORM(INTEL_CHERRYVIEW),
> GEN(8),
> - .display = &chv_display,
> .is_lp = 1,
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
> .has_64bit_reloc = 1,
> @@ -882,43 +486,17 @@ static const struct intel_device_info chv_info = {
> GEN9_DEFAULT_PAGE_SIZES, \
> .has_gt_uc = 1
>
> -static const struct intel_display_device_info skl_display = {
> - .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
> - .dbuf.slice_mask = BIT(DBUF_S1),
> - .has_ddi = 1,
> - .has_dp_mst = 1,
> - .has_fpga_dbg = 1,
> - .has_hotplug = 1,
> - .has_ipc = 1,
> - .has_psr = 1,
> - .has_psr_hw_tracking = 1,
> - HSW_PIPE_OFFSETS,
> - IVB_CURSOR_OFFSETS,
> - IVB_COLORS,
> -
> - .__runtime_defaults.ip.ver = 9,
> - .__runtime_defaults.has_dmc = 1,
> - .__runtime_defaults.has_hdcp = 1,
> - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> - .__runtime_defaults.cpu_transcoder_mask =
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
> #define SKL_PLATFORM \
> GEN9_FEATURES, \
> PLATFORM(INTEL_SKYLAKE)
>
> static const struct intel_device_info skl_gt1_info = {
> SKL_PLATFORM,
> - .display = &skl_display,
> .gt = 1,
> };
>
> static const struct intel_device_info skl_gt2_info = {
> SKL_PLATFORM,
> - .display = &skl_display,
> .gt = 2,
> };
>
> @@ -930,13 +508,11 @@ static const struct intel_device_info skl_gt2_info = {
>
> static const struct intel_device_info skl_gt3_info = {
> SKL_GT3_PLUS_PLATFORM,
> - .display = &skl_display,
> .gt = 3,
> };
>
> static const struct intel_device_info skl_gt4_info = {
> SKL_GT3_PLUS_PLATFORM,
> - .display = &skl_display,
> .gt = 4,
> };
>
> @@ -962,53 +538,14 @@ static const struct intel_device_info skl_gt4_info = {
> GEN_DEFAULT_REGIONS, \
> LEGACY_CACHELEVEL
>
> -#define GEN9_LP_DISPLAY \
> - .dbuf.slice_mask = BIT(DBUF_S1), \
> - .has_dp_mst = 1, \
> - .has_ddi = 1, \
> - .has_fpga_dbg = 1, \
> - .has_hotplug = 1, \
> - .has_ipc = 1, \
> - .has_psr = 1, \
> - .has_psr_hw_tracking = 1, \
> - HSW_PIPE_OFFSETS, \
> - IVB_CURSOR_OFFSETS, \
> - IVB_COLORS, \
> - \
> - .__runtime_defaults.has_dmc = 1, \
> - .__runtime_defaults.has_hdcp = 1, \
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
> - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> - .__runtime_defaults.cpu_transcoder_mask = \
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
> - BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C)
> -
> -static const struct intel_display_device_info bxt_display = {
> - GEN9_LP_DISPLAY,
> - .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
> -
> - .__runtime_defaults.ip.ver = 9,
> -};
> -
> static const struct intel_device_info bxt_info = {
> GEN9_LP_FEATURES,
> PLATFORM(INTEL_BROXTON),
> - .display = &bxt_display,
> -};
> -
> -static const struct intel_display_device_info glk_display = {
> - GEN9_LP_DISPLAY,
> - .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
> - GLK_COLORS,
> -
> - .__runtime_defaults.ip.ver = 10,
> };
>
> static const struct intel_device_info glk_info = {
> GEN9_LP_FEATURES,
> PLATFORM(INTEL_GEMINILAKE),
> - .display = &glk_display,
> };
>
> #define KBL_PLATFORM \
> @@ -1017,19 +554,16 @@ static const struct intel_device_info glk_info = {
>
> static const struct intel_device_info kbl_gt1_info = {
> KBL_PLATFORM,
> - .display = &skl_display,
> .gt = 1,
> };
>
> static const struct intel_device_info kbl_gt2_info = {
> KBL_PLATFORM,
> - .display = &skl_display,
> .gt = 2,
> };
>
> static const struct intel_device_info kbl_gt3_info = {
> KBL_PLATFORM,
> - .display = &skl_display,
> .gt = 3,
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> @@ -1041,19 +575,16 @@ static const struct intel_device_info kbl_gt3_info = {
>
> static const struct intel_device_info cfl_gt1_info = {
> CFL_PLATFORM,
> - .display = &skl_display,
> .gt = 1,
> };
>
> static const struct intel_device_info cfl_gt2_info = {
> CFL_PLATFORM,
> - .display = &skl_display,
> .gt = 2,
> };
>
> static const struct intel_device_info cfl_gt3_info = {
> CFL_PLATFORM,
> - .display = &skl_display,
> .gt = 3,
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> @@ -1065,13 +596,11 @@ static const struct intel_device_info cfl_gt3_info = {
>
> static const struct intel_device_info cml_gt1_info = {
> CML_PLATFORM,
> - .display = &skl_display,
> .gt = 1,
> };
>
> static const struct intel_device_info cml_gt2_info = {
> CML_PLATFORM,
> - .display = &skl_display,
> .gt = 2,
> };
>
> @@ -1087,54 +616,11 @@ static const struct intel_device_info cml_gt2_info = {
> .has_coherent_ggtt = false, \
> .has_logical_ring_elsq = 1
>
> -static const struct intel_display_device_info gen11_display = {
> - .abox_mask = BIT(0),
> - .dbuf.size = 2048,
> - .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2),
> - .has_ddi = 1,
> - .has_dp_mst = 1,
> - .has_fpga_dbg = 1,
> - .has_hotplug = 1,
> - .has_ipc = 1,
> - .has_psr = 1,
> - .has_psr_hw_tracking = 1,
> - .pipe_offsets = {
> - [TRANSCODER_A] = PIPE_A_OFFSET,
> - [TRANSCODER_B] = PIPE_B_OFFSET,
> - [TRANSCODER_C] = PIPE_C_OFFSET,
> - [TRANSCODER_EDP] = PIPE_EDP_OFFSET,
> - [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
> - [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
> - },
> - .trans_offsets = {
> - [TRANSCODER_A] = TRANSCODER_A_OFFSET,
> - [TRANSCODER_B] = TRANSCODER_B_OFFSET,
> - [TRANSCODER_C] = TRANSCODER_C_OFFSET,
> - [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET,
> - [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
> - [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
> - },
> - IVB_CURSOR_OFFSETS,
> - ICL_COLORS,
> -
> - .__runtime_defaults.ip.ver = 11,
> - .__runtime_defaults.has_dmc = 1,
> - .__runtime_defaults.has_dsc = 1, \
> - .__runtime_defaults.has_hdcp = 1,
> - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> - .__runtime_defaults.cpu_transcoder_mask =
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) |
> - BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> -};
> -
> static const struct intel_device_info icl_info = {
> GEN11_FEATURES,
> PLATFORM(INTEL_ICELAKE),
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> - .display = &gen11_display,
> };
>
> static const struct intel_device_info ehl_info = {
> @@ -1142,7 +628,6 @@ static const struct intel_device_info ehl_info = {
> PLATFORM(INTEL_ELKHARTLAKE),
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> .__runtime.ppgtt_size = 36,
> - .display = &gen11_display,
> };
>
> static const struct intel_device_info jsl_info = {
> @@ -1150,7 +635,6 @@ static const struct intel_device_info jsl_info = {
> PLATFORM(INTEL_JASPERLAKE),
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> .__runtime.ppgtt_size = 36,
> - .display = &gen11_display,
> };
>
> #define GEN12_FEATURES \
> @@ -1161,70 +645,11 @@ static const struct intel_device_info jsl_info = {
> .has_pxp = 1, \
> .max_pat_index = 3
>
> -#define XE_D_DISPLAY \
> - .abox_mask = GENMASK(2, 1), \
> - .dbuf.size = 2048, \
> - .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
> - .has_ddi = 1, \
> - .has_dp_mst = 1, \
> - .has_dsb = 1, \
> - .has_fpga_dbg = 1, \
> - .has_hotplug = 1, \
> - .has_ipc = 1, \
> - .has_psr = 1, \
> - .has_psr_hw_tracking = 1, \
> - .pipe_offsets = { \
> - [TRANSCODER_A] = PIPE_A_OFFSET, \
> - [TRANSCODER_B] = PIPE_B_OFFSET, \
> - [TRANSCODER_C] = PIPE_C_OFFSET, \
> - [TRANSCODER_D] = PIPE_D_OFFSET, \
> - [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> - [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> - }, \
> - .trans_offsets = { \
> - [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> - [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> - [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> - [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
> - [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> - [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> - }, \
> - TGL_CURSOR_OFFSETS, \
> - ICL_COLORS, \
> - \
> - .__runtime_defaults.ip.ver = 12, \
> - .__runtime_defaults.has_dmc = 1, \
> - .__runtime_defaults.has_dsc = 1, \
> - .__runtime_defaults.has_hdcp = 1, \
> - .__runtime_defaults.pipe_mask = \
> - BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> - .__runtime_defaults.cpu_transcoder_mask = \
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
> - BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
> -
> -static const struct intel_display_device_info tgl_display = {
> - XE_D_DISPLAY,
> -};
> -
> static const struct intel_device_info tgl_info = {
> GEN12_FEATURES,
> PLATFORM(INTEL_TIGERLAKE),
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> - .display = &tgl_display,
> -};
> -
> -static const struct intel_display_device_info rkl_display = {
> - XE_D_DISPLAY,
> - .abox_mask = BIT(0),
> - .has_hti = 1,
> - .has_psr_hw_tracking = 0,
> -
> - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> - .__runtime_defaults.cpu_transcoder_mask =
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
> };
>
> static const struct intel_device_info rkl_info = {
> @@ -1232,7 +657,6 @@ static const struct intel_device_info rkl_info = {
> PLATFORM(INTEL_ROCKETLAKE),
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
> - .display = &rkl_display,
> };
>
> #define DGFX_FEATURES \
> @@ -1254,13 +678,6 @@ static const struct intel_device_info dg1_info = {
> BIT(VCS0) | BIT(VCS2),
> /* Wa_16011227922 */
> .__runtime.ppgtt_size = 47,
> - .display = &tgl_display,
> -};
> -
> -static const struct intel_display_device_info adl_s_display = {
> - XE_D_DISPLAY,
> - .has_hti = 1,
> - .has_psr_hw_tracking = 0,
> };
>
> static const struct intel_device_info adl_s_info = {
> @@ -1269,61 +686,6 @@ static const struct intel_device_info adl_s_info = {
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> .dma_mask_size = 39,
> - .display = &adl_s_display,
> -};
> -
> -#define XE_LPD_FEATURES \
> - .abox_mask = GENMASK(1, 0), \
> - .color = { \
> - .degamma_lut_size = 129, .gamma_lut_size = 1024, \
> - .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> - DRM_COLOR_LUT_EQUAL_CHANNELS, \
> - }, \
> - .dbuf.size = 4096, \
> - .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
> - BIT(DBUF_S4), \
> - .has_ddi = 1, \
> - .has_dp_mst = 1, \
> - .has_dsb = 1, \
> - .has_fpga_dbg = 1, \
> - .has_hotplug = 1, \
> - .has_ipc = 1, \
> - .has_psr = 1, \
> - .pipe_offsets = { \
> - [TRANSCODER_A] = PIPE_A_OFFSET, \
> - [TRANSCODER_B] = PIPE_B_OFFSET, \
> - [TRANSCODER_C] = PIPE_C_OFFSET, \
> - [TRANSCODER_D] = PIPE_D_OFFSET, \
> - [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> - [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> - }, \
> - .trans_offsets = { \
> - [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> - [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> - [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> - [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
> - [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> - [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> - }, \
> - TGL_CURSOR_OFFSETS, \
> - \
> - .__runtime_defaults.ip.ver = 13, \
> - .__runtime_defaults.has_dmc = 1, \
> - .__runtime_defaults.has_dsc = 1, \
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
> - .__runtime_defaults.has_hdcp = 1, \
> - .__runtime_defaults.pipe_mask = \
> - BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
> -
> -static const struct intel_display_device_info xe_lpd_display = {
> - XE_LPD_FEATURES,
> - .has_cdclk_crawl = 1,
> - .has_psr_hw_tracking = 0,
> -
> - .__runtime_defaults.cpu_transcoder_mask =
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
> - BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> };
>
> static const struct intel_device_info adl_p_info = {
> @@ -1332,7 +694,6 @@ static const struct intel_device_info adl_p_info = {
> .__runtime.platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> .__runtime.ppgtt_size = 48,
> - .display = &xe_lpd_display,
> .dma_mask_size = 39,
> };
>
> @@ -1380,7 +741,6 @@ static const struct intel_device_info xehpsdv_info = {
> XE_HPM_FEATURES,
> DGFX_FEATURES,
> PLATFORM(INTEL_XEHPSDV),
> - .display = &no_display,
> .has_64k_pages = 1,
> .has_media_ratio_mode = 1,
> .__runtime.platform_engine_mask =
> @@ -1409,23 +769,12 @@ static const struct intel_device_info xehpsdv_info = {
> BIT(VCS0) | BIT(VCS2) | \
> BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
>
> -static const struct intel_display_device_info xe_hpd_display = {
> - XE_LPD_FEATURES,
> - .has_cdclk_squash = 1,
> -
> - .__runtime_defaults.cpu_transcoder_mask =
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> -};
> -
> static const struct intel_device_info dg2_info = {
> DG2_FEATURES,
> - .display = &xe_hpd_display,
> };
>
> static const struct intel_device_info ats_m_info = {
> DG2_FEATURES,
> - .display = &no_display,
> .require_force_probe = 1,
> .tuning_thread_rr_after_dep = 1,
> };
> @@ -1447,7 +796,6 @@ static const struct intel_device_info pvc_info = {
> .__runtime.graphics.ip.rel = 60,
> .__runtime.media.ip.rel = 60,
> PLATFORM(INTEL_PONTEVECCHIO),
> - .display = &no_display,
> .has_flat_ccs = 0,
> .max_pat_index = 7,
> .__runtime.platform_engine_mask =
> @@ -1468,18 +816,6 @@ static const struct intel_gt_definition xelpmp_extra_gt[] = {
> {}
> };
>
> -static const struct intel_display_device_info xe_lpdp_display = {
> - XE_LPD_FEATURES,
> - .has_cdclk_crawl = 1,
> - .has_cdclk_squash = 1,
> -
> - .__runtime_defaults.ip.ver = 14,
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
> - .__runtime_defaults.cpu_transcoder_mask =
> - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> -};
> -
> static const struct intel_device_info mtl_info = {
> XE_HP_FEATURES,
> /*
> @@ -1490,7 +826,6 @@ static const struct intel_device_info mtl_info = {
> .__runtime.graphics.ip.rel = 70,
> .__runtime.media.ip.ver = 13,
> PLATFORM(INTEL_METEORLAKE),
> - .display = &xe_lpdp_display,
> .extra_gt_list = xelpmp_extra_gt,
> .has_flat_ccs = 0,
> .has_gmd_id = 1,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2a9ab8de8421..f1ba1eae26ca 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1966,15 +1966,6 @@
> #define _TRANS_VSYNC_DSI1 0x6b814
> #define _TRANS_VSYNCSHIFT_DSI1 0x6b828
>
> -#define TRANSCODER_A_OFFSET 0x60000
> -#define TRANSCODER_B_OFFSET 0x61000
> -#define TRANSCODER_C_OFFSET 0x62000
> -#define CHV_TRANSCODER_C_OFFSET 0x63000
> -#define TRANSCODER_D_OFFSET 0x63000
> -#define TRANSCODER_EDP_OFFSET 0x6f000
> -#define TRANSCODER_DSI0_OFFSET 0x6b000
> -#define TRANSCODER_DSI1_OFFSET 0x6b800
> -
> #define TRANS_HTOTAL(trans) _MMIO_TRANS2((trans), _TRANS_HTOTAL_A)
> #define TRANS_HBLANK(trans) _MMIO_TRANS2((trans), _TRANS_HBLANK_A)
> #define TRANS_HSYNC(trans) _MMIO_TRANS2((trans), _TRANS_HSYNC_A)
> @@ -2622,23 +2613,6 @@
> #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
> #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
>
> -#define PIPE_A_OFFSET 0x70000
> -#define PIPE_B_OFFSET 0x71000
> -#define PIPE_C_OFFSET 0x72000
> -#define PIPE_D_OFFSET 0x73000
> -#define CHV_PIPE_C_OFFSET 0x74000
> -/*
> - * There's actually no pipe EDP. Some pipe registers have
> - * simply shifted from the pipe to the transcoder, while
> - * keeping their original offset. Thus we need PIPE_EDP_OFFSET
> - * to access such registers in transcoder EDP.
> - */
> -#define PIPE_EDP_OFFSET 0x7f000
> -
> -/* ICL DSI 0 and 1 */
> -#define PIPE_DSI0_OFFSET 0x7b000
> -#define PIPE_DSI1_OFFSET 0x7b800
> -
> #define TRANSCONF(trans) _MMIO_PIPE2((trans), _TRANSACONF)
> #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
> #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
> @@ -3099,13 +3073,6 @@
> #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(pipe, _CUR_CHICKEN_A)
> #define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE)
>
> -#define CURSOR_A_OFFSET 0x70080
> -#define CURSOR_B_OFFSET 0x700c0
> -#define CHV_CURSOR_C_OFFSET 0x700e0
> -#define IVB_CURSOR_B_OFFSET 0x71080
> -#define IVB_CURSOR_C_OFFSET 0x72080
> -#define TGL_CURSOR_D_OFFSET 0x73080
> -
> /* Display A control */
> #define _DSPAADDR_VLV 0x7017C /* vlv/chv */
> #define _DSPACNTR 0x70180
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 4d158927c78b..e1507ae59f2d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -574,7 +574,6 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
> {
> struct intel_device_info *info;
> struct intel_runtime_info *runtime;
> - struct intel_display_runtime_info *display_runtime;
>
> /* Setup the write-once "constant" device info */
> info = mkwrite_device_info(i915);
> @@ -583,9 +582,10 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
> /* Initialize initial runtime info from static const data and pdev. */
> runtime = RUNTIME_INFO(i915);
> memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
> - display_runtime = DISPLAY_RUNTIME_INFO(i915);
> - memcpy(display_runtime, &DISPLAY_INFO(i915)->__runtime_defaults,
> - sizeof(*display_runtime));
> +
> + /* Probe display support */
> + info->display = intel_display_device_probe(device_id);
> + *DISPLAY_RUNTIME_INFO(i915) = DISPLAY_INFO(i915)->__runtime_defaults;
>
> runtime->device_id = device_id;
> }
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [Intel-xe] [PATCH v2 4/6] drm/i915/display: Make display responsible for probing its own IP
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 4/6] drm/i915/display: Make display responsible for probing its own IP Matt Roper
2023-05-23 7:51 ` Andrzej Hajda
@ 2023-05-23 12:58 ` Jani Nikula
1 sibling, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2023-05-23 12:58 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: Matt Roper, intel-xe, Andrzej Hajda
On Mon, 22 May 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
> +static const struct intel_display_device_info xe_lpdp_display = {
> + XE_LPD_FEATURES,
> + .has_cdclk_crawl = 1,
> + .has_cdclk_squash = 1,
> +
> + .__runtime_defaults.ip.ver = 14,
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> +};
> +
> +static const struct pci_device_id intel_display_ids[] = {
Since this is not used for MODULE_DEVICE_TABLE(), there's no requirement
for the array to be struct pci_device_id.
You can either have a struct with compatible members, or just undef and
redefine INTEL_VGA_DEVICE() to initialize a struct with pci id and const
struct intel_display_device_info *, so you can avoid the cast in
intel_display_device_probe().
See what's done with subplatform init arrays in intel_device_info.c.
This too is nitpicking, and can be fixed later.
> + INTEL_I830_IDS(&i830_display),
> + INTEL_I845G_IDS(&i845_display),
> + INTEL_I85X_IDS(&i85x_display),
> + INTEL_I865G_IDS(&i865g_display),
> + INTEL_I915G_IDS(&i915g_display),
> + INTEL_I915GM_IDS(&i915gm_display),
> + INTEL_I945G_IDS(&i945g_display),
> + INTEL_I945GM_IDS(&i945gm_display),
> + INTEL_I965G_IDS(&i965g_display),
> + INTEL_G33_IDS(&g33_display),
> + INTEL_I965GM_IDS(&i965gm_display),
> + INTEL_GM45_IDS(&gm45_display),
> + INTEL_G45_IDS(&g45_display),
> + INTEL_PINEVIEW_G_IDS(&g33_display),
> + INTEL_PINEVIEW_M_IDS(&g33_display),
> + INTEL_IRONLAKE_D_IDS(&ilk_d_display),
> + INTEL_IRONLAKE_M_IDS(&ilk_m_display),
> + INTEL_SNB_D_IDS(&snb_display),
> + INTEL_SNB_M_IDS(&snb_display),
> + INTEL_IVB_Q_IDS(NULL), /* must be first IVB in list */
> + INTEL_IVB_M_IDS(&ivb_display),
> + INTEL_IVB_D_IDS(&ivb_display),
> + INTEL_HSW_IDS(&hsw_display),
> + INTEL_VLV_IDS(&vlv_display),
> + INTEL_BDW_IDS(&bdw_display),
> + INTEL_CHV_IDS(&chv_display),
> + INTEL_SKL_IDS(&skl_display),
> + INTEL_BXT_IDS(&bxt_display),
> + INTEL_GLK_IDS(&glk_display),
> + INTEL_KBL_IDS(&skl_display),
> + INTEL_CFL_IDS(&skl_display),
> + INTEL_ICL_11_IDS(&gen11_display),
> + INTEL_EHL_IDS(&gen11_display),
> + INTEL_JSL_IDS(&gen11_display),
> + INTEL_TGL_12_IDS(&tgl_display),
> + INTEL_DG1_IDS(&tgl_display),
> + INTEL_RKL_IDS(&rkl_display),
> + INTEL_ADLS_IDS(&adl_s_display),
> + INTEL_RPLS_IDS(&adl_s_display),
> + INTEL_ADLP_IDS(&xe_lpd_display),
> + INTEL_ADLN_IDS(&xe_lpd_display),
> + INTEL_RPLP_IDS(&xe_lpd_display),
> + INTEL_DG2_IDS(&xe_hpd_display),
> +
> + /* FIXME: Replace this with a GMD_ID lookup */
> + INTEL_MTL_IDS(&xe_lpdp_display),
> +};
> +
> +const struct intel_display_device_info *
> +intel_display_device_probe(u16 pci_devid)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
> + if (intel_display_ids[i].device == pci_devid)
> + return (struct intel_display_device_info *)intel_display_ids[i].driver_data;
> + }
> +
I wonder if a debug message here would be helpful. *shrug*.
> + return &no_display;
> +}
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 4d158927c78b..e1507ae59f2d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -574,7 +574,6 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
> {
> struct intel_device_info *info;
> struct intel_runtime_info *runtime;
> - struct intel_display_runtime_info *display_runtime;
>
> /* Setup the write-once "constant" device info */
> info = mkwrite_device_info(i915);
> @@ -583,9 +582,10 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
> /* Initialize initial runtime info from static const data and pdev. */
> runtime = RUNTIME_INFO(i915);
> memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
> - display_runtime = DISPLAY_RUNTIME_INFO(i915);
> - memcpy(display_runtime, &DISPLAY_INFO(i915)->__runtime_defaults,
> - sizeof(*display_runtime));
> +
> + /* Probe display support */
> + info->display = intel_display_device_probe(device_id);
> + *DISPLAY_RUNTIME_INFO(i915) = DISPLAY_INFO(i915)->__runtime_defaults;
I think I'd keep the memcpy.
Acked-by: Jani Nikula <jani.nikula@intel.com>
>
> runtime->device_id = device_id;
> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v2 5/6] drm/i915/display: Handle GMD_ID identification in display code
2023-05-22 20:23 [Intel-gfx] [PATCH v2 0/6] i915: Move display identification/probing under display/ Matt Roper
` (3 preceding siblings ...)
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 4/6] drm/i915/display: Make display responsible for probing its own IP Matt Roper
@ 2023-05-22 20:23 ` Matt Roper
2023-05-23 8:03 ` Andrzej Hajda
2023-05-23 13:02 ` [Intel-gfx] [Intel-xe] " Jani Nikula
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 6/6] drm/i915/display: Move feature test macros to intel_display_device.h Matt Roper
` (5 subsequent siblings)
10 siblings, 2 replies; 22+ messages in thread
From: Matt Roper @ 2023-05-22 20:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, intel-xe
For platforms with GMD_ID support (i.e., everything MTL and beyond),
identification of the display IP present should be based on the contents
of the GMD_ID register rather than a PCI devid match.
Note that since GMD_ID readout requires access to the PCI BAR, a slight
change to the driver init sequence is needed --- pci_enable_device() is
now called before i915_driver_create().
v2:
- Fix use of uninitialized i915 pointer in error path if
pci_enable_device() fails before the i915 device is created. (lkp)
- Use drm_device parameter to intel_display_device_probe. This goes
against i915 conventions, but since the primary goal here is to make
it easy to call this function from other drivers (like Xe) and since
we don't need anything from the i915 structure, this seems like an
exception where drm_device is a more natural fit.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
.../drm/i915/display/intel_display_device.c | 64 +++++++++++++++++--
.../drm/i915/display/intel_display_device.h | 5 +-
drivers/gpu/drm/i915/i915_driver.c | 17 +++--
drivers/gpu/drm/i915/intel_device_info.c | 12 ++--
4 files changed, 81 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 3c5941c8788d..6605487c3890 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -6,7 +6,10 @@
#include <drm/i915_pciids.h>
#include <drm/drm_color_mgmt.h>
#include <linux/mod_devicetable.h>
+#include <linux/pci.h>
+#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display_device.h"
#include "intel_display_power.h"
#include "intel_display_reg_defs.h"
@@ -692,18 +695,69 @@ static const struct pci_device_id intel_display_ids[] = {
INTEL_RPLP_IDS(&xe_lpd_display),
INTEL_DG2_IDS(&xe_hpd_display),
- /* FIXME: Replace this with a GMD_ID lookup */
- INTEL_MTL_IDS(&xe_lpdp_display),
+ /*
+ * Do not add any GMD_ID-based platforms to this list. They will
+ * be probed automatically based on the IP version reported by
+ * the hardware.
+ */
};
+struct {
+ u16 ver;
+ u16 rel;
+ const struct intel_display_device_info *display;
+} gmdid_display_map[] = {
+ { 14, 0, &xe_lpdp_display },
+};
+
+static const struct intel_display_device_info *
+probe_gmdid_display(struct drm_device *drm, u16 *ver, u16 *rel, u16 *step)
+{
+ struct pci_dev *pdev = to_pci_dev(drm->dev);
+ void __iomem *addr;
+ u32 val;
+ int i;
+
+ addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));
+ if (!addr) {
+ drm_err(drm, "Cannot map MMIO BAR to read display GMD_ID\n");
+ return &no_display;
+ }
+
+ val = ioread32(addr);
+ pci_iounmap(pdev, addr);
+
+ if (val == 0)
+ /* Platform doesn't have display */
+ return &no_display;
+
+ *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
+ *rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
+ *step = REG_FIELD_GET(GMD_ID_STEP, val);
+
+ for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++)
+ if (*ver == gmdid_display_map[i].ver &&
+ *rel == gmdid_display_map[i].rel)
+ return gmdid_display_map[i].display;
+
+ drm_err(drm, "Unrecognized display IP version %d.%02d; disabling display.\n",
+ *ver, *rel);
+ return &no_display;
+}
+
const struct intel_display_device_info *
-intel_display_device_probe(u16 pci_devid)
+intel_display_device_probe(struct drm_device *drm, bool has_gmdid,
+ u16 *gmdid_ver, u16 *gmdid_rel, u16 *gmdid_step)
{
+ struct pci_dev *pdev = to_pci_dev(drm->dev);
int i;
+ if (has_gmdid)
+ return probe_gmdid_display(drm, gmdid_ver, gmdid_rel, gmdid_step);
+
for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
- if (intel_display_ids[i].device == pci_devid)
- return (struct intel_display_device_info *)intel_display_ids[i].driver_data;
+ if (intel_display_ids[i].device == pdev->device)
+ return (const struct intel_display_device_info *)intel_display_ids[i].driver_data;
}
return &no_display;
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 1f7d08b3ad6b..2a14943313ad 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -80,7 +80,10 @@ struct intel_display_device_info {
} color;
};
+struct drm_device;
+
const struct intel_display_device_info *
-intel_display_device_probe(u16 pci_devid);
+intel_display_device_probe(struct drm_device *drm, bool has_gmdid,
+ u16 *ver, u16 *rel, u16 *step);
#endif
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 522733a89946..37532e55327d 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -754,13 +754,17 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
struct drm_i915_private *i915;
int ret;
- i915 = i915_driver_create(pdev, ent);
- if (IS_ERR(i915))
- return PTR_ERR(i915);
-
ret = pci_enable_device(pdev);
- if (ret)
- goto out_fini;
+ if (ret) {
+ pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret));
+ return ret;
+ }
+
+ i915 = i915_driver_create(pdev, ent);
+ if (IS_ERR(i915)) {
+ ret = PTR_ERR(i915);
+ goto out_pci_disable;
+ }
ret = i915_driver_early_probe(i915);
if (ret < 0)
@@ -843,7 +847,6 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
i915_driver_late_release(i915);
out_pci_disable:
pci_disable_device(pdev);
-out_fini:
i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index e1507ae59f2d..85105639d55d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -345,7 +345,6 @@ static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_
static void intel_ipver_early_init(struct drm_i915_private *i915)
{
struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
- struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
if (!HAS_GMD_ID(i915)) {
drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
@@ -366,8 +365,6 @@ static void intel_ipver_early_init(struct drm_i915_private *i915)
RUNTIME_INFO(i915)->graphics.ip.ver = 12;
RUNTIME_INFO(i915)->graphics.ip.rel = 70;
}
- ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
- (struct intel_ip_version *)&display_runtime->ip);
ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
&runtime->media.ip);
}
@@ -574,6 +571,7 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
{
struct intel_device_info *info;
struct intel_runtime_info *runtime;
+ u16 ver, rel, step;
/* Setup the write-once "constant" device info */
info = mkwrite_device_info(i915);
@@ -584,8 +582,14 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
/* Probe display support */
- info->display = intel_display_device_probe(device_id);
+ info->display = intel_display_device_probe(&i915->drm, info->has_gmd_id,
+ &ver, &rel, &step);
*DISPLAY_RUNTIME_INFO(i915) = DISPLAY_INFO(i915)->__runtime_defaults;
+ if (info->has_gmd_id) {
+ DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver;
+ DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel;
+ DISPLAY_RUNTIME_INFO(i915)->ip.step = step;
+ }
runtime->device_id = device_id;
}
--
2.40.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH v2 5/6] drm/i915/display: Handle GMD_ID identification in display code
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 5/6] drm/i915/display: Handle GMD_ID identification in display code Matt Roper
@ 2023-05-23 8:03 ` Andrzej Hajda
2023-05-23 13:02 ` [Intel-gfx] [Intel-xe] " Jani Nikula
1 sibling, 0 replies; 22+ messages in thread
From: Andrzej Hajda @ 2023-05-23 8:03 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: intel-xe
On 22.05.2023 22:23, Matt Roper wrote:
> For platforms with GMD_ID support (i.e., everything MTL and beyond),
> identification of the display IP present should be based on the contents
> of the GMD_ID register rather than a PCI devid match.
>
> Note that since GMD_ID readout requires access to the PCI BAR, a slight
> change to the driver init sequence is needed --- pci_enable_device() is
> now called before i915_driver_create().
>
> v2:
> - Fix use of uninitialized i915 pointer in error path if
> pci_enable_device() fails before the i915 device is created. (lkp)
> - Use drm_device parameter to intel_display_device_probe. This goes
> against i915 conventions, but since the primary goal here is to make
> it easy to call this function from other drivers (like Xe) and since
> we don't need anything from the i915 structure, this seems like an
> exception where drm_device is a more natural fit.
I am curious about how this driver separation will look like. I guess
there will be common struct for both drivers (i915, xe), lets call it
intel_display (maybe even existing one, slightly extended). In this case
intel_display_device_probe could use it instead of drm_device, but this
can wait for later conversion steps.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Regards
Andrzej
> ---
> .../drm/i915/display/intel_display_device.c | 64 +++++++++++++++++--
> .../drm/i915/display/intel_display_device.h | 5 +-
> drivers/gpu/drm/i915/i915_driver.c | 17 +++--
> drivers/gpu/drm/i915/intel_device_info.c | 12 ++--
> 4 files changed, 81 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 3c5941c8788d..6605487c3890 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -6,7 +6,10 @@
> #include <drm/i915_pciids.h>
> #include <drm/drm_color_mgmt.h>
> #include <linux/mod_devicetable.h>
> +#include <linux/pci.h>
>
> +#include "i915_drv.h"
> +#include "i915_reg.h"
> #include "intel_display_device.h"
> #include "intel_display_power.h"
> #include "intel_display_reg_defs.h"
> @@ -692,18 +695,69 @@ static const struct pci_device_id intel_display_ids[] = {
> INTEL_RPLP_IDS(&xe_lpd_display),
> INTEL_DG2_IDS(&xe_hpd_display),
>
> - /* FIXME: Replace this with a GMD_ID lookup */
> - INTEL_MTL_IDS(&xe_lpdp_display),
> + /*
> + * Do not add any GMD_ID-based platforms to this list. They will
> + * be probed automatically based on the IP version reported by
> + * the hardware.
> + */
> };
>
> +struct {
> + u16 ver;
> + u16 rel;
> + const struct intel_display_device_info *display;
> +} gmdid_display_map[] = {
> + { 14, 0, &xe_lpdp_display },
> +};
> +
> +static const struct intel_display_device_info *
> +probe_gmdid_display(struct drm_device *drm, u16 *ver, u16 *rel, u16 *step)
> +{
> + struct pci_dev *pdev = to_pci_dev(drm->dev);
> + void __iomem *addr;
> + u32 val;
> + int i;
> +
> + addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));
> + if (!addr) {
> + drm_err(drm, "Cannot map MMIO BAR to read display GMD_ID\n");
> + return &no_display;
> + }
> +
> + val = ioread32(addr);
> + pci_iounmap(pdev, addr);
> +
> + if (val == 0)
> + /* Platform doesn't have display */
> + return &no_display;
> +
> + *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
> + *rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
> + *step = REG_FIELD_GET(GMD_ID_STEP, val);
> +
> + for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++)
> + if (*ver == gmdid_display_map[i].ver &&
> + *rel == gmdid_display_map[i].rel)
> + return gmdid_display_map[i].display;
> +
> + drm_err(drm, "Unrecognized display IP version %d.%02d; disabling display.\n",
> + *ver, *rel);
> + return &no_display;
> +}
> +
> const struct intel_display_device_info *
> -intel_display_device_probe(u16 pci_devid)
> +intel_display_device_probe(struct drm_device *drm, bool has_gmdid,
> + u16 *gmdid_ver, u16 *gmdid_rel, u16 *gmdid_step)
> {
> + struct pci_dev *pdev = to_pci_dev(drm->dev);
> int i;
>
> + if (has_gmdid)
> + return probe_gmdid_display(drm, gmdid_ver, gmdid_rel, gmdid_step);
> +
> for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
> - if (intel_display_ids[i].device == pci_devid)
> - return (struct intel_display_device_info *)intel_display_ids[i].driver_data;
> + if (intel_display_ids[i].device == pdev->device)
> + return (const struct intel_display_device_info *)intel_display_ids[i].driver_data;
> }
>
> return &no_display;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 1f7d08b3ad6b..2a14943313ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -80,7 +80,10 @@ struct intel_display_device_info {
> } color;
> };
>
> +struct drm_device;
> +
> const struct intel_display_device_info *
> -intel_display_device_probe(u16 pci_devid);
> +intel_display_device_probe(struct drm_device *drm, bool has_gmdid,
> + u16 *ver, u16 *rel, u16 *step);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 522733a89946..37532e55327d 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -754,13 +754,17 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> struct drm_i915_private *i915;
> int ret;
>
> - i915 = i915_driver_create(pdev, ent);
> - if (IS_ERR(i915))
> - return PTR_ERR(i915);
> -
> ret = pci_enable_device(pdev);
> - if (ret)
> - goto out_fini;
> + if (ret) {
> + pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret));
> + return ret;
> + }
> +
> + i915 = i915_driver_create(pdev, ent);
> + if (IS_ERR(i915)) {
> + ret = PTR_ERR(i915);
> + goto out_pci_disable;
> + }
>
> ret = i915_driver_early_probe(i915);
> if (ret < 0)
> @@ -843,7 +847,6 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> i915_driver_late_release(i915);
> out_pci_disable:
> pci_disable_device(pdev);
> -out_fini:
> i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index e1507ae59f2d..85105639d55d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -345,7 +345,6 @@ static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_
> static void intel_ipver_early_init(struct drm_i915_private *i915)
> {
> struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
> - struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
>
> if (!HAS_GMD_ID(i915)) {
> drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
> @@ -366,8 +365,6 @@ static void intel_ipver_early_init(struct drm_i915_private *i915)
> RUNTIME_INFO(i915)->graphics.ip.ver = 12;
> RUNTIME_INFO(i915)->graphics.ip.rel = 70;
> }
> - ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
> - (struct intel_ip_version *)&display_runtime->ip);
> ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
> &runtime->media.ip);
> }
> @@ -574,6 +571,7 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
> {
> struct intel_device_info *info;
> struct intel_runtime_info *runtime;
> + u16 ver, rel, step;
>
> /* Setup the write-once "constant" device info */
> info = mkwrite_device_info(i915);
> @@ -584,8 +582,14 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
> memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
>
> /* Probe display support */
> - info->display = intel_display_device_probe(device_id);
> + info->display = intel_display_device_probe(&i915->drm, info->has_gmd_id,
> + &ver, &rel, &step);
> *DISPLAY_RUNTIME_INFO(i915) = DISPLAY_INFO(i915)->__runtime_defaults;
> + if (info->has_gmd_id) {
> + DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver;
> + DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel;
> + DISPLAY_RUNTIME_INFO(i915)->ip.step = step;
> + }
>
> runtime->device_id = device_id;
> }
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [Intel-xe] [PATCH v2 5/6] drm/i915/display: Handle GMD_ID identification in display code
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 5/6] drm/i915/display: Handle GMD_ID identification in display code Matt Roper
2023-05-23 8:03 ` Andrzej Hajda
@ 2023-05-23 13:02 ` Jani Nikula
2023-05-23 14:43 ` Matt Roper
1 sibling, 1 reply; 22+ messages in thread
From: Jani Nikula @ 2023-05-23 13:02 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: Matt Roper, intel-xe
On Mon, 22 May 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
> For platforms with GMD_ID support (i.e., everything MTL and beyond),
> identification of the display IP present should be based on the contents
> of the GMD_ID register rather than a PCI devid match.
>
> Note that since GMD_ID readout requires access to the PCI BAR, a slight
> change to the driver init sequence is needed --- pci_enable_device() is
> now called before i915_driver_create().
>
> v2:
> - Fix use of uninitialized i915 pointer in error path if
> pci_enable_device() fails before the i915 device is created. (lkp)
> - Use drm_device parameter to intel_display_device_probe. This goes
> against i915 conventions, but since the primary goal here is to make
> it easy to call this function from other drivers (like Xe) and since
> we don't need anything from the i915 structure, this seems like an
> exception where drm_device is a more natural fit.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> .../drm/i915/display/intel_display_device.c | 64 +++++++++++++++++--
> .../drm/i915/display/intel_display_device.h | 5 +-
> drivers/gpu/drm/i915/i915_driver.c | 17 +++--
> drivers/gpu/drm/i915/intel_device_info.c | 12 ++--
> 4 files changed, 81 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 3c5941c8788d..6605487c3890 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -6,7 +6,10 @@
> #include <drm/i915_pciids.h>
> #include <drm/drm_color_mgmt.h>
> #include <linux/mod_devicetable.h>
> +#include <linux/pci.h>
>
> +#include "i915_drv.h"
> +#include "i915_reg.h"
> #include "intel_display_device.h"
> #include "intel_display_power.h"
> #include "intel_display_reg_defs.h"
> @@ -692,18 +695,69 @@ static const struct pci_device_id intel_display_ids[] = {
> INTEL_RPLP_IDS(&xe_lpd_display),
> INTEL_DG2_IDS(&xe_hpd_display),
>
> - /* FIXME: Replace this with a GMD_ID lookup */
> - INTEL_MTL_IDS(&xe_lpdp_display),
> + /*
> + * Do not add any GMD_ID-based platforms to this list. They will
> + * be probed automatically based on the IP version reported by
> + * the hardware.
> + */
> };
>
> +struct {
> + u16 ver;
> + u16 rel;
> + const struct intel_display_device_info *display;
> +} gmdid_display_map[] = {
> + { 14, 0, &xe_lpdp_display },
> +};
> +
> +static const struct intel_display_device_info *
> +probe_gmdid_display(struct drm_device *drm, u16 *ver, u16 *rel, u16 *step)
Please always prefer struct drm_i915_private * over struct drm_device *.
> +{
> + struct pci_dev *pdev = to_pci_dev(drm->dev);
> + void __iomem *addr;
> + u32 val;
> + int i;
> +
> + addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));
> + if (!addr) {
> + drm_err(drm, "Cannot map MMIO BAR to read display GMD_ID\n");
> + return &no_display;
> + }
> +
> + val = ioread32(addr);
> + pci_iounmap(pdev, addr);
> +
> + if (val == 0)
> + /* Platform doesn't have display */
> + return &no_display;
> +
> + *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
> + *rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
> + *step = REG_FIELD_GET(GMD_ID_STEP, val);
> +
> + for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++)
> + if (*ver == gmdid_display_map[i].ver &&
> + *rel == gmdid_display_map[i].rel)
> + return gmdid_display_map[i].display;
> +
> + drm_err(drm, "Unrecognized display IP version %d.%02d; disabling display.\n",
> + *ver, *rel);
> + return &no_display;
> +}
> +
> const struct intel_display_device_info *
> -intel_display_device_probe(u16 pci_devid)
> +intel_display_device_probe(struct drm_device *drm, bool has_gmdid,
> + u16 *gmdid_ver, u16 *gmdid_rel, u16 *gmdid_step)
Ditto.
> {
> + struct pci_dev *pdev = to_pci_dev(drm->dev);
> int i;
>
> + if (has_gmdid)
> + return probe_gmdid_display(drm, gmdid_ver, gmdid_rel, gmdid_step);
> +
> for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
> - if (intel_display_ids[i].device == pci_devid)
> - return (struct intel_display_device_info *)intel_display_ids[i].driver_data;
> + if (intel_display_ids[i].device == pdev->device)
> + return (const struct intel_display_device_info *)intel_display_ids[i].driver_data;
> }
>
> return &no_display;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 1f7d08b3ad6b..2a14943313ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -80,7 +80,10 @@ struct intel_display_device_info {
> } color;
> };
>
> +struct drm_device;
> +
Please keep forward declarations near the top of the file, right after
includes.
> const struct intel_display_device_info *
> -intel_display_device_probe(u16 pci_devid);
> +intel_display_device_probe(struct drm_device *drm, bool has_gmdid,
> + u16 *ver, u16 *rel, u16 *step);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 522733a89946..37532e55327d 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -754,13 +754,17 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> struct drm_i915_private *i915;
> int ret;
>
> - i915 = i915_driver_create(pdev, ent);
> - if (IS_ERR(i915))
> - return PTR_ERR(i915);
> -
> ret = pci_enable_device(pdev);
> - if (ret)
> - goto out_fini;
> + if (ret) {
> + pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret));
> + return ret;
> + }
> +
> + i915 = i915_driver_create(pdev, ent);
> + if (IS_ERR(i915)) {
> + ret = PTR_ERR(i915);
> + goto out_pci_disable;
> + }
>
> ret = i915_driver_early_probe(i915);
> if (ret < 0)
> @@ -843,7 +847,6 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> i915_driver_late_release(i915);
> out_pci_disable:
> pci_disable_device(pdev);
> -out_fini:
> i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index e1507ae59f2d..85105639d55d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -345,7 +345,6 @@ static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_
> static void intel_ipver_early_init(struct drm_i915_private *i915)
> {
> struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
> - struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
>
> if (!HAS_GMD_ID(i915)) {
> drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
> @@ -366,8 +365,6 @@ static void intel_ipver_early_init(struct drm_i915_private *i915)
> RUNTIME_INFO(i915)->graphics.ip.ver = 12;
> RUNTIME_INFO(i915)->graphics.ip.rel = 70;
> }
> - ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
> - (struct intel_ip_version *)&display_runtime->ip);
> ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
> &runtime->media.ip);
> }
> @@ -574,6 +571,7 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
> {
> struct intel_device_info *info;
> struct intel_runtime_info *runtime;
> + u16 ver, rel, step;
>
> /* Setup the write-once "constant" device info */
> info = mkwrite_device_info(i915);
> @@ -584,8 +582,14 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
> memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
>
> /* Probe display support */
> - info->display = intel_display_device_probe(device_id);
> + info->display = intel_display_device_probe(&i915->drm, info->has_gmd_id,
> + &ver, &rel, &step);
> *DISPLAY_RUNTIME_INFO(i915) = DISPLAY_INFO(i915)->__runtime_defaults;
> + if (info->has_gmd_id) {
> + DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver;
> + DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel;
> + DISPLAY_RUNTIME_INFO(i915)->ip.step = step;
> + }
The division of initialization responsibilities between here and
intel_display_device_probe() is perhaps a bit odd?
Nothing that can't be fixed later though, I guess.
BR,
Jani.
>
> runtime->device_id = device_id;
> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [Intel-xe] [PATCH v2 5/6] drm/i915/display: Handle GMD_ID identification in display code
2023-05-23 13:02 ` [Intel-gfx] [Intel-xe] " Jani Nikula
@ 2023-05-23 14:43 ` Matt Roper
0 siblings, 0 replies; 22+ messages in thread
From: Matt Roper @ 2023-05-23 14:43 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, May 23, 2023 at 04:02:46PM +0300, Jani Nikula wrote:
> On Mon, 22 May 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
> > For platforms with GMD_ID support (i.e., everything MTL and beyond),
> > identification of the display IP present should be based on the contents
> > of the GMD_ID register rather than a PCI devid match.
> >
> > Note that since GMD_ID readout requires access to the PCI BAR, a slight
> > change to the driver init sequence is needed --- pci_enable_device() is
> > now called before i915_driver_create().
> >
> > v2:
> > - Fix use of uninitialized i915 pointer in error path if
> > pci_enable_device() fails before the i915 device is created. (lkp)
> > - Use drm_device parameter to intel_display_device_probe. This goes
> > against i915 conventions, but since the primary goal here is to make
> > it easy to call this function from other drivers (like Xe) and since
> > we don't need anything from the i915 structure, this seems like an
> > exception where drm_device is a more natural fit.
> >
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > .../drm/i915/display/intel_display_device.c | 64 +++++++++++++++++--
> > .../drm/i915/display/intel_display_device.h | 5 +-
> > drivers/gpu/drm/i915/i915_driver.c | 17 +++--
> > drivers/gpu/drm/i915/intel_device_info.c | 12 ++--
> > 4 files changed, 81 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> > index 3c5941c8788d..6605487c3890 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> > @@ -6,7 +6,10 @@
> > #include <drm/i915_pciids.h>
> > #include <drm/drm_color_mgmt.h>
> > #include <linux/mod_devicetable.h>
> > +#include <linux/pci.h>
> >
> > +#include "i915_drv.h"
> > +#include "i915_reg.h"
> > #include "intel_display_device.h"
> > #include "intel_display_power.h"
> > #include "intel_display_reg_defs.h"
> > @@ -692,18 +695,69 @@ static const struct pci_device_id intel_display_ids[] = {
> > INTEL_RPLP_IDS(&xe_lpd_display),
> > INTEL_DG2_IDS(&xe_hpd_display),
> >
> > - /* FIXME: Replace this with a GMD_ID lookup */
> > - INTEL_MTL_IDS(&xe_lpdp_display),
> > + /*
> > + * Do not add any GMD_ID-based platforms to this list. They will
> > + * be probed automatically based on the IP version reported by
> > + * the hardware.
> > + */
> > };
> >
> > +struct {
> > + u16 ver;
> > + u16 rel;
> > + const struct intel_display_device_info *display;
> > +} gmdid_display_map[] = {
> > + { 14, 0, &xe_lpdp_display },
> > +};
> > +
> > +static const struct intel_display_device_info *
> > +probe_gmdid_display(struct drm_device *drm, u16 *ver, u16 *rel, u16 *step)
>
> Please always prefer struct drm_i915_private * over struct drm_device *.
>
> > +{
> > + struct pci_dev *pdev = to_pci_dev(drm->dev);
> > + void __iomem *addr;
> > + u32 val;
> > + int i;
> > +
> > + addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));
> > + if (!addr) {
> > + drm_err(drm, "Cannot map MMIO BAR to read display GMD_ID\n");
> > + return &no_display;
> > + }
> > +
> > + val = ioread32(addr);
> > + pci_iounmap(pdev, addr);
> > +
> > + if (val == 0)
> > + /* Platform doesn't have display */
> > + return &no_display;
> > +
> > + *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
> > + *rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
> > + *step = REG_FIELD_GET(GMD_ID_STEP, val);
> > +
> > + for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++)
> > + if (*ver == gmdid_display_map[i].ver &&
> > + *rel == gmdid_display_map[i].rel)
> > + return gmdid_display_map[i].display;
> > +
> > + drm_err(drm, "Unrecognized display IP version %d.%02d; disabling display.\n",
> > + *ver, *rel);
> > + return &no_display;
> > +}
> > +
> > const struct intel_display_device_info *
> > -intel_display_device_probe(u16 pci_devid)
> > +intel_display_device_probe(struct drm_device *drm, bool has_gmdid,
> > + u16 *gmdid_ver, u16 *gmdid_rel, u16 *gmdid_step)
>
> Ditto.
I was a bit torn on this one. Although we usually use drm_i915_private
in i915 code, in this case it seems like it adds a needless dependency
on i915 types and leads to more complications when calling this from
non-i915 code (like Xe). What we really need here is just 'struct
pci_dev' to obtain the device ID and map the BAR, but drm_device
lets us also use the drm_err() calls.
But for now I can just put this back to drm_i915_private; we can revisit
this later once we have more driver restructuring to move away from
drm_i915_private in a more global manner.
Matt
>
> > {
> > + struct pci_dev *pdev = to_pci_dev(drm->dev);
> > int i;
> >
> > + if (has_gmdid)
> > + return probe_gmdid_display(drm, gmdid_ver, gmdid_rel, gmdid_step);
> > +
> > for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
> > - if (intel_display_ids[i].device == pci_devid)
> > - return (struct intel_display_device_info *)intel_display_ids[i].driver_data;
> > + if (intel_display_ids[i].device == pdev->device)
> > + return (const struct intel_display_device_info *)intel_display_ids[i].driver_data;
> > }
> >
> > return &no_display;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> > index 1f7d08b3ad6b..2a14943313ad 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > @@ -80,7 +80,10 @@ struct intel_display_device_info {
> > } color;
> > };
> >
> > +struct drm_device;
> > +
>
> Please keep forward declarations near the top of the file, right after
> includes.
>
> > const struct intel_display_device_info *
> > -intel_display_device_probe(u16 pci_devid);
> > +intel_display_device_probe(struct drm_device *drm, bool has_gmdid,
> > + u16 *ver, u16 *rel, u16 *step);
> >
> > #endif
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> > index 522733a89946..37532e55327d 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -754,13 +754,17 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> > struct drm_i915_private *i915;
> > int ret;
> >
> > - i915 = i915_driver_create(pdev, ent);
> > - if (IS_ERR(i915))
> > - return PTR_ERR(i915);
> > -
> > ret = pci_enable_device(pdev);
> > - if (ret)
> > - goto out_fini;
> > + if (ret) {
> > + pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret));
> > + return ret;
> > + }
> > +
> > + i915 = i915_driver_create(pdev, ent);
> > + if (IS_ERR(i915)) {
> > + ret = PTR_ERR(i915);
> > + goto out_pci_disable;
> > + }
> >
> > ret = i915_driver_early_probe(i915);
> > if (ret < 0)
> > @@ -843,7 +847,6 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> > i915_driver_late_release(i915);
> > out_pci_disable:
> > pci_disable_device(pdev);
> > -out_fini:
> > i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
> > return ret;
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> > index e1507ae59f2d..85105639d55d 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -345,7 +345,6 @@ static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_
> > static void intel_ipver_early_init(struct drm_i915_private *i915)
> > {
> > struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
> > - struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
> >
> > if (!HAS_GMD_ID(i915)) {
> > drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
> > @@ -366,8 +365,6 @@ static void intel_ipver_early_init(struct drm_i915_private *i915)
> > RUNTIME_INFO(i915)->graphics.ip.ver = 12;
> > RUNTIME_INFO(i915)->graphics.ip.rel = 70;
> > }
> > - ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
> > - (struct intel_ip_version *)&display_runtime->ip);
> > ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
> > &runtime->media.ip);
> > }
> > @@ -574,6 +571,7 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
> > {
> > struct intel_device_info *info;
> > struct intel_runtime_info *runtime;
> > + u16 ver, rel, step;
> >
> > /* Setup the write-once "constant" device info */
> > info = mkwrite_device_info(i915);
> > @@ -584,8 +582,14 @@ void intel_device_info_driver_create(struct drm_i915_private *i915,
> > memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
> >
> > /* Probe display support */
> > - info->display = intel_display_device_probe(device_id);
> > + info->display = intel_display_device_probe(&i915->drm, info->has_gmd_id,
> > + &ver, &rel, &step);
> > *DISPLAY_RUNTIME_INFO(i915) = DISPLAY_INFO(i915)->__runtime_defaults;
> > + if (info->has_gmd_id) {
> > + DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver;
> > + DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel;
> > + DISPLAY_RUNTIME_INFO(i915)->ip.step = step;
> > + }
>
> The division of initialization responsibilities between here and
> intel_display_device_probe() is perhaps a bit odd?
>
> Nothing that can't be fixed later though, I guess.
>
> BR,
> Jani.
>
> >
> > runtime->device_id = device_id;
> > }
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v2 6/6] drm/i915/display: Move feature test macros to intel_display_device.h
2023-05-22 20:23 [Intel-gfx] [PATCH v2 0/6] i915: Move display identification/probing under display/ Matt Roper
` (4 preceding siblings ...)
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 5/6] drm/i915/display: Handle GMD_ID identification in display code Matt Roper
@ 2023-05-22 20:23 ` Matt Roper
2023-05-23 8:06 ` Andrzej Hajda
2023-05-22 21:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Move display identification/probing under display/ (rev2) Patchwork
` (4 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Matt Roper @ 2023-05-22 20:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, intel-xe
It makes sense to keep the display feature test macros centralized
within the display code.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
.../drm/i915/display/intel_display_device.h | 40 +++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 60 -------------------
2 files changed, 40 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 2a14943313ad..343def9e7933 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -29,6 +29,46 @@
func(overlay_needs_physical); \
func(supports_tv);
+#define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
+#define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl)
+#define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash)
+#define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
+#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915))
+#define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi)
+#define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
+#define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc)
+#define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
+#define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst)
+#define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
+#define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13)
+#define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb)
+#define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
+#define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
+#define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg)
+#define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2)
+#define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4)
+#define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915))
+#define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch)
+#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
+#define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
+#define HAS_IPS(i915) (IS_HSW_ULT(i915) || IS_BROADWELL(i915))
+#define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
+#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
+#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
+#define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay)
+#define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr)
+#define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking)
+#define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12)
+#define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
+#define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
+ BIT(trans)) != 0)
+#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
+#define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
+#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
+#define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical)
+#define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv)
+
+
struct intel_display_runtime_info {
struct {
u16 ver;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7a8a12d12790..64f383fe7e23 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -785,10 +785,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
})
-#define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay)
-#define OVERLAY_NEEDS_PHYSICAL(i915) \
- (DISPLAY_INFO(i915)->overlay_needs_physical)
-
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915))
@@ -799,41 +795,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define NEEDS_WaRsDisableCoarsePowerGating(i915) \
(IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
-#define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4)
-#define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 11 || \
- IS_GEMINILAKE(i915) || \
- IS_KABYLAKE(i915))
-
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming.
*/
#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
!(IS_I915G(i915) || IS_I915GM(i915)))
-#define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv)
-#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
-#define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2)
-#define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
-#define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
-
-#define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13)
-
-#define HAS_IPS(i915) (IS_HSW_ULT(i915) || IS_BROADWELL(i915))
-
-#define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst)
-#define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
-
-#define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
-
-#define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl)
-#define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash)
-#define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi)
-#define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg)
-#define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr)
-#define HAS_PSR_HW_TRACKING(i915) \
- (DISPLAY_INFO(i915)->has_psr_hw_tracking)
-#define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12)
-#define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
#define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
#define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
@@ -841,11 +808,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
-#define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc)
-#define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb)
-#define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
-#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
-
#define HAS_HECI_PXP(i915) \
(INTEL_INFO(i915)->has_heci_pxp)
@@ -854,8 +816,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))
-#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
-
#define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
#define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
@@ -872,9 +832,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
*/
#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
-#define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
-#define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
-
#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
@@ -892,12 +849,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
-#define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch)
-
#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
-#define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
-
#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
/* DPF == dynamic parity feature */
@@ -905,14 +858,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \
2 : HAS_L3_DPF(i915))
-#define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
-
-#define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
-
-#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
-
-#define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
-
/* Only valid when HAS_DISPLAY() is true */
#define INTEL_DISPLAY_ENABLED(i915) \
(drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)), \
@@ -922,11 +867,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GUC_DEPRIVILEGE(i915) \
(INTEL_INFO(i915)->has_guc_deprivilege)
-#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || \
- IS_ALDERLAKE_S(i915))
-
-#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
-
#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
--
2.40.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH v2 6/6] drm/i915/display: Move feature test macros to intel_display_device.h
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 6/6] drm/i915/display: Move feature test macros to intel_display_device.h Matt Roper
@ 2023-05-23 8:06 ` Andrzej Hajda
0 siblings, 0 replies; 22+ messages in thread
From: Andrzej Hajda @ 2023-05-23 8:06 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: intel-xe
On 22.05.2023 22:23, Matt Roper wrote:
> It makes sense to keep the display feature test macros centralized
> within the display code.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Regards
Andrzej
> ---
> .../drm/i915/display/intel_display_device.h | 40 +++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 60 -------------------
> 2 files changed, 40 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 2a14943313ad..343def9e7933 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -29,6 +29,46 @@
> func(overlay_needs_physical); \
> func(supports_tv);
>
> +#define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
> +#define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl)
> +#define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash)
> +#define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
> +#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915))
> +#define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi)
> +#define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
> +#define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc)
> +#define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
> +#define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst)
> +#define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
> +#define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13)
> +#define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb)
> +#define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
> +#define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
> +#define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg)
> +#define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2)
> +#define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4)
> +#define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915))
> +#define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch)
> +#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
> +#define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
> +#define HAS_IPS(i915) (IS_HSW_ULT(i915) || IS_BROADWELL(i915))
> +#define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
> +#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
> +#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
> +#define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay)
> +#define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr)
> +#define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking)
> +#define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12)
> +#define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
> +#define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
> + BIT(trans)) != 0)
> +#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
> +#define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
> +#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
> +#define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical)
> +#define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv)
> +
> +
> struct intel_display_runtime_info {
> struct {
> u16 ver;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7a8a12d12790..64f383fe7e23 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -785,10 +785,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
> })
>
> -#define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay)
> -#define OVERLAY_NEEDS_PHYSICAL(i915) \
> - (DISPLAY_INFO(i915)->overlay_needs_physical)
> -
> /* Early gen2 have a totally busted CS tlb and require pinned batches. */
> #define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915))
>
> @@ -799,41 +795,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define NEEDS_WaRsDisableCoarsePowerGating(i915) \
> (IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
>
> -#define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4)
> -#define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 11 || \
> - IS_GEMINILAKE(i915) || \
> - IS_KABYLAKE(i915))
> -
> /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
> * rows, which changed the alignment requirements and fence programming.
> */
> #define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
> !(IS_I915G(i915) || IS_I915GM(i915)))
> -#define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv)
> -#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
>
> -#define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2)
> -#define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
> -#define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
> -
> -#define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13)
> -
> -#define HAS_IPS(i915) (IS_HSW_ULT(i915) || IS_BROADWELL(i915))
> -
> -#define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst)
> -#define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
> -
> -#define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
> -
> -#define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl)
> -#define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash)
> -#define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi)
> -#define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg)
> -#define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr)
> -#define HAS_PSR_HW_TRACKING(i915) \
> - (DISPLAY_INFO(i915)->has_psr_hw_tracking)
> -#define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12)
> -#define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
>
> #define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
> #define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
> @@ -841,11 +808,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
>
> -#define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc)
> -#define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb)
> -#define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
> -#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
> -
> #define HAS_HECI_PXP(i915) \
> (INTEL_INFO(i915)->has_heci_pxp)
>
> @@ -854,8 +816,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))
>
> -#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
> -
> #define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
> #define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
>
> @@ -872,9 +832,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> */
> #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
>
> -#define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
> -#define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
> -
> #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
> #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
>
> @@ -892,12 +849,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
>
> -#define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch)
> -
> #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
>
> -#define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
> -
> #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
>
> /* DPF == dynamic parity feature */
> @@ -905,14 +858,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \
> 2 : HAS_L3_DPF(i915))
>
> -#define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
> -
> -#define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
> -
> -#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
> -
> -#define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
> -
> /* Only valid when HAS_DISPLAY() is true */
> #define INTEL_DISPLAY_ENABLED(i915) \
> (drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)), \
> @@ -922,11 +867,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_GUC_DEPRIVILEGE(i915) \
> (INTEL_INFO(i915)->has_guc_deprivilege)
>
> -#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || \
> - IS_ALDERLAKE_S(i915))
> -
> -#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
> -
> #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
>
> #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Move display identification/probing under display/ (rev2)
2023-05-22 20:23 [Intel-gfx] [PATCH v2 0/6] i915: Move display identification/probing under display/ Matt Roper
` (5 preceding siblings ...)
2023-05-22 20:23 ` [Intel-gfx] [PATCH v2 6/6] drm/i915/display: Move feature test macros to intel_display_device.h Matt Roper
@ 2023-05-22 21:36 ` Patchwork
2023-05-22 21:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2023-05-22 21:36 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: Move display identification/probing under display/ (rev2)
URL : https://patchwork.freedesktop.org/series/117931/
State : warning
== Summary ==
Error: dim checkpatch failed
7abc5ebe1565 drm/i915/display: Move display device info to header under display/
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:16: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#16:
new file mode 100644
-:33: ERROR:MULTISTATEMENT_MACRO_USE_DO_WHILE: Macros with multiple statements should be enclosed in a do - while loop
#33: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:13:
+#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
+ /* Keep in alphabetical order */ \
+ func(cursor_needs_physical); \
+ func(has_cdclk_crawl); \
+ func(has_cdclk_squash); \
+ func(has_ddi); \
+ func(has_dp_mst); \
+ func(has_dsb); \
+ func(has_fpga_dbg); \
+ func(has_gmch); \
+ func(has_hotplug); \
+ func(has_hti); \
+ func(has_ipc); \
+ func(has_overlay); \
+ func(has_psr); \
+ func(has_psr_hw_tracking); \
+ func(overlay_needs_physical); \
+ func(supports_tv);
-:33: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'func' - possible side-effects?
#33: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:13:
+#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
+ /* Keep in alphabetical order */ \
+ func(cursor_needs_physical); \
+ func(has_cdclk_crawl); \
+ func(has_cdclk_squash); \
+ func(has_ddi); \
+ func(has_dp_mst); \
+ func(has_dsb); \
+ func(has_fpga_dbg); \
+ func(has_gmch); \
+ func(has_hotplug); \
+ func(has_hti); \
+ func(has_ipc); \
+ func(has_overlay); \
+ func(has_psr); \
+ func(has_psr_hw_tracking); \
+ func(overlay_needs_physical); \
+ func(supports_tv);
-:33: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon
#33: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:13:
+#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
+ /* Keep in alphabetical order */ \
+ func(cursor_needs_physical); \
+ func(has_cdclk_crawl); \
+ func(has_cdclk_squash); \
+ func(has_ddi); \
+ func(has_dp_mst); \
+ func(has_dsb); \
+ func(has_fpga_dbg); \
+ func(has_gmch); \
+ func(has_hotplug); \
+ func(has_hti); \
+ func(has_ipc); \
+ func(has_overlay); \
+ func(has_psr); \
+ func(has_psr_hw_tracking); \
+ func(overlay_needs_physical); \
+ func(supports_tv);
total: 1 errors, 2 warnings, 1 checks, 127 lines checked
ebdedffdd60c drm/i915: Convert INTEL_INFO()->display to a pointer
-:231: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#231: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:39:
+#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display->pipe_offsets[(pipe)] - \
-:232: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#232: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:40:
+ INTEL_INFO(dev_priv)->display->pipe_offsets[PIPE_A] + \
-:236: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#236: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:42:
+#define _MMIO_TRANS2(tran, reg) _MMIO(INTEL_INFO(dev_priv)->display->trans_offsets[(tran)] - \
-:237: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#237: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:43:
+ INTEL_INFO(dev_priv)->display->trans_offsets[TRANSCODER_A] + \
-:241: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#241: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:45:
+#define _MMIO_CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display->cursor_offsets[(pipe)] - \
-:242: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#242: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:46:
+ INTEL_INFO(dev_priv)->display->cursor_offsets[PIPE_A] + \
-:1206: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#1206: FILE: drivers/gpu/drm/i915/i915_pci.c:844:
+ .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
-:1738: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#1738: FILE: drivers/gpu/drm/i915/intel_device_info.c:141:
+#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display->name))
total: 0 errors, 7 warnings, 1 checks, 1610 lines checked
38edf7571527 drm/i915/display: Move display runtime info to display structure
-:67: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#67: FILE: drivers/gpu/drm/i915/display/intel_display.h:108:
+#define sprite_name(p, s) ((p) * DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
-:85: WARNING:SPACING: space prohibited between function name and open parenthesis '('
#85: FILE: drivers/gpu/drm/i915/display/intel_display.h:232:
+ for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
-:193: WARNING:LONG_LINE_COMMENT: line length of 101 exceeds 100 columns
#193: FILE: drivers/gpu/drm/i915/i915_drv.h:208:
+ struct intel_display_runtime_info __display_runtime; /* Access with DISPLAY_RUNTIME_INFO() */
-:228: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#228: FILE: drivers/gpu/drm/i915/i915_drv.h:836:
+#define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
-:728: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#728: FILE: drivers/gpu/drm/i915/i915_pci.c:1122:
+ .__runtime_defaults.has_dsc = 1, \
total: 0 errors, 4 warnings, 1 checks, 1066 lines checked
ee9ace8faa7f drm/i915/display: Make display responsible for probing its own IP
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:40: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#40:
new file mode 100644
-:454: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#454: FILE: drivers/gpu/drm/i915/display/intel_display_device.c:410:
+ .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
-:546: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#546: FILE: drivers/gpu/drm/i915/display/intel_display_device.c:502:
+ .__runtime_defaults.has_dsc = 1, \
total: 0 errors, 3 warnings, 0 checks, 1888 lines checked
0fb257b3c1cd drm/i915/display: Handle GMD_ID identification in display code
-:112: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#112: FILE: drivers/gpu/drm/i915/display/intel_display_device.c:760:
+ return (const struct intel_display_device_info *)intel_display_ids[i].driver_data;
total: 0 errors, 1 warnings, 0 checks, 162 lines checked
78014ea6b958 drm/i915/display: Move feature test macros to intel_display_device.h
-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#23: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:35:
+#define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:36:
+#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915))
-:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#28: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:40:
+#define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
-:30: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#30: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:42:
+#define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
-:38: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#38: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:50:
+#define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915))
-:40: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#40: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:52:
+#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#42: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:54:
+#define HAS_IPS(i915) (IS_HSW_ULT(i915) || IS_BROADWELL(i915))
-:44: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#44: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:56:
+#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
-:50: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#50: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:62:
+#define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
-:59: CHECK:LINE_SPACING: Please don't use multiple blank lines
#59: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:71:
+
+
total: 0 errors, 0 warnings, 10 checks, 162 lines checked
^ permalink raw reply [flat|nested] 22+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Move display identification/probing under display/ (rev2)
2023-05-22 20:23 [Intel-gfx] [PATCH v2 0/6] i915: Move display identification/probing under display/ Matt Roper
` (6 preceding siblings ...)
2023-05-22 21:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Move display identification/probing under display/ (rev2) Patchwork
@ 2023-05-22 21:36 ` Patchwork
2023-05-22 21:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2023-05-22 21:36 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: Move display identification/probing under display/ (rev2)
URL : https://patchwork.freedesktop.org/series/117931/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 22+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for i915: Move display identification/probing under display/ (rev2)
2023-05-22 20:23 [Intel-gfx] [PATCH v2 0/6] i915: Move display identification/probing under display/ Matt Roper
` (7 preceding siblings ...)
2023-05-22 21:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-05-22 21:46 ` Patchwork
2023-05-23 6:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-05-23 13:07 ` [Intel-gfx] [PATCH v2 0/6] i915: Move display identification/probing under display/ Jani Nikula
10 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2023-05-22 21:46 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10359 bytes --]
== Series Details ==
Series: i915: Move display identification/probing under display/ (rev2)
URL : https://patchwork.freedesktop.org/series/117931/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13175 -> Patchwork_117931v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/index.html
Participating hosts (39 -> 38)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_117931v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap@basic:
- bat-dg2-8: NOTRUN -> [SKIP][1] ([i915#4083])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-dg2-8: NOTRUN -> [SKIP][2] ([i915#4077]) +2 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@gem_mmap_gtt@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg2-8: NOTRUN -> [SKIP][3] ([i915#4079]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg2-8: NOTRUN -> [SKIP][4] ([i915#5354] / [i915#7561])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rps@basic-api:
- bat-dg2-8: NOTRUN -> [SKIP][5] ([i915#6621])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@gt_lrc:
- bat-dg2-11: [PASS][6] -> [INCOMPLETE][7] ([i915#7609] / [i915#7913])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13175/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@guc:
- bat-rpls-2: [PASS][8] -> [DMESG-WARN][9] ([i915#7852])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13175/bat-rpls-2/igt@i915_selftest@live@guc.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-rpls-2/igt@i915_selftest@live@guc.html
- bat-rpls-1: [PASS][10] -> [DMESG-WARN][11] ([i915#7852])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13175/bat-rpls-1/igt@i915_selftest@live@guc.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-rpls-1/igt@i915_selftest@live@guc.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-dg2-8: NOTRUN -> [SKIP][12] ([i915#6645])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][13] ([i915#5190])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][14] ([i915#4215] / [i915#5190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-8: NOTRUN -> [SKIP][15] ([i915#4212]) +7 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- bat-dg2-8: NOTRUN -> [SKIP][16] ([i915#7828]) +8 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][17] ([i915#4103] / [i915#4213]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-8: NOTRUN -> [SKIP][18] ([fdo#109285])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-8: NOTRUN -> [SKIP][19] ([i915#5274])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_psr@cursor_plane_move:
- bat-dg2-8: NOTRUN -> [SKIP][20] ([i915#1072]) +3 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@kms_psr@cursor_plane_move.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg2-8: NOTRUN -> [SKIP][21] ([i915#3555] / [i915#4579])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg2-8: NOTRUN -> [SKIP][22] ([i915#3708])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg2-8: NOTRUN -> [SKIP][23] ([i915#3708] / [i915#4077]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-write:
- bat-dg2-8: NOTRUN -> [SKIP][24] ([i915#3291] / [i915#3708]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-dg2-8/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_mocs:
- {bat-mtlp-8}: [DMESG-FAIL][25] ([i915#7059]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13175/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@migrate:
- bat-atsm-1: [DMESG-FAIL][27] ([i915#7699] / [i915#7913]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13175/bat-atsm-1/igt@i915_selftest@live@migrate.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-atsm-1/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@slpc:
- {bat-mtlp-8}: [DMESG-WARN][29] ([i915#6367]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13175/bat-mtlp-8/igt@i915_selftest@live@slpc.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-mtlp-8/igt@i915_selftest@live@slpc.html
- bat-rpls-1: [DMESG-WARN][31] ([i915#6367]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13175/bat-rpls-1/igt@i915_selftest@live@slpc.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/bat-rpls-1/igt@i915_selftest@live@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7852]: https://gitlab.freedesktop.org/drm/intel/issues/7852
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#8189]: https://gitlab.freedesktop.org/drm/intel/issues/8189
[i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497
Build changes
-------------
* Linux: CI_DRM_13175 -> Patchwork_117931v2
CI-20190529: 20190529
CI_DRM_13175: 4c702fe1c1be3fe0bb9de7143b9e2fa03a74a884 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7300: da81a90afee713460d783164f2456524623d3016 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_117931v2: 4c702fe1c1be3fe0bb9de7143b9e2fa03a74a884 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
9e059a40828f drm/i915/display: Move feature test macros to intel_display_device.h
2800d12fdcec drm/i915/display: Handle GMD_ID identification in display code
3dfa969c5414 drm/i915/display: Make display responsible for probing its own IP
d701ca2e3e87 drm/i915/display: Move display runtime info to display structure
ecbcd8dd0c25 drm/i915: Convert INTEL_INFO()->display to a pointer
ffef35accb59 drm/i915/display: Move display device info to header under display/
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/index.html
[-- Attachment #2: Type: text/html, Size: 11879 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for i915: Move display identification/probing under display/ (rev2)
2023-05-22 20:23 [Intel-gfx] [PATCH v2 0/6] i915: Move display identification/probing under display/ Matt Roper
` (8 preceding siblings ...)
2023-05-22 21:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-05-23 6:28 ` Patchwork
2023-05-23 13:07 ` [Intel-gfx] [PATCH v2 0/6] i915: Move display identification/probing under display/ Jani Nikula
10 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2023-05-23 6:28 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7447 bytes --]
== Series Details ==
Series: i915: Move display identification/probing under display/ (rev2)
URL : https://patchwork.freedesktop.org/series/117931/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13175_full -> Patchwork_117931v2_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_117931v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@drm_mm@all-tests:
- shard-apl: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4579]) +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/shard-apl6/igt@drm_mm@all-tests.html
* igt@gem_close_race@multigpu-basic-process:
- shard-apl: NOTRUN -> [SKIP][2] ([fdo#109271]) +39 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/shard-apl6/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-apl: [PASS][3] -> [ABORT][4] ([i915#180])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13175/shard-apl3/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/shard-apl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/shard-apl6/igt@gem_huc_copy@huc-copy.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][6] -> [ABORT][7] ([i915#5566])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13175/shard-apl7/igt@gen9_exec_parse@allowed-all.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/shard-apl7/igt@gen9_exec_parse@allowed-all.html
* igt@kms_color@ctm-max@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271]) +21 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/shard-snb1/igt@kms_color@ctm-max@pipe-a-hdmi-a-1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#79])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13175/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4579]) +13 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/shard-snb4/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-b-vga-1.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-flow@rcs0:
- {shard-rkl}: [FAIL][12] ([i915#2842]) -> [PASS][13] +2 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13175/shard-rkl-6/igt@gem_exec_fair@basic-flow@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/shard-rkl-6/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [FAIL][14] ([i915#2842]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13175/shard-glk3/igt@gem_exec_fair@basic-none-share@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/shard-glk5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- {shard-rkl}: [SKIP][16] ([i915#1397]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13175/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/shard-rkl-3/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a1:
- shard-glk: [FAIL][18] ([i915#2122]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13175/shard-glk6/igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a1.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/shard-glk2/igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a1.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [ABORT][20] ([i915#180]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13175/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
Build changes
-------------
* Linux: CI_DRM_13175 -> Patchwork_117931v2
CI-20190529: 20190529
CI_DRM_13175: 4c702fe1c1be3fe0bb9de7143b9e2fa03a74a884 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7300: da81a90afee713460d783164f2456524623d3016 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_117931v2: 4c702fe1c1be3fe0bb9de7143b9e2fa03a74a884 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v2/index.html
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^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH v2 0/6] i915: Move display identification/probing under display/
2023-05-22 20:23 [Intel-gfx] [PATCH v2 0/6] i915: Move display identification/probing under display/ Matt Roper
` (9 preceding siblings ...)
2023-05-23 6:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-05-23 13:07 ` Jani Nikula
10 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2023-05-23 13:07 UTC (permalink / raw)
To: Matt Roper, intel-gfx
Cc: Lucas De Marchi, Matt Roper, intel-xe, Andrzej Hajda
On Mon, 22 May 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
> Since i915's display code will soon be shared by two DRM drivers (i915
> and Xe), it makes sense for the display code itself to be responsible
> for recognizing the platform it's running on rather than relying on the
> making the top-level DRM driver handle this. This also becomes more
> important for all platforms MTL and beyond where we're not really
> supposed to identify platform behavior by PCI device ID anymore, but
> rather by the hardware IP version reported by the device through the
> GMD_ID register.
>
> This series creates a more well-defined split between display and
> non-display deviceinfo/runtimeinfo and then moves the definition of the
> display-specific feature flags under the display/ code. Finally, it
> switches MTL (and all future platforms), to select the display feature
> flags based on the hardware's GMD_ID identification.
My primary gripe with this series is that I didn't think of it myself.
I was always hung up on making device info (i915->__info) itself a
pointer, and got stuck there.
Nice job, and many thanks!
I see that there are already a bunch of reviews, so I didn't dig into
all the details. I left some nitpicky comments, but nothing that can't
be fixed later.
Acked-by: Jani Nikula <jani.nikula@intel.com>
BR,
Jani.
>
> v2:
> - Move DISPLAY_INFO() definition one patch earlier. (Andrzej)
> - Rename display's runtime default structure to __runtime_defaults to
> make it more clear what the purpose is. (Andrzej)
> - Simplify copy of runtime defaults to per-device runtime data.
> (Andrzej)
> - Fix uninitialized ptr use on error path during device probe. (lkp)
> - Add extra patch moving display-specific feature test macros to
> display/intel_display_device.h
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Andrzej Hajda <andrzej.hajda@intel.com>
>
> Matt Roper (5):
> drm/i915/display: Move display device info to header under display/
> drm/i915: Convert INTEL_INFO()->display to a pointer
> drm/i915/display: Move display runtime info to display structure
> drm/i915/display: Make display responsible for probing its own IP
> drm/i915/display: Handle GMD_ID identification in display code
> drm/i915/display: Move feature test macros to intel_display_device.h
>
> drivers/gpu/drm/i915/Makefile | 2 +
> drivers/gpu/drm/i915/display/intel_color.c | 31 +-
> drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
> drivers/gpu/drm/i915/display/intel_cursor.c | 4 +-
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.h | 10 +-
> .../drm/i915/display/intel_display_device.c | 764 ++++++++++++++++++
> .../drm/i915/display/intel_display_device.h | 129 +++
> .../drm/i915/display/intel_display_power.c | 6 +-
> .../drm/i915/display/intel_display_reg_defs.h | 14 +-
> drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 6 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hti.c | 2 +-
> .../drm/i915/display/skl_universal_plane.c | 2 +-
> drivers/gpu/drm/i915/display/skl_watermark.c | 8 +-
> drivers/gpu/drm/i915/i915_driver.c | 17 +-
> drivers/gpu/drm/i915/i915_drv.h | 65 +-
> drivers/gpu/drm/i915/i915_pci.c | 382 +--------
> drivers/gpu/drm/i915/i915_reg.h | 33 -
> drivers/gpu/drm/i915/intel_device_info.c | 113 +--
> drivers/gpu/drm/i915/intel_device_info.h | 67 +-
> drivers/gpu/drm/i915/intel_step.c | 8 +-
> 23 files changed, 1030 insertions(+), 641 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.h
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 22+ messages in thread