[Intel-gfx] [PATCH 0/2] Add support for LMEM PCIe resizable bar

[Intel-gfx] [PATCH 0/2] Add support for LMEM PCIe resizable bar

[priyanka.dandamudi]

From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>

Added support to resize the bar to maximum supported.
Also, added new modparam lmem_bar_size which can resize the bar to one of the supported sizes.

Akeem G Abodunrin (1):
  drm/i915: Add support for LMEM PCIe resizable bar

Priyanka Dandamudi (1):
  drm/i915: Add lmem_bar_size modparam

 drivers/gpu/drm/i915/gt/intel_region_lmem.c |   4 +
 drivers/gpu/drm/i915/i915_driver.c          | 118 ++++++++++++++++++++
 drivers/gpu/drm/i915/i915_params.c          |   2 +
 drivers/gpu/drm/i915/i915_params.h          |   1 +
 4 files changed, 125 insertions(+)

-- 
2.25.1

[Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[priyanka.dandamudi]

From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>

Add support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible with 32-bit
systems. So, those devices cannot claim larger memory BAR windows size due
to the system BIOS limitation. With this change, it would be possible to
reprogram the windows of the bridge directly above the requesting device
on the same BAR type.

Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
 drivers/gpu/drm/i915/i915_driver.c | 92 ++++++++++++++++++++++++++++++
 1 file changed, 92 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index d26dcca7e654..4bdb471cb2e2 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
 		__intel_gt_reset(to_gt(i915), ALL_ENGINES);
 }
 
+static void __release_bars(struct pci_dev *pdev)
+{
+	int resno;
+
+	for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
+		if (pci_resource_len(pdev, resno))
+			pci_release_resource(pdev, resno);
+	}
+}
+
+static void
+__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
+{
+	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+	int bar_size = pci_rebar_bytes_to_size(size);
+	int ret;
+
+	__release_bars(pdev);
+
+	ret = pci_resize_resource(pdev, resno, bar_size);
+	if (ret) {
+		drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
+			 resno, 1 << bar_size, ERR_PTR(ret));
+		return;
+	}
+
+	drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
+}
+
+/* BAR size starts from 1MB - 2^20 */
+#define BAR_SIZE_SHIFT 20
+static resource_size_t
+__lmem_rebar_size(struct drm_i915_private *i915, int resno)
+{
+	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+	u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
+	resource_size_t size;
+
+	if (!rebar)
+		return 0;
+
+	size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
+
+	if (size <= pci_resource_len(pdev, resno))
+		return 0;
+
+	return size;
+}
+
+#define LMEM_BAR_NUM 2
+static void i915_resize_lmem_bar(struct drm_i915_private *i915)
+{
+	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+	struct pci_bus *root = pdev->bus;
+	struct resource *root_res;
+	resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
+	u32 pci_cmd;
+	int i;
+
+	if (!rebar_size)
+		return;
+
+	/* Find out if root bus contains 64bit memory addressing */
+	while (root->parent)
+		root = root->parent;
+
+	pci_bus_for_each_resource(root, root_res, i) {
+		if (root_res && root_res->flags & (IORESOURCE_MEM |
+					IORESOURCE_MEM_64) && root_res->start > 0x100000000ull)
+			break;
+	}
+
+	/* pci_resize_resource will fail anyways */
+	if (!root_res) {
+		drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
+		return;
+	}
+
+	/* First disable PCI memory decoding references */
+	pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
+	pci_write_config_dword(pdev, PCI_COMMAND,
+			       pci_cmd & ~PCI_COMMAND_MEMORY);
+
+	__resize_bar(i915, LMEM_BAR_NUM, rebar_size);
+
+	pci_assign_unassigned_bus_resources(pdev->bus);
+	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
+}
+
 /**
  * i915_driver_early_probe - setup state not requiring device access
  * @dev_priv: device private
@@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 
 	disable_rpm_wakeref_asserts(&i915->runtime_pm);
 
+	if (HAS_LMEM(i915))
+		i915_resize_lmem_bar(i915);
+
 	intel_vgpu_detect(i915);
 
 	ret = intel_gt_probe_all(i915);
-- 
2.25.1

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[Jani Nikula]

On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
> From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>
> Add support for the local memory PICe resizable bar, so that
> local memory can be resized to the maximum size supported by the device,
> and mapped correctly to the PCIe memory bar. It is usual that GPU
> devices expose only 256MB BARs primarily to be compatible with 32-bit
> systems. So, those devices cannot claim larger memory BAR windows size due
> to the system BIOS limitation. With this change, it would be possible to
> reprogram the windows of the bridge directly above the requesting device
> on the same BAR type.
>
> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Stuart Summers <stuart.summers@intel.com>
> Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>

Please see https://lore.kernel.org/r/87pmj8vesm.fsf@intel.com

> ---
>  drivers/gpu/drm/i915/i915_driver.c | 92 ++++++++++++++++++++++++++++++
>  1 file changed, 92 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index d26dcca7e654..4bdb471cb2e2 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
>  		__intel_gt_reset(to_gt(i915), ALL_ENGINES);
>  }
>  
> +static void __release_bars(struct pci_dev *pdev)
> +{
> +	int resno;
> +
> +	for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
> +		if (pci_resource_len(pdev, resno))
> +			pci_release_resource(pdev, resno);
> +	}
> +}
> +
> +static void
> +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
> +{
> +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> +	int bar_size = pci_rebar_bytes_to_size(size);
> +	int ret;
> +
> +	__release_bars(pdev);
> +
> +	ret = pci_resize_resource(pdev, resno, bar_size);
> +	if (ret) {
> +		drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
> +			 resno, 1 << bar_size, ERR_PTR(ret));
> +		return;
> +	}
> +
> +	drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
> +}
> +
> +/* BAR size starts from 1MB - 2^20 */
> +#define BAR_SIZE_SHIFT 20
> +static resource_size_t
> +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
> +{
> +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> +	u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
> +	resource_size_t size;
> +
> +	if (!rebar)
> +		return 0;
> +
> +	size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
> +
> +	if (size <= pci_resource_len(pdev, resno))
> +		return 0;
> +
> +	return size;
> +}
> +
> +#define LMEM_BAR_NUM 2
> +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
> +{
> +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> +	struct pci_bus *root = pdev->bus;
> +	struct resource *root_res;
> +	resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
> +	u32 pci_cmd;
> +	int i;
> +
> +	if (!rebar_size)
> +		return;
> +
> +	/* Find out if root bus contains 64bit memory addressing */
> +	while (root->parent)
> +		root = root->parent;
> +
> +	pci_bus_for_each_resource(root, root_res, i) {
> +		if (root_res && root_res->flags & (IORESOURCE_MEM |
> +					IORESOURCE_MEM_64) && root_res->start > 0x100000000ull)
> +			break;
> +	}
> +
> +	/* pci_resize_resource will fail anyways */
> +	if (!root_res) {
> +		drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
> +		return;
> +	}
> +
> +	/* First disable PCI memory decoding references */
> +	pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
> +	pci_write_config_dword(pdev, PCI_COMMAND,
> +			       pci_cmd & ~PCI_COMMAND_MEMORY);
> +
> +	__resize_bar(i915, LMEM_BAR_NUM, rebar_size);
> +
> +	pci_assign_unassigned_bus_resources(pdev->bus);
> +	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
> +}
> +
>  /**
>   * i915_driver_early_probe - setup state not requiring device access
>   * @dev_priv: device private
> @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>  
>  	disable_rpm_wakeref_asserts(&i915->runtime_pm);
>  
> +	if (HAS_LMEM(i915))
> +		i915_resize_lmem_bar(i915);
> +
>  	intel_vgpu_detect(i915);
>  
>  	ret = intel_gt_probe_all(i915);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[Lucas De Marchi]

Cc'ing intel-pci, lkml, Bjorn

On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
>On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
>> From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>>
>> Add support for the local memory PICe resizable bar, so that
>> local memory can be resized to the maximum size supported by the device,
>> and mapped correctly to the PCIe memory bar. It is usual that GPU
>> devices expose only 256MB BARs primarily to be compatible with 32-bit
>> systems. So, those devices cannot claim larger memory BAR windows size due
>> to the system BIOS limitation. With this change, it would be possible to
>> reprogram the windows of the bridge directly above the requesting device
>> on the same BAR type.

There is a big caveat here that this may be too late as other drivers
may have already mapped their BARs - so probably too late in the pci scan
for it to be effective. In fact, after using this for a while, it seems
to fail too often, particularly on CFL systems.

Do we have any alternative to be done in the PCI subsystem during the
scan?  There is other work in progress to allow i915 to use the rest of
the device memory even with a smaller BAR, but it would be better if we
can improve our chances of succeeding the resize.

thanks
Lucas De Marchi


>>
>> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
>> Cc: Stuart Summers <stuart.summers@intel.com>
>> Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
>> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
>> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
>> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>
>Please see https://lore.kernel.org/r/87pmj8vesm.fsf@intel.com
>
>> ---
>>  drivers/gpu/drm/i915/i915_driver.c | 92 ++++++++++++++++++++++++++++++
>>  1 file changed, 92 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
>> index d26dcca7e654..4bdb471cb2e2 100644
>> --- a/drivers/gpu/drm/i915/i915_driver.c
>> +++ b/drivers/gpu/drm/i915/i915_driver.c
>> @@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
>>  		__intel_gt_reset(to_gt(i915), ALL_ENGINES);
>>  }
>>
>> +static void __release_bars(struct pci_dev *pdev)
>> +{
>> +	int resno;
>> +
>> +	for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
>> +		if (pci_resource_len(pdev, resno))
>> +			pci_release_resource(pdev, resno);
>> +	}
>> +}
>> +
>> +static void
>> +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
>> +{
>> +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> +	int bar_size = pci_rebar_bytes_to_size(size);
>> +	int ret;
>> +
>> +	__release_bars(pdev);
>> +
>> +	ret = pci_resize_resource(pdev, resno, bar_size);
>> +	if (ret) {
>> +		drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
>> +			 resno, 1 << bar_size, ERR_PTR(ret));
>> +		return;
>> +	}
>> +
>> +	drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
>> +}
>> +
>> +/* BAR size starts from 1MB - 2^20 */
>> +#define BAR_SIZE_SHIFT 20
>> +static resource_size_t
>> +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
>> +{
>> +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> +	u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
>> +	resource_size_t size;
>> +
>> +	if (!rebar)
>> +		return 0;
>> +
>> +	size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
>> +
>> +	if (size <= pci_resource_len(pdev, resno))
>> +		return 0;
>> +
>> +	return size;
>> +}
>> +
>> +#define LMEM_BAR_NUM 2
>> +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
>> +{
>> +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> +	struct pci_bus *root = pdev->bus;
>> +	struct resource *root_res;
>> +	resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
>> +	u32 pci_cmd;
>> +	int i;
>> +
>> +	if (!rebar_size)
>> +		return;
>> +
>> +	/* Find out if root bus contains 64bit memory addressing */
>> +	while (root->parent)
>> +		root = root->parent;
>> +
>> +	pci_bus_for_each_resource(root, root_res, i) {
>> +		if (root_res && root_res->flags & (IORESOURCE_MEM |
>> +					IORESOURCE_MEM_64) && root_res->start > 0x100000000ull)
>> +			break;
>> +	}
>> +
>> +	/* pci_resize_resource will fail anyways */
>> +	if (!root_res) {
>> +		drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
>> +		return;
>> +	}
>> +
>> +	/* First disable PCI memory decoding references */
>> +	pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
>> +	pci_write_config_dword(pdev, PCI_COMMAND,
>> +			       pci_cmd & ~PCI_COMMAND_MEMORY);
>> +
>> +	__resize_bar(i915, LMEM_BAR_NUM, rebar_size);
>> +
>> +	pci_assign_unassigned_bus_resources(pdev->bus);
>> +	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
>> +}
>> +
>>  /**
>>   * i915_driver_early_probe - setup state not requiring device access
>>   * @dev_priv: device private
>> @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>>
>>  	disable_rpm_wakeref_asserts(&i915->runtime_pm);
>>
>> +	if (HAS_LMEM(i915))
>> +		i915_resize_lmem_bar(i915);
>> +
>>  	intel_vgpu_detect(i915);
>>
>>  	ret = intel_gt_probe_all(i915);
>
>-- 
>Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[Bjorn Helgaas]

[+cc Christian, author of pci_resize_resource(), Sergei, author of
rebalancing patches]

Hi Lucas,

On Fri, Jun 17, 2022 at 11:44:41AM -0700, Lucas De Marchi wrote:
> Cc'ing intel-pci, lkml, Bjorn
> 
> On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
> > On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
> > > From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> > > 
> > > Add support for the local memory PICe resizable bar, so that
> > > local memory can be resized to the maximum size supported by the device,
> > > and mapped correctly to the PCIe memory bar. It is usual that GPU
> > > devices expose only 256MB BARs primarily to be compatible with 32-bit
> > > systems. So, those devices cannot claim larger memory BAR windows size due
> > > to the system BIOS limitation. With this change, it would be possible to
> > > reprogram the windows of the bridge directly above the requesting device
> > > on the same BAR type.
> 
> There is a big caveat here that this may be too late as other drivers
> may have already mapped their BARs - so probably too late in the pci scan
> for it to be effective. In fact, after using this for a while, it seems
> to fail too often, particularly on CFL systems.

Help me understand the "too late" part.  Do you mean that there is
enough available space for the max BAR size, but it's fragmented and
therefore not usable?  And that if we could do something earlier,
before drivers have claimed their devices, we might be able to compact
the BARs of other devices to make a larger contiguous available space?

That is theoretically possible, but I think the current
pci_resize_resource() only supports resizing of the specified BAR and
any upstream bridge windows.  I don't think it supports moving BARs of
other devices.

Sergei did some nice work that might help with this situation because
it can move BARs around more generally.  It hasn't quite achieved
critical mass yet, but maybe this would help get there:

  https://lore.kernel.org/linux-pci/20201218174011.340514-1-s.miroshnichenko@yadro.com/

If I understand Sergei's series correctly, this rebalancing actually
cannot be done during enumeration because we only move BARs if a
driver for the device indicates that it supports it, so there would be
no requirement to do this early.

> Do we have any alternative to be done in the PCI subsystem during the
> scan?  There is other work in progress to allow i915 to use the rest of
> the device memory even with a smaller BAR, but it would be better if we
> can improve our chances of succeeding the resize.

> > > Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> > > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> > > Cc: Stuart Summers <stuart.summers@intel.com>
> > > Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
> > > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> > > Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> > > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> > 
> > Please see https://lore.kernel.org/r/87pmj8vesm.fsf@intel.com
> > 
> > > ---
> > >  drivers/gpu/drm/i915/i915_driver.c | 92 ++++++++++++++++++++++++++++++
> > >  1 file changed, 92 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> > > index d26dcca7e654..4bdb471cb2e2 100644
> > > --- a/drivers/gpu/drm/i915/i915_driver.c
> > > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > > @@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
> > >  		__intel_gt_reset(to_gt(i915), ALL_ENGINES);
> > >  }
> > > 
> > > +static void __release_bars(struct pci_dev *pdev)
> > > +{
> > > +	int resno;
> > > +
> > > +	for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
> > > +		if (pci_resource_len(pdev, resno))
> > > +			pci_release_resource(pdev, resno);
> > > +	}
> > > +}
> > > +
> > > +static void
> > > +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
> > > +{
> > > +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > > +	int bar_size = pci_rebar_bytes_to_size(size);
> > > +	int ret;
> > > +
> > > +	__release_bars(pdev);
> > > +
> > > +	ret = pci_resize_resource(pdev, resno, bar_size);
> > > +	if (ret) {
> > > +		drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
> > > +			 resno, 1 << bar_size, ERR_PTR(ret));
> > > +		return;
> > > +	}
> > > +
> > > +	drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
> > > +}
> > > +
> > > +/* BAR size starts from 1MB - 2^20 */
> > > +#define BAR_SIZE_SHIFT 20
> > > +static resource_size_t
> > > +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
> > > +{
> > > +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > > +	u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
> > > +	resource_size_t size;
> > > +
> > > +	if (!rebar)
> > > +		return 0;
> > > +
> > > +	size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
> > > +
> > > +	if (size <= pci_resource_len(pdev, resno))
> > > +		return 0;
> > > +
> > > +	return size;
> > > +}
> > > +
> > > +#define LMEM_BAR_NUM 2
> > > +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
> > > +{
> > > +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > > +	struct pci_bus *root = pdev->bus;
> > > +	struct resource *root_res;
> > > +	resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
> > > +	u32 pci_cmd;
> > > +	int i;
> > > +
> > > +	if (!rebar_size)
> > > +		return;
> > > +
> > > +	/* Find out if root bus contains 64bit memory addressing */
> > > +	while (root->parent)
> > > +		root = root->parent;
> > > +
> > > +	pci_bus_for_each_resource(root, root_res, i) {
> > > +		if (root_res && root_res->flags & (IORESOURCE_MEM |
> > > +					IORESOURCE_MEM_64) && root_res->start > 0x100000000ull)
> > > +			break;
> > > +	}
> > > +
> > > +	/* pci_resize_resource will fail anyways */
> > > +	if (!root_res) {
> > > +		drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
> > > +		return;
> > > +	}
> > > +
> > > +	/* First disable PCI memory decoding references */
> > > +	pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
> > > +	pci_write_config_dword(pdev, PCI_COMMAND,
> > > +			       pci_cmd & ~PCI_COMMAND_MEMORY);
> > > +
> > > +	__resize_bar(i915, LMEM_BAR_NUM, rebar_size);
> > > +
> > > +	pci_assign_unassigned_bus_resources(pdev->bus);
> > > +	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
> > > +}
> > > +
> > >  /**
> > >   * i915_driver_early_probe - setup state not requiring device access
> > >   * @dev_priv: device private
> > > @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> > > 
> > >  	disable_rpm_wakeref_asserts(&i915->runtime_pm);
> > > 
> > > +	if (HAS_LMEM(i915))
> > > +		i915_resize_lmem_bar(i915);
> > > +
> > >  	intel_vgpu_detect(i915);
> > > 
> > >  	ret = intel_gt_probe_all(i915);
> > 
> > -- 
> > Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[Lucas De Marchi]

On Fri, Jun 17, 2022 at 03:32:52PM -0500, Bjorn Helgaas wrote:
>[+cc Christian, author of pci_resize_resource(), Sergei, author of
>rebalancing patches]
>
>Hi Lucas,
>
>On Fri, Jun 17, 2022 at 11:44:41AM -0700, Lucas De Marchi wrote:
>> Cc'ing intel-pci, lkml, Bjorn
>>
>> On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
>> > On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
>> > > From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>> > >
>> > > Add support for the local memory PICe resizable bar, so that
>> > > local memory can be resized to the maximum size supported by the device,
>> > > and mapped correctly to the PCIe memory bar. It is usual that GPU
>> > > devices expose only 256MB BARs primarily to be compatible with 32-bit
>> > > systems. So, those devices cannot claim larger memory BAR windows size due
>> > > to the system BIOS limitation. With this change, it would be possible to
>> > > reprogram the windows of the bridge directly above the requesting device
>> > > on the same BAR type.
>>
>> There is a big caveat here that this may be too late as other drivers
>> may have already mapped their BARs - so probably too late in the pci scan
>> for it to be effective. In fact, after using this for a while, it seems
>> to fail too often, particularly on CFL systems.
>
>Help me understand the "too late" part.  Do you mean that there is
>enough available space for the max BAR size, but it's fragmented and
>therefore not usable?  And that if we could do something earlier,
>before drivers have claimed their devices, we might be able to compact
>the BARs of other devices to make a larger contiguous available space?

yes. I will dig some logs I had in the past to confirm.


>That is theoretically possible, but I think the current
>pci_resize_resource() only supports resizing of the specified BAR and
>any upstream bridge windows.  I don't think it supports moving BARs of
>other devices.
>
>Sergei did some nice work that might help with this situation because
>it can move BARs around more generally.  It hasn't quite achieved
>critical mass yet, but maybe this would help get there:
>
>  https://lore.kernel.org/linux-pci/20201218174011.340514-1-s.miroshnichenko@yadro.com/

oh... I hadn't thought about pause/ioremap/unpause. That looks rad :).
So it seems this would integrate neatly with
pci_resize_resource() (what this patch is doing), as long as drivers for
devices affected implement
.bar_fixed()/.rescan_prepare()/.rescan_done(). That seems it would solve
our issues too.

thanks
Lucas De Marchi

>
>If I understand Sergei's series correctly, this rebalancing actually
>cannot be done during enumeration because we only move BARs if a
>driver for the device indicates that it supports it, so there would be
>no requirement to do this early.
>
>> Do we have any alternative to be done in the PCI subsystem during the
>> scan?  There is other work in progress to allow i915 to use the rest of
>> the device memory even with a smaller BAR, but it would be better if we
>> can improve our chances of succeeding the resize.
>
>> > > Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>> > > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
>> > > Cc: Stuart Summers <stuart.summers@intel.com>
>> > > Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
>> > > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
>> > > Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
>> > > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>> >
>> > Please see https://lore.kernel.org/r/87pmj8vesm.fsf@intel.com
>> >
>> > > ---
>> > >  drivers/gpu/drm/i915/i915_driver.c | 92 ++++++++++++++++++++++++++++++
>> > >  1 file changed, 92 insertions(+)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
>> > > index d26dcca7e654..4bdb471cb2e2 100644
>> > > --- a/drivers/gpu/drm/i915/i915_driver.c
>> > > +++ b/drivers/gpu/drm/i915/i915_driver.c
>> > > @@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
>> > >  		__intel_gt_reset(to_gt(i915), ALL_ENGINES);
>> > >  }
>> > >
>> > > +static void __release_bars(struct pci_dev *pdev)
>> > > +{
>> > > +	int resno;
>> > > +
>> > > +	for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
>> > > +		if (pci_resource_len(pdev, resno))
>> > > +			pci_release_resource(pdev, resno);
>> > > +	}
>> > > +}
>> > > +
>> > > +static void
>> > > +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
>> > > +{
>> > > +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> > > +	int bar_size = pci_rebar_bytes_to_size(size);
>> > > +	int ret;
>> > > +
>> > > +	__release_bars(pdev);
>> > > +
>> > > +	ret = pci_resize_resource(pdev, resno, bar_size);
>> > > +	if (ret) {
>> > > +		drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
>> > > +			 resno, 1 << bar_size, ERR_PTR(ret));
>> > > +		return;
>> > > +	}
>> > > +
>> > > +	drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
>> > > +}
>> > > +
>> > > +/* BAR size starts from 1MB - 2^20 */
>> > > +#define BAR_SIZE_SHIFT 20
>> > > +static resource_size_t
>> > > +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
>> > > +{
>> > > +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> > > +	u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
>> > > +	resource_size_t size;
>> > > +
>> > > +	if (!rebar)
>> > > +		return 0;
>> > > +
>> > > +	size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
>> > > +
>> > > +	if (size <= pci_resource_len(pdev, resno))
>> > > +		return 0;
>> > > +
>> > > +	return size;
>> > > +}
>> > > +
>> > > +#define LMEM_BAR_NUM 2
>> > > +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
>> > > +{
>> > > +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> > > +	struct pci_bus *root = pdev->bus;
>> > > +	struct resource *root_res;
>> > > +	resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
>> > > +	u32 pci_cmd;
>> > > +	int i;
>> > > +
>> > > +	if (!rebar_size)
>> > > +		return;
>> > > +
>> > > +	/* Find out if root bus contains 64bit memory addressing */
>> > > +	while (root->parent)
>> > > +		root = root->parent;
>> > > +
>> > > +	pci_bus_for_each_resource(root, root_res, i) {
>> > > +		if (root_res && root_res->flags & (IORESOURCE_MEM |
>> > > +					IORESOURCE_MEM_64) && root_res->start > 0x100000000ull)
>> > > +			break;
>> > > +	}
>> > > +
>> > > +	/* pci_resize_resource will fail anyways */
>> > > +	if (!root_res) {
>> > > +		drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
>> > > +		return;
>> > > +	}
>> > > +
>> > > +	/* First disable PCI memory decoding references */
>> > > +	pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
>> > > +	pci_write_config_dword(pdev, PCI_COMMAND,
>> > > +			       pci_cmd & ~PCI_COMMAND_MEMORY);
>> > > +
>> > > +	__resize_bar(i915, LMEM_BAR_NUM, rebar_size);
>> > > +
>> > > +	pci_assign_unassigned_bus_resources(pdev->bus);
>> > > +	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
>> > > +}
>> > > +
>> > >  /**
>> > >   * i915_driver_early_probe - setup state not requiring device access
>> > >   * @dev_priv: device private
>> > > @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>> > >
>> > >  	disable_rpm_wakeref_asserts(&i915->runtime_pm);
>> > >
>> > > +	if (HAS_LMEM(i915))
>> > > +		i915_resize_lmem_bar(i915);
>> > > +
>> > >  	intel_vgpu_detect(i915);
>> > >
>> > >  	ret = intel_gt_probe_all(i915);
>> >
>> > --
>> > Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[Christian König]

Am 17.06.22 um 23:27 schrieb Lucas De Marchi:
> On Fri, Jun 17, 2022 at 03:32:52PM -0500, Bjorn Helgaas wrote:
>> [+cc Christian, author of pci_resize_resource(), Sergei, author of
>> rebalancing patches]
>>
>> Hi Lucas,
>>
>> On Fri, Jun 17, 2022 at 11:44:41AM -0700, Lucas De Marchi wrote:
>>> Cc'ing intel-pci, lkml, Bjorn
>>>
>>> On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
>>> > On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
>>> > > From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>>> > >
>>> > > Add support for the local memory PICe resizable bar, so that
>>> > > local memory can be resized to the maximum size supported by the 
>>> device,
>>> > > and mapped correctly to the PCIe memory bar. It is usual that GPU
>>> > > devices expose only 256MB BARs primarily to be compatible with 
>>> 32-bit
>>> > > systems. So, those devices cannot claim larger memory BAR 
>>> windows size due
>>> > > to the system BIOS limitation. With this change, it would be 
>>> possible to
>>> > > reprogram the windows of the bridge directly above the 
>>> requesting device
>>> > > on the same BAR type.
>>>
>>> There is a big caveat here that this may be too late as other drivers
>>> may have already mapped their BARs - so probably too late in the pci 
>>> scan
>>> for it to be effective. In fact, after using this for a while, it seems
>>> to fail too often, particularly on CFL systems.
>>
>> Help me understand the "too late" part.  Do you mean that there is
>> enough available space for the max BAR size, but it's fragmented and
>> therefore not usable?  And that if we could do something earlier,
>> before drivers have claimed their devices, we might be able to compact
>> the BARs of other devices to make a larger contiguous available space?
>
> yes. I will dig some logs I had in the past to confirm.
>
>
>> That is theoretically possible, but I think the current
>> pci_resize_resource() only supports resizing of the specified BAR and
>> any upstream bridge windows.  I don't think it supports moving BARs of
>> other devices.
>>
>> Sergei did some nice work that might help with this situation because
>> it can move BARs around more generally.  It hasn't quite achieved
>> critical mass yet, but maybe this would help get there:
>>
>>  https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Flinux-pci%2F20201218174011.340514-1-s.miroshnichenko%40yadro.com%2F&amp;data=05%7C01%7Cchristian.koenig%40amd.com%7C8096027f68484d0656b108da50a82e7d%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637910980509199388%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=%2FfntE2FTQ8wmLnz4wnzk94R0GMLEwVs7Mj18%2B9Q6PJk%3D&amp;reserved=0 
>>
>
> oh... I hadn't thought about pause/ioremap/unpause. That looks rad :).
> So it seems this would integrate neatly with
> pci_resize_resource() (what this patch is doing), as long as drivers for
> devices affected implement
> .bar_fixed()/.rescan_prepare()/.rescan_done(). That seems it would solve
> our issues too.

Well we never ran into any of the issues you describe with PCIe BAR 
resize for GPUs so there must be something you do differently to AMD 
hardware regarding this.

Additional to that keep in mind that you can't resize the BAR before 
kicking out vgacon/efifb or otherwise it can happen that the just 
released 256MiB window is still used while you try to resize it. When 
you do that you usually end up with a hard lockup of the system.

Regards,
Christian.

>
> thanks
> Lucas De Marchi
>
>>
>> If I understand Sergei's series correctly, this rebalancing actually
>> cannot be done during enumeration because we only move BARs if a
>> driver for the device indicates that it supports it, so there would be
>> no requirement to do this early.
>>
>>> Do we have any alternative to be done in the PCI subsystem during the
>>> scan?  There is other work in progress to allow i915 to use the rest of
>>> the device memory even with a smaller BAR, but it would be better if we
>>> can improve our chances of succeeding the resize.
>>
>>> > > Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>>> > > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
>>> > > Cc: Stuart Summers <stuart.summers@intel.com>
>>> > > Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
>>> > > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
>>> > > Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
>>> > > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>>> >
>>> > Please see 
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fr%2F87pmj8vesm.fsf%40intel.com&amp;data=05%7C01%7Cchristian.koenig%40amd.com%7C8096027f68484d0656b108da50a82e7d%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637910980509199388%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=d4cf7HQ6t7y1Xobwjdt8im%2Fh0E5IZsXgzQDpsB2vCU4%3D&amp;reserved=0
>>> >
>>> > > ---
>>> > >  drivers/gpu/drm/i915/i915_driver.c | 92 
>>> ++++++++++++++++++++++++++++++
>>> > >  1 file changed, 92 insertions(+)
>>> > >
>>> > > diff --git a/drivers/gpu/drm/i915/i915_driver.c 
>>> b/drivers/gpu/drm/i915/i915_driver.c
>>> > > index d26dcca7e654..4bdb471cb2e2 100644
>>> > > --- a/drivers/gpu/drm/i915/i915_driver.c
>>> > > +++ b/drivers/gpu/drm/i915/i915_driver.c
>>> > > @@ -303,6 +303,95 @@ static void sanitize_gpu(struct 
>>> drm_i915_private *i915)
>>> > >          __intel_gt_reset(to_gt(i915), ALL_ENGINES);
>>> > >  }
>>> > >
>>> > > +static void __release_bars(struct pci_dev *pdev)
>>> > > +{
>>> > > +    int resno;
>>> > > +
>>> > > +    for (resno = PCI_STD_RESOURCES; resno < 
>>> PCI_STD_RESOURCE_END; resno++) {
>>> > > +        if (pci_resource_len(pdev, resno))
>>> > > +            pci_release_resource(pdev, resno);
>>> > > +    }
>>> > > +}
>>> > > +
>>> > > +static void
>>> > > +__resize_bar(struct drm_i915_private *i915, int resno, 
>>> resource_size_t size)
>>> > > +{
>>> > > +    struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>>> > > +    int bar_size = pci_rebar_bytes_to_size(size);
>>> > > +    int ret;
>>> > > +
>>> > > +    __release_bars(pdev);
>>> > > +
>>> > > +    ret = pci_resize_resource(pdev, resno, bar_size);
>>> > > +    if (ret) {
>>> > > +        drm_info(&i915->drm, "Failed to resize BAR%d to %dM 
>>> (%pe)\n",
>>> > > +             resno, 1 << bar_size, ERR_PTR(ret));
>>> > > +        return;
>>> > > +    }
>>> > > +
>>> > > +    drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << 
>>> bar_size);
>>> > > +}
>>> > > +
>>> > > +/* BAR size starts from 1MB - 2^20 */
>>> > > +#define BAR_SIZE_SHIFT 20
>>> > > +static resource_size_t
>>> > > +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
>>> > > +{
>>> > > +    struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>>> > > +    u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
>>> > > +    resource_size_t size;
>>> > > +
>>> > > +    if (!rebar)
>>> > > +        return 0;
>>> > > +
>>> > > +    size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
>>> > > +
>>> > > +    if (size <= pci_resource_len(pdev, resno))
>>> > > +        return 0;
>>> > > +
>>> > > +    return size;
>>> > > +}
>>> > > +
>>> > > +#define LMEM_BAR_NUM 2
>>> > > +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
>>> > > +{
>>> > > +    struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>>> > > +    struct pci_bus *root = pdev->bus;
>>> > > +    struct resource *root_res;
>>> > > +    resource_size_t rebar_size = __lmem_rebar_size(i915, 
>>> LMEM_BAR_NUM);
>>> > > +    u32 pci_cmd;
>>> > > +    int i;
>>> > > +
>>> > > +    if (!rebar_size)
>>> > > +        return;
>>> > > +
>>> > > +    /* Find out if root bus contains 64bit memory addressing */
>>> > > +    while (root->parent)
>>> > > +        root = root->parent;
>>> > > +
>>> > > +    pci_bus_for_each_resource(root, root_res, i) {
>>> > > +        if (root_res && root_res->flags & (IORESOURCE_MEM |
>>> > > +                    IORESOURCE_MEM_64) && root_res->start > 
>>> 0x100000000ull)
>>> > > +            break;
>>> > > +    }
>>> > > +
>>> > > +    /* pci_resize_resource will fail anyways */
>>> > > +    if (!root_res) {
>>> > > +        drm_info(&i915->drm, "Can't resize LMEM BAR - platform 
>>> support is missing\n");
>>> > > +        return;
>>> > > +    }
>>> > > +
>>> > > +    /* First disable PCI memory decoding references */
>>> > > +    pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
>>> > > +    pci_write_config_dword(pdev, PCI_COMMAND,
>>> > > +                   pci_cmd & ~PCI_COMMAND_MEMORY);
>>> > > +
>>> > > +    __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
>>> > > +
>>> > > + pci_assign_unassigned_bus_resources(pdev->bus);
>>> > > +    pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
>>> > > +}
>>> > > +
>>> > >  /**
>>> > >   * i915_driver_early_probe - setup state not requiring device 
>>> access
>>> > >   * @dev_priv: device private
>>> > > @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, 
>>> const struct pci_device_id *ent)
>>> > >
>>> > > disable_rpm_wakeref_asserts(&i915->runtime_pm);
>>> > >
>>> > > +    if (HAS_LMEM(i915))
>>> > > +        i915_resize_lmem_bar(i915);
>>> > > +
>>> > >      intel_vgpu_detect(i915);
>>> > >
>>> > >      ret = intel_gt_probe_all(i915);
>>> >
>>> > --
>>> > Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[Dandamudi, Priyanka]

> -----Original Message-----
> From: Christian König <christian.koenig@amd.com>
> Sent: 18 June 2022 08:45 PM
> To: De Marchi, Lucas <lucas.demarchi@intel.com>; Bjorn Helgaas
> <helgaas@kernel.org>
> Cc: linux-pci@vger.kernel.org; intel-gfx@lists.freedesktop.org; Sergei
> Miroshnichenko <s.miroshnichenko@yadro.com>; linux-
> kernel@vger.kernel.org; Dandamudi, Priyanka
> <priyanka.dandamudi@intel.com>; Auld, Matthew
> <matthew.auld@intel.com>; Bjorn Helgaas <bhelgaas@google.com>
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe
> resizable bar
> 
> Am 17.06.22 um 23:27 schrieb Lucas De Marchi:
> > On Fri, Jun 17, 2022 at 03:32:52PM -0500, Bjorn Helgaas wrote:
> >> [+cc Christian, author of pci_resize_resource(), Sergei, author of
> >> rebalancing patches]
> >>
> >> Hi Lucas,
> >>
> >> On Fri, Jun 17, 2022 at 11:44:41AM -0700, Lucas De Marchi wrote:
> >>> Cc'ing intel-pci, lkml, Bjorn
> >>>
> >>> On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
> >>> > On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
> >>> > > From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> >>> > >
> >>> > > Add support for the local memory PICe resizable bar, so that
> >>> > > local memory can be resized to the maximum size supported by the
> >>> device,
> >>> > > and mapped correctly to the PCIe memory bar. It is usual that
> >>> > > GPU devices expose only 256MB BARs primarily to be compatible
> >>> > > with
> >>> 32-bit
> >>> > > systems. So, those devices cannot claim larger memory BAR
> >>> windows size due
> >>> > > to the system BIOS limitation. With this change, it would be
> >>> possible to
> >>> > > reprogram the windows of the bridge directly above the
> >>> requesting device
> >>> > > on the same BAR type.
> >>>
> >>> There is a big caveat here that this may be too late as other
> >>> drivers may have already mapped their BARs - so probably too late in
> >>> the pci scan for it to be effective. In fact, after using this for a
> >>> while, it seems to fail too often, particularly on CFL systems.
> >>
> >> Help me understand the "too late" part.  Do you mean that there is
> >> enough available space for the max BAR size, but it's fragmented and
> >> therefore not usable?  And that if we could do something earlier,
> >> before drivers have claimed their devices, we might be able to
> >> compact the BARs of other devices to make a larger contiguous available
> space?
> >
> > yes. I will dig some logs I had in the past to confirm.
> >
> >
> >> That is theoretically possible, but I think the current
> >> pci_resize_resource() only supports resizing of the specified BAR and
> >> any upstream bridge windows.  I don't think it supports moving BARs
> >> of other devices.
> >>
> >> Sergei did some nice work that might help with this situation because
> >> it can move BARs around more generally.  It hasn't quite achieved
> >> critical mass yet, but maybe this would help get there:
> >>
> >>
> >>
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flor
> >> e.kernel.org%2Flinux-pci%2F20201218174011.340514-1-
> s.miroshnichenko%4
> >>
> 0yadro.com%2F&amp;data=05%7C01%7Cchristian.koenig%40amd.com%7C8
> 096027
> >>
> f68484d0656b108da50a82e7d%7C3dd8961fe4884e608e11a82d994e183d%7C
> 0%7C0%
> >>
> 7C637910980509199388%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjA
> wMDAiLCJQ
> >>
> IjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;
> sdata=
> >>
> %2FfntE2FTQ8wmLnz4wnzk94R0GMLEwVs7Mj18%2B9Q6PJk%3D&amp;reser
> ved=0
> >>
> >
> > oh... I hadn't thought about pause/ioremap/unpause. That looks rad :).
> > So it seems this would integrate neatly with
> > pci_resize_resource() (what this patch is doing), as long as drivers
> > for devices affected implement
> > .bar_fixed()/.rescan_prepare()/.rescan_done(). That seems it would
> > solve our issues too.
> 
> Well we never ran into any of the issues you describe with PCIe BAR resize
> for GPUs so there must be something you do differently to AMD hardware
> regarding this.
> 
> Additional to that keep in mind that you can't resize the BAR before kicking
> out vgacon/efifb or otherwise it can happen that the just released 256MiB
> window is still used while you try to resize it. When you do that you usually
> end up with a hard lockup of the system.
> 
> Regards,
> Christian.
> 
> >
> > thanks
> > Lucas De Marchi
> >
> >>
> >> If I understand Sergei's series correctly, this rebalancing actually
> >> cannot be done during enumeration because we only move BARs if a
> >> driver for the device indicates that it supports it, so there would
> >> be no requirement to do this early.
> >>
> >>> Do we have any alternative to be done in the PCI subsystem during
> >>> the scan?  There is other work in progress to allow i915 to use the
> >>> rest of the device memory even with a smaller BAR, but it would be
> >>> better if we can improve our chances of succeeding the resize.
> >>
> >>> > > Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> >>> > > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> >>> > > Cc: Stuart Summers <stuart.summers@intel.com>
> >>> > > Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
> >>> > > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> >>> > > Signed-off-by: Priyanka Dandamudi
> <priyanka.dandamudi@intel.com>
> >>> > > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> >>> >
> >>> > Please see
> >>>
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flo
> >>>
> re.kernel.org%2Fr%2F87pmj8vesm.fsf%40intel.com&amp;data=05%7C01%7C
> ch
> >>>
> ristian.koenig%40amd.com%7C8096027f68484d0656b108da50a82e7d%7C3d
> d896
> >>>
> 1fe4884e608e11a82d994e183d%7C0%7C0%7C637910980509199388%7CUnk
> nown%7C
> >>>
> TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiL
> CJX
> >>>
> VCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=d4cf7HQ6t7y1Xobwjdt8im%
> 2Fh0E5IZ
> >>> sXgzQDpsB2vCU4%3D&amp;reserved=0
> >>> >
> >>> > > ---
> >>> > >  drivers/gpu/drm/i915/i915_driver.c | 92
> >>> ++++++++++++++++++++++++++++++
> >>> > >  1 file changed, 92 insertions(+)
> >>> > >
> >>> > > diff --git a/drivers/gpu/drm/i915/i915_driver.c
> >>> b/drivers/gpu/drm/i915/i915_driver.c
> >>> > > index d26dcca7e654..4bdb471cb2e2 100644
> >>> > > --- a/drivers/gpu/drm/i915/i915_driver.c
> >>> > > +++ b/drivers/gpu/drm/i915/i915_driver.c
> >>> > > @@ -303,6 +303,95 @@ static void sanitize_gpu(struct
> >>> drm_i915_private *i915)
> >>> > >          __intel_gt_reset(to_gt(i915), ALL_ENGINES);
> >>> > >  }
> >>> > >
> >>> > > +static void __release_bars(struct pci_dev *pdev) {
> >>> > > +    int resno;
> >>> > > +
> >>> > > +    for (resno = PCI_STD_RESOURCES; resno <
> >>> PCI_STD_RESOURCE_END; resno++) {
> >>> > > +        if (pci_resource_len(pdev, resno))
> >>> > > +            pci_release_resource(pdev, resno);
> >>> > > +    }
> >>> > > +}
> >>> > > +
> >>> > > +static void
> >>> > > +__resize_bar(struct drm_i915_private *i915, int resno,
> >>> resource_size_t size)
> >>> > > +{
> >>> > > +    struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> >>> > > +    int bar_size = pci_rebar_bytes_to_size(size);
> >>> > > +    int ret;
> >>> > > +
> >>> > > +    __release_bars(pdev);
> >>> > > +
> >>> > > +    ret = pci_resize_resource(pdev, resno, bar_size);
> >>> > > +    if (ret) {
> >>> > > +        drm_info(&i915->drm, "Failed to resize BAR%d to %dM
> >>> (%pe)\n",
> >>> > > +             resno, 1 << bar_size, ERR_PTR(ret));
> >>> > > +        return;
> >>> > > +    }
> >>> > > +
> >>> > > +    drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 <<
> >>> bar_size);
> >>> > > +}
> >>> > > +
> >>> > > +/* BAR size starts from 1MB - 2^20 */ #define BAR_SIZE_SHIFT 20
> >>> > > +static resource_size_t __lmem_rebar_size(struct
> >>> > > +drm_i915_private *i915, int resno) {
> >>> > > +    struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> >>> > > +    u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
> >>> > > +    resource_size_t size;
> >>> > > +
> >>> > > +    if (!rebar)
> >>> > > +        return 0;
> >>> > > +
> >>> > > +    size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
> >>> > > +
> >>> > > +    if (size <= pci_resource_len(pdev, resno))
> >>> > > +        return 0;
> >>> > > +
> >>> > > +    return size;
> >>> > > +}
> >>> > > +
> >>> > > +#define LMEM_BAR_NUM 2
> >>> > > +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
> >>> > > +{
> >>> > > +    struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> >>> > > +    struct pci_bus *root = pdev->bus;
> >>> > > +    struct resource *root_res;
> >>> > > +    resource_size_t rebar_size = __lmem_rebar_size(i915,
> >>> LMEM_BAR_NUM);
> >>> > > +    u32 pci_cmd;
> >>> > > +    int i;
> >>> > > +
> >>> > > +    if (!rebar_size)
> >>> > > +        return;
> >>> > > +
> >>> > > +    /* Find out if root bus contains 64bit memory addressing */
> >>> > > +    while (root->parent)
> >>> > > +        root = root->parent;
> >>> > > +
> >>> > > +    pci_bus_for_each_resource(root, root_res, i) {
> >>> > > +        if (root_res && root_res->flags & (IORESOURCE_MEM |
> >>> > > +                    IORESOURCE_MEM_64) && root_res->start >
> >>> 0x100000000ull)
> >>> > > +            break;
> >>> > > +    }
> >>> > > +
> >>> > > +    /* pci_resize_resource will fail anyways */
> >>> > > +    if (!root_res) {
> >>> > > +        drm_info(&i915->drm, "Can't resize LMEM BAR - platform
> >>> support is missing\n");
> >>> > > +        return;
> >>> > > +    }
> >>> > > +
> >>> > > +    /* First disable PCI memory decoding references */
> >>> > > +    pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
> >>> > > +    pci_write_config_dword(pdev, PCI_COMMAND,
> >>> > > +                   pci_cmd & ~PCI_COMMAND_MEMORY);
> >>> > > +
> >>> > > +    __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
> >>> > > +
> >>> > > + pci_assign_unassigned_bus_resources(pdev->bus);
> >>> > > +    pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd); }
> >>> > > +
> >>> > >  /**
> >>> > >   * i915_driver_early_probe - setup state not requiring device
> >>> access
> >>> > >   * @dev_priv: device private
> >>> > > @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev,
> >>> const struct pci_device_id *ent)
> >>> > >
> >>> > > disable_rpm_wakeref_asserts(&i915->runtime_pm);
> >>> > >
> >>> > > +    if (HAS_LMEM(i915))
> >>> > > +        i915_resize_lmem_bar(i915);
> >>> > > +
> >>> > >      intel_vgpu_detect(i915);
> >>> > >
> >>> > >      ret = intel_gt_probe_all(i915);
> >>> >
> >>> > --
> >>> > Jani Nikula, Intel Open Source Graphics Center

[Dandamudi, Priyanka] 
@De Marchi, Lucas
Can I proceed with the current approach or is there anything I need to add to it?

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[Thomas Hellström (Intel)]

Hi,

On 6/24/22 06:02, Dandamudi, Priyanka wrote:
>
>> -----Original Message-----
>> From: Christian König <christian.koenig@amd.com>
>> Sent: 18 June 2022 08:45 PM
>> To: De Marchi, Lucas <lucas.demarchi@intel.com>; Bjorn Helgaas
>> <helgaas@kernel.org>
>> Cc: linux-pci@vger.kernel.org; intel-gfx@lists.freedesktop.org; Sergei
>> Miroshnichenko <s.miroshnichenko@yadro.com>; linux-
>> kernel@vger.kernel.org; Dandamudi, Priyanka
>> <priyanka.dandamudi@intel.com>; Auld, Matthew
>> <matthew.auld@intel.com>; Bjorn Helgaas <bhelgaas@google.com>
>> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe
>> resizable bar
>>
>> Am 17.06.22 um 23:27 schrieb Lucas De Marchi:
>>> On Fri, Jun 17, 2022 at 03:32:52PM -0500, Bjorn Helgaas wrote:
>>>> [+cc Christian, author of pci_resize_resource(), Sergei, author of
>>>> rebalancing patches]
>>>>
>>>> Hi Lucas,
>>>>
>>>> On Fri, Jun 17, 2022 at 11:44:41AM -0700, Lucas De Marchi wrote:
>>>>> Cc'ing intel-pci, lkml, Bjorn
>>>>>
>>>>> On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
>>>>>> On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
>>>>>>> From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>>>>>>>
>>>>>>> Add support for the local memory PICe resizable bar, so that
>>>>>>> local memory can be resized to the maximum size supported by the
>>>>> device,
>>>>>>> and mapped correctly to the PCIe memory bar. It is usual that
>>>>>>> GPU devices expose only 256MB BARs primarily to be compatible
>>>>>>> with
>>>>> 32-bit
>>>>>>> systems. So, those devices cannot claim larger memory BAR
>>>>> windows size due
>>>>>>> to the system BIOS limitation. With this change, it would be
>>>>> possible to
>>>>>>> reprogram the windows of the bridge directly above the
>>>>> requesting device
>>>>>>> on the same BAR type.
>>>>> There is a big caveat here that this may be too late as other
>>>>> drivers may have already mapped their BARs - so probably too late in
>>>>> the pci scan for it to be effective. In fact, after using this for a
>>>>> while, it seems to fail too often, particularly on CFL systems.
>>>> Help me understand the "too late" part.  Do you mean that there is
>>>> enough available space for the max BAR size, but it's fragmented and
>>>> therefore not usable?  And that if we could do something earlier,
>>>> before drivers have claimed their devices, we might be able to
>>>> compact the BARs of other devices to make a larger contiguous available
>> space?
>>> yes. I will dig some logs I had in the past to confirm.
>>>
>>>
>>>> That is theoretically possible, but I think the current
>>>> pci_resize_resource() only supports resizing of the specified BAR and
>>>> any upstream bridge windows.  I don't think it supports moving BARs
>>>> of other devices.
>>>>
>>>> Sergei did some nice work that might help with this situation because
>>>> it can move BARs around more generally.  It hasn't quite achieved
>>>> critical mass yet, but maybe this would help get there:
>>>>
>>>>
>>>>
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flor
>>>> e.kernel.org%2Flinux-pci%2F20201218174011.340514-1-
>> s.miroshnichenko%4
>> 0yadro.com%2F&amp;data=05%7C01%7Cchristian.koenig%40amd.com%7C8
>> 096027
>> f68484d0656b108da50a82e7d%7C3dd8961fe4884e608e11a82d994e183d%7C
>> 0%7C0%
>> 7C637910980509199388%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjA
>> wMDAiLCJQ
>> IjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;
>> sdata=
>> %2FfntE2FTQ8wmLnz4wnzk94R0GMLEwVs7Mj18%2B9Q6PJk%3D&amp;reser
>> ved=0
>>> oh... I hadn't thought about pause/ioremap/unpause. That looks rad :).
>>> So it seems this would integrate neatly with
>>> pci_resize_resource() (what this patch is doing), as long as drivers
>>> for devices affected implement
>>> .bar_fixed()/.rescan_prepare()/.rescan_done(). That seems it would
>>> solve our issues too.
>> Well we never ran into any of the issues you describe with PCIe BAR resize
>> for GPUs so there must be something you do differently to AMD hardware
>> regarding this.
>>
>> Additional to that keep in mind that you can't resize the BAR before kicking
>> out vgacon/efifb or otherwise it can happen that the just released 256MiB
>> window is still used while you try to resize it. When you do that you usually
>> end up with a hard lockup of the system.
>>
>> Regards,
>> Christian.
>>
>>> thanks
>>> Lucas De Marchi
>>>
>>>> If I understand Sergei's series correctly, this rebalancing actually
>>>> cannot be done during enumeration because we only move BARs if a
>>>> driver for the device indicates that it supports it, so there would
>>>> be no requirement to do this early.
>>>>
>>>>> Do we have any alternative to be done in the PCI subsystem during
>>>>> the scan?  There is other work in progress to allow i915 to use the
>>>>> rest of the device memory even with a smaller BAR, but it would be
>>>>> better if we can improve our chances of succeeding the resize.
>>>>>>> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>>>>>>> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
>>>>>>> Cc: Stuart Summers <stuart.summers@intel.com>
>>>>>>> Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
>>>>>>> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
>>>>>>> Signed-off-by: Priyanka Dandamudi
>> <priyanka.dandamudi@intel.com>
>>>>>>> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>>>>>> Please see
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flo
>> re.kernel.org%2Fr%2F87pmj8vesm.fsf%40intel.com&amp;data=05%7C01%7C
>> ch
>> ristian.koenig%40amd.com%7C8096027f68484d0656b108da50a82e7d%7C3d
>> d896
>> 1fe4884e608e11a82d994e183d%7C0%7C0%7C637910980509199388%7CUnk
>> nown%7C
>> TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiL
>> CJX
>> VCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=d4cf7HQ6t7y1Xobwjdt8im%
>> 2Fh0E5IZ
>>>>> sXgzQDpsB2vCU4%3D&amp;reserved=0
>>>>>>> ---
>>>>>>>    drivers/gpu/drm/i915/i915_driver.c | 92
>>>>> ++++++++++++++++++++++++++++++
>>>>>>>    1 file changed, 92 insertions(+)
>>>>>>>
>>>>>>> diff --git a/drivers/gpu/drm/i915/i915_driver.c
>>>>> b/drivers/gpu/drm/i915/i915_driver.c
>>>>>>> index d26dcca7e654..4bdb471cb2e2 100644
>>>>>>> --- a/drivers/gpu/drm/i915/i915_driver.c
>>>>>>> +++ b/drivers/gpu/drm/i915/i915_driver.c
>>>>>>> @@ -303,6 +303,95 @@ static void sanitize_gpu(struct
>>>>> drm_i915_private *i915)
>>>>>>>            __intel_gt_reset(to_gt(i915), ALL_ENGINES);
>>>>>>>    }
>>>>>>>
>>>>>>> +static void __release_bars(struct pci_dev *pdev) {
>>>>>>> +    int resno;
>>>>>>> +
>>>>>>> +    for (resno = PCI_STD_RESOURCES; resno <
>>>>> PCI_STD_RESOURCE_END; resno++) {
>>>>>>> +        if (pci_resource_len(pdev, resno))
>>>>>>> +            pci_release_resource(pdev, resno);
>>>>>>> +    }
>>>>>>> +}
>>>>>>> +
>>>>>>> +static void
>>>>>>> +__resize_bar(struct drm_i915_private *i915, int resno,
>>>>> resource_size_t size)
>>>>>>> +{
>>>>>>> +    struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>>>>>>> +    int bar_size = pci_rebar_bytes_to_size(size);
>>>>>>> +    int ret;
>>>>>>> +
>>>>>>> +    __release_bars(pdev);
>>>>>>> +
>>>>>>> +    ret = pci_resize_resource(pdev, resno, bar_size);
>>>>>>> +    if (ret) {
>>>>>>> +        drm_info(&i915->drm, "Failed to resize BAR%d to %dM
>>>>> (%pe)\n",
>>>>>>> +             resno, 1 << bar_size, ERR_PTR(ret));
>>>>>>> +        return;
>>>>>>> +    }
>>>>>>> +
>>>>>>> +    drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 <<
>>>>> bar_size);
>>>>>>> +}
>>>>>>> +
>>>>>>> +/* BAR size starts from 1MB - 2^20 */ #define BAR_SIZE_SHIFT 20
>>>>>>> +static resource_size_t __lmem_rebar_size(struct
>>>>>>> +drm_i915_private *i915, int resno) {
>>>>>>> +    struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>>>>>>> +    u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
>>>>>>> +    resource_size_t size;
>>>>>>> +
>>>>>>> +    if (!rebar)
>>>>>>> +        return 0;
>>>>>>> +
>>>>>>> +    size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
>>>>>>> +
>>>>>>> +    if (size <= pci_resource_len(pdev, resno))
>>>>>>> +        return 0;
>>>>>>> +
>>>>>>> +    return size;
>>>>>>> +}
>>>>>>> +
>>>>>>> +#define LMEM_BAR_NUM 2
>>>>>>> +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
>>>>>>> +{
>>>>>>> +    struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>>>>>>> +    struct pci_bus *root = pdev->bus;
>>>>>>> +    struct resource *root_res;
>>>>>>> +    resource_size_t rebar_size = __lmem_rebar_size(i915,
>>>>> LMEM_BAR_NUM);
>>>>>>> +    u32 pci_cmd;
>>>>>>> +    int i;
>>>>>>> +
>>>>>>> +    if (!rebar_size)
>>>>>>> +        return;
>>>>>>> +
>>>>>>> +    /* Find out if root bus contains 64bit memory addressing */
>>>>>>> +    while (root->parent)
>>>>>>> +        root = root->parent;
>>>>>>> +
>>>>>>> +    pci_bus_for_each_resource(root, root_res, i) {
>>>>>>> +        if (root_res && root_res->flags & (IORESOURCE_MEM |
>>>>>>> +                    IORESOURCE_MEM_64) && root_res->start >
>>>>> 0x100000000ull)
>>>>>>> +            break;
>>>>>>> +    }
>>>>>>> +
>>>>>>> +    /* pci_resize_resource will fail anyways */
>>>>>>> +    if (!root_res) {
>>>>>>> +        drm_info(&i915->drm, "Can't resize LMEM BAR - platform
>>>>> support is missing\n");
>>>>>>> +        return;
>>>>>>> +    }
>>>>>>> +
>>>>>>> +    /* First disable PCI memory decoding references */
>>>>>>> +    pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
>>>>>>> +    pci_write_config_dword(pdev, PCI_COMMAND,
>>>>>>> +                   pci_cmd & ~PCI_COMMAND_MEMORY);
>>>>>>> +
>>>>>>> +    __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
>>>>>>> +
>>>>>>> + pci_assign_unassigned_bus_resources(pdev->bus);
>>>>>>> +    pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd); }
>>>>>>> +
>>>>>>>    /**
>>>>>>>     * i915_driver_early_probe - setup state not requiring device
>>>>> access
>>>>>>>     * @dev_priv: device private
>>>>>>> @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev,
>>>>> const struct pci_device_id *ent)
>>>>>>> disable_rpm_wakeref_asserts(&i915->runtime_pm);
>>>>>>>
>>>>>>> +    if (HAS_LMEM(i915))
>>>>>>> +        i915_resize_lmem_bar(i915);
>>>>>>> +
>>>>>>>        intel_vgpu_detect(i915);
>>>>>>>
>>>>>>>        ret = intel_gt_probe_all(i915);
>>>>>> --
>>>>>> Jani Nikula, Intel Open Source Graphics Center
> [Dandamudi, Priyanka]
> @De Marchi, Lucas
> Can I proceed with the current approach or is there anything I need to add to it?

IMO we should be good to go. From my understanding, the problem that 
Lucas brings up doesn't yet have a solution other than WIP, so if we end 
up not being able to resize, we'd fall back to using the small BAR with 
Matthew's work.

That said, If we keep hitting errors when resizing, we should, as 
Christian says, compare with AMD (since they are not seeing this) and 
see what, if anything, can be done differently.

Thanks,

Thomas

[Intel-gfx] [PATCH 2/2] drm/i915: Add lmem_bar_size modparam

[priyanka.dandamudi]

From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>

For testing purposes, support forcing the lmem_bar_size through a new
modparam. In CI we only have a limited number of configurations for DG2,
but we still need to be reasonably sure we get a usable device (also
verifying we report the correct values for things like
probed_cpu_visible_size etc) with all the potential lmem_bar sizes that
we might expect see in the wild.

v2: Update commit message and a minor modification.(Matt)

Cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_region_lmem.c |  4 +++
 drivers/gpu/drm/i915/i915_driver.c          | 28 ++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_params.c          |  2 ++
 drivers/gpu/drm/i915/i915_params.h          |  1 +
 4 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index e9c12e0d6f59..4614c30f878f 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -111,6 +111,10 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
 		flat_ccs_base = intel_gt_read_register(gt, XEHPSDV_FLAT_CCS_BASE_ADDR);
 		flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * SZ_64K;
 
+		/* XXX: Remove this once we have small-bar uapi bits */
+		if (i915->params.lmem_bar_size > 0)
+			lmem_size = pci_resource_len(pdev, 2);
+
 		/* FIXME: Remove this when we have small-bar enabled */
 		if (pci_resource_len(pdev, 2) < lmem_size) {
 			drm_err(&i915->drm, "System requires small-BAR support, which is currently unsupported on this kernel\n");
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 4bdb471cb2e2..b2763b032012 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -362,8 +362,34 @@ static void i915_resize_lmem_bar(struct drm_i915_private *i915)
 	u32 pci_cmd;
 	int i;
 
-	if (!rebar_size)
+	if (i915->params.lmem_bar_size > 0) {
+		u32 lmem_bar_size;
+		u32 set_bit;
+		u32 rebar;
+		u32 msb;
+		int k;
+
+		lmem_bar_size = i915->params.lmem_bar_size;
+		rebar = pci_rebar_get_possible_sizes(pdev, LMEM_BAR_NUM);
+		msb = __fls(rebar);
+
+		for (k = msb; k >= 0; k--) {
+			set_bit = (1 << k);
+
+			if (set_bit & rebar) {
+				if (set_bit == lmem_bar_size) {
+					rebar_size = 1ULL << (__fls(lmem_bar_size) +
+							BAR_SIZE_SHIFT);
+
+					if (rebar_size == pci_resource_len(pdev, LMEM_BAR_NUM))
+						return;
+					break;
+				}
+			}
+		}
+	} else if (!rebar_size) {
 		return;
+	}
 
 	/* Find out if root bus contains 64bit memory addressing */
 	while (root->parent)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 701fbc98afa0..6fc475a5db61 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -204,6 +204,8 @@ i915_param_named_unsafe(request_timeout_ms, uint, 0600,
 
 i915_param_named_unsafe(lmem_size, uint, 0400,
 			"Set the lmem size(in MiB) for each region. (default: 0, all memory)");
+i915_param_named_unsafe(lmem_bar_size, uint, 0400,
+			"Set the lmem bar size(in MiB).");
 
 static __always_inline void _print_param(struct drm_printer *p,
 					 const char *name,
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index b5e7ea45d191..2733cb6cfe09 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -74,6 +74,7 @@ struct drm_printer;
 	param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
 	param(unsigned int, request_timeout_ms, CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
 	param(unsigned int, lmem_size, 0, 0400) \
+	param(unsigned int, lmem_bar_size, 0, 0400) \
 	/* leave bools at the end to not create holes */ \
 	param(bool, enable_hangcheck, true, 0600) \
 	param(bool, load_detect_test, false, 0600) \
-- 
2.25.1

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add lmem_bar_size modparam

[Das, Nirmoy]

On 6/16/2022 5:12 PM, priyanka.dandamudi@intel.com wrote:
> From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
>
> For testing purposes, support forcing the lmem_bar_size through a new
> modparam. In CI we only have a limited number of configurations for DG2,
> but we still need to be reasonably sure we get a usable device (also
> verifying we report the correct values for things like
> probed_cpu_visible_size etc) with all the potential lmem_bar sizes that
> we might expect see in the wild.
>
> v2: Update commit message and a minor modification.(Matt)
>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_region_lmem.c |  4 +++
>   drivers/gpu/drm/i915/i915_driver.c          | 28 ++++++++++++++++++++-
>   drivers/gpu/drm/i915/i915_params.c          |  2 ++
>   drivers/gpu/drm/i915/i915_params.h          |  1 +
>   4 files changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index e9c12e0d6f59..4614c30f878f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -111,6 +111,10 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
>   		flat_ccs_base = intel_gt_read_register(gt, XEHPSDV_FLAT_CCS_BASE_ADDR);
>   		flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * SZ_64K;
>   
> +		/* XXX: Remove this once we have small-bar uapi bits */
> +		if (i915->params.lmem_bar_size > 0)
> +			lmem_size = pci_resource_len(pdev, 2);
> +
>   		/* FIXME: Remove this when we have small-bar enabled */
>   		if (pci_resource_len(pdev, 2) < lmem_size) {
>   			drm_err(&i915->drm, "System requires small-BAR support, which is currently unsupported on this kernel\n");
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 4bdb471cb2e2..b2763b032012 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -362,8 +362,34 @@ static void i915_resize_lmem_bar(struct drm_i915_private *i915)
>   	u32 pci_cmd;
>   	int i;
>   
> -	if (!rebar_size)
> +	if (i915->params.lmem_bar_size > 0) {
> +		u32 lmem_bar_size;
> +		u32 set_bit;
> +		u32 rebar;
> +		u32 msb;
> +		int k;
> +
> +		lmem_bar_size = i915->params.lmem_bar_size;
> +		rebar = pci_rebar_get_possible_sizes(pdev, LMEM_BAR_NUM);
> +		msb = __fls(rebar);
> +
> +		for (k = msb; k >= 0; k--) {
> +			set_bit = (1 << k);
> +
> +			if (set_bit & rebar) {
> +				if (set_bit == lmem_bar_size) {
> +					rebar_size = 1ULL << (__fls(lmem_bar_size) +
> +							BAR_SIZE_SHIFT);


We have pci_rebar_bytes_to_size() helper function for this please use that.


Nirmoy

> +
> +					if (rebar_size == pci_resource_len(pdev, LMEM_BAR_NUM))
> +						return;
> +					break;
> +				}
> +			}
> +		}
> +	} else if (!rebar_size) {
>   		return;
> +	}
>   
>   	/* Find out if root bus contains 64bit memory addressing */
>   	while (root->parent)
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 701fbc98afa0..6fc475a5db61 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -204,6 +204,8 @@ i915_param_named_unsafe(request_timeout_ms, uint, 0600,
>   
>   i915_param_named_unsafe(lmem_size, uint, 0400,
>   			"Set the lmem size(in MiB) for each region. (default: 0, all memory)");
> +i915_param_named_unsafe(lmem_bar_size, uint, 0400,
> +			"Set the lmem bar size(in MiB).");
>   
>   static __always_inline void _print_param(struct drm_printer *p,
>   					 const char *name,
> diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
> index b5e7ea45d191..2733cb6cfe09 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -74,6 +74,7 @@ struct drm_printer;
>   	param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
>   	param(unsigned int, request_timeout_ms, CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
>   	param(unsigned int, lmem_size, 0, 0400) \
> +	param(unsigned int, lmem_bar_size, 0, 0400) \
>   	/* leave bools at the end to not create holes */ \
>   	param(bool, enable_hangcheck, true, 0600) \
>   	param(bool, load_detect_test, false, 0600) \

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add lmem_bar_size modparam

[Das, Nirmoy]

On 6/17/2022 9:54 AM, Das, Nirmoy wrote:
>
> On 6/16/2022 5:12 PM, priyanka.dandamudi@intel.com wrote:
>> From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
>>
>> For testing purposes, support forcing the lmem_bar_size through a new
>> modparam. In CI we only have a limited number of configurations for DG2,
>> but we still need to be reasonably sure we get a usable device (also
>> verifying we report the correct values for things like
>> probed_cpu_visible_size etc) with all the potential lmem_bar sizes that
>> we might expect see in the wild.
>>
>> v2: Update commit message and a minor modification.(Matt)
>>
>> Cc: Matthew Auld <matthew.auld@intel.com>
>> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_region_lmem.c |  4 +++
>>   drivers/gpu/drm/i915/i915_driver.c          | 28 ++++++++++++++++++++-
>>   drivers/gpu/drm/i915/i915_params.c          |  2 ++
>>   drivers/gpu/drm/i915/i915_params.h          |  1 +
>>   4 files changed, 34 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c 
>> b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
>> index e9c12e0d6f59..4614c30f878f 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
>> @@ -111,6 +111,10 @@ static struct intel_memory_region 
>> *setup_lmem(struct intel_gt *gt)
>>           flat_ccs_base = intel_gt_read_register(gt, 
>> XEHPSDV_FLAT_CCS_BASE_ADDR);
>>           flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * 
>> SZ_64K;
>>   +        /* XXX: Remove this once we have small-bar uapi bits */
>> +        if (i915->params.lmem_bar_size > 0)
>> +            lmem_size = pci_resource_len(pdev, 2);
>> +
>>           /* FIXME: Remove this when we have small-bar enabled */
>>           if (pci_resource_len(pdev, 2) < lmem_size) {
>>               drm_err(&i915->drm, "System requires small-BAR support, 
>> which is currently unsupported on this kernel\n");
>> diff --git a/drivers/gpu/drm/i915/i915_driver.c 
>> b/drivers/gpu/drm/i915/i915_driver.c
>> index 4bdb471cb2e2..b2763b032012 100644
>> --- a/drivers/gpu/drm/i915/i915_driver.c
>> +++ b/drivers/gpu/drm/i915/i915_driver.c
>> @@ -362,8 +362,34 @@ static void i915_resize_lmem_bar(struct 
>> drm_i915_private *i915)
>>       u32 pci_cmd;
>>       int i;
>>   -    if (!rebar_size)
>> +    if (i915->params.lmem_bar_size > 0) {
>> +        u32 lmem_bar_size;
>> +        u32 set_bit;
>> +        u32 rebar;
>> +        u32 msb;
>> +        int k;
>> +
>> +        lmem_bar_size = i915->params.lmem_bar_size;
>> +        rebar = pci_rebar_get_possible_sizes(pdev, LMEM_BAR_NUM);
>> +        msb = __fls(rebar);
>> +
>> +        for (k = msb; k >= 0; k--) {
>> +            set_bit = (1 << k);
>> +
>> +            if (set_bit & rebar) {
>> +                if (set_bit == lmem_bar_size) {
>> +                    rebar_size = 1ULL << (__fls(lmem_bar_size) +
>> +                            BAR_SIZE_SHIFT);
>
>
> We have pci_rebar_bytes_to_size() helper function for this please use 
> that.


What I mean is: these calculations are confusing(at-least for me).


You could do:

if (i915->params.lmem_bar_size)

     rebar_size = i915->params.lmem_bar_size (in bytes)

else

     rebar_size = device lmem_size; --> we need this to make sure we 
only rebar till roundup_pow_of_two(), not max of 
pci_rebar_get_possible_sizes().


Now validate that  pci_rebar_bytes_to_size(rebar_size) is within 
pci_rebar_get_possible_sizes() range.


Regards,

Nirmoy


>
> Nirmoy
>
>> +
>> +                    if (rebar_size == pci_resource_len(pdev, 
>> LMEM_BAR_NUM))
>> +                        return;
>> +                    break;
>> +                }
>> +            }
>> +        }
>> +    } else if (!rebar_size) {
>>           return;
>> +    }
>>         /* Find out if root bus contains 64bit memory addressing */
>>       while (root->parent)
>> diff --git a/drivers/gpu/drm/i915/i915_params.c 
>> b/drivers/gpu/drm/i915/i915_params.c
>> index 701fbc98afa0..6fc475a5db61 100644
>> --- a/drivers/gpu/drm/i915/i915_params.c
>> +++ b/drivers/gpu/drm/i915/i915_params.c
>> @@ -204,6 +204,8 @@ i915_param_named_unsafe(request_timeout_ms, uint, 
>> 0600,
>>     i915_param_named_unsafe(lmem_size, uint, 0400,
>>               "Set the lmem size(in MiB) for each region. (default: 
>> 0, all memory)");
>> +i915_param_named_unsafe(lmem_bar_size, uint, 0400,
>> +            "Set the lmem bar size(in MiB).");
>>     static __always_inline void _print_param(struct drm_printer *p,
>>                        const char *name,
>> diff --git a/drivers/gpu/drm/i915/i915_params.h 
>> b/drivers/gpu/drm/i915/i915_params.h
>> index b5e7ea45d191..2733cb6cfe09 100644
>> --- a/drivers/gpu/drm/i915/i915_params.h
>> +++ b/drivers/gpu/drm/i915/i915_params.h
>> @@ -74,6 +74,7 @@ struct drm_printer;
>>       param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
>>       param(unsigned int, request_timeout_ms, 
>> CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 
>> 0600 : 0) \
>>       param(unsigned int, lmem_size, 0, 0400) \
>> +    param(unsigned int, lmem_bar_size, 0, 0400) \
>>       /* leave bools at the end to not create holes */ \
>>       param(bool, enable_hangcheck, true, 0600) \
>>       param(bool, load_detect_test, false, 0600) \

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add support for LMEM PCIe resizable bar

[Patchwork]

== Series Details ==

Series: Add support for LMEM PCIe resizable bar
URL   : https://patchwork.freedesktop.org/series/105231/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Add support for LMEM PCIe resizable bar

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5653 bytes --]

== Series Details ==

Series: Add support for LMEM PCIe resizable bar
URL   : https://patchwork.freedesktop.org/series/105231/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11769 -> Patchwork_105231v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/index.html

Participating hosts (34 -> 34)
------------------------------

  Additional (1): fi-bdw-gvtdvm 
  Missing    (1): fi-bdw-samus 

Known issues
------------

  Here are the changes found in Patchwork_105231v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-g3258:       [PASS][1] -> [INCOMPLETE][2] ([i915#3303] / [i915#4785])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@requests:
    - fi-blb-e6850:       [PASS][3] -> [DMESG-FAIL][4] ([i915#4528])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/fi-blb-e6850/igt@i915_selftest@live@requests.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-blb-e6850/igt@i915_selftest@live@requests.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - fi-bdw-gvtdvm:      NOTRUN -> [INCOMPLETE][5] ([i915#4817])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-bdw-gvtdvm/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-hsw-4770:        NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-hsw-4770/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-bdw-gvtdvm:      NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +7 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-bdw-gvtdvm/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_flip@basic-plain-flip:
    - fi-bdw-gvtdvm:      NOTRUN -> [SKIP][8] ([fdo#109271]) +47 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-bdw-gvtdvm/igt@kms_flip@basic-plain-flip.html

  * igt@kms_flip@basic-plain-flip@a-edp1:
    - fi-tgl-u2:          [PASS][9] -> [DMESG-WARN][10] ([i915#402])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html

  * igt@runner@aborted:
    - fi-blb-e6850:       NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#2403] / [i915#4312])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-blb-e6850/igt@runner@aborted.html
    - fi-hsw-g3258:       NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#4312])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-hsw-g3258/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0@smem:
    - {fi-ehl-2}:         [DMESG-WARN][13] ([i915#5122]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-4770:        [INCOMPLETE][15] ([i915#4785]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html

  * igt@kms_busy@basic@flip:
    - fi-tgl-u2:          [DMESG-WARN][17] ([i915#402]) -> [PASS][18] +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/fi-tgl-u2/igt@kms_busy@basic@flip.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/fi-tgl-u2/igt@kms_busy@basic@flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122


Build changes
-------------

  * Linux: CI_DRM_11769 -> Patchwork_105231v1

  CI-20190529: 20190529
  CI_DRM_11769: 01048fa55e6f8ef81536a461c0d08e66f1d33bfd @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6533: 6b5107d91827962808441db6b98e478aa9e67bdb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_105231v1: 01048fa55e6f8ef81536a461c0d08e66f1d33bfd @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

27527a467445 drm/i915: Add lmem_bar_size modparam
d0652c3b539a drm/i915: Add support for LMEM PCIe resizable bar

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/index.html

[-- Attachment #2: Type: text/html, Size: 7093 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for Add support for LMEM PCIe resizable bar

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 38301 bytes --]

== Series Details ==

Series: Add support for LMEM PCIe resizable bar
URL   : https://patchwork.freedesktop.org/series/105231/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11769_full -> Patchwork_105231v1_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_105231v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-iclb:         NOTRUN -> [SKIP][1] ([i915#5327])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb1/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_create@create-massive:
    - shard-skl:          NOTRUN -> [DMESG-WARN][2] ([i915#4991])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl4/igt@gem_create@create-massive.html

  * igt@gem_ctx_persistence@hang:
    - shard-skl:          NOTRUN -> [SKIP][3] ([fdo#109271]) +314 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl7/igt@gem_ctx_persistence@hang.html

  * igt@gem_ctx_persistence@many-contexts:
    - shard-tglb:         [PASS][4] -> [FAIL][5] ([i915#2410])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-tglb7/igt@gem_ctx_persistence@many-contexts.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb1/igt@gem_ctx_persistence@many-contexts.html

  * igt@gem_eio@in-flight-suspend:
    - shard-kbl:          [PASS][6] -> [DMESG-WARN][7] ([i915#180])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-kbl1/igt@gem_eio@in-flight-suspend.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-kbl4/igt@gem_eio@in-flight-suspend.html

  * igt@gem_eio@kms:
    - shard-tglb:         [PASS][8] -> [FAIL][9] ([i915#5784])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-tglb6/igt@gem_eio@kms.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb2/igt@gem_eio@kms.html

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-kbl:          NOTRUN -> [FAIL][10] ([i915#6117])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-kbl7/igt@gem_exec_balancer@parallel-ordering.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-apl:          [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-apl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][15] ([i915#2842]) +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb2/igt@gem_exec_fair@basic-none@vcs1.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-tglb:         [PASS][16] -> [FAIL][17] ([i915#2842])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-tglb8/igt@gem_exec_fair@basic-pace@vcs0.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb6/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_exec_whisper@basic-queues-priority-all:
    - shard-iclb:         [PASS][18] -> [INCOMPLETE][19] ([i915#5498])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-iclb4/igt@gem_exec_whisper@basic-queues-priority-all.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb1/igt@gem_exec_whisper@basic-queues-priority-all.html

  * igt@gem_huc_copy@huc-copy:
    - shard-skl:          NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#2190])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl7/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs:
    - shard-glk:          NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-glk6/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html

  * igt@gem_lmem_swapping@parallel-random:
    - shard-kbl:          NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4613])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-kbl7/igt@gem_lmem_swapping@parallel-random.html

  * igt@gem_lmem_swapping@verify-ccs:
    - shard-skl:          NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#4613]) +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl4/igt@gem_lmem_swapping@verify-ccs.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-apl:          NOTRUN -> [WARN][24] ([i915#2658])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl7/igt@gem_pwrite@basic-exhaustion.html
    - shard-skl:          NOTRUN -> [WARN][25] ([i915#2658])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl6/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
    - shard-glk:          NOTRUN -> [SKIP][26] ([fdo#109271]) +33 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-glk6/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-apl:          NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3323])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl6/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gen3_render_tiledx_blits:
    - shard-iclb:         NOTRUN -> [SKIP][28] ([fdo#109289]) +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb1/igt@gen3_render_tiledx_blits.html

  * igt@gen7_exec_parse@bitmasks:
    - shard-tglb:         NOTRUN -> [SKIP][29] ([fdo#109289])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb7/igt@gen7_exec_parse@bitmasks.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-skl:          [PASS][30] -> [DMESG-WARN][31] ([i915#5566] / [i915#716])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-skl7/igt@gen9_exec_parse@allowed-single.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl1/igt@gen9_exec_parse@allowed-single.html
    - shard-apl:          [PASS][32] -> [DMESG-WARN][33] ([i915#5566] / [i915#716])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-apl1/igt@gen9_exec_parse@allowed-single.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl7/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-iclb:         NOTRUN -> [SKIP][34] ([i915#2856])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb1/igt@gen9_exec_parse@bb-start-far.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-skl:          NOTRUN -> [FAIL][35] ([i915#454])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl7/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-iclb:         [PASS][36] -> [SKIP][37] ([i915#4281])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-iclb8/igt@i915_pm_dc@dc9-dpms.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-tglb:         NOTRUN -> [SKIP][38] ([i915#1769])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][39] ([i915#5286])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb7/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][40] ([fdo#111614])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb7/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][41] ([i915#3743]) +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
    - shard-iclb:         NOTRUN -> [SKIP][42] ([fdo#110723])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb1/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-skl:          NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#1888])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl4/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-kbl:          NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#3886]) +2 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-kbl7/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-glk:          NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3886])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-glk6/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#3886]) +1 similar issue
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl6/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
    - shard-skl:          NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#1888] / [i915#3886])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl9/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#3886]) +9 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl4/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][49] ([fdo#109271]) +73 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl6/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][50] ([i915#3689])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb7/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs.html

  * igt@kms_chamelium@hdmi-mode-timings:
    - shard-kbl:          NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-kbl7/igt@kms_chamelium@hdmi-mode-timings.html

  * igt@kms_color_chamelium@pipe-b-ctm-green-to-red:
    - shard-skl:          NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +14 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl7/igt@kms_color_chamelium@pipe-b-ctm-green-to-red.html

  * igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
    - shard-apl:          NOTRUN -> [SKIP][53] ([fdo#109271] / [fdo#111827]) +6 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl7/igt@kms_color_chamelium@pipe-b-ctm-red-to-blue.html

  * igt@kms_color_chamelium@pipe-b-degamma:
    - shard-iclb:         NOTRUN -> [SKIP][54] ([fdo#109284] / [fdo#111827]) +1 similar issue
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb1/igt@kms_color_chamelium@pipe-b-degamma.html

  * igt@kms_color_chamelium@pipe-d-ctm-blue-to-red:
    - shard-glk:          NOTRUN -> [SKIP][55] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-glk6/igt@kms_color_chamelium@pipe-d-ctm-blue-to-red.html

  * igt@kms_cursor_crc@pipe-b-cursor-max-size-offscreen:
    - shard-tglb:         NOTRUN -> [SKIP][56] ([i915#3359]) +1 similar issue
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb7/igt@kms_cursor_crc@pipe-b-cursor-max-size-offscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-apl:          NOTRUN -> [DMESG-WARN][57] ([i915#180])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-c-cursor-512x512-rapid-movement:
    - shard-iclb:         NOTRUN -> [SKIP][58] ([fdo#109278] / [fdo#109279]) +2 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb1/igt@kms_cursor_crc@pipe-c-cursor-512x512-rapid-movement.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [PASS][59] -> [DMESG-WARN][60] ([i915#180])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-d-cursor-max-size-sliding:
    - shard-iclb:         NOTRUN -> [SKIP][61] ([fdo#109278]) +8 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb1/igt@kms_cursor_crc@pipe-d-cursor-max-size-sliding.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-tglb:         NOTRUN -> [SKIP][62] ([i915#4103])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          [PASS][63] -> [FAIL][64] ([i915#2346])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
    - shard-skl:          NOTRUN -> [FAIL][65] ([i915#2346])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
    - shard-iclb:         [PASS][66] -> [FAIL][67] ([i915#2346])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-iclb5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@pipe-d-torture-bo:
    - shard-apl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#533])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl6/igt@kms_cursor_legacy@pipe-d-torture-bo.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-tglb:         NOTRUN -> [SKIP][69] ([fdo#109274] / [fdo#111825]) +2 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb7/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-skl:          NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#3701])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
    - shard-kbl:          NOTRUN -> [SKIP][71] ([fdo#109271]) +33 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-kbl7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-blt:
    - shard-tglb:         NOTRUN -> [SKIP][72] ([fdo#109280] / [fdo#111825]) +3 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt:
    - shard-iclb:         NOTRUN -> [SKIP][73] ([fdo#109280]) +5 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_hdr@bpc-switch@pipe-a-dp-1:
    - shard-kbl:          [PASS][74] -> [FAIL][75] ([i915#1188])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-kbl6/igt@kms_hdr@bpc-switch@pipe-a-dp-1.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-kbl1/igt@kms_hdr@bpc-switch@pipe-a-dp-1.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - shard-skl:          NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#533]) +2 similar issues
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
    - shard-kbl:          NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#533])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-kbl7/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-glk:          NOTRUN -> [FAIL][78] ([fdo#108145] / [i915#265]) +1 similar issue
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-glk6/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
    - shard-skl:          NOTRUN -> [FAIL][79] ([i915#265])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          NOTRUN -> [FAIL][80] ([fdo#108145] / [i915#265])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_plane_scaling@invalid-num-scalers@pipe-a-edp-1-invalid-num-scalers:
    - shard-skl:          NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#5776]) +2 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl4/igt@kms_plane_scaling@invalid-num-scalers@pipe-a-edp-1-invalid-num-scalers.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-edp-1:
    - shard-iclb:         NOTRUN -> [SKIP][82] ([i915#5235]) +2 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb1/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-edp-1.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
    - shard-apl:          NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#658])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl6/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-skl:          NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#658]) +5 similar issues
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl4/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-iclb:         [PASS][85] -> [SKIP][86] ([i915#5519])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-iclb2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_sysfs_edid_timing:
    - shard-skl:          NOTRUN -> [FAIL][87] ([IGT#2])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl4/igt@kms_sysfs_edid_timing.html

  * igt@kms_writeback@writeback-check-output:
    - shard-skl:          NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#2437])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl7/igt@kms_writeback@writeback-check-output.html

  * igt@nouveau_crc@pipe-c-source-outp-complete:
    - shard-iclb:         NOTRUN -> [SKIP][89] ([i915#2530])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb1/igt@nouveau_crc@pipe-c-source-outp-complete.html

  * igt@perf@polling-small-buf:
    - shard-skl:          NOTRUN -> [FAIL][90] ([i915#1722])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl6/igt@perf@polling-small-buf.html

  * igt@prime_nv_api@i915_self_import:
    - shard-iclb:         NOTRUN -> [SKIP][91] ([fdo#109291])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb1/igt@prime_nv_api@i915_self_import.html

  * igt@prime_nv_pcopy@test3_5:
    - shard-tglb:         NOTRUN -> [SKIP][92] ([fdo#109291])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb7/igt@prime_nv_pcopy@test3_5.html

  * igt@prime_vgem@basic-userptr:
    - shard-tglb:         NOTRUN -> [SKIP][93] ([fdo#109295] / [i915#3301])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb7/igt@prime_vgem@basic-userptr.html

  * igt@sw_sync@sync_multi_timeline_wait:
    - shard-kbl:          NOTRUN -> [FAIL][94] ([i915#6140])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-kbl7/igt@sw_sync@sync_multi_timeline_wait.html
    - shard-apl:          NOTRUN -> [FAIL][95] ([i915#6140])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl6/igt@sw_sync@sync_multi_timeline_wait.html

  * igt@sysfs_clients@sema-10:
    - shard-glk:          NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#2994])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-glk6/igt@sysfs_clients@sema-10.html

  * igt@sysfs_clients@sema-50:
    - shard-skl:          NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#2994]) +1 similar issue
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl7/igt@sysfs_clients@sema-50.html

  
#### Possible fixes ####

  * igt@gem_eio@in-flight-contexts-immediate:
    - shard-tglb:         [TIMEOUT][98] ([i915#3063]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-tglb6/igt@gem_eio@in-flight-contexts-immediate.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb2/igt@gem_eio@in-flight-contexts-immediate.html

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         [FAIL][100] ([i915#5784]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-tglb8/igt@gem_eio@unwedge-stress.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb7/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-bb-first:
    - shard-iclb:         [SKIP][102] ([i915#4525]) -> [PASS][103] +1 similar issue
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-iclb6/igt@gem_exec_balancer@parallel-bb-first.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [FAIL][104] ([i915#2842]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-kbl:          [FAIL][106] ([i915#2842]) -> [PASS][107] +1 similar issue
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-kbl3/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_exec_whisper@basic-fds-all:
    - shard-glk:          [INCOMPLETE][108] ([i915#5843]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-glk4/igt@gem_exec_whisper@basic-fds-all.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-glk6/igt@gem_exec_whisper@basic-fds-all.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          [DMESG-WARN][110] ([i915#5566] / [i915#716]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-glk6/igt@gen9_exec_parse@allowed-all.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-glk3/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_module_load@reload:
    - shard-iclb:         [DMESG-WARN][112] ([i915#4391]) -> [PASS][113] +1 similar issue
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-iclb7/igt@i915_module_load@reload.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb1/igt@i915_module_load@reload.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-skl:          [INCOMPLETE][114] ([i915#5713]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_cursor_legacy@cursor-vs-flip-legacy:
    - shard-iclb:         [DMESG-WARN][116] ([i915#1888]) -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-iclb6/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb8/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html

  * {igt@kms_dither@fb-8bpc-vs-panel-8bpc@pipe-a-hdmi-a-1}:
    - shard-glk:          [SKIP][118] ([fdo#109271]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-glk8/igt@kms_dither@fb-8bpc-vs-panel-8bpc@pipe-a-hdmi-a-1.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-glk7/igt@kms_dither@fb-8bpc-vs-panel-8bpc@pipe-a-hdmi-a-1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-kbl:          [INCOMPLETE][120] ([i915#3614]) -> [PASS][121]
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-kbl3/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
    - shard-skl:          [FAIL][122] ([i915#2122]) -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-skl9/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-apl:          [DMESG-WARN][124] ([i915#180]) -> [PASS][125] +2 similar issues
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-apl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [SKIP][126] ([fdo#109441]) -> [PASS][127]
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-iclb6/igt@kms_psr@psr2_no_drrs.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb2/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-skl:          [DMESG-WARN][128] ([i915#1982]) -> [PASS][129]
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-skl1/igt@kms_rotation_crc@bad-pixel-format.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl1/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
    - shard-snb:          [DMESG-WARN][130] ([i915#5090]) -> [PASS][131]
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-snb6/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-snb7/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html

  * igt@kms_vblank@pipe-c-ts-continuation-modeset-rpm:
    - shard-apl:          [SKIP][132] ([fdo#109271]) -> [PASS][133]
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-apl4/igt@kms_vblank@pipe-c-ts-continuation-modeset-rpm.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl6/igt@kms_vblank@pipe-c-ts-continuation-modeset-rpm.html

  * igt@perf@polling-parameterized:
    - shard-skl:          [FAIL][134] ([i915#5639]) -> [PASS][135]
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-skl10/igt@perf@polling-parameterized.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl1/igt@perf@polling-parameterized.html

  * igt@perf_pmu@rc6-suspend:
    - shard-kbl:          [DMESG-WARN][136] ([i915#180]) -> [PASS][137]
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-kbl4/igt@perf_pmu@rc6-suspend.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-kbl7/igt@perf_pmu@rc6-suspend.html

  
#### Warnings ####

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-iclb:         [FAIL][138] ([i915#6117]) -> [SKIP][139] ([i915#4525])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb5/igt@gem_exec_balancer@parallel-ordering.html

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc:
    - shard-skl:          [SKIP][140] ([fdo#109271]) -> [SKIP][141] ([fdo#109271] / [i915#1888])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-skl1/igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-skl1/igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
    - shard-iclb:         [SKIP][142] ([i915#658]) -> [SKIP][143] ([i915#2920])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-iclb6/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html

  * igt@runner@aborted:
    - shard-apl:          ([FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153]) ([fdo#109271] / [i915#3002] / [i915#4312] / [i915#5257])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-apl4/igt@runner@aborted.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-apl7/igt@runner@aborted.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-apl7/igt@runner@aborted.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-apl1/igt@runner@aborted.html
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11769/shard-apl3/igt@runner@aborted.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl6/igt@runner@aborted.html
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl6/igt@runner@aborted.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl7/igt@runner@aborted.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl8/igt@runner@aborted.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/shard-apl8/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3614]: https://gitlab.freedesktop.org/drm/intel/issues/3614
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
  [i915#5090]: https://gitlab.freedesktop.org/drm/intel/issues/5090
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5498]: https://gitlab.freedesktop.org/drm/intel/issues/5498
  [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
  [i915#5713]: https://gitlab.freedesktop.org/drm/intel/issues/5713
  [i915#5776]: https://gitlab.freedesktop.org/drm/intel/issues/5776
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#5843]: https://gitlab.freedesktop.org/drm/intel/issues/5843
  [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
  [i915#6140]: https://gitlab.freedesktop.org/drm/intel/issues/6140
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716


Build changes
-------------

  * Linux: CI_DRM_11769 -> Patchwork_105231v1

  CI-20190529: 20190529
  CI_DRM_11769: 01048fa55e6f8ef81536a461c0d08e66f1d33bfd @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6533: 6b5107d91827962808441db6b98e478aa9e67bdb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_105231v1: 01048fa55e6f8ef81536a461c0d08e66f1d33bfd @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105231v1/index.html

[-- Attachment #2: Type: text/html, Size: 47658 bytes --]

[Intel-gfx] [PATCH 0/2] Add support for LMEM PCIe resizable bar

[priyanka.dandamudi]

From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>

Added support to resize the bar to maximum supported,
only when bar is not set to maximum by default.
Also, added new modparam lmem_bar_size which can resize the bar
provided if it is among the supported sizes.

Akeem G Abodunrin (1):
  drm/i915: Add support for LMEM PCIe resizable bar

Priyanka Dandamudi (1):
  drm/i915: Add lmem_bar_size modparam

 drivers/gpu/drm/i915/gt/intel_region_lmem.c |   3 +
 drivers/gpu/drm/i915/i915_driver.c          | 126 ++++++++++++++++++++
 drivers/gpu/drm/i915/i915_params.c          |   2 +
 drivers/gpu/drm/i915/i915_params.h          |   1 +
 4 files changed, 132 insertions(+)

-- 
2.27.0

[Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[priyanka.dandamudi]

From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>

This patch adds support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible with 32-bit
systems. So, those devices cannot claim larger memory BAR windows size due
to the system BIOS limitation. With this change, it would be possible to
reprogram the windows of the bridge directly above the requesting device
on the same BAR type.

Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
---
 drivers/gpu/drm/i915/i915_driver.c | 103 +++++++++++++++++++++++++++++
 1 file changed, 103 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index b47746152d97..8d33a6a31675 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -303,6 +303,106 @@ static void sanitize_gpu(struct drm_i915_private *i915)
 		__intel_gt_reset(to_gt(i915), ALL_ENGINES);
 }
 
+static void __release_bars(struct pci_dev *pdev)
+{
+	int resno;
+
+	for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
+		if (pci_resource_len(pdev, resno))
+			pci_release_resource(pdev, resno);
+	}
+}
+
+static void
+__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
+{
+	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+	int bar_size = pci_rebar_bytes_to_size(size);
+	int ret;
+
+	__release_bars(pdev);
+
+	ret = pci_resize_resource(pdev, resno, bar_size);
+	if (ret) {
+		drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
+			 resno, 1 << bar_size, ERR_PTR(ret));
+		return;
+	}
+
+	drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
+}
+
+/* BAR size starts from 1MB - 2^20 */
+#define BAR_SIZE_SHIFT 20
+static resource_size_t
+__lmem_rebar_size(struct drm_i915_private *i915, int resno)
+{
+	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+	u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
+	resource_size_t size;
+
+	if (!rebar)
+		return 0;
+
+	size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
+
+	if (size <= pci_resource_len(pdev, resno))
+		return 0;
+
+	return size;
+}
+
+/**
+ * i915_resize_lmem_bar - resize local memory BAR
+ * @i915: device private
+ *
+ * This function will attempt to resize LMEM bar to make all memory accessible.
+ * Whether it will be successful depends on both device and platform
+ * capabilities. Any errors are non-critical, even if resize fails, we go back
+ * to the previous configuration.
+ */
+#define LMEM_BAR_NUM 2
+static void i915_resize_lmem_bar(struct drm_i915_private *i915)
+{
+	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+	struct pci_bus *root = pdev->bus;
+	struct resource *root_res;
+	resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
+	u32 pci_cmd;
+	int i;
+
+	if (!rebar_size)
+		return;
+
+	/* Find out if root bus contains 64bit memory addressing */
+	while (root->parent)
+		root = root->parent;
+
+	pci_bus_for_each_resource(root, root_res, i) {
+		if (root_res &&
+				root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
+				root_res->start > 0x100000000ull)
+			break;
+	}
+
+	/* pci_resize_resource will fail anyways */
+	if (!root_res) {
+		drm_info(&i915->drm,
+				"Can't resize LMEM BAR - platform support is missing\n");
+		return;
+	}
+
+	/* First disable PCI memory decoding references */
+	pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
+	pci_write_config_dword(pdev, PCI_COMMAND,
+			       pci_cmd & ~PCI_COMMAND_MEMORY);
+
+	__resize_bar(i915, LMEM_BAR_NUM, rebar_size);
+
+	pci_assign_unassigned_bus_resources(pdev->bus);
+	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
+}
+
 /**
  * i915_driver_early_probe - setup state not requiring device access
  * @dev_priv: device private
@@ -836,6 +936,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 
 	disable_rpm_wakeref_asserts(&i915->runtime_pm);
 
+	if (HAS_LMEM(i915))
+		i915_resize_lmem_bar(i915);
+
 	intel_vgpu_detect(i915);
 
 	ret = intel_gt_probe_all(i915);
-- 
2.27.0

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar

[Matthew Auld]

On 15/06/2022 06:43, priyanka.dandamudi@intel.com wrote:
> From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> 
> This patch adds support for the local memory PICe resizable bar, so that
> local memory can be resized to the maximum size supported by the device,
> and mapped correctly to the PCIe memory bar. It is usual that GPU
> devices expose only 256MB BARs primarily to be compatible with 32-bit
> systems. So, those devices cannot claim larger memory BAR windows size due
> to the system BIOS limitation. With this change, it would be possible to
> reprogram the windows of the bridge directly above the requesting device
> on the same BAR type.
> 
> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Stuart Summers <stuart.summers@intel.com>
> Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_driver.c | 103 +++++++++++++++++++++++++++++
>   1 file changed, 103 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index b47746152d97..8d33a6a31675 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -303,6 +303,106 @@ static void sanitize_gpu(struct drm_i915_private *i915)
>   		__intel_gt_reset(to_gt(i915), ALL_ENGINES);
>   }
>   
> +static void __release_bars(struct pci_dev *pdev)
> +{
> +	int resno;
> +
> +	for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
> +		if (pci_resource_len(pdev, resno))
> +			pci_release_resource(pdev, resno);
> +	}
> +}
> +
> +static void
> +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
> +{
> +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> +	int bar_size = pci_rebar_bytes_to_size(size);
> +	int ret;
> +
> +	__release_bars(pdev);
> +
> +	ret = pci_resize_resource(pdev, resno, bar_size);
> +	if (ret) {
> +		drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
> +			 resno, 1 << bar_size, ERR_PTR(ret));
> +		return;
> +	}
> +
> +	drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
> +}
> +
> +/* BAR size starts from 1MB - 2^20 */
> +#define BAR_SIZE_SHIFT 20
> +static resource_size_t
> +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
> +{
> +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> +	u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
> +	resource_size_t size;
> +
> +	if (!rebar)
> +		return 0;
> +
> +	size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
> +
> +	if (size <= pci_resource_len(pdev, resno))
> +		return 0;
> +
> +	return size;
> +}
> +
> +/**
> + * i915_resize_lmem_bar - resize local memory BAR
> + * @i915: device private

We don't normally add kernel-doc for static functions.

There are also some checkpatch warnings that need to be fixed, but 
otherwise this looks reasonable to me, and the flow seems to closely 
match what amdgpu is already doing with their bar resizing stuff,
Reviewed-by: Matthew Auld <matthew.auld@intel.com>

> + *
> + * This function will attempt to resize LMEM bar to make all memory accessible.
> + * Whether it will be successful depends on both device and platform
> + * capabilities. Any errors are non-critical, even if resize fails, we go back
> + * to the previous configuration.
> + */
> +#define LMEM_BAR_NUM 2
> +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
> +{
> +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> +	struct pci_bus *root = pdev->bus;
> +	struct resource *root_res;
> +	resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
> +	u32 pci_cmd;
> +	int i;
> +
> +	if (!rebar_size)
> +		return;
> +
> +	/* Find out if root bus contains 64bit memory addressing */
> +	while (root->parent)
> +		root = root->parent;
> +
> +	pci_bus_for_each_resource(root, root_res, i) {
> +		if (root_res &&
> +				root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
> +				root_res->start > 0x100000000ull)
> +			break;
> +	}
> +
> +	/* pci_resize_resource will fail anyways */
> +	if (!root_res) {
> +		drm_info(&i915->drm,
> +				"Can't resize LMEM BAR - platform support is missing\n");
> +		return;
> +	}
> +
> +	/* First disable PCI memory decoding references */
> +	pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
> +	pci_write_config_dword(pdev, PCI_COMMAND,
> +			       pci_cmd & ~PCI_COMMAND_MEMORY);
> +
> +	__resize_bar(i915, LMEM_BAR_NUM, rebar_size);
> +
> +	pci_assign_unassigned_bus_resources(pdev->bus);
> +	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
> +}
> +
>   /**
>    * i915_driver_early_probe - setup state not requiring device access
>    * @dev_priv: device private
> @@ -836,6 +936,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>   
>   	disable_rpm_wakeref_asserts(&i915->runtime_pm);
>   
> +	if (HAS_LMEM(i915))
> +		i915_resize_lmem_bar(i915);
> +
>   	intel_vgpu_detect(i915);
>   
>   	ret = intel_gt_probe_all(i915);