* Re: [PATCH 02/15] drm/i915/dsb: DSB context creation. [not found] ` <16108ca4-8bc5-cd7f-4cdc-bd22406a00fa@intel.com> @ 2019-08-20 14:42 ` Jani Nikula 0 siblings, 0 replies; 2+ messages in thread From: Jani Nikula @ 2019-08-20 14:42 UTC (permalink / raw) To: Animesh Manna, intel-gfx; +Cc: Michel Thierry On Wed, 14 Aug 2019, Animesh Manna <animesh.manna@intel.com> wrote: > Yes, have missed and local build also could not catch as maybe object > files were present in that directory. > Fixed the issue and latest trybot link - > https://patchwork.freedesktop.org/series/65161/ I don't have the patches. I'm not subscribed to the trybot list, really most people shouldn't be, and trybot is not for review anyway. Patches won't be applied from trybot list either, intel-gfx only. You can use trybot if you need to debug an issue or test something out, but it shouldn't be part of your usual upstream workflow. If you want to get anything reviewed or merged upstream, that's not it. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 2+ messages in thread
* [PATCH 00/15] DSB enablement. @ 2019-07-01 6:26 Animesh Manna 2019-07-01 6:26 ` [PATCH 02/15] drm/i915/dsb: DSB context creation Animesh Manna 0 siblings, 1 reply; 2+ messages in thread From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi, Michel Thierry Display State Buffer (DSB) is hardware capability which allows driver to batch submit HW programming. As part of initial enablement common api created which currently used to program gamma lut proramming. Going forwad DSB support can be added for HDR and flip related operation. Few changes of this patch series is not tested, sending version 1 for design review, will be testing in parallel. HSDES: 1209978241 BSpec: 32020 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Imre Deak <imre.deak@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Shashank Sharma <shashank.sharma@intel.com> Cc: Swati Sharma <swati2.sharma@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Animesh Manna (15): drm/i915/dsb: feature flag added for display state buffer. drm/i915/dsb: DSB context creation. drm/i915/dsb: single register write function for DSB. drm/i915/dsb: Added enum for reg write capability. drm/i915/dsb: Indexed register write function for DSB. drm/i915/dsb: Update i915_write to call dsb-write. drm/i915/dsb: Register definition of DSB registers. drm/i915/dsb: Check DSB engine status. drm/i915/dsb: functions to enable/disable DSB engine. drm/i915/dsb: function to trigger workload execution of DSB. drm/i915/dsb: function to destroy DSB context. drm/i915/dsb: Early prepare of dsb context. drm/i915/dsb: Cleanup of DSB context. drm/i915/dsb: Documentation for DSB. drm/i915/dsb: Enable gamma lut programming using DSB. Documentation/gpu/i915.rst | 9 + drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_color.c | 4 + drivers/gpu/drm/i915/display/intel_display.c | 34 +++ drivers/gpu/drm/i915/i915_drv.h | 9 +- drivers/gpu/drm/i915/i915_reg.h | 53 +++- drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 6 + drivers/gpu/drm/i915/intel_dsb.c | 305 +++++++++++++++++++ drivers/gpu/drm/i915/intel_dsb.h | 48 +++ 10 files changed, 460 insertions(+), 10 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_dsb.c create mode 100644 drivers/gpu/drm/i915/intel_dsb.h -- 2.21.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 2+ messages in thread
* [PATCH 02/15] drm/i915/dsb: DSB context creation. 2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna @ 2019-07-01 6:26 ` Animesh Manna 0 siblings, 0 replies; 2+ messages in thread From: Animesh Manna @ 2019-07-01 6:26 UTC (permalink / raw) To: intel-gfx; +Cc: Michel Thierry, Jani Nikula The function will internally get the gem buffer from global GTT which is mapped in cpu domain to feed the data + opcode for DSB engine. Cc: Imre Deak <imre.deak@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 4 ++ drivers/gpu/drm/i915/intel_dsb.c | 65 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_dsb.h | 31 +++++++++++++++ 5 files changed, 102 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_dsb.c create mode 100644 drivers/gpu/drm/i915/intel_dsb.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 3bd8f0349a8a..3416ba15b949 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -49,6 +49,7 @@ i915-y += i915_drv.o \ i915_sysfs.o \ intel_csr.o \ intel_device_info.o \ + intel_dsb.o \ intel_pm.o \ intel_runtime_pm.o \ intel_sideband.o \ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ca6d3e2fe7a6..237c17427780 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -76,6 +76,7 @@ #include "gt/intel_workarounds.h" #include "intel_device_info.h" +#include "intel_dsb.h" #include "intel_runtime_pm.h" #include "intel_uc.h" #include "intel_uncore.h" diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 1d58f7ec5d84..a05a047d78af 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -988,6 +988,10 @@ struct intel_crtc { /* scalers available on this crtc */ int num_scalers; + + /* per pipe DSB related info */ + struct intel_dsb dsb[MAX_DSB_PER_PIPE]; + int dsb_in_use; }; struct intel_plane { diff --git a/drivers/gpu/drm/i915/intel_dsb.c b/drivers/gpu/drm/i915/intel_dsb.c new file mode 100644 index 000000000000..de6a8a901d88 --- /dev/null +++ b/drivers/gpu/drm/i915/intel_dsb.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2019 Intel Corporation + * + */ + +#include "i915_drv.h" + +#define DSB_BUF_SIZE (2 * PAGE_SIZE) + +struct intel_dsb * +intel_dsb_get(struct intel_crtc *crtc) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *i915 = to_i915(dev); + struct drm_i915_gem_object *obj; + struct i915_vma *vma; + struct intel_dsb *dsb; + intel_wakeref_t wakeref; + int i; + + WARN_ON(crtc->dsb_in_use >= MAX_DSB_PER_PIPE); + + for (i = 0; i < MAX_DSB_PER_PIPE; i++) { + if (!crtc->dsb[i].cmd_buf) { + dsb = &crtc->dsb[i]; + dsb->id = i; + } + } + + dsb = &crtc->dsb[crtc->dsb_in_use]; + dsb->crtc = crtc; + if (!HAS_DSB(i915)) + return dsb; + + wakeref = intel_runtime_pm_get(&i915->runtime_pm); + mutex_lock(&i915->drm.struct_mutex); + + obj = i915_gem_object_create_shmem(i915, DSB_BUF_SIZE); + if (IS_ERR(obj)) + goto err; + + vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); + if (IS_ERR(vma)) { + DRM_DEBUG_KMS("Vma creation failed.\n"); + i915_gem_object_put(obj); + goto err; + } + + dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC); + if (IS_ERR(dsb->cmd_buf)) { + DRM_DEBUG_KMS("Command buffer creation failed.\n"); + dsb->cmd_buf = NULL; + goto err; + } + crtc->dsb_in_use++; + dsb->cmd_buf_head = (uintptr_t)i915_ggtt_offset(vma); + dsb->vma = vma; + + memset(dsb->cmd_buf, 0, DSB_BUF_SIZE); +err: + mutex_unlock(&i915->drm.struct_mutex); + intel_runtime_pm_put(&i915->runtime_pm, wakeref); + return dsb; +} diff --git a/drivers/gpu/drm/i915/intel_dsb.h b/drivers/gpu/drm/i915/intel_dsb.h new file mode 100644 index 000000000000..50a2a6590a71 --- /dev/null +++ b/drivers/gpu/drm/i915/intel_dsb.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright © 2019 Intel Corporation + */ + +#ifndef _INTEL_DSB_H +#define _INTEL_DSB_H + +struct intel_crtc; +struct i915_vma; + +enum dsb_id { + INVALID_DSB = -1, + DSB1, + DSB2, + DSB3, + MAX_DSB_PER_PIPE +}; + +struct intel_dsb { + struct intel_crtc *crtc; + enum dsb_id id; + u32 *cmd_buf; + u32 cmd_buf_head; + struct i915_vma *vma; +}; + +struct intel_dsb * +intel_dsb_get(struct intel_crtc *crtc); + +#endif -- 2.21.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 2+ messages in thread
end of thread, other threads:[~2019-08-20 14:42 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
[not found] <20190813195917.30679-1-animesh.manna@intel.com>
[not found] ` <20190813195917.30679-2-animesh.manna@intel.com>
[not found] ` <87d0h7erk9.fsf@intel.com>
[not found] ` <16108ca4-8bc5-cd7f-4cdc-bd22406a00fa@intel.com>
2019-08-20 14:42 ` [PATCH 02/15] drm/i915/dsb: DSB context creation Jani Nikula
2019-07-01 6:26 [PATCH 00/15] DSB enablement Animesh Manna
2019-07-01 6:26 ` [PATCH 02/15] drm/i915/dsb: DSB context creation Animesh Manna
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).