* [Intel-gfx] [PATCH] drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display
@ 2021-12-10 12:27 Ville Syrjala
2021-12-10 13:12 ` Jani Nikula
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Ville Syrjala @ 2021-12-10 12:27 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Collect the dipslay related mask under the display sub-structure
in intel_device_info.
Note that there is a slight change in behaviour in that we zero
out .display entirely when !HAS_DISPLAY (aka. pipe_mask==0), so
now we also zero out the other masks (although cpu_transocder_mask
should already be zero of pipe_mask is zero). abox_mask is
only used by the display core init when HAS_DISPLAY is true, so
the actual behaviour of the system shouldn't change despite the
zeroing of these masks.
There is a lot more display stuff directly in device info that
could be moved over. Maybe someone else will be inspired to do it...
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.h | 4 +-
.../drm/i915/display/intel_display_power.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/i915_pci.c | 76 +++++++++----------
drivers/gpu/drm/i915/intel_device_info.c | 24 +++---
drivers/gpu/drm/i915/intel_device_info.h | 9 +--
6 files changed, 61 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 4b688a9727b3..43fd2f0a3e5e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -372,7 +372,7 @@ enum hpd_pin {
#define for_each_pipe(__dev_priv, __p) \
for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
- for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p))
+ for_each_if(INTEL_INFO(__dev_priv)->display.pipe_mask & BIT(__p))
#define for_each_pipe_masked(__dev_priv, __p, __mask) \
for_each_pipe(__dev_priv, __p) \
@@ -380,7 +380,7 @@ enum hpd_pin {
#define for_each_cpu_transcoder(__dev_priv, __t) \
for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
- for_each_if (INTEL_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
+ for_each_if (INTEL_INFO(__dev_priv)->display.cpu_transcoder_mask & BIT(__t))
#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
for_each_cpu_transcoder(__dev_priv, __t) \
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 229b4c127c6c..05babdcf5f2e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5370,7 +5370,7 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
static void icl_mbus_init(struct drm_i915_private *dev_priv)
{
- unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask;
+ unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask;
u32 mask, val, i;
if (IS_ALDERLAKE_P(dev_priv))
@@ -5830,7 +5830,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
enum intel_dram_type type = dev_priv->dram_info.type;
u8 num_channels = dev_priv->dram_info.num_channels;
const struct buddy_page_mask *table;
- unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
+ unsigned long abox_mask = INTEL_INFO(dev_priv)->display.abox_mask;
int config, i;
/* BW_BUDDY registers are not used on dgpu's beyond DG1 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a0f54a69b11d..47a9b1cb8eab 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1509,7 +1509,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_PSR_HW_TRACKING(dev_priv) \
(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
#define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
-#define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
+#define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
@@ -1562,9 +1562,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define GT_FREQUENCY_MULTIPLIER 50
#define GEN9_FREQ_SCALER 3
-#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
+#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->display.pipe_mask))
-#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
+#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.pipe_mask != 0)
#define HAS_VRR(i915) (GRAPHICS_VER(i915) >= 11)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 708a23415e9c..27cba75eb255 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -162,8 +162,8 @@
#define I830_FEATURES \
GEN(2), \
.is_mobile = 1, \
- .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
+ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.display.has_overlay = 1, \
.display.cursor_needs_physical = 1, \
.display.overlay_needs_physical = 1, \
@@ -183,8 +183,8 @@
#define I845_FEATURES \
GEN(2), \
- .pipe_mask = BIT(PIPE_A), \
- .cpu_transcoder_mask = BIT(TRANSCODER_A), \
+ .display.pipe_mask = BIT(PIPE_A), \
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A), \
.display.has_overlay = 1, \
.display.overlay_needs_physical = 1, \
.display.has_gmch = 1, \
@@ -225,8 +225,8 @@ static const struct intel_device_info i865g_info = {
#define GEN3_FEATURES \
GEN(3), \
- .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
+ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.display.has_gmch = 1, \
.gpu_reset_clobbers_display = true, \
.platform_engine_mask = BIT(RCS0), \
@@ -315,8 +315,8 @@ static const struct intel_device_info pnv_m_info = {
#define GEN4_FEATURES \
GEN(4), \
- .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
+ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.display.has_hotplug = 1, \
.display.has_gmch = 1, \
.gpu_reset_clobbers_display = true, \
@@ -368,8 +368,8 @@ static const struct intel_device_info gm45_info = {
#define GEN5_FEATURES \
GEN(5), \
- .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
+ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.display.has_hotplug = 1, \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
.has_snoop = true, \
@@ -398,8 +398,8 @@ static const struct intel_device_info ilk_m_info = {
#define GEN6_FEATURES \
GEN(6), \
- .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
+ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.display.has_hotplug = 1, \
.display.has_fbc = 1, \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
@@ -449,8 +449,8 @@ static const struct intel_device_info snb_m_gt2_info = {
#define GEN7_FEATURES \
GEN(7), \
- .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
+ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
.display.has_hotplug = 1, \
.display.has_fbc = 1, \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
@@ -504,8 +504,8 @@ static const struct intel_device_info ivb_q_info = {
GEN7_FEATURES,
PLATFORM(INTEL_IVYBRIDGE),
.gt = 2,
- .pipe_mask = 0, /* legal, last one wins */
- .cpu_transcoder_mask = 0,
+ .display.pipe_mask = 0, /* legal, last one wins */
+ .display.cpu_transcoder_mask = 0,
.has_l3_dpf = 1,
};
@@ -513,8 +513,8 @@ static const struct intel_device_info vlv_info = {
PLATFORM(INTEL_VALLEYVIEW),
GEN(7),
.is_lp = 1,
- .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
+ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
.has_runtime_pm = 1,
.has_rc6 = 1,
.has_reset_engine = true,
@@ -538,7 +538,7 @@ static const struct intel_device_info vlv_info = {
#define G75_FEATURES \
GEN7_FEATURES, \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
.display.has_ddi = 1, \
.display.has_fpga_dbg = 1, \
@@ -608,8 +608,8 @@ static const struct intel_device_info bdw_gt3_info = {
static const struct intel_device_info chv_info = {
PLATFORM(INTEL_CHERRYVIEW),
GEN(8),
- .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
+ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
.display.has_hotplug = 1,
.is_lp = 1,
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
@@ -686,8 +686,8 @@ static const struct intel_device_info skl_gt4_info = {
.dbuf.slice_mask = BIT(DBUF_S1), \
.display.has_hotplug = 1, \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
- .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
.has_64bit_reloc = 1, \
@@ -795,8 +795,8 @@ static const struct intel_device_info cml_gt2_info = {
#define GEN11_FEATURES \
GEN9_FEATURES, \
GEN11_DEFAULT_PAGE_SIZES, \
- .abox_mask = BIT(0), \
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ .display.abox_mask = BIT(0), \
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
.pipe_offsets = { \
@@ -847,9 +847,9 @@ static const struct intel_device_info jsl_info = {
#define GEN12_FEATURES \
GEN11_FEATURES, \
GEN(12), \
- .abox_mask = GENMASK(2, 1), \
- .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ .display.abox_mask = GENMASK(2, 1), \
+ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
.pipe_offsets = { \
@@ -884,9 +884,9 @@ static const struct intel_device_info tgl_info = {
static const struct intel_device_info rkl_info = {
GEN12_FEATURES,
PLATFORM(INTEL_ROCKETLAKE),
- .abox_mask = BIT(0),
- .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ .display.abox_mask = BIT(0),
+ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C),
.display.has_hti = 1,
.display.has_psr_hw_tracking = 0,
@@ -906,7 +906,7 @@ static const struct intel_device_info dg1_info = {
DGFX_FEATURES,
.graphics.rel = 10,
PLATFORM(INTEL_DG1),
- .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
.require_force_probe = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
@@ -918,7 +918,7 @@ static const struct intel_device_info dg1_info = {
static const struct intel_device_info adl_s_info = {
GEN12_FEATURES,
PLATFORM(INTEL_ALDERLAKE_S),
- .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
.display.has_hti = 1,
.display.has_psr_hw_tracking = 0,
.platform_engine_mask =
@@ -935,7 +935,7 @@ static const struct intel_device_info adl_s_info = {
}
#define XE_LPD_FEATURES \
- .abox_mask = GENMASK(1, 0), \
+ .display.abox_mask = GENMASK(1, 0), \
.color = { .degamma_lut_size = 128, .gamma_lut_size = 1024, \
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
DRM_COLOR_LUT_EQUAL_CHANNELS, \
@@ -955,7 +955,7 @@ static const struct intel_device_info adl_s_info = {
.display.has_ipc = 1, \
.display.has_psr = 1, \
.display.ver = 13, \
- .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
.pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
@@ -978,7 +978,7 @@ static const struct intel_device_info adl_p_info = {
GEN12_FEATURES,
XE_LPD_FEATURES,
PLATFORM(INTEL_ALDERLAKE_P),
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
.display.has_cdclk_crawl = 1,
@@ -1028,7 +1028,7 @@ static const struct intel_device_info xehpsdv_info = {
PLATFORM(INTEL_XEHPSDV),
.display = { },
.has_64k_pages = 1,
- .pipe_mask = 0,
+ .display.pipe_mask = 0,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
@@ -1052,7 +1052,7 @@ static const struct intel_device_info dg2_info = {
BIT(VECS0) | BIT(VECS1) |
BIT(VCS0) | BIT(VCS2),
.require_force_probe = 1,
- .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
};
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index a3446a2abcb2..04fd266d70e2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -326,33 +326,33 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
drm_info(&dev_priv->drm,
"Display fused off, disabling\n");
- info->pipe_mask = 0;
- info->cpu_transcoder_mask = 0;
+ info->display.pipe_mask = 0;
+ info->display.cpu_transcoder_mask = 0;
} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
drm_info(&dev_priv->drm, "PipeC fused off\n");
- info->pipe_mask &= ~BIT(PIPE_C);
- info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
+ info->display.pipe_mask &= ~BIT(PIPE_C);
+ info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
}
} else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
- info->pipe_mask &= ~BIT(PIPE_A);
- info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
+ info->display.pipe_mask &= ~BIT(PIPE_A);
+ info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
}
if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
- info->pipe_mask &= ~BIT(PIPE_B);
- info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
+ info->display.pipe_mask &= ~BIT(PIPE_B);
+ info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
}
if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
- info->pipe_mask &= ~BIT(PIPE_C);
- info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
+ info->display.pipe_mask &= ~BIT(PIPE_C);
+ info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
}
if (DISPLAY_VER(dev_priv) >= 12 &&
(dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
- info->pipe_mask &= ~BIT(PIPE_D);
- info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
+ info->display.pipe_mask &= ~BIT(PIPE_D);
+ info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
}
if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 213ae2c07126..78597d382445 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -196,11 +196,6 @@ struct intel_device_info {
u8 gt; /* GT number, 0 if undefined */
- u8 pipe_mask;
- u8 cpu_transcoder_mask;
-
- u8 abox_mask;
-
#define DEFINE_FLAG(name) u8 name:1
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
@@ -209,6 +204,10 @@ struct intel_device_info {
u8 ver;
u8 rel;
+ u8 pipe_mask;
+ u8 cpu_transcoder_mask;
+ u8 abox_mask;
+
#define DEFINE_FLAG(name) u8 name:1
DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
--
2.32.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display
2021-12-10 12:27 [Intel-gfx] [PATCH] drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display Ville Syrjala
@ 2021-12-10 13:12 ` Jani Nikula
2021-12-10 15:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2021-12-10 13:12 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 10 Dec 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Collect the dipslay related mask under the display sub-structure
> in intel_device_info.
>
> Note that there is a slight change in behaviour in that we zero
> out .display entirely when !HAS_DISPLAY (aka. pipe_mask==0), so
> now we also zero out the other masks (although cpu_transocder_mask
> should already be zero of pipe_mask is zero). abox_mask is
> only used by the display core init when HAS_DISPLAY is true, so
> the actual behaviour of the system shouldn't change despite the
> zeroing of these masks.
>
> There is a lot more display stuff directly in device info that
> could be moved over. Maybe someone else will be inspired to do it...
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.h | 4 +-
> .../drm/i915/display/intel_display_power.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.h | 6 +-
> drivers/gpu/drm/i915/i915_pci.c | 76 +++++++++----------
> drivers/gpu/drm/i915/intel_device_info.c | 24 +++---
> drivers/gpu/drm/i915/intel_device_info.h | 9 +--
> 6 files changed, 61 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 4b688a9727b3..43fd2f0a3e5e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -372,7 +372,7 @@ enum hpd_pin {
>
> #define for_each_pipe(__dev_priv, __p) \
> for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
> - for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p))
> + for_each_if(INTEL_INFO(__dev_priv)->display.pipe_mask & BIT(__p))
>
> #define for_each_pipe_masked(__dev_priv, __p, __mask) \
> for_each_pipe(__dev_priv, __p) \
> @@ -380,7 +380,7 @@ enum hpd_pin {
>
> #define for_each_cpu_transcoder(__dev_priv, __t) \
> for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
> - for_each_if (INTEL_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
> + for_each_if (INTEL_INFO(__dev_priv)->display.cpu_transcoder_mask & BIT(__t))
>
> #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
> for_each_cpu_transcoder(__dev_priv, __t) \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 229b4c127c6c..05babdcf5f2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5370,7 +5370,7 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
>
> static void icl_mbus_init(struct drm_i915_private *dev_priv)
> {
> - unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask;
> + unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask;
> u32 mask, val, i;
>
> if (IS_ALDERLAKE_P(dev_priv))
> @@ -5830,7 +5830,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> enum intel_dram_type type = dev_priv->dram_info.type;
> u8 num_channels = dev_priv->dram_info.num_channels;
> const struct buddy_page_mask *table;
> - unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
> + unsigned long abox_mask = INTEL_INFO(dev_priv)->display.abox_mask;
> int config, i;
>
> /* BW_BUDDY registers are not used on dgpu's beyond DG1 */
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a0f54a69b11d..47a9b1cb8eab 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1509,7 +1509,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_PSR_HW_TRACKING(dev_priv) \
> (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
> #define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
> -#define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
> +#define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
>
> #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
> #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
> @@ -1562,9 +1562,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define GT_FREQUENCY_MULTIPLIER 50
> #define GEN9_FREQ_SCALER 3
>
> -#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
> +#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->display.pipe_mask))
>
> -#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
> +#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.pipe_mask != 0)
>
> #define HAS_VRR(i915) (GRAPHICS_VER(i915) >= 11)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 708a23415e9c..27cba75eb255 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -162,8 +162,8 @@
> #define I830_FEATURES \
> GEN(2), \
> .is_mobile = 1, \
> - .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> + .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> + .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> .display.has_overlay = 1, \
> .display.cursor_needs_physical = 1, \
> .display.overlay_needs_physical = 1, \
> @@ -183,8 +183,8 @@
>
> #define I845_FEATURES \
> GEN(2), \
> - .pipe_mask = BIT(PIPE_A), \
> - .cpu_transcoder_mask = BIT(TRANSCODER_A), \
> + .display.pipe_mask = BIT(PIPE_A), \
> + .display.cpu_transcoder_mask = BIT(TRANSCODER_A), \
> .display.has_overlay = 1, \
> .display.overlay_needs_physical = 1, \
> .display.has_gmch = 1, \
> @@ -225,8 +225,8 @@ static const struct intel_device_info i865g_info = {
>
> #define GEN3_FEATURES \
> GEN(3), \
> - .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> + .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> + .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> .platform_engine_mask = BIT(RCS0), \
> @@ -315,8 +315,8 @@ static const struct intel_device_info pnv_m_info = {
>
> #define GEN4_FEATURES \
> GEN(4), \
> - .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> + .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> + .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> .display.has_hotplug = 1, \
> .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> @@ -368,8 +368,8 @@ static const struct intel_device_info gm45_info = {
>
> #define GEN5_FEATURES \
> GEN(5), \
> - .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> + .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> + .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> .display.has_hotplug = 1, \
> .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
> .has_snoop = true, \
> @@ -398,8 +398,8 @@ static const struct intel_device_info ilk_m_info = {
>
> #define GEN6_FEATURES \
> GEN(6), \
> - .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> + .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> + .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> .display.has_hotplug = 1, \
> .display.has_fbc = 1, \
> .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> @@ -449,8 +449,8 @@ static const struct intel_device_info snb_m_gt2_info = {
>
> #define GEN7_FEATURES \
> GEN(7), \
> - .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
> + .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> + .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
> .display.has_hotplug = 1, \
> .display.has_fbc = 1, \
> .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> @@ -504,8 +504,8 @@ static const struct intel_device_info ivb_q_info = {
> GEN7_FEATURES,
> PLATFORM(INTEL_IVYBRIDGE),
> .gt = 2,
> - .pipe_mask = 0, /* legal, last one wins */
> - .cpu_transcoder_mask = 0,
> + .display.pipe_mask = 0, /* legal, last one wins */
> + .display.cpu_transcoder_mask = 0,
> .has_l3_dpf = 1,
> };
>
> @@ -513,8 +513,8 @@ static const struct intel_device_info vlv_info = {
> PLATFORM(INTEL_VALLEYVIEW),
> GEN(7),
> .is_lp = 1,
> - .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> + .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> + .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> .has_runtime_pm = 1,
> .has_rc6 = 1,
> .has_reset_engine = true,
> @@ -538,7 +538,7 @@ static const struct intel_device_info vlv_info = {
> #define G75_FEATURES \
> GEN7_FEATURES, \
> .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> + .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
> .display.has_ddi = 1, \
> .display.has_fpga_dbg = 1, \
> @@ -608,8 +608,8 @@ static const struct intel_device_info bdw_gt3_info = {
> static const struct intel_device_info chv_info = {
> PLATFORM(INTEL_CHERRYVIEW),
> GEN(8),
> - .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
> + .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
> .display.has_hotplug = 1,
> .is_lp = 1,
> .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
> @@ -686,8 +686,8 @@ static const struct intel_device_info skl_gt4_info = {
> .dbuf.slice_mask = BIT(DBUF_S1), \
> .display.has_hotplug = 1, \
> .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
> - .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> + .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> + .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
> BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
> .has_64bit_reloc = 1, \
> @@ -795,8 +795,8 @@ static const struct intel_device_info cml_gt2_info = {
> #define GEN11_FEATURES \
> GEN9_FEATURES, \
> GEN11_DEFAULT_PAGE_SIZES, \
> - .abox_mask = BIT(0), \
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> + .display.abox_mask = BIT(0), \
> + .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
> BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> .pipe_offsets = { \
> @@ -847,9 +847,9 @@ static const struct intel_device_info jsl_info = {
> #define GEN12_FEATURES \
> GEN11_FEATURES, \
> GEN(12), \
> - .abox_mask = GENMASK(2, 1), \
> - .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> + .display.abox_mask = GENMASK(2, 1), \
> + .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> + .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
> BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> .pipe_offsets = { \
> @@ -884,9 +884,9 @@ static const struct intel_device_info tgl_info = {
> static const struct intel_device_info rkl_info = {
> GEN12_FEATURES,
> PLATFORM(INTEL_ROCKETLAKE),
> - .abox_mask = BIT(0),
> - .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + .display.abox_mask = BIT(0),
> + .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> BIT(TRANSCODER_C),
> .display.has_hti = 1,
> .display.has_psr_hw_tracking = 0,
> @@ -906,7 +906,7 @@ static const struct intel_device_info dg1_info = {
> DGFX_FEATURES,
> .graphics.rel = 10,
> PLATFORM(INTEL_DG1),
> - .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> + .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> .require_force_probe = 1,
> .platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
> @@ -918,7 +918,7 @@ static const struct intel_device_info dg1_info = {
> static const struct intel_device_info adl_s_info = {
> GEN12_FEATURES,
> PLATFORM(INTEL_ALDERLAKE_S),
> - .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> + .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> .display.has_hti = 1,
> .display.has_psr_hw_tracking = 0,
> .platform_engine_mask =
> @@ -935,7 +935,7 @@ static const struct intel_device_info adl_s_info = {
> }
>
> #define XE_LPD_FEATURES \
> - .abox_mask = GENMASK(1, 0), \
> + .display.abox_mask = GENMASK(1, 0), \
> .color = { .degamma_lut_size = 128, .gamma_lut_size = 1024, \
> .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
> DRM_COLOR_LUT_EQUAL_CHANNELS, \
> @@ -955,7 +955,7 @@ static const struct intel_device_info adl_s_info = {
> .display.has_ipc = 1, \
> .display.has_psr = 1, \
> .display.ver = 13, \
> - .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> + .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> .pipe_offsets = { \
> [TRANSCODER_A] = PIPE_A_OFFSET, \
> [TRANSCODER_B] = PIPE_B_OFFSET, \
> @@ -978,7 +978,7 @@ static const struct intel_device_info adl_p_info = {
> GEN12_FEATURES,
> XE_LPD_FEATURES,
> PLATFORM(INTEL_ALDERLAKE_P),
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
> BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
> .display.has_cdclk_crawl = 1,
> @@ -1028,7 +1028,7 @@ static const struct intel_device_info xehpsdv_info = {
> PLATFORM(INTEL_XEHPSDV),
> .display = { },
> .has_64k_pages = 1,
> - .pipe_mask = 0,
> + .display.pipe_mask = 0,
> .platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) |
> BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
> @@ -1052,7 +1052,7 @@ static const struct intel_device_info dg2_info = {
> BIT(VECS0) | BIT(VECS1) |
> BIT(VCS0) | BIT(VCS2),
> .require_force_probe = 1,
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index a3446a2abcb2..04fd266d70e2 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -326,33 +326,33 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
> drm_info(&dev_priv->drm,
> "Display fused off, disabling\n");
> - info->pipe_mask = 0;
> - info->cpu_transcoder_mask = 0;
> + info->display.pipe_mask = 0;
> + info->display.cpu_transcoder_mask = 0;
> } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
> drm_info(&dev_priv->drm, "PipeC fused off\n");
> - info->pipe_mask &= ~BIT(PIPE_C);
> - info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
> + info->display.pipe_mask &= ~BIT(PIPE_C);
> + info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
> }
> } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
> u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
>
> if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
> - info->pipe_mask &= ~BIT(PIPE_A);
> - info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
> + info->display.pipe_mask &= ~BIT(PIPE_A);
> + info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
> }
> if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
> - info->pipe_mask &= ~BIT(PIPE_B);
> - info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
> + info->display.pipe_mask &= ~BIT(PIPE_B);
> + info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
> }
> if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
> - info->pipe_mask &= ~BIT(PIPE_C);
> - info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
> + info->display.pipe_mask &= ~BIT(PIPE_C);
> + info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
> }
>
> if (DISPLAY_VER(dev_priv) >= 12 &&
> (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
> - info->pipe_mask &= ~BIT(PIPE_D);
> - info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
> + info->display.pipe_mask &= ~BIT(PIPE_D);
> + info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
> }
>
> if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 213ae2c07126..78597d382445 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -196,11 +196,6 @@ struct intel_device_info {
>
> u8 gt; /* GT number, 0 if undefined */
>
> - u8 pipe_mask;
> - u8 cpu_transcoder_mask;
> -
> - u8 abox_mask;
> -
> #define DEFINE_FLAG(name) u8 name:1
> DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
> #undef DEFINE_FLAG
> @@ -209,6 +204,10 @@ struct intel_device_info {
> u8 ver;
> u8 rel;
>
> + u8 pipe_mask;
> + u8 cpu_transcoder_mask;
> + u8 abox_mask;
> +
> #define DEFINE_FLAG(name) u8 name:1
> DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
> #undef DEFINE_FLAG
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display
2021-12-10 12:27 [Intel-gfx] [PATCH] drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display Ville Syrjala
2021-12-10 13:12 ` Jani Nikula
@ 2021-12-10 15:37 ` Patchwork
2021-12-10 15:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-12-10 15:37 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display
URL : https://patchwork.freedesktop.org/series/97864/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9fb166758466 drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display
-:45: WARNING:SPACING: space prohibited between function name and open parenthesis '('
#45: FILE: drivers/gpu/drm/i915/display/intel_display.h:383:
+ for_each_if (INTEL_INFO(__dev_priv)->display.cpu_transcoder_mask & BIT(__t))
-:80: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#80: FILE: drivers/gpu/drm/i915/i915_drv.h:1512:
+#define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
total: 0 errors, 2 warnings, 0 checks, 325 lines checked
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display
2021-12-10 12:27 [Intel-gfx] [PATCH] drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display Ville Syrjala
2021-12-10 13:12 ` Jani Nikula
2021-12-10 15:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2021-12-10 15:38 ` Patchwork
2021-12-10 16:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-12-11 12:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-12-10 15:38 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display
URL : https://patchwork.freedesktop.org/series/97864/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display
2021-12-10 12:27 [Intel-gfx] [PATCH] drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display Ville Syrjala
` (2 preceding siblings ...)
2021-12-10 15:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-12-10 16:06 ` Patchwork
2021-12-11 12:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-12-10 16:06 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5438 bytes --]
== Series Details ==
Series: drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display
URL : https://patchwork.freedesktop.org/series/97864/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10988 -> Patchwork_21822
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/index.html
Participating hosts (45 -> 35)
------------------------------
Missing (10): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 bat-jsl-2 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_21822 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-skl-6600u: NOTRUN -> [SKIP][2] ([fdo#109271]) +18 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/fi-skl-6600u/igt@amdgpu/amd_cs_nop@sync-fork-gfx0.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [PASS][3] -> [INCOMPLETE][4] ([i915#2940])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-cfl-8109u: [PASS][5] -> [DMESG-WARN][6] ([i915#165]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/fi-cfl-8109u/igt@kms_force_connector_basic@force-connector-state.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/fi-cfl-8109u/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#4269])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] ([i915#165] / [i915#295]) +13 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@runner@aborted:
- fi-bsw-n3050: NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/fi-bsw-n3050/igt@runner@aborted.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [INCOMPLETE][12] ([i915#4006]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][14] ([i915#3921]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: [FAIL][16] ([i915#4547]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4006]: https://gitlab.freedesktop.org/drm/intel/issues/4006
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
Build changes
-------------
* Linux: CI_DRM_10988 -> Patchwork_21822
CI-20190529: 20190529
CI_DRM_10988: 24a4093e85c578905d39ebe14225dbeb5b6f07d5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6305: 136258e86a093fdb50a7a341de1c09ac9a076fea @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21822: 9fb166758466b3fe1902f74d998edbbd2ccd058d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9fb166758466 drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/index.html
[-- Attachment #2: Type: text/html, Size: 6478 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display
2021-12-10 12:27 [Intel-gfx] [PATCH] drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display Ville Syrjala
` (3 preceding siblings ...)
2021-12-10 16:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-12-11 12:03 ` Patchwork
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-12-11 12:03 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30295 bytes --]
== Series Details ==
Series: drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display
URL : https://patchwork.freedesktop.org/series/97864/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10988_full -> Patchwork_21822_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21822_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21822_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21822_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_big_fb@linear-64bpp-rotate-180:
- shard-iclb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-iclb2/igt@kms_big_fb@linear-64bpp-rotate-180.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-iclb6/igt@kms_big_fb@linear-64bpp-rotate-180.html
Known issues
------------
Here are the changes found in Patchwork_21822_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@engines-hostile-preempt:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-snb5/igt@gem_ctx_persistence@engines-hostile-preempt.html
* igt@gem_ctx_sseu@engines:
- shard-tglb: NOTRUN -> [SKIP][4] ([i915#280])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-tglb3/igt@gem_ctx_sseu@engines.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-tglb: [PASS][5] -> [TIMEOUT][6] ([i915#3063])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-tglb8/igt@gem_eio@in-flight-contexts-1us.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-tglb8/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#4547])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-skl8/igt@gem_exec_capture@pi@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-skl8/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-iclb7/igt@gem_exec_fair@basic-pace@bcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-iclb5/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-sync@rcs0:
- shard-tglb: [PASS][13] -> [SKIP][14] ([i915#2848])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-tglb2/igt@gem_exec_fair@basic-sync@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-tglb2/igt@gem_exec_fair@basic-sync@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][15] -> [SKIP][16] ([i915#2190])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-tglb8/igt@gem_huc_copy@huc-copy.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-tglb7/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-kbl6/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_mmap_offset@clear:
- shard-tglb: [PASS][18] -> [INCOMPLETE][19] ([i915#3683])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-tglb2/igt@gem_mmap_offset@clear.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-tglb2/igt@gem_mmap_offset@clear.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#1436] / [i915#716])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-skl7/igt@gen9_exec_parse@allowed-single.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-skl8/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-apl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#658])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-apl4/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][23] -> [FAIL][24] ([i915#454])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: [PASS][25] -> [INCOMPLETE][26] ([i915#151])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-skl6/igt@i915_pm_rpm@system-suspend-execbuf.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-skl7/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3777]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-kbl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-tglb: [PASS][28] -> [FAIL][29] ([i915#3743]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-tglb2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-tglb2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3886])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-skl10/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3886]) +3 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-apl3/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3886]) +4 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-kbl4/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_cdclk@mode-transition:
- shard-apl: NOTRUN -> [SKIP][33] ([fdo#109271]) +59 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-apl3/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium@vga-hpd-without-ddc:
- shard-kbl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +9 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-kbl3/igt@kms_chamelium@vga-hpd-without-ddc.html
* igt@kms_color@pipe-b-ctm-green-to-red:
- shard-skl: [PASS][35] -> [DMESG-WARN][36] ([i915#1982])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-skl9/igt@kms_color@pipe-b-ctm-green-to-red.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-skl7/igt@kms_color@pipe-b-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-a-degamma:
- shard-snb: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-snb5/igt@kms_color_chamelium@pipe-a-degamma.html
* igt@kms_color_chamelium@pipe-b-ctm-0-75:
- shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +5 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-apl3/igt@kms_color_chamelium@pipe-b-ctm-0-75.html
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> [TIMEOUT][39] ([i915#1319])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-kbl3/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][40] ([i915#2105])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-kbl6/igt@kms_content_protection@uevent.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-skl: NOTRUN -> [SKIP][41] ([fdo#109271]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-skl9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][42] -> [FAIL][43] ([i915#2346])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [PASS][44] -> [FAIL][45] ([i915#79])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][46] -> [DMESG-WARN][47] ([i915#180]) +2 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [PASS][48] -> [FAIL][49] ([i915#2122]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-skl10/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs:
- shard-apl: NOTRUN -> [DMESG-WARN][50] ([i915#1226])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-apl7/igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][51] -> [DMESG-WARN][52] ([i915#180]) +6 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
- shard-snb: NOTRUN -> [SKIP][53] ([fdo#109271]) +42 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-snb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#533])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-apl4/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][55] ([i915#265])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][56] ([i915#265])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-kbl6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][57] ([fdo#108145] / [i915#265]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-kbl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][58] -> [FAIL][59] ([fdo#108145] / [i915#265])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#658]) +4 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-kbl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][61] ([fdo#109271]) +130 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-kbl3/igt@kms_universal_plane@disable-primary-vs-flip-pipe-d.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-kbl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#533]) +3 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-kbl3/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-check-output:
- shard-kbl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#2437])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-kbl6/igt@kms_writeback@writeback-check-output.html
* igt@perf@blocking:
- shard-skl: [PASS][64] -> [FAIL][65] ([i915#1542]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-skl4/igt@perf@blocking.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-skl1/igt@perf@blocking.html
* igt@sysfs_clients@create:
- shard-kbl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2994])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-kbl6/igt@sysfs_clients@create.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][67] ([i915#2842]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk: [FAIL][69] ([i915#2842]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-glk5/igt@gem_exec_fair@basic-pace@vcs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-glk9/igt@gem_exec_fair@basic-pace@vcs0.html
- shard-tglb: [FAIL][71] ([i915#2842]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-tglb8/igt@gem_exec_fair@basic-pace@vcs0.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-tglb7/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- {shard-rkl}: [FAIL][73] ([i915#2842]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-1/igt@gem_exec_fair@basic-throttle@rcs0.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-1/igt@gem_exec_fair@basic-throttle@rcs0.html
- shard-iclb: [FAIL][75] ([i915#2849]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][77] ([i915#180]) -> [PASS][78] +3 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-kbl6/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_pm_rpm@modeset-lpsp:
- {shard-rkl}: [SKIP][79] ([i915#1397]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-1/igt@i915_pm_rpm@modeset-lpsp.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][81] ([i915#3921]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-snb6/igt@i915_selftest@live@hangcheck.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-snb5/igt@i915_selftest@live@hangcheck.html
* igt@kms_async_flips@async-flip-with-page-flip-events:
- {shard-rkl}: [SKIP][83] ([i915#1845]) -> [PASS][84] +19 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-2/igt@kms_async_flips@async-flip-with-page-flip-events.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_big_fb@linear-64bpp-rotate-180:
- shard-glk: [FAIL][85] ([i915#1888] / [i915#3653]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-glk7/igt@kms_big_fb@linear-64bpp-rotate-180.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-glk4/igt@kms_big_fb@linear-64bpp-rotate-180.html
* igt@kms_color@pipe-b-ctm-negative:
- {shard-rkl}: ([PASS][87], [SKIP][88]) ([i915#1149] / [i915#4098]) -> [PASS][89]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-6/igt@kms_color@pipe-b-ctm-negative.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-4/igt@kms_color@pipe-b-ctm-negative.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@kms_color@pipe-b-ctm-negative.html
* igt@kms_color@pipe-c-invalid-ctm-matrix-sizes:
- {shard-rkl}: ([PASS][90], [SKIP][91]) ([i915#4070]) -> [PASS][92]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-4/igt@kms_color@pipe-c-invalid-ctm-matrix-sizes.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-6/igt@kms_color@pipe-c-invalid-ctm-matrix-sizes.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-4/igt@kms_color@pipe-c-invalid-ctm-matrix-sizes.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen:
- {shard-rkl}: [SKIP][93] ([fdo#112022] / [i915#4070]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-1/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding:
- {shard-rkl}: ([SKIP][95], [PASS][96]) ([fdo#112022]) -> [PASS][97]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-4/igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- {shard-rkl}: [SKIP][98] ([fdo#112022]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge:
- {shard-rkl}: [SKIP][100] ([i915#1849] / [i915#4070]) -> [PASS][101] +2 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-2/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- {shard-rkl}: ([SKIP][102], [SKIP][103]) ([fdo#111825] / [i915#4070]) -> [PASS][104]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-4/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- {shard-rkl}: [SKIP][105] ([fdo#111825]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-4/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_cursor_legacy@short-flip-before-cursor-toggle:
- {shard-rkl}: [SKIP][107] ([fdo#111825] / [i915#4070]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-1/igt@kms_cursor_legacy@short-flip-before-cursor-toggle.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@kms_cursor_legacy@short-flip-before-cursor-toggle.html
* igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled:
- {shard-rkl}: [SKIP][109] ([fdo#111314]) -> [PASS][110] +2 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [DMESG-WARN][111] ([i915#180]) -> [PASS][112] +2 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
- shard-skl: [FAIL][113] ([i915#2122]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-skl7/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render:
- {shard-rkl}: [SKIP][115] ([i915#1849]) -> [PASS][116] +17 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- {shard-rkl}: ([SKIP][117], [SKIP][118]) ([i915#1849] / [i915#4098]) -> [PASS][119]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][120] ([i915#1188]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a:
- {shard-rkl}: ([PASS][122], [SKIP][123]) ([i915#4098]) -> [PASS][124]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
- {shard-rkl}: [SKIP][125] ([i915#4098]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-4/igt@kms_pipe_crc_basic@hang-read-crc-pipe-b.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@kms_pipe_crc_basic@hang-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][127] ([fdo#108145] / [i915#265]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@cursor_mmap_gtt:
- {shard-rkl}: [SKIP][129] ([i915#1072]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-1/igt@kms_psr@cursor_mmap_gtt.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@kms_psr@cursor_mmap_gtt.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][131] ([fdo#109441]) -> [PASS][132] +2 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_universal_plane@universal-plane-pipe-b-functional:
- {shard-rkl}: [SKIP][133] ([i915#1845] / [i915#4070]) -> [PASS][134]
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-rkl-2/igt@kms_universal_plane@universal-plane-pipe-b-functional.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-rkl-6/igt@kms_universal_plane@universal-plane-pipe-b-functional.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][135] ([i915#180] / [i915#295]) -> [PASS][136]
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-apl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf_pmu@module-unload:
- shard-skl: [DMESG-WARN][137] ([i915#1982] / [i915#262]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-skl10/igt@perf_pmu@module-unload.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-skl6/igt@perf_pmu@module-unload.html
* igt@sysfs_heartbeat_interval@mixed@rcs0:
- shard-skl: [FAIL][139] ([i915#1731]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-skl1/igt@sysfs_heartbeat_interval@mixed@rcs0.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-skl10/igt@sysfs_heartbeat_interval@mixed@rcs0.html
#### Warnings ####
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-tglb: [FAIL][141] ([i915#2842]) -> [SKIP][142] ([i915#2848])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-tglb6/igt@gem_exec_fair@basic-throttle@rcs0.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-tglb2/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-iclb: [SKIP][143] ([i915#2920]) -> [SKIP][144] ([i915#658]) +3 similar issues
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-iclb6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-3:
- shard-iclb: [SKIP][145] ([i915#658]) -> [SKIP][146] ([i915#2920]) +2 similar issues
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-iclb5/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-iclb: [FAIL][147] ([i915#4148]) -> [SKIP][148] ([i915#658])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10988/shard-iclb2/igt@kms_psr2_su@page_flip-xrgb8888.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/shard-iclb7/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153],
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21822/index.html
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-- links below jump to the message on this page --
2021-12-10 12:27 [Intel-gfx] [PATCH] drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display Ville Syrjala
2021-12-10 13:12 ` Jani Nikula
2021-12-10 15:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2021-12-10 15:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-12-10 16:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-12-11 12:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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