From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915: Use named initializers for DPLL info
Date: Thu, 12 Oct 2023 17:52:09 +0300 [thread overview]
Message-ID: <87il7b28rq.fsf@intel.com> (raw)
In-Reply-To: <20231012123522.26045-2-ville.syrjala@linux.intel.com>
On Thu, 12 Oct 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use named initializers when populating the DPLL info. This
> is just more convenient and less error prone as we no longer
> have to keep the initializers in a specific order.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Nitpick, it's designated initializer. ;)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 130 +++++++++---------
> 1 file changed, 67 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 399653a20f98..b7997b096796 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -631,9 +631,9 @@ static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
> };
>
> static const struct dpll_info pch_plls[] = {
> - { "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
> - { "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
> - { },
> + { .name = "PCH DPLL A", .funcs = &ibx_pch_dpll_funcs, .id = DPLL_ID_PCH_PLL_A, },
> + { .name = "PCH DPLL B", .funcs = &ibx_pch_dpll_funcs, .id = DPLL_ID_PCH_PLL_B, },
> + {}
> };
>
> static const struct intel_dpll_mgr pch_pll_mgr = {
> @@ -1239,13 +1239,16 @@ static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
> };
>
> static const struct dpll_info hsw_plls[] = {
> - { "WRPLL 1", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1, 0 },
> - { "WRPLL 2", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2, 0 },
> - { "SPLL", &hsw_ddi_spll_funcs, DPLL_ID_SPLL, 0 },
> - { "LCPLL 810", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810, INTEL_DPLL_ALWAYS_ON },
> - { "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON },
> - { "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON },
> - { },
> + { .name = "WRPLL 1", .funcs = &hsw_ddi_wrpll_funcs, .id = DPLL_ID_WRPLL1, },
> + { .name = "WRPLL 2", .funcs = &hsw_ddi_wrpll_funcs, .id = DPLL_ID_WRPLL2, },
> + { .name = "SPLL", .funcs = &hsw_ddi_spll_funcs, .id = DPLL_ID_SPLL, },
> + { .name = "LCPLL 810", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_810,
> + .flags = INTEL_DPLL_ALWAYS_ON, },
> + { .name = "LCPLL 1350", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_1350,
> + .flags = INTEL_DPLL_ALWAYS_ON, },
> + { .name = "LCPLL 2700", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_2700,
> + .flags = INTEL_DPLL_ALWAYS_ON, },
> + {}
> };
>
> static const struct intel_dpll_mgr hsw_pll_mgr = {
> @@ -1921,11 +1924,12 @@ static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
> };
>
> static const struct dpll_info skl_plls[] = {
> - { "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
> - { "DPLL 1", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
> - { "DPLL 2", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
> - { "DPLL 3", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL3, 0 },
> - { },
> + { .name = "DPLL 0", .funcs = &skl_ddi_dpll0_funcs, .id = DPLL_ID_SKL_DPLL0,
> + .flags = INTEL_DPLL_ALWAYS_ON, },
> + { .name = "DPLL 1", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL1, },
> + { .name = "DPLL 2", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL2, },
> + { .name = "DPLL 3", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL3, },
> + {}
> };
>
> static const struct intel_dpll_mgr skl_pll_mgr = {
> @@ -2376,10 +2380,10 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
> };
>
> static const struct dpll_info bxt_plls[] = {
> - { "PORT PLL A", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
> - { "PORT PLL B", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
> - { "PORT PLL C", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
> - { },
> + { .name = "PORT PLL A", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL0, },
> + { .name = "PORT PLL B", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL1, },
> + { .name = "PORT PLL C", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL2, },
> + {}
> };
>
> static const struct intel_dpll_mgr bxt_pll_mgr = {
> @@ -4014,14 +4018,14 @@ static const struct intel_shared_dpll_funcs mg_pll_funcs = {
> };
>
> static const struct dpll_info icl_plls[] = {
> - { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> - { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
> - { "TBT PLL", &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
> - { "MG PLL 1", &mg_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
> - { "MG PLL 2", &mg_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
> - { "MG PLL 3", &mg_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
> - { "MG PLL 4", &mg_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
> - { },
> + { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> + { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> + { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> + { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> + { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> + { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> + {}
> };
>
> static const struct intel_dpll_mgr icl_pll_mgr = {
> @@ -4035,10 +4039,10 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
> };
>
> static const struct dpll_info ehl_plls[] = {
> - { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> - { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
> - { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
> - { },
> + { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> + { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> + { .name = "DPLL 4", .funcs = &combo_pll_funcs, .id = DPLL_ID_EHL_DPLL4, },
> + {}
> };
>
> static const struct intel_dpll_mgr ehl_pll_mgr = {
> @@ -4058,16 +4062,16 @@ static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
> };
>
> static const struct dpll_info tgl_plls[] = {
> - { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> - { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
> - { "TBT PLL", &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
> - { "TC PLL 1", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
> - { "TC PLL 2", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
> - { "TC PLL 3", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
> - { "TC PLL 4", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
> - { "TC PLL 5", &dkl_pll_funcs, DPLL_ID_TGL_MGPLL5, 0 },
> - { "TC PLL 6", &dkl_pll_funcs, DPLL_ID_TGL_MGPLL6, 0 },
> - { },
> + { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> + { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> + { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> + { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> + { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> + { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> + { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5, },
> + { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6, },
> + {}
> };
>
> static const struct intel_dpll_mgr tgl_pll_mgr = {
> @@ -4081,10 +4085,10 @@ static const struct intel_dpll_mgr tgl_pll_mgr = {
> };
>
> static const struct dpll_info rkl_plls[] = {
> - { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> - { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
> - { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
> - { },
> + { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> + { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> + { .name = "DPLL 4", .funcs = &combo_pll_funcs, .id = DPLL_ID_EHL_DPLL4, },
> + {}
> };
>
> static const struct intel_dpll_mgr rkl_pll_mgr = {
> @@ -4097,11 +4101,11 @@ static const struct intel_dpll_mgr rkl_pll_mgr = {
> };
>
> static const struct dpll_info dg1_plls[] = {
> - { "DPLL 0", &combo_pll_funcs, DPLL_ID_DG1_DPLL0, 0 },
> - { "DPLL 1", &combo_pll_funcs, DPLL_ID_DG1_DPLL1, 0 },
> - { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
> - { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
> - { },
> + { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL0, },
> + { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL1, },
> + { .name = "DPLL 2", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL2, },
> + { .name = "DPLL 3", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL3, },
> + {}
> };
>
> static const struct intel_dpll_mgr dg1_pll_mgr = {
> @@ -4114,11 +4118,11 @@ static const struct intel_dpll_mgr dg1_pll_mgr = {
> };
>
> static const struct dpll_info adls_plls[] = {
> - { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> - { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
> - { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
> - { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
> - { },
> + { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> + { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> + { .name = "DPLL 2", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL2, },
> + { .name = "DPLL 3", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL3, },
> + {}
> };
>
> static const struct intel_dpll_mgr adls_pll_mgr = {
> @@ -4131,14 +4135,14 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
> };
>
> static const struct dpll_info adlp_plls[] = {
> - { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> - { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
> - { "TBT PLL", &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
> - { "TC PLL 1", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
> - { "TC PLL 2", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
> - { "TC PLL 3", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
> - { "TC PLL 4", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
> - { },
> + { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> + { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> + { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> + { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> + { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> + { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> + {}
> };
>
> static const struct intel_dpll_mgr adlp_pll_mgr = {
--
Jani Nikula, Intel
next prev parent reply other threads:[~2023-10-12 14:52 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-12 12:35 [Intel-gfx] [PATCH 0/4] drm/i915: DPLL code cleanups Ville Syrjala
2023-10-12 12:35 ` [Intel-gfx] [PATCH 1/4] drm/i915: Use named initializers for DPLL info Ville Syrjala
2023-10-12 14:52 ` Jani Nikula [this message]
2023-10-12 12:35 ` [Intel-gfx] [PATCH 2/4] drm/i915: Abstract the extra JSL/EHL DPLL4 power domain better Ville Syrjala
2023-10-12 14:56 ` Jani Nikula
2023-10-12 16:20 ` Imre Deak
2023-10-12 12:35 ` [Intel-gfx] [PATCH 3/4] drm/i915: Move the DPLL extra power domain handling up one level Ville Syrjala
2023-10-12 14:56 ` Jani Nikula
2023-10-12 12:35 ` [Intel-gfx] [PATCH 4/4] drm/i915: Extract _intel_{enable, disable}_shared_dpll() Ville Syrjala
2023-10-12 14:57 ` Jani Nikula
2023-10-12 18:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: DPLL code cleanups Patchwork
2023-10-12 18:33 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-10-13 22:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: DPLL code cleanups (rev2) Patchwork
2023-10-13 23:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-17 16:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: DPLL code cleanups (rev4) Patchwork
2023-10-17 16:36 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-10-27 22:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: DPLL code cleanups (rev5) Patchwork
2023-10-27 22:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-30 7:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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