From: Jani Nikula <jani.nikula@linux.intel.com>
To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
Intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/3] drm/i915: Replace "INTEL_INFO->gen == x" checks with IS_GENx
Date: Tue, 10 May 2016 10:47:46 +0300 [thread overview]
Message-ID: <87inymbbh9.fsf@intel.com> (raw)
In-Reply-To: <1462542231-7321-3-git-send-email-tvrtko.ursulin@linux.intel.com>
On Fri, 06 May 2016, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> This way optimization from a previous patch works even better.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
> drivers/gpu/drm/i915/i915_dma.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_tiling.c | 2 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> drivers/gpu/drm/i915/i915_irq.c | 4 ++--
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_lrc.c | 4 ++--
> drivers/gpu/drm/i915/intel_lvds.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++---
> 15 files changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 6ad008c196b5..e264f168ef02 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2310,12 +2310,12 @@ static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_engine_cs *engine;
>
> - if (INTEL_INFO(dev)->gen == 6)
> + if (IS_GEN6(dev_priv))
> seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
>
> for_each_engine(engine, dev_priv) {
> seq_printf(m, "%s\n", engine->name);
> - if (INTEL_INFO(dev)->gen == 7)
> + if (IS_GEN7(dev_priv))
> seq_printf(m, "GFX_MODE: 0x%08x\n",
> I915_READ(RING_MODE_GEN7(engine)));
> seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 01163da51b1d..a65c85c8317c 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -888,7 +888,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> DRM_INFO("Display disabled (module parameter)\n");
> info->num_pipes = 0;
> } else if (info->num_pipes > 0 &&
> - (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
> + (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
> HAS_PCH_SPLIT(dev)) {
> u32 fuse_strap = I915_READ(FUSE_STRAP);
> u32 sfuse_strap = I915_READ(SFUSE_STRAP);
> @@ -912,7 +912,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> DRM_INFO("PipeC fused off\n");
> info->num_pipes -= 1;
> }
> - } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
> + } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
> u32 dfsm = I915_READ(SKL_DFSM);
> u8 disabled_mask = 0;
> bool invalid;
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index da6532da44e3..f27cc15b6f8e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -548,7 +548,7 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
>
> #ifdef CONFIG_INTEL_IOMMU
> /* Enable semaphores on SNB when IO remapping is off */
> - if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
> + if (IS_GEN6(dev) && intel_iommu_gfx_mapped)
> return false;
> #endif
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 459561991081..15fcbcece13c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2702,7 +2702,7 @@ struct drm_i915_cmd_table {
> IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
> IS_KABYLAKE(dev) || IS_BROXTON(dev))
> #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
> -#define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
> +#define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
>
> #define HAS_CSR(dev) (IS_GEN9(dev))
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index a88e6c9e9516..f2e42c0cc5be 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1982,7 +1982,7 @@ i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
> return size;
>
> /* Previous chips need a power-of-two fence region when tiling */
> - if (INTEL_INFO(dev)->gen == 3)
> + if (IS_GEN3(dev))
> gtt_size = 1024*1024;
> else
> gtt_size = 512*1024;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index d284b17af431..61e85c2b500d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -144,7 +144,7 @@ int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
>
> #ifdef CONFIG_INTEL_IOMMU
> /* Disable ppgtt on SNB if VT-d is on. */
> - if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
> + if (IS_GEN6(dev) && intel_iommu_gfx_mapped) {
> DRM_INFO("Disabling PPGTT because VT-d is on\n");
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index 68fde8fba803..f9253f2b7ba0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -56,7 +56,7 @@ int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
>
> /* See the comment at the drm_mm_init() call for more about this check.
> * WaSkipStolenMemoryFirstPage:bdw,chv (incomplete) */
> - if (INTEL_INFO(dev_priv)->gen == 8 && start < 4096)
> + if (IS_GEN8(dev_priv) && start < 4096)
> start = 4096;
>
> mutex_lock(&dev_priv->mm.stolen_lock);
> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> index 829dab69895f..2fcb4afade19 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -125,7 +125,7 @@ i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
> if (INTEL_INFO(obj->base.dev)->gen >= 4)
> return true;
>
> - if (INTEL_INFO(obj->base.dev)->gen == 3) {
> + if (IS_GEN3(obj->base.dev)) {
> if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
> return false;
> } else {
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 89725c9efc25..12a749c9707a 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -411,7 +411,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
> err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
> }
>
> - if (INTEL_INFO(dev)->gen == 7)
> + if (IS_GEN7(dev))
> err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
>
> for (i = 0; i < ARRAY_SIZE(error->ring); i++)
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 2f6fd33c07ba..ba84b9b17fc2 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4674,12 +4674,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev->driver->disable_vblank = ironlake_disable_vblank;
> dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
> } else {
> - if (INTEL_INFO(dev_priv)->gen == 2) {
> + if (IS_GEN2(dev_priv)) {
> dev->driver->irq_preinstall = i8xx_irq_preinstall;
> dev->driver->irq_postinstall = i8xx_irq_postinstall;
> dev->driver->irq_handler = i8xx_irq_handler;
> dev->driver->irq_uninstall = i8xx_irq_uninstall;
> - } else if (INTEL_INFO(dev_priv)->gen == 3) {
> + } else if (IS_GEN3(dev_priv)) {
> dev->driver->irq_preinstall = i915_irq_preinstall;
> dev->driver->irq_postinstall = i915_irq_postinstall;
> dev->driver->irq_uninstall = i915_irq_uninstall;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 45c218db86be..1385423ac960 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1204,7 +1204,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
> u32 val;
>
> /* ILK FDI PLL is always enabled */
> - if (INTEL_INFO(dev_priv)->gen == 5)
> + if (IS_GEN5(dev_priv))
> return;
>
> /* On Haswell, DDI ports are responsible for the FDI PLL setup */
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index d8763524319d..f614a07a07bb 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1387,7 +1387,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
> batch = kmap_atomic(page);
> offset = 0;
>
> - if (INTEL_INFO(engine->dev)->gen == 8) {
> + if (IS_GEN8(engine->dev)) {
> ret = gen8_init_indirectctx_bb(engine,
> &wa_ctx->indirect_ctx,
> batch,
> @@ -1401,7 +1401,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
> &offset);
> if (ret)
> goto out;
> - } else if (INTEL_INFO(engine->dev)->gen == 9) {
> + } else if (IS_GEN9(engine->dev)) {
> ret = gen9_init_indirectctx_bb(engine,
> &wa_ctx->indirect_ctx,
> batch,
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index bc53c0dd34d0..d65fd945607a 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -190,7 +190,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
> /* Set the dithering flag on LVDS as needed, note that there is no
> * special lvds dither control bit on pch-split platforms, dithering is
> * only controlled through the PIPECONF reg. */
> - if (INTEL_INFO(dev)->gen == 4) {
> + if (IS_GEN4(dev_priv)) {
> /* Bspec wording suggests that LVDS port dithering only exists
> * for 18bpp panels. */
> if (crtc->config->dither && crtc->config->pipe_bpp == 18)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 017c431f9363..5f17f682d37b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2146,14 +2146,14 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
> static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
> {
> /* ILK sprite LP0 latency is 1300 ns */
> - if (INTEL_INFO(dev)->gen == 5)
> + if (IS_GEN5(dev))
> wm[0] = 13;
> }
>
> static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
> {
> /* ILK cursor LP0 latency is 1300 ns */
> - if (INTEL_INFO(dev)->gen == 5)
> + if (IS_GEN5(dev))
> wm[0] = 13;
>
> /* WaDoubleCursorLP3Latency:ivb */
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8f3eb3033da0..710cd598c701 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1236,7 +1236,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
>
> /* Required for the hardware to program scanline values for waiting */
> /* WaEnableFlushTlbInvalidationMode:snb */
> - if (INTEL_INFO(dev)->gen == 6)
> + if (IS_GEN6(dev_priv))
> I915_WRITE(GFX_MODE,
> _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
>
> @@ -2536,7 +2536,7 @@ void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
> * the semaphore value, then when the seqno moves backwards all
> * future waits will complete instantly (causing rendering corruption).
> */
> - if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) {
> + if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
> I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
> I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
> if (HAS_VEBOX(dev_priv))
> @@ -2808,7 +2808,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> engine->init_context = intel_rcs_ctx_init;
> engine->add_request = gen6_add_request;
> engine->flush = gen7_render_ring_flush;
> - if (INTEL_INFO(dev)->gen == 6)
> + if (IS_GEN6(dev_priv))
> engine->flush = gen6_render_ring_flush;
> engine->irq_get = gen6_ring_get_irq;
> engine->irq_put = gen6_ring_put_irq;
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2016-05-10 7:47 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-06 13:43 [PATCH 1/3] drm/i915: Make IS_GENx macros work on a mask Tvrtko Ursulin
2016-05-06 13:43 ` [PATCH 2/3] drm/i915: Promote IS_BROADWELL to a simple macro Tvrtko Ursulin
2016-05-06 14:00 ` Ville Syrjälä
2016-05-06 14:18 ` Tvrtko Ursulin
2016-05-06 14:29 ` Ville Syrjälä
2016-05-06 14:44 ` Tvrtko Ursulin
2016-05-06 14:51 ` Chris Wilson
2016-05-06 14:58 ` Ville Syrjälä
2016-05-06 13:43 ` [PATCH 3/3] drm/i915: Replace "INTEL_INFO->gen == x" checks with IS_GENx Tvrtko Ursulin
2016-05-06 13:59 ` Chris Wilson
2016-05-06 14:16 ` Tvrtko Ursulin
2016-05-06 14:20 ` Tvrtko Ursulin
2016-05-09 14:18 ` Dave Gordon
2016-05-10 7:47 ` Jani Nikula [this message]
2016-05-06 14:16 ` [PATCH 1/2] drm/i915: Introduce INTEL_GEN_RANGE macro Tvrtko Ursulin
2016-05-06 14:16 ` [PATCH 2/2] drm/i915: Do not use a bitfield for INTEL_INFO->num_pipes Tvrtko Ursulin
2016-05-06 19:21 ` Dave Gordon
2016-05-06 14:33 ` [PATCH 1/2] drm/i915: Introduce INTEL_GEN_RANGE macro Chris Wilson
2016-05-06 19:11 ` Dave Gordon
2016-05-09 12:32 ` Jani Nikula
2016-05-09 14:26 ` Dave Gordon
2016-05-09 14:40 ` Jani Nikula
2016-05-09 15:23 ` Chris Wilson
2016-05-10 7:54 ` Jani Nikula
2016-05-06 14:28 ` [PATCH 1/3] drm/i915: Make IS_GENx macros work on a mask Chris Wilson
2016-05-06 14:36 ` Tvrtko Ursulin
2016-05-06 14:43 ` Chris Wilson
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