From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: michel.thierry@intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/bdw: 3D_CHICKEN3 has write mask bits
Date: Mon, 07 Jul 2014 16:06:02 +0300 [thread overview]
Message-ID: <87k37puxmt.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <1404733217-13185-1-git-send-email-michel.thierry@intel.com>
michel.thierry@intel.com writes:
> From: Michel Thierry <michel.thierry@intel.com>
>
> The workaround to limit SDE poly depth FIFO to 2 is not applied because
> 3D Chicken-3 mask bit is not set.
>
> WaLimitSizeOfSDEPolyFifo is only for BDW-A and could be removed.
>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 31ae2b4..ae68df6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5360,7 +5360,7 @@ static void gen8_init_clock_gating(struct drm_device *dev)
> I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
>
> I915_WRITE(_3D_CHICKEN3,
> - _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
> + _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
>
> I915_WRITE(COMMON_SLICE_CHICKEN2,
> _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
> --
> 1.9.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2014-07-07 13:06 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-07 11:40 [PATCH] drm/i915/bdw: 3D_CHICKEN3 has write mask bits michel.thierry
2014-07-07 13:06 ` Mika Kuoppala [this message]
2014-07-07 16:31 ` Daniel Vetter
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