* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER
2018-03-23 19:58 [PATCH] drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER Paulo Zanoni
@ 2018-03-23 20:08 ` Patchwork
2018-03-23 20:23 ` ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2018-03-23 20:08 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER
URL : https://patchwork.freedesktop.org/series/40601/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ed3487826478 drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER
-:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#14:
Reference: commit 04416108ccea ("drm/i915/cnl: Add registers related to voltage swing sequences.")
total: 0 errors, 1 warnings, 0 checks, 11 lines checked
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^ permalink raw reply [flat|nested] 6+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER
2018-03-23 19:58 [PATCH] drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER Paulo Zanoni
2018-03-23 20:08 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2018-03-23 20:23 ` Patchwork
2018-03-23 21:29 ` [PATCH] " Rodrigo Vivi
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2018-03-23 20:23 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER
URL : https://patchwork.freedesktop.org/series/40601/
State : success
== Summary ==
Series 40601v1 drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER
https://patchwork.freedesktop.org/api/1.0/series/40601/revisions/1/mbox/
---- Known issues:
Test debugfs_test:
Subgroup read_all_entries:
incomplete -> PASS (fi-snb-2520m) fdo#103713
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass -> FAIL (fi-gdg-551) fdo#102575
Test prime_vgem:
Subgroup basic-fence-flip:
fail -> PASS (fi-ilk-650) fdo#104008
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:444s
fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:444s
fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:382s
fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:540s
fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:298s
fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:519s
fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:518s
fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:522s
fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:508s
fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:411s
fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:511s
fi-cnl-y3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:589s
fi-elk-e7500 total:285 pass:225 dwarn:1 dfail:0 fail:0 skip:59 time:430s
fi-gdg-551 total:285 pass:176 dwarn:0 dfail:0 fail:1 skip:108 time:316s
fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:540s
fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:403s
fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:423s
fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:475s
fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:432s
fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:476s
fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:467s
fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:514s
fi-pnv-d510 total:285 pass:219 dwarn:1 dfail:0 fail:0 skip:65 time:655s
fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:444s
fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:538s
fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:506s
fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:495s
fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:430s
fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:445s
fi-snb-2520m total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:592s
fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:408s
Blacklisted hosts:
fi-cfl-s3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:569s
fi-cnl-psr total:224 pass:198 dwarn:0 dfail:0 fail:1 skip:24
fi-glk-j4005 total:285 pass:255 dwarn:1 dfail:0 fail:0 skip:29 time:488s
101f8aec6229d54ff241bb46b9d7bfc92cf682e9 drm-tip: 2018y-03m-23d-17h-52m-01s UTC integration manifest
ed3487826478 drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8482/issues.html
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER
2018-03-23 19:58 [PATCH] drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER Paulo Zanoni
2018-03-23 20:08 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-03-23 20:23 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-03-23 21:29 ` Rodrigo Vivi
2018-03-24 1:47 ` ✓ Fi.CI.IGT: success for " Patchwork
2018-03-26 13:11 ` [PATCH] " Jani Nikula
4 siblings, 0 replies; 6+ messages in thread
From: Rodrigo Vivi @ 2018-03-23 21:29 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Fri, Mar 23, 2018 at 12:58:53PM -0700, Paulo Zanoni wrote:
> Protect the macro parameters with parens in order to avoid priority
> issues on macro evaluation when the macro argument is not a single
> operand.
>
> This is not a problem today, but it could be in the future. I found
> this while reviewing a patch that introduces new callers for the
> macros.
>
> Reference: commit 04416108ccea ("drm/i915/cnl: Add registers related to voltage swing sequences.")
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index da2f6c623ab2..49c90e1aa796 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1729,9 +1729,9 @@ enum i915_power_well_id {
>
> #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
> #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
> -#define SWING_SEL_UPPER(x) ((x >> 3) << 15)
> +#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
> #define SWING_SEL_UPPER_MASK (1 << 15)
> -#define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
> +#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
> #define SWING_SEL_LOWER_MASK (0x7 << 11)
> #define RCOMP_SCALAR(x) ((x) << 0)
> #define RCOMP_SCALAR_MASK (0xFF << 0)
> --
> 2.14.3
>
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^ permalink raw reply [flat|nested] 6+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER
2018-03-23 19:58 [PATCH] drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER Paulo Zanoni
` (2 preceding siblings ...)
2018-03-23 21:29 ` [PATCH] " Rodrigo Vivi
@ 2018-03-24 1:47 ` Patchwork
2018-03-26 13:11 ` [PATCH] " Jani Nikula
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2018-03-24 1:47 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER
URL : https://patchwork.freedesktop.org/series/40601/
State : success
== Summary ==
---- Known issues:
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
fail -> PASS (shard-hsw) fdo#100368 +1
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
shard-apl total:3484 pass:1820 dwarn:1 dfail:0 fail:7 skip:1655 time:12996s
shard-hsw total:3484 pass:1773 dwarn:1 dfail:0 fail:2 skip:1707 time:11721s
shard-snb total:3484 pass:1363 dwarn:1 dfail:0 fail:3 skip:2117 time:7016s
Blacklisted hosts:
shard-kbl total:3484 pass:1944 dwarn:1 dfail:0 fail:10 skip:1529 time:9893s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8482/shards.html
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER
2018-03-23 19:58 [PATCH] drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER Paulo Zanoni
` (3 preceding siblings ...)
2018-03-24 1:47 ` ✓ Fi.CI.IGT: success for " Patchwork
@ 2018-03-26 13:11 ` Jani Nikula
4 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2018-03-26 13:11 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
On Fri, 23 Mar 2018, Paulo Zanoni <paulo.r.zanoni@intel.com> wrote:
> Protect the macro parameters with parens in order to avoid priority
> issues on macro evaluation when the macro argument is not a single
> operand.
>
> This is not a problem today, but it could be in the future. I found
> this while reviewing a patch that introduces new callers for the
> macros.
>
> Reference: commit 04416108ccea ("drm/i915/cnl: Add registers related to voltage swing sequences.")
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index da2f6c623ab2..49c90e1aa796 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1729,9 +1729,9 @@ enum i915_power_well_id {
>
> #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
> #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
> -#define SWING_SEL_UPPER(x) ((x >> 3) << 15)
> +#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
> #define SWING_SEL_UPPER_MASK (1 << 15)
> -#define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
> +#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
Unrelated to the patch at hand, but why do we have >> 3 and & 7 here
like this? We could have a single SWING_SEL_MASK() and SWING_SEL() that
would do the split to two parts. For future follow-up...
BR,
Jani.
> #define SWING_SEL_LOWER_MASK (0x7 << 11)
> #define RCOMP_SCALAR(x) ((x) << 0)
> #define RCOMP_SCALAR_MASK (0xFF << 0)
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 6+ messages in thread