* [PATCH 0/4] drm/i915/dmc_wl: Introduce debugfs interface
@ 2025-01-17 22:06 Gustavo Sousa
2025-01-17 22:06 ` [PATCH 1/4] drm/i915/dmc_wl: Pass offset instead of reg to range table iterator Gustavo Sousa
` (7 more replies)
0 siblings, 8 replies; 35+ messages in thread
From: Gustavo Sousa @ 2025-01-17 22:06 UTC (permalink / raw)
To: intel-gfx, intel-xe
The DMC wakelock code needs to keep track of register offsets that need
the wakelock for proper access. If one of the necessary offsets are
missed, then the failure in asserting the wakelock is very likely to
cause problems down the road.
A miss could happen for at least two different reasons:
- We might have forgotten to add the offset (or range) to the relevant
tables tracked by the driver in the first place.
- Or updates to either the DMC firmware or the display IP that require
new offsets to be tracked and we fail to realize that.
To help capture these cases, let's introduce a debugfs interface for the
DMC wakelock. The debugfs exports a file for looking up untracked
offsets and another for defining extra ranges to be tracked by our
driver during runtime, without the need of edit+re-compile+re-load
cycle.
See the added documentation and commit message for details.
Gustavo Sousa (4):
drm/i915/dmc_wl: Pass offset instead of reg to range table iterator
drm/i915/dmc_wl: Add debugfs for untracked offsets
drm/i915/dmc_wl: Add extra_ranges debugfs
drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_debugfs.c | 2 +
.../drm/i915/display/intel_display_params.c | 5 +
.../drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 23 +-
drivers/gpu/drm/i915/display/intel_dmc_wl.h | 2 +
.../drm/i915/display/intel_dmc_wl_debugfs.c | 517 ++++++++++++++++++
.../drm/i915/display/intel_dmc_wl_debugfs.h | 36 ++
drivers/gpu/drm/xe/Makefile | 1 +
9 files changed, 581 insertions(+), 7 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
--
2.48.0
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 1/4] drm/i915/dmc_wl: Pass offset instead of reg to range table iterator
2025-01-17 22:06 [PATCH 0/4] drm/i915/dmc_wl: Introduce debugfs interface Gustavo Sousa
@ 2025-01-17 22:06 ` Gustavo Sousa
2025-01-22 8:23 ` Luca Coelho
2025-01-17 22:06 ` [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets Gustavo Sousa
` (6 subsequent siblings)
7 siblings, 1 reply; 35+ messages in thread
From: Gustavo Sousa @ 2025-01-17 22:06 UTC (permalink / raw)
To: intel-gfx, intel-xe
We will add another function that checks the offset in an upcoming
change. Instead of passing the reg variable to only extract the offset
later, let's extract the offset before so that we do not need to repeat
ourselves.
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index 43884740f8ea..330b43a72e08 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -227,11 +227,9 @@ static void __intel_dmc_wl_take(struct intel_display *display)
wl->taken = true;
}
-static bool intel_dmc_wl_reg_in_range(i915_reg_t reg,
- const struct intel_dmc_wl_range ranges[])
+static bool intel_dmc_wl_offset_in_ranges(u32 offset,
+ const struct intel_dmc_wl_range ranges[])
{
- u32 offset = i915_mmio_reg_offset(reg);
-
for (int i = 0; ranges[i].start; i++) {
u32 end = ranges[i].end ?: ranges[i].start;
@@ -247,6 +245,7 @@ static bool intel_dmc_wl_check_range(struct intel_display *display,
u32 dc_state)
{
const struct intel_dmc_wl_range *ranges;
+ u32 offset = i915_mmio_reg_offset(reg);
if (display->params.enable_dmc_wl == ENABLE_DMC_WL_ANY_REGISTER)
return true;
@@ -255,7 +254,7 @@ static bool intel_dmc_wl_check_range(struct intel_display *display,
* Check that the offset is in one of the ranges for which
* registers are powered off during DC states.
*/
- if (intel_dmc_wl_reg_in_range(reg, powered_off_ranges))
+ if (intel_dmc_wl_offset_in_ranges(offset, powered_off_ranges))
return true;
/*
@@ -274,7 +273,7 @@ static bool intel_dmc_wl_check_range(struct intel_display *display,
ranges = NULL;
}
- if (ranges && intel_dmc_wl_reg_in_range(reg, ranges))
+ if (ranges && intel_dmc_wl_offset_in_ranges(offset, ranges))
return true;
return false;
--
2.48.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets
2025-01-17 22:06 [PATCH 0/4] drm/i915/dmc_wl: Introduce debugfs interface Gustavo Sousa
2025-01-17 22:06 ` [PATCH 1/4] drm/i915/dmc_wl: Pass offset instead of reg to range table iterator Gustavo Sousa
@ 2025-01-17 22:06 ` Gustavo Sousa
2025-01-22 9:06 ` Luca Coelho
` (2 more replies)
2025-01-17 22:06 ` [PATCH 3/4] drm/i915/dmc_wl: Add extra_ranges debugfs Gustavo Sousa
` (5 subsequent siblings)
7 siblings, 3 replies; 35+ messages in thread
From: Gustavo Sousa @ 2025-01-17 22:06 UTC (permalink / raw)
To: intel-gfx, intel-xe
The DMC wakelock code needs to keep track of register offsets that need
the wakelock for proper access. If one of the necessary offsets are
missed, then the failure in asserting the wakelock is very likely to
cause problems down the road.
A miss could happen for at least two different reasons:
- We might have forgotten to add the offset (or range) to the relevant
tables tracked by the driver in the first place.
- Or updates to either the DMC firmware or the display IP that require
new offsets to be tracked and we fail to realize that.
To help capture these cases, let's introduce a debugfs interface for the
DMC wakelock.
In this part, we export a buffer containing offsets of registers that
were considered not needing the wakelock by our driver. In an upcoming
change we will also allow defining an extra set of offset ranges to be
tracked by our driver.
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_debugfs.c | 2 +
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 5 +-
drivers/gpu/drm/i915/display/intel_dmc_wl.h | 2 +
.../drm/i915/display/intel_dmc_wl_debugfs.c | 251 ++++++++++++++++++
.../drm/i915/display/intel_dmc_wl_debugfs.h | 29 ++
drivers/gpu/drm/xe/Makefile | 1 +
7 files changed, 290 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3dda9f0eda82..ac1ab79de9c8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -251,6 +251,7 @@ i915-y += \
display/intel_display_wa.o \
display/intel_dmc.o \
display/intel_dmc_wl.o \
+ display/intel_dmc_wl_debugfs.o \
display/intel_dpio_phy.o \
display/intel_dpll.o \
display/intel_dpll_mgr.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f1d76484025a..b032535f4830 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -26,6 +26,7 @@
#include "intel_display_power_well.h"
#include "intel_display_types.h"
#include "intel_dmc.h"
+#include "intel_dmc_wl_debugfs.h"
#include "intel_dp.h"
#include "intel_dp_link_training.h"
#include "intel_dp_mst.h"
@@ -883,6 +884,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
intel_bios_debugfs_register(display);
intel_cdclk_debugfs_register(display);
+ intel_dmc_wl_debugfs_register(display);
intel_dmc_debugfs_register(display);
intel_dp_test_debugfs_register(display);
intel_fbc_debugfs_register(display);
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index 330b43a72e08..3686d4e90167 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -338,6 +338,7 @@ void intel_dmc_wl_init(struct intel_display *display)
spin_lock_init(&wl->lock);
refcount_set(&wl->refcount,
display->params.enable_dmc_wl == ENABLE_DMC_WL_ALWAYS_LOCKED ? 1 : 0);
+ intel_dmc_wl_debugfs_init(display);
}
/* Must only be called as part of enabling dynamic DC states. */
@@ -444,8 +445,10 @@ void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg)
spin_lock_irqsave(&wl->lock, flags);
if (i915_mmio_reg_valid(reg) &&
- !intel_dmc_wl_check_range(display, reg, wl->dc_state))
+ !intel_dmc_wl_check_range(display, reg, wl->dc_state)) {
+ intel_dmc_wl_debugfs_log_untracked(display, i915_mmio_reg_offset(reg));
goto out_unlock;
+ }
if (!wl->enabled) {
if (!refcount_inc_not_zero(&wl->refcount))
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.h b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
index 5488fbdf29b8..d11b0ab50b3c 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
@@ -11,6 +11,7 @@
#include <linux/refcount.h>
#include "i915_reg_defs.h"
+#include "intel_dmc_wl_debugfs.h"
struct intel_display;
@@ -27,6 +28,7 @@ struct intel_dmc_wl {
*/
u32 dc_state;
struct delayed_work work;
+ struct intel_dmc_wl_dbg dbg;
};
void intel_dmc_wl_init(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
new file mode 100644
index 000000000000..41e59d775fe5
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2025 Intel Corporation
+ */
+
+#include <linux/debugfs.h>
+
+#include <drm/drm_device.h>
+#include <drm/drm_managed.h>
+#include <drm/drm_print.h>
+
+#include "intel_display_core.h"
+#include "intel_dmc_wl_debugfs.h"
+
+#define DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX 65536
+
+/*
+ * DOC: DMC wakelock debugfs
+ *
+ * The DMC wakelock code needs to keep track of register offsets that need the
+ * wakelock for proper access. If one of the necessary offsets are missed, then
+ * the failure in asserting the wakelock is very likely to cause problems down
+ * the road.
+ *
+ * A miss could happen for at least two different reasons:
+ *
+ * - We might have forgotten to add the offset (or range) to the relevant
+ * tables tracked by the driver in the first place.
+ *
+ * - Or updates to either the DMC firmware or the display IP that require new
+ * offsets to be tracked and we fail to realize that.
+ *
+ * To help capture these cases, we provide the intel_dmc_wl/ debugfs directory,
+ * which exports a buffer of untracked register offsets.
+ *
+ * Untracked offsets
+ * -----------------
+ *
+ * This is a buffer that records every register offset that went through the
+ * DMC wakelock check and was deemed not needing the wakelock for MMIO access.
+ *
+ * To activate the logging of offsets into such a buffer, one can do::
+ *
+ * # echo -1 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
+ *
+ * This will create a buffer with the maximum number of entries allowed
+ * (DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX). A positive value can be used instead to
+ * define a different size:
+ *
+ * # echo 1024 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
+ *
+ * Every write to untracked_size will cause the buffer to be reset.
+ *
+ * It is also possible to read untracked_size in order to get the current
+ * value.
+ *
+ * After enabled, the buffer starts getting filled with offsets as MMIOs are
+ * performed by the driver.
+ *
+ * In order to view the content of the buffer, one can do::
+ *
+ * # cat /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked
+ * 0x000c4000
+ * 0x0016fe50
+ * 0x000c7200
+ * 0x000c7204
+ * 0x00045230
+ * 0x00046440
+ * 0x00045234
+ * 0x0016fa48
+ * 0x0016fa40
+ * 0x0016fa5c
+ * (...)
+ *
+ * The order of those offsets does not reflect the order the checks were done
+ * (some recently seen offsets are skipped to save space).
+ *
+ * Once done with it, the logging can be disabled with::
+ *
+ * # echo 0 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
+ */
+
+static int untracked_size_get(void *data, u64 *val)
+{
+ struct intel_display *display = data;
+ struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dbg->lock, flags);
+ *val = dbg->untracked.size;
+ spin_unlock_irqrestore(&dbg->lock, flags);
+
+ return 0;
+}
+
+static int untracked_size_set(void *data, u64 val)
+{
+ struct intel_display *display = data;
+ struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
+ s64 new_size;
+ u32 *old_offsets;
+ u32 *new_offsets;
+ unsigned long flags;
+
+ new_size = (s64)val;
+
+ if (new_size == -1) {
+ new_size = DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX;
+ } else if (new_size < 0) {
+ drm_err(display->drm,
+ "%lld is invalid for untracked_size, the only negative value allowed is -1\n",
+ new_size);
+ return -EINVAL;
+ } else if (new_size > DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX) {
+ drm_err(display->drm,
+ "%lld too big for untracked_size, maximum allowed value is %d\n",
+ new_size,
+ DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX);
+ return -EINVAL;
+ }
+
+ if (new_size == 0) {
+ new_offsets = NULL;
+ } else {
+ new_offsets = drmm_kmalloc_array(display->drm, new_size, sizeof(*new_offsets),
+ GFP_KERNEL);
+
+ if (!new_offsets)
+ return -ENOMEM;
+ }
+
+ spin_lock_irqsave(&dbg->lock, flags);
+ old_offsets = dbg->untracked.offsets;
+ dbg->untracked.offsets = new_offsets;
+ dbg->untracked.size = new_size;
+ dbg->untracked.head = 0;
+ dbg->untracked.len = 0;
+ dbg->untracked.overflow = false;
+ spin_unlock_irqrestore(&dbg->lock, flags);
+
+ if (old_offsets)
+ drmm_kfree(display->drm, old_offsets);
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE_SIGNED(untracked_size_fops,
+ untracked_size_get,
+ untracked_size_set,
+ "%lld\n");
+
+static int untracked_show(struct seq_file *m, void *data)
+{
+ struct intel_display *display = m->private;
+ struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
+ unsigned long flags;
+ size_t remaining;
+ size_t i;
+
+ spin_lock_irqsave(&dbg->lock, flags);
+
+ remaining = dbg->untracked.len;
+ i = dbg->untracked.head;
+
+ while (remaining--) {
+ if (i == 0)
+ i = dbg->untracked.size;
+
+ seq_printf(m, "0x%08x\n", dbg->untracked.offsets[--i]);
+ }
+
+ spin_unlock_irqrestore(&dbg->lock, flags);
+
+ return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(untracked);
+
+void intel_dmc_wl_debugfs_init(struct intel_display *display)
+{
+ struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
+
+ spin_lock_init(&dbg->lock);
+}
+
+void intel_dmc_wl_debugfs_register(struct intel_display *display)
+{
+ struct dentry *dir;
+
+ if (!HAS_DMC_WAKELOCK(display))
+ return;
+
+ dir = debugfs_create_dir("intel_dmc_wl", display->drm->debugfs_root);
+ if (IS_ERR(dir))
+ return;
+
+ debugfs_create_file("untracked_size", 0644, dir, display,
+ &untracked_size_fops);
+ debugfs_create_file("untracked", 0644, dir, display,
+ &untracked_fops);
+}
+
+static bool untracked_has_recent_offset(struct intel_display *display, u32 offset)
+{
+ struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
+ int look_back = 32;
+ size_t i;
+
+ if (look_back > dbg->untracked.len)
+ look_back = dbg->untracked.len;
+
+ i = dbg->untracked.head;
+
+ while (look_back--) {
+ if (i == 0)
+ i = dbg->untracked.size;
+
+ if (dbg->untracked.offsets[--i] == offset)
+ return true;
+ }
+
+ return false;
+}
+
+void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset)
+{
+ struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dbg->lock, flags);
+
+ if (!dbg->untracked.size)
+ goto out_unlock;
+
+ /* Save some space by not repeating recent offsets. */
+ if (untracked_has_recent_offset(display, offset))
+ goto out_unlock;
+
+ dbg->untracked.offsets[dbg->untracked.head] = offset;
+ dbg->untracked.head = (dbg->untracked.head + 1) % dbg->untracked.size;
+ if (dbg->untracked.len < dbg->untracked.size)
+ dbg->untracked.len++;
+
+ if (dbg->untracked.len == dbg->untracked.size && !dbg->untracked.overflow) {
+ dbg->untracked.overflow = true;
+ drm_warn(display->drm, "Overflow detected in DMC wakelock debugfs untracked offsets\n");
+ }
+
+out_unlock:
+ spin_unlock_irqrestore(&dbg->lock, flags);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
new file mode 100644
index 000000000000..9437c324966f
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright (C) 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_DMC_WL_DEBUGFS_H__
+#define __INTEL_DMC_WL_DEBUGFS_H__
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+
+struct intel_display;
+
+struct intel_dmc_wl_dbg {
+ spinlock_t lock; /* protects everything below */
+ struct {
+ u32 *offsets;
+ size_t head;
+ size_t len;
+ size_t size;
+ bool overflow;
+ } untracked;
+};
+
+void intel_dmc_wl_debugfs_init(struct intel_display *display);
+void intel_dmc_wl_debugfs_register(struct intel_display *display);
+void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset);
+
+#endif /* __INTEL_DMC_WL_DEBUGFS_H__ */
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 81f63258a7e1..f03fbdbcb1a4 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -221,6 +221,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
i915-display/intel_display_wa.o \
i915-display/intel_dkl_phy.o \
i915-display/intel_dmc.o \
+ i915-display/intel_dmc_wl_debugfs.o \
i915-display/intel_dp.o \
i915-display/intel_dp_aux.o \
i915-display/intel_dp_aux_backlight.o \
--
2.48.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 3/4] drm/i915/dmc_wl: Add extra_ranges debugfs
2025-01-17 22:06 [PATCH 0/4] drm/i915/dmc_wl: Introduce debugfs interface Gustavo Sousa
2025-01-17 22:06 ` [PATCH 1/4] drm/i915/dmc_wl: Pass offset instead of reg to range table iterator Gustavo Sousa
2025-01-17 22:06 ` [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets Gustavo Sousa
@ 2025-01-17 22:06 ` Gustavo Sousa
2025-01-22 10:19 ` Luca Coelho
2025-01-30 8:30 ` Vivekanandan, Balasubramani
2025-01-17 22:06 ` [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1 Gustavo Sousa
` (4 subsequent siblings)
7 siblings, 2 replies; 35+ messages in thread
From: Gustavo Sousa @ 2025-01-17 22:06 UTC (permalink / raw)
To: intel-gfx, intel-xe
We already have a way of finding the set of untracked offsets for which
there has been one or more MMIO operations via the
"intel_dmc_wl/untracked" debugfs interface.
However, in order to try adding one or more of those registers to the
set of tracked offsets, one would need to manually change the source
code and re-compile the driver.
To make debugging easier, also add a "intel_dmc_wl/extra_ranges" debugfs
interface so that extra offsets to be tracked can be defined during
runtime, removing the need of re-compilation or even module reloading.
With "intel_dmc_wl/untracked" and "intel_dmc_wl/extra_ranges", one could
even come up with a search algorithm to find missing offsets when
debugging a failing test case in a similar fashion to git-bisect. Such
an algorithm is subject for a future tool, probably implemented in
another repository (e.g. IGT).
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 7 +
.../drm/i915/display/intel_dmc_wl_debugfs.c | 254 +++++++++++++++++-
.../drm/i915/display/intel_dmc_wl_debugfs.h | 7 +
3 files changed, 267 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index 3686d4e90167..c9740250be73 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -276,6 +276,13 @@ static bool intel_dmc_wl_check_range(struct intel_display *display,
if (ranges && intel_dmc_wl_offset_in_ranges(offset, ranges))
return true;
+ /*
+ * Call to check extra ranges from debugfs only as last resort to avoid
+ * taking intel_dmc_wl_dbg's spinlock.
+ */
+ if (intel_dmc_wl_debugfs_offset_in_extra_ranges(display, offset))
+ return true;
+
return false;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
index 41e59d775fe5..1493d296ac98 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
@@ -3,6 +3,8 @@
* Copyright (C) 2025 Intel Corporation
*/
+#include <linux/kstrtox.h>
+#include <linux/ctype.h>
#include <linux/debugfs.h>
#include <drm/drm_device.h>
@@ -13,6 +15,7 @@
#include "intel_dmc_wl_debugfs.h"
#define DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX 65536
+#define DEBUGFS_EXTRA_RANGES_MAX 255
/*
* DOC: DMC wakelock debugfs
@@ -31,7 +34,8 @@
* offsets to be tracked and we fail to realize that.
*
* To help capture these cases, we provide the intel_dmc_wl/ debugfs directory,
- * which exports a buffer of untracked register offsets.
+ * which exports a buffer of untracked register offsets and also allows extra
+ * register offsets to be tracked by the driver.
*
* Untracked offsets
* -----------------
@@ -78,6 +82,43 @@
* Once done with it, the logging can be disabled with::
*
* # echo 0 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
+ *
+ * Tracking extra ranges
+ * ---------------------
+ *
+ * After looking at a list of untracked offsets via intel_dmc_wl/untracked, it
+ * is likely that one would want to check whether tracking a suspicious
+ * set of register offsets (i.e. asserting the DMC wakelock for them) would
+ * solve a bug.
+ *
+ * Instead of adding the offsets manually in the source code (which would
+ * require re-compiling and reloading the module) the intel_dmc_wl/extra_ranges
+ * debugfs interface allow defining extra ranges during runtime, which can
+ * significantly speed up debugging time.
+ *
+ * Every write to intel_dmc_wl/untracked defines a new set of ranges to be
+ * tracked. The input format is a whitespace-separated list of ranges and each
+ * range is in the format <start_offset>..<end_offset>, with ..<end_offset>
+ * being optional. Note that <end_offset> is inclusive.
+ *
+ * Examples::
+ *
+ * # echo 0x44400..0x4440c \ # Track a single range of 4 registers
+ * > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
+ *
+ * # echo 0x44400..0x4440c 0x44410..0x4441c \ # Track 2 ranges
+ * > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
+ *
+ * # echo 0x44400 0x44410..0x4441c \ # Track a single register and 1 range
+ * > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
+ *
+ * # echo \ # Do not track extra ranges anymore
+ * > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
+ *
+ * The new set of extra ranges take effect after the write operation, meaning
+ * that the next MMIOs made by the driver for registers that match those
+ * offsets will assert the wakelock (besides the offsets already hardcoded in
+ * the driver).
*/
static int untracked_size_get(void *data, u64 *val)
@@ -176,6 +217,189 @@ static int untracked_show(struct seq_file *m, void *data)
DEFINE_SHOW_ATTRIBUTE(untracked);
+static int extra_ranges_show(struct seq_file *m, void *data)
+{
+ struct intel_display *display = m->private;
+ struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dbg->lock, flags);
+
+ if (!dbg->extra_ranges)
+ goto out_unlock;
+
+ for (int i = 0; dbg->extra_ranges[i].start; i++) {
+ if (dbg->extra_ranges[i].end)
+ seq_printf(m, "0x%08x..0x%08x\n",
+ dbg->extra_ranges[i].start,
+ dbg->extra_ranges[i].end);
+ else
+ seq_printf(m, "0x%08x\n", dbg->extra_ranges[i].start);
+ }
+
+out_unlock:
+ spin_unlock_irqrestore(&dbg->lock, flags);
+
+ return 0;
+}
+
+/*
+ * Parse *p to match the pattern <start_offset>..<end_offset> and store the
+ * offsets into *dest, if dest is not NULL.
+ *
+ * Leading whitespaces are ignored and ..<end_offset> is optional. Both offsets
+ * are expected to be expressed in hexadecimal.
+ *
+ * The pointer *p is updated to point at the next character in the string for
+ * parsing a new range.
+ *
+ * On success, 1 is returned if a valid range was found and 0 is returned if
+ * there is no range left to parse. On error, a negative error number is
+ * returned.
+ */
+static int parse_single_extra_range(struct intel_display *display,
+ char **p,
+ struct intel_dmc_wl_dbg_extra_range *dest)
+{
+ char c;
+ char *s;
+ char *range_substr;
+ int err;
+ u32 val;
+
+ while (isspace(**p))
+ ++*p;
+
+ if (**p == '\0')
+ return 0;
+
+ range_substr = *p;
+
+ /* s is the <start_offset> substr */
+ s = *p;
+ while (!isspace(**p) && **p != '.' && **p != '\0')
+ ++*p;
+ c = **p;
+ **p = '\0';
+ err = kstrtou32(s, 16, &val);
+ **p = c;
+ if (err)
+ goto out_err;
+
+ if (dest)
+ dest->start = val;
+
+ if (**p != '.') {
+ /* only the "start offset" was passed */
+ if (dest)
+ dest->end = 0;
+ return 1;
+ }
+
+ if (*(++*p) != '.') {
+ err = -EINVAL;
+ goto out_err;
+ }
+
+ /* s is the <end_offset> substr */
+ s = ++*p;
+ while (!isspace(**p) && **p != '\0')
+ ++*p;
+ c = **p;
+ **p = '\0';
+ err = kstrtou32(s, 16, &val);
+ **p = c;
+ if (err)
+ goto out_err;
+
+ if (dest)
+ dest->end = val;
+
+ return 1;
+
+out_err:
+ while (!isspace(**p) && **p != '\0')
+ ++*p;
+ c = **p;
+ **p = '\0';
+ drm_err(display->drm, "invalid DMC Wakelock extra range: %s\n", range_substr);
+ **p = c;
+
+ return err;
+}
+
+static struct intel_dmc_wl_dbg_extra_range *
+parse_extra_ranges(struct intel_display *display, char *s)
+{
+ struct intel_dmc_wl_dbg_extra_range *ranges;
+ char *p;
+ int num_ranges;
+ int err;
+
+ /* Do a first pass and validate everything. */
+ p = s;
+ num_ranges = 0;
+ while ((err = parse_single_extra_range(display, &p, NULL)) > 0) {
+ num_ranges++;
+ if (num_ranges > DEBUGFS_EXTRA_RANGES_MAX) {
+ drm_err(display->drm, "Too many DMC wakelock extra ranges, maximum is %d\n",
+ DEBUGFS_EXTRA_RANGES_MAX);
+ return ERR_PTR(-EINVAL);
+ }
+ }
+
+ if (err < 0)
+ return ERR_PTR(err);
+
+ /* Now allocate and do a second pass storing the parsed ranges. */
+ ranges = drmm_kmalloc_array(display->drm, num_ranges + 1, sizeof(*ranges), GFP_KERNEL);
+ if (!ranges)
+ return ERR_PTR(-ENOMEM);
+
+ p = s;
+ num_ranges = 0;
+ while (parse_single_extra_range(display, &p, &ranges[num_ranges]) > 0)
+ num_ranges++;
+
+ ranges[num_ranges].start = 0; /* Sentinel value. */
+
+ return ranges;
+}
+
+static ssize_t extra_ranges_write(struct file *file,
+ const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ struct seq_file *m = file->private_data;
+ struct intel_display *display = m->private;
+ struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
+ struct intel_dmc_wl_dbg_extra_range *old_extra_ranges;
+ struct intel_dmc_wl_dbg_extra_range *new_extra_ranges;
+ unsigned long flags;
+ char *kbuf;
+
+ kbuf = memdup_user_nul(ubuf, len);
+ if (IS_ERR(kbuf))
+ return PTR_ERR(kbuf);
+
+ new_extra_ranges = parse_extra_ranges(display, kbuf);
+ kfree(kbuf);
+ if (IS_ERR(new_extra_ranges))
+ return PTR_ERR(new_extra_ranges);
+
+ spin_lock_irqsave(&dbg->lock, flags);
+ old_extra_ranges = dbg->extra_ranges;
+ dbg->extra_ranges = new_extra_ranges;
+ spin_unlock_irqrestore(&dbg->lock, flags);
+
+ if (old_extra_ranges)
+ drmm_kfree(display->drm, old_extra_ranges);
+
+ return len;
+}
+
+DEFINE_SHOW_STORE_ATTRIBUTE(extra_ranges);
+
void intel_dmc_wl_debugfs_init(struct intel_display *display)
{
struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
@@ -198,6 +422,8 @@ void intel_dmc_wl_debugfs_register(struct intel_display *display)
&untracked_size_fops);
debugfs_create_file("untracked", 0644, dir, display,
&untracked_fops);
+ debugfs_create_file("extra_ranges", 0644, dir, display,
+ &extra_ranges_fops);
}
static bool untracked_has_recent_offset(struct intel_display *display, u32 offset)
@@ -249,3 +475,29 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
out_unlock:
spin_unlock_irqrestore(&dbg->lock, flags);
}
+
+bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
+{
+ struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
+ bool ret = false;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dbg->lock, flags);
+
+ if (!dbg->extra_ranges)
+ goto out_unlock;
+
+ for (int i = 0; dbg->extra_ranges[i].start; i++) {
+ u32 end = dbg->extra_ranges[i].end ?: dbg->extra_ranges[i].start;
+
+ if (dbg->extra_ranges[i].start <= offset && offset <= end) {
+ ret = true;
+ goto out_unlock;
+ }
+ }
+
+out_unlock:
+ spin_unlock_irqrestore(&dbg->lock, flags);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
index 9437c324966f..ae61217a2789 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
@@ -11,6 +11,11 @@
struct intel_display;
+struct intel_dmc_wl_dbg_extra_range {
+ u32 start;
+ u32 end;
+};
+
struct intel_dmc_wl_dbg {
spinlock_t lock; /* protects everything below */
struct {
@@ -20,10 +25,12 @@ struct intel_dmc_wl_dbg {
size_t size;
bool overflow;
} untracked;
+ struct intel_dmc_wl_dbg_extra_range *extra_ranges;
};
void intel_dmc_wl_debugfs_init(struct intel_display *display);
void intel_dmc_wl_debugfs_register(struct intel_display *display);
void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset);
+bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset);
#endif /* __INTEL_DMC_WL_DEBUGFS_H__ */
--
2.48.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1
2025-01-17 22:06 [PATCH 0/4] drm/i915/dmc_wl: Introduce debugfs interface Gustavo Sousa
` (2 preceding siblings ...)
2025-01-17 22:06 ` [PATCH 3/4] drm/i915/dmc_wl: Add extra_ranges debugfs Gustavo Sousa
@ 2025-01-17 22:06 ` Gustavo Sousa
2025-01-22 10:24 ` Luca Coelho
` (2 more replies)
2025-01-17 23:15 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc_wl: Introduce debugfs interface Patchwork
` (3 subsequent siblings)
7 siblings, 3 replies; 35+ messages in thread
From: Gustavo Sousa @ 2025-01-17 22:06 UTC (permalink / raw)
To: intel-gfx, intel-xe
We use a spinlock to protect DMC wakelock debugfs data, since it is also
accessed by the core DMC wakelock logic. Taking the spinlock when the
debugfs is not in use introduces a small but unnecessary penalty.
Since the debugfs functionality is only expected to be used for, uh,
debugging sessions, let's protect it behind a module parameter
enable_dmc_wl_debugfs. That way, we only take the lock if the feature
was enabled in the first place.
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
.../gpu/drm/i915/display/intel_display_params.c | 5 +++++
.../gpu/drm/i915/display/intel_display_params.h | 1 +
.../gpu/drm/i915/display/intel_dmc_wl_debugfs.c | 16 +++++++++++++++-
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
index c4f1ab43fc0c..bc36d1b0ef87 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -133,6 +133,11 @@ intel_display_param_named_unsafe(enable_dmc_wl, int, 0400,
"(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register, 3=always locked) "
"Default: -1");
+intel_display_param_named_unsafe(enable_dmc_wl_debugfs, bool, 0400,
+ "Enable DMC wakelock debugfs"
+ "(0=disabled, 1=enabled) "
+ "Default: 0");
+
__maybe_unused
static void _param_print_bool(struct drm_printer *p, const char *driver_name,
const char *name, bool val)
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
index 5317138e6044..cb7dc1bc6846 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -48,6 +48,7 @@ struct drm_printer;
param(bool, psr_safest_params, false, 0400) \
param(bool, enable_psr2_sel_fetch, true, 0400) \
param(int, enable_dmc_wl, -1, 0400) \
+ param(bool, enable_dmc_wl_debugfs, false, 0400) \
#define MEMBER(T, member, ...) T member;
struct intel_display_params {
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
index 1493d296ac98..f4e4c7a5a730 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
@@ -37,6 +37,9 @@
* which exports a buffer of untracked register offsets and also allows extra
* register offsets to be tracked by the driver.
*
+ * The debugfs directory is only exported if the module parameter
+ * enable_dmc_wl_debugfs=1 is passed.
+ *
* Untracked offsets
* -----------------
*
@@ -411,6 +414,9 @@ void intel_dmc_wl_debugfs_register(struct intel_display *display)
{
struct dentry *dir;
+ if (!display->params.enable_dmc_wl_debugfs)
+ return;
+
if (!HAS_DMC_WAKELOCK(display))
return;
@@ -453,6 +459,9 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
unsigned long flags;
+ if (!display->params.enable_dmc_wl_debugfs)
+ return;
+
spin_lock_irqsave(&dbg->lock, flags);
if (!dbg->untracked.size)
@@ -479,9 +488,14 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
{
struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
- bool ret = false;
+ bool ret;
unsigned long flags;
+ if (!display->params.enable_dmc_wl_debugfs)
+ return false;
+
+ ret = false;
+
spin_lock_irqsave(&dbg->lock, flags);
if (!dbg->extra_ranges)
--
2.48.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc_wl: Introduce debugfs interface
2025-01-17 22:06 [PATCH 0/4] drm/i915/dmc_wl: Introduce debugfs interface Gustavo Sousa
` (3 preceding siblings ...)
2025-01-17 22:06 ` [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1 Gustavo Sousa
@ 2025-01-17 23:15 ` Patchwork
2025-01-17 23:15 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2025-01-17 23:15 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dmc_wl: Introduce debugfs interface
URL : https://patchwork.freedesktop.org/series/143696/
State : warning
== Summary ==
Error: dim checkpatch failed
6c801299b19b drm/i915/dmc_wl: Pass offset instead of reg to range table iterator
86fa0b28b846 drm/i915/dmc_wl: Add debugfs for untracked offsets
-:106: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#106:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 340 lines checked
5d537d966369 drm/i915/dmc_wl: Add extra_ranges debugfs
9ffaea1e9846 drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1
-:27: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#27: FILE: drivers/gpu/drm/i915/display/intel_display_params.c:137:
+intel_display_param_named_unsafe(enable_dmc_wl_debugfs, bool, 0400,
+ "Enable DMC wakelock debugfs"
total: 0 errors, 0 warnings, 1 checks, 60 lines checked
^ permalink raw reply [flat|nested] 35+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915/dmc_wl: Introduce debugfs interface
2025-01-17 22:06 [PATCH 0/4] drm/i915/dmc_wl: Introduce debugfs interface Gustavo Sousa
` (4 preceding siblings ...)
2025-01-17 23:15 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc_wl: Introduce debugfs interface Patchwork
@ 2025-01-17 23:15 ` Patchwork
2025-01-17 23:28 ` ✓ i915.CI.BAT: success " Patchwork
2025-01-20 12:34 ` ✗ i915.CI.Full: failure " Patchwork
7 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2025-01-17 23:15 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dmc_wl: Introduce debugfs interface
URL : https://patchwork.freedesktop.org/series/143696/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 35+ messages in thread
* ✓ i915.CI.BAT: success for drm/i915/dmc_wl: Introduce debugfs interface
2025-01-17 22:06 [PATCH 0/4] drm/i915/dmc_wl: Introduce debugfs interface Gustavo Sousa
` (5 preceding siblings ...)
2025-01-17 23:15 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2025-01-17 23:28 ` Patchwork
2025-01-20 12:34 ` ✗ i915.CI.Full: failure " Patchwork
7 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2025-01-17 23:28 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4849 bytes --]
== Series Details ==
Series: drm/i915/dmc_wl: Introduce debugfs interface
URL : https://patchwork.freedesktop.org/series/143696/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15979 -> Patchwork_143696v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/index.html
Participating hosts (44 -> 42)
------------------------------
Missing (2): bat-apl-1 fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_143696v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- bat-adls-6: [PASS][1] -> [FAIL][2] ([i915#13401])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/bat-adls-6/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/bat-adls-6/igt@i915_pm_rpm@module-reload.html
- bat-dg1-7: [PASS][3] -> [FAIL][4] ([i915#13401])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/bat-dg1-7/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/bat-dg1-7/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@workarounds:
- bat-mtlp-6: [PASS][5] -> [DMESG-FAIL][6] ([i915#12061]) +1 other test dmesg-fail
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: [PASS][7] -> [SKIP][8] ([i915#9197]) +3 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
#### Possible fixes ####
* igt@i915_selftest@live:
- bat-arlh-3: [INCOMPLETE][9] ([i915#12061] / [i915#12445]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/bat-arlh-3/igt@i915_selftest@live.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/bat-arlh-3/igt@i915_selftest@live.html
- bat-jsl-3: [INCOMPLETE][11] ([i915#12445] / [i915#13241]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/bat-jsl-3/igt@i915_selftest@live.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/bat-jsl-3/igt@i915_selftest@live.html
* igt@i915_selftest@live@gem_contexts:
- bat-arlh-3: [INCOMPLETE][13] -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/bat-arlh-3/igt@i915_selftest@live@gem_contexts.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/bat-arlh-3/igt@i915_selftest@live@gem_contexts.html
- bat-jsl-3: [INCOMPLETE][15] ([i915#13241]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/bat-jsl-3/igt@i915_selftest@live@gem_contexts.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/bat-jsl-3/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@workarounds:
- bat-arlh-3: [DMESG-FAIL][17] ([i915#12061]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/bat-arlh-3/igt@i915_selftest@live@workarounds.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/bat-arlh-3/igt@i915_selftest@live@workarounds.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12445]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12445
[i915#13241]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13241
[i915#13401]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13401
[i915#13494]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13494
[i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197
Build changes
-------------
* Linux: CI_DRM_15979 -> Patchwork_143696v1
CI-20190529: 20190529
CI_DRM_15979: 4fc988de9f5e17d19edb5fc0a0fbc15a8fc837f4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8198: 1d1ae626601119d249b530547b9e226c6a684144 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_143696v1: 4fc988de9f5e17d19edb5fc0a0fbc15a8fc837f4 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/index.html
[-- Attachment #2: Type: text/html, Size: 5902 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* ✗ i915.CI.Full: failure for drm/i915/dmc_wl: Introduce debugfs interface
2025-01-17 22:06 [PATCH 0/4] drm/i915/dmc_wl: Introduce debugfs interface Gustavo Sousa
` (6 preceding siblings ...)
2025-01-17 23:28 ` ✓ i915.CI.BAT: success " Patchwork
@ 2025-01-20 12:34 ` Patchwork
7 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2025-01-20 12:34 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 100271 bytes --]
== Series Details ==
Series: drm/i915/dmc_wl: Introduce debugfs interface
URL : https://patchwork.freedesktop.org/series/143696/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15979_full -> Patchwork_143696v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_143696v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_143696v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_143696v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@core_getversion@all-cards:
- shard-tglu: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-tglu-5/igt@core_getversion@all-cards.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@core_getversion@all-cards.html
* igt@gem_lmem_swapping@parallel-random-verify@lmem0:
- shard-dg2: [PASS][3] -> [ABORT][4] +1 other test abort
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-dg2-1/igt@gem_lmem_swapping@parallel-random-verify@lmem0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-10/igt@gem_lmem_swapping@parallel-random-verify@lmem0.html
* igt@gem_tiled_swapping@non-threaded:
- shard-tglu-1: NOTRUN -> [FAIL][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@gem_tiled_swapping@non-threaded.html
* igt@gen9_exec_parse@bb-large:
- shard-glk: [PASS][6] -> [ABORT][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-glk4/igt@gen9_exec_parse@bb-large.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-glk9/igt@gen9_exec_parse@bb-large.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-glk: [PASS][8] -> [DMESG-WARN][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-glk2/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-glk9/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
#### Warnings ####
* igt@kms_prime@d3hot:
- shard-tglu: [SKIP][10] ([i915#6524]) -> [ABORT][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-tglu-8/igt@kms_prime@d3hot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-6/igt@kms_prime@d3hot.html
Known issues
------------
Here are the changes found in Patchwork_143696v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-dg2: NOTRUN -> [SKIP][12] ([i915#8411]) +2 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@drm_fdinfo@busy@vcs1:
- shard-dg1: NOTRUN -> [SKIP][13] ([i915#8414]) +6 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-17/igt@drm_fdinfo@busy@vcs1.html
* igt@drm_fdinfo@virtual-busy-all:
- shard-dg2: NOTRUN -> [SKIP][14] ([i915#8414]) +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-7/igt@drm_fdinfo@virtual-busy-all.html
* igt@gem_basic@multigpu-create-close:
- shard-dg2: NOTRUN -> [SKIP][15] ([i915#7697])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@gem_basic@multigpu-create-close.html
* igt@gem_ccs@block-copy-compressed:
- shard-tglu: NOTRUN -> [SKIP][16] ([i915#3555] / [i915#9323])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@block-multicopy-compressed:
- shard-dg1: NOTRUN -> [SKIP][17] ([i915#9323])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-17/igt@gem_ccs@block-multicopy-compressed.html
* igt@gem_ccs@suspend-resume:
- shard-rkl: NOTRUN -> [SKIP][18] ([i915#9323])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-2/igt@gem_ccs@suspend-resume.html
- shard-tglu: NOTRUN -> [SKIP][19] ([i915#9323])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-5/igt@gem_ccs@suspend-resume.html
* igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-smem-lmem0:
- shard-dg2: NOTRUN -> [INCOMPLETE][20] ([i915#12392] / [i915#7297])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-1/igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-smem-lmem0.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-mtlp: NOTRUN -> [SKIP][21] ([i915#7697])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_ctx_persistence@file:
- shard-snb: NOTRUN -> [SKIP][22] ([i915#1099]) +4 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-snb2/igt@gem_ctx_persistence@file.html
* igt@gem_ctx_persistence@heartbeat-close:
- shard-dg1: NOTRUN -> [SKIP][23] ([i915#8555]) +1 other test skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@gem_ctx_persistence@heartbeat-close.html
* igt@gem_ctx_persistence@heartbeat-hostile:
- shard-dg2: NOTRUN -> [SKIP][24] ([i915#8555]) +1 other test skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-7/igt@gem_ctx_persistence@heartbeat-hostile.html
* igt@gem_ctx_sseu@engines:
- shard-rkl: NOTRUN -> [SKIP][25] ([i915#280])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@gem_ctx_sseu@engines.html
- shard-dg1: NOTRUN -> [SKIP][26] ([i915#280]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@gem_ctx_sseu@engines.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-tglu: NOTRUN -> [SKIP][27] ([i915#280])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_ctx_sseu@mmap-args:
- shard-dg2: NOTRUN -> [SKIP][28] ([i915#280])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-8/igt@gem_ctx_sseu@mmap-args.html
- shard-tglu-1: NOTRUN -> [SKIP][29] ([i915#280])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_eio@reset-stress:
- shard-snb: NOTRUN -> [FAIL][30] ([i915#8898])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-snb7/igt@gem_eio@reset-stress.html
- shard-dg1: NOTRUN -> [FAIL][31] ([i915#12543] / [i915#5784])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@bonded-dual:
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#4771]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@gem_exec_balancer@bonded-dual.html
* igt@gem_exec_balancer@invalid-bonds:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#4036])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-8/igt@gem_exec_balancer@invalid-bonds.html
- shard-dg1: NOTRUN -> [SKIP][34] ([i915#4036])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@gem_exec_balancer@invalid-bonds.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-tglu: NOTRUN -> [SKIP][35] ([i915#4525])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_balancer@sliced:
- shard-dg2: NOTRUN -> [SKIP][36] ([i915#4812])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@gem_exec_balancer@sliced.html
* igt@gem_exec_capture@capture-invisible:
- shard-dg2: NOTRUN -> [SKIP][37] ([i915#6334]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-2/igt@gem_exec_capture@capture-invisible.html
* igt@gem_exec_capture@capture-recoverable:
- shard-tglu: NOTRUN -> [SKIP][38] ([i915#6344])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-7/igt@gem_exec_capture@capture-recoverable.html
* igt@gem_exec_fence@submit:
- shard-dg1: NOTRUN -> [SKIP][39] ([i915#4812])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@gem_exec_fence@submit.html
* igt@gem_exec_flush@basic-batch-kernel-default-uc:
- shard-dg2: NOTRUN -> [SKIP][40] ([i915#3539] / [i915#4852]) +2 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
* igt@gem_exec_flush@basic-uc-rw-default:
- shard-dg1: NOTRUN -> [SKIP][41] ([i915#3539] / [i915#4852]) +1 other test skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@gem_exec_flush@basic-uc-rw-default.html
* igt@gem_exec_flush@basic-uc-set-default:
- shard-dg1: NOTRUN -> [SKIP][42] ([i915#3539])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-17/igt@gem_exec_flush@basic-uc-set-default.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-dg2: NOTRUN -> [SKIP][43] ([i915#5107])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_exec_reloc@basic-cpu-wc-active:
- shard-mtlp: NOTRUN -> [SKIP][44] ([i915#3281]) +4 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@gem_exec_reloc@basic-cpu-wc-active.html
* igt@gem_exec_reloc@basic-gtt:
- shard-dg2: NOTRUN -> [SKIP][45] ([i915#3281]) +14 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-2/igt@gem_exec_reloc@basic-gtt.html
* igt@gem_exec_reloc@basic-gtt-wc-noreloc:
- shard-rkl: NOTRUN -> [SKIP][46] ([i915#3281]) +11 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html
* igt@gem_exec_reloc@basic-write-gtt-active:
- shard-dg1: NOTRUN -> [SKIP][47] ([i915#3281]) +10 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@gem_exec_reloc@basic-write-gtt-active.html
* igt@gem_exec_suspend@basic-s4-devices:
- shard-rkl: NOTRUN -> [ABORT][48] ([i915#7975] / [i915#8213]) +2 other tests abort
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-7/igt@gem_exec_suspend@basic-s4-devices.html
* igt@gem_fence_thrash@bo-write-verify-none:
- shard-dg2: NOTRUN -> [SKIP][49] ([i915#4860])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@gem_fence_thrash@bo-write-verify-none.html
* igt@gem_fenced_exec_thrash@2-spare-fences:
- shard-dg1: NOTRUN -> [SKIP][50] ([i915#4860]) +1 other test skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-17/igt@gem_fenced_exec_thrash@2-spare-fences.html
* igt@gem_lmem_swapping@massive:
- shard-tglu: NOTRUN -> [SKIP][51] ([i915#4613]) +1 other test skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@gem_lmem_swapping@massive.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][52] ([i915#4613]) +1 other test skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
- shard-dg1: NOTRUN -> [SKIP][53] ([i915#12193])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs@lmem0:
- shard-dg1: NOTRUN -> [SKIP][54] ([i915#4565])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@gem_lmem_swapping@parallel-random-verify-ccs@lmem0.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [PASS][55] -> [TIMEOUT][56] ([i915#5493]) +1 other test timeout
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-dg2-2/igt@gem_lmem_swapping@smem-oom@lmem0.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-3/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_lmem_swapping@verify-random:
- shard-rkl: NOTRUN -> [SKIP][57] ([i915#4613]) +2 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-7/igt@gem_lmem_swapping@verify-random.html
* igt@gem_media_fill@media-fill:
- shard-mtlp: NOTRUN -> [SKIP][58] ([i915#8289])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@gem_media_fill@media-fill.html
* igt@gem_mmap@pf-nonblock:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#4083]) +6 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@gem_mmap@pf-nonblock.html
* igt@gem_mmap@short-mmap:
- shard-mtlp: NOTRUN -> [SKIP][60] ([i915#4083]) +2 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@gem_mmap@short-mmap.html
* igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
- shard-mtlp: NOTRUN -> [SKIP][61] ([i915#4077])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
* igt@gem_mmap_gtt@hang:
- shard-dg2: NOTRUN -> [SKIP][62] ([i915#4077]) +19 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@gem_mmap_gtt@hang.html
* igt@gem_mmap_wc@copy:
- shard-dg1: NOTRUN -> [SKIP][63] ([i915#4083]) +3 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@gem_mmap_wc@copy.html
* igt@gem_partial_pwrite_pread@reads-uncached:
- shard-dg2: NOTRUN -> [SKIP][64] ([i915#3282]) +8 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@gem_partial_pwrite_pread@reads-uncached.html
* igt@gem_partial_pwrite_pread@write-display:
- shard-mtlp: NOTRUN -> [SKIP][65] ([i915#3282])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@gem_partial_pwrite_pread@write-display.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-rkl: NOTRUN -> [SKIP][66] ([i915#3282]) +5 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-3/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_pread@exhaustion:
- shard-dg1: NOTRUN -> [SKIP][67] ([i915#3282]) +7 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@gem_pread@exhaustion.html
- shard-snb: NOTRUN -> [WARN][68] ([i915#2658])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-snb2/igt@gem_pread@exhaustion.html
* igt@gem_pxp@create-protected-buffer:
- shard-rkl: NOTRUN -> [TIMEOUT][69] ([i915#12964])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@gem_pxp@create-protected-buffer.html
* igt@gem_pxp@create-regular-context-1:
- shard-rkl: NOTRUN -> [TIMEOUT][70] ([i915#12917] / [i915#12964])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-3/igt@gem_pxp@create-regular-context-1.html
* igt@gem_pxp@hw-rejects-pxp-buffer:
- shard-tglu: NOTRUN -> [SKIP][71] ([i915#13398]) +1 other test skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@gem_pxp@hw-rejects-pxp-buffer.html
* igt@gem_pxp@reject-modify-context-protection-off-3:
- shard-dg1: NOTRUN -> [SKIP][72] ([i915#4270]) +2 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@gem_pxp@reject-modify-context-protection-off-3.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-dg2: NOTRUN -> [SKIP][73] ([i915#4270]) +6 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][74] ([i915#8428])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#5190] / [i915#8428]) +7 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-8/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#4079]) +4 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-7/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
- shard-rkl: NOTRUN -> [SKIP][77] ([i915#8411])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-7/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-dg2: NOTRUN -> [SKIP][78] ([i915#4885])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_tiled_partial_pwrite_pread@writes-after-reads:
- shard-dg1: NOTRUN -> [SKIP][79] ([i915#4077]) +12 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@gem_tiled_partial_pwrite_pread@writes-after-reads.html
* igt@gem_tiled_pread_pwrite:
- shard-dg1: NOTRUN -> [SKIP][80] ([i915#4079]) +2 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@gem_tiled_pread_pwrite.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-rkl: NOTRUN -> [SKIP][81] ([i915#3297])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-2/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-tglu-1: NOTRUN -> [SKIP][82] ([i915#3297]) +1 other test skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-tglu: NOTRUN -> [SKIP][83] ([i915#3297]) +2 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-7/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#3297] / [i915#4880]) +1 other test skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
- shard-dg1: NOTRUN -> [SKIP][85] ([i915#3297] / [i915#4880]) +1 other test skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@readonly-unsync:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#3297]) +3 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-8/igt@gem_userptr_blits@readonly-unsync.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-dg1: NOTRUN -> [SKIP][87] ([i915#3297]) +2 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-17/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gem_vm_create@invalid-create:
- shard-snb: NOTRUN -> [SKIP][88] +338 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-snb2/igt@gem_vm_create@invalid-create.html
* igt@gen7_exec_parse@bitmasks:
- shard-dg2: NOTRUN -> [SKIP][89] +17 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-2/igt@gen7_exec_parse@bitmasks.html
* igt@gen9_exec_parse@batch-zero-length:
- shard-mtlp: NOTRUN -> [SKIP][90] ([i915#2856])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@gen9_exec_parse@batch-zero-length.html
* igt@gen9_exec_parse@bb-secure:
- shard-tglu: NOTRUN -> [SKIP][91] ([i915#2527] / [i915#2856]) +2 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@gen9_exec_parse@bb-secure.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-tglu-1: NOTRUN -> [SKIP][92] ([i915#2527] / [i915#2856]) +1 other test skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@gen9_exec_parse@bb-start-cmd.html
- shard-dg1: NOTRUN -> [SKIP][93] ([i915#2527]) +3 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@bb-start-out:
- shard-rkl: NOTRUN -> [SKIP][94] ([i915#2527]) +1 other test skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-7/igt@gen9_exec_parse@bb-start-out.html
* igt@gen9_exec_parse@unaligned-access:
- shard-dg2: NOTRUN -> [SKIP][95] ([i915#2856]) +6 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@gen9_exec_parse@unaligned-access.html
* igt@i915_fb_tiling:
- shard-dg1: NOTRUN -> [SKIP][96] ([i915#4881])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@i915_fb_tiling.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglu: [PASS][97] -> [ABORT][98] ([i915#12817] / [i915#9820])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-tglu-3/igt@i915_module_load@reload-with-fault-injection.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-6/igt@i915_module_load@reload-with-fault-injection.html
- shard-dg2: NOTRUN -> [DMESG-WARN][99] ([i915#10887] / [i915#13475])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_api@freq-reset-multiple:
- shard-tglu: NOTRUN -> [SKIP][100] ([i915#8399])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@i915_pm_freq_api@freq-reset-multiple.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-bcs0:
- shard-dg1: NOTRUN -> [FAIL][101] ([i915#3591]) +1 other test fail
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-bcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0:
- shard-dg1: NOTRUN -> [FAIL][102] ([i915#12739] / [i915#3591])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
- shard-tglu-1: NOTRUN -> [WARN][103] ([i915#2681]) +4 other tests warn
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
* igt@i915_pm_rps@thresholds-idle-park:
- shard-mtlp: NOTRUN -> [SKIP][104] ([i915#11681])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@i915_pm_rps@thresholds-idle-park.html
* igt@i915_pm_sseu@full-enable:
- shard-dg2: NOTRUN -> [SKIP][105] ([i915#4387])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@test-query-geometry-subslices:
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#5723])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@i915_query@test-query-geometry-subslices.html
- shard-dg1: NOTRUN -> [SKIP][107] ([i915#5723])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@i915_query@test-query-geometry-subslices.html
* igt@i915_selftest@live@workarounds:
- shard-mtlp: [PASS][108] -> [DMESG-FAIL][109] ([i915#12061]) +1 other test dmesg-fail
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-mtlp-7/igt@i915_selftest@live@workarounds.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-1/igt@i915_selftest@live@workarounds.html
* igt@i915_selftest@mock:
- shard-snb: NOTRUN -> [DMESG-WARN][110] ([i915#9311]) +1 other test dmesg-warn
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-snb7/igt@i915_selftest@mock.html
* igt@i915_selftest@mock@memory_region:
- shard-dg2: NOTRUN -> [DMESG-WARN][111] ([i915#9311]) +1 other test dmesg-warn
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-7/igt@i915_selftest@mock@memory_region.html
- shard-rkl: NOTRUN -> [DMESG-WARN][112] ([i915#9311]) +1 other test dmesg-warn
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-7/igt@i915_selftest@mock@memory_region.html
- shard-dg1: NOTRUN -> [DMESG-WARN][113] ([i915#9311]) +1 other test dmesg-warn
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@i915_selftest@mock@memory_region.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- shard-dg1: NOTRUN -> [SKIP][114] ([i915#4212])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@clobberred-modifier:
- shard-dg2: NOTRUN -> [SKIP][115] ([i915#4212]) +1 other test skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-2/igt@kms_addfb_basic@clobberred-modifier.html
* igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-hdmi-a-3-4-rc-ccs:
- shard-dg2: NOTRUN -> [SKIP][116] ([i915#8709]) +23 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-hdmi-a-3-4-rc-ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][117] ([i915#8709]) +3 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-3/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-4-y-rc-ccs:
- shard-dg1: NOTRUN -> [SKIP][118] ([i915#8709]) +7 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-4-y-rc-ccs.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#9531])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-dg2: NOTRUN -> [SKIP][120] ([i915#1769] / [i915#3555])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
- shard-tglu-1: NOTRUN -> [SKIP][121] ([i915#1769] / [i915#3555])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-rkl: NOTRUN -> [SKIP][122] ([i915#1769] / [i915#3555])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
- shard-dg1: NOTRUN -> [SKIP][123] ([i915#1769] / [i915#3555]) +1 other test skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][124] ([i915#5286]) +4 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-7/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-dg1: NOTRUN -> [SKIP][125] ([i915#5286])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-17/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-tglu-1: NOTRUN -> [SKIP][126] ([i915#5286]) +2 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
- shard-dg1: NOTRUN -> [SKIP][127] ([i915#4538] / [i915#5286]) +5 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-tglu: NOTRUN -> [SKIP][128] ([i915#5286]) +4 other tests skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@linear-64bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][129] ([i915#3638]) +2 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-2/igt@kms_big_fb@linear-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-dg1: NOTRUN -> [SKIP][130] ([i915#3638]) +2 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-dg2: NOTRUN -> [SKIP][131] ([i915#5190]) +3 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-2/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-rkl: [PASS][132] -> [DMESG-WARN][133] ([i915#12917] / [i915#12964])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-rkl-7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-dg2: NOTRUN -> [SKIP][134] ([i915#4538] / [i915#5190]) +16 other tests skip
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
- shard-dg1: NOTRUN -> [SKIP][135] ([i915#4538]) +7 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- shard-mtlp: NOTRUN -> [SKIP][136] +4 other tests skip
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][137] ([i915#6095]) +173 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][138] ([i915#10307] / [i915#10434] / [i915#6095]) +5 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
- shard-rkl: NOTRUN -> [SKIP][139] ([i915#12313])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#12313]) +2 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
* igt@kms_ccs@bad-rotation-90-y-tiled-ccs@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][141] ([i915#6095]) +9 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_ccs@bad-rotation-90-y-tiled-ccs@pipe-a-edp-1.html
* igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][142] ([i915#6095]) +24 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-1.html
* igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-c-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][143] ([i915#6095]) +59 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-5/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-c-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
- shard-mtlp: NOTRUN -> [SKIP][144] ([i915#12313])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][145] ([i915#6095]) +77 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-3/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][146] ([i915#6095]) +22 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-7/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#10307] / [i915#6095]) +150 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3.html
* igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][148] ([i915#12313])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
- shard-dg1: NOTRUN -> [SKIP][149] ([i915#12313]) +1 other test skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
* igt@kms_cdclk@mode-transition:
- shard-tglu-1: NOTRUN -> [SKIP][150] ([i915#3742])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][151] ([i915#7213]) +3 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-7/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html
* igt@kms_chamelium_audio@hdmi-audio:
- shard-dg2: NOTRUN -> [SKIP][152] ([i915#11151] / [i915#7828]) +14 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_chamelium_audio@hdmi-audio.html
* igt@kms_chamelium_color@ctm-0-50:
- shard-tglu-1: NOTRUN -> [SKIP][153] +35 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_chamelium_color@ctm-0-50.html
* igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
- shard-tglu-1: NOTRUN -> [SKIP][154] ([i915#11151] / [i915#7828]) +4 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium_hpd@dp-hpd:
- shard-rkl: NOTRUN -> [SKIP][155] ([i915#11151] / [i915#7828]) +6 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@kms_chamelium_hpd@dp-hpd.html
* igt@kms_chamelium_hpd@dp-hpd-after-suspend:
- shard-dg1: NOTRUN -> [SKIP][156] ([i915#11151] / [i915#7828]) +9 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-17/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
* igt@kms_chamelium_hpd@vga-hpd-without-ddc:
- shard-tglu: NOTRUN -> [SKIP][157] ([i915#11151] / [i915#7828]) +5 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-5/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html
* igt@kms_content_protection@legacy:
- shard-dg1: NOTRUN -> [SKIP][158] ([i915#7116] / [i915#9424])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic-type-0:
- shard-dg2: NOTRUN -> [SKIP][159] ([i915#9424]) +1 other test skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@srm:
- shard-dg2: NOTRUN -> [SKIP][160] ([i915#7118])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-8/igt@kms_content_protection@srm.html
- shard-tglu-1: NOTRUN -> [SKIP][161] ([i915#6944] / [i915#7116] / [i915#7118])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_content_protection@srm.html
- shard-dg1: NOTRUN -> [SKIP][162] ([i915#7116])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_content_protection@srm.html
* igt@kms_content_protection@type1:
- shard-dg2: NOTRUN -> [SKIP][163] ([i915#7118] / [i915#9424])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_content_protection@type1.html
- shard-tglu: NOTRUN -> [SKIP][164] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424]) +1 other test skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-7/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-offscreen-32x32:
- shard-tglu-1: NOTRUN -> [SKIP][165] ([i915#3555]) +5 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_cursor_crc@cursor-offscreen-32x32.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-tglu: NOTRUN -> [SKIP][166] ([i915#13049]) +1 other test skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-5/igt@kms_cursor_crc@cursor-offscreen-512x170.html
- shard-rkl: NOTRUN -> [SKIP][167] ([i915#13049])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-2/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-offscreen-64x21:
- shard-mtlp: NOTRUN -> [SKIP][168] ([i915#8814])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_cursor_crc@cursor-offscreen-64x21.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-dg2: NOTRUN -> [SKIP][169] ([i915#13049])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-random-32x10:
- shard-tglu: NOTRUN -> [SKIP][170] ([i915#3555]) +3 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@kms_cursor_crc@cursor-random-32x10.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-dg1: NOTRUN -> [SKIP][171] ([i915#13049])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-17/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-rkl: NOTRUN -> [SKIP][172] ([i915#3555]) +5 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_cursor_crc@cursor-rapid-movement-max-size:
- shard-dg2: NOTRUN -> [SKIP][173] ([i915#3555]) +9 other tests skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-mtlp: NOTRUN -> [SKIP][174] ([i915#13049])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-dg2: NOTRUN -> [SKIP][175] ([i915#13046] / [i915#5354]) +5 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-snb: [PASS][176] -> [SKIP][177] +2 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-snb7/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-snb7/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-tglu: NOTRUN -> [SKIP][178] ([i915#4103])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-rkl: NOTRUN -> [SKIP][179] ([i915#4103])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
- shard-dg1: NOTRUN -> [SKIP][180] ([i915#4103] / [i915#4213])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions:
- shard-rkl: NOTRUN -> [DMESG-WARN][181] ([i915#12964]) +6 other tests dmesg-warn
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-rkl: NOTRUN -> [SKIP][182] +17 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-7/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-mtlp: NOTRUN -> [SKIP][183] ([i915#9809])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
- shard-tglu: NOTRUN -> [SKIP][184] +59 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-5/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][185] -> [FAIL][186] ([i915#2346])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-mtlp: [PASS][187] -> [FAIL][188] ([i915#2346])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-mtlp-4/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-mtlp: NOTRUN -> [SKIP][189] ([i915#4213])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-dg2: NOTRUN -> [SKIP][190] ([i915#4103] / [i915#4213]) +1 other test skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-tglu: NOTRUN -> [SKIP][191] ([i915#1769] / [i915#3555] / [i915#3804])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][192] ([i915#3804])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dp_aux_dev:
- shard-dg2: NOTRUN -> [SKIP][193] ([i915#1257])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_dp_aux_dev.html
- shard-tglu: NOTRUN -> [SKIP][194] ([i915#1257])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-7/igt@kms_dp_aux_dev.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-dg1: NOTRUN -> [SKIP][195] ([i915#3840])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-17/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-tglu-1: NOTRUN -> [SKIP][196] ([i915#3840])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-bpc:
- shard-dg2: NOTRUN -> [SKIP][197] ([i915#3555] / [i915#3840])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-8/igt@kms_dsc@dsc-with-bpc.html
- shard-tglu-1: NOTRUN -> [SKIP][198] ([i915#3555] / [i915#3840])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_dsc@dsc-with-formats:
- shard-dg1: NOTRUN -> [SKIP][199] ([i915#3555] / [i915#3840]) +1 other test skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@kms_dsc@dsc-with-formats.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-rkl: NOTRUN -> [SKIP][200] ([i915#3555] / [i915#3840])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-2/igt@kms_dsc@dsc-with-output-formats.html
- shard-tglu: NOTRUN -> [SKIP][201] ([i915#3555] / [i915#3840])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-5/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-tglu: NOTRUN -> [SKIP][202] ([i915#3469])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-7/igt@kms_fbcon_fbt@psr-suspend.html
- shard-dg2: NOTRUN -> [SKIP][203] ([i915#3469])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@chamelium:
- shard-dg2: NOTRUN -> [SKIP][204] ([i915#4854])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-2x:
- shard-dg1: NOTRUN -> [SKIP][205] ([i915#1839])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@kms_feature_discovery@display-2x.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-dg1: NOTRUN -> [SKIP][206] ([i915#9934]) +9 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-mtlp: NOTRUN -> [SKIP][207] ([i915#8381])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-flip-vs-fences-interruptible:
- shard-rkl: NOTRUN -> [SKIP][208] ([i915#9934]) +3 other tests skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-2/igt@kms_flip@2x-flip-vs-fences-interruptible.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][209] ([i915#3637]) +1 other test skip
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset:
- shard-dg2: NOTRUN -> [SKIP][210] ([i915#9934]) +13 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html
- shard-tglu: NOTRUN -> [SKIP][211] ([i915#3637]) +3 other tests skip
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-7/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
- shard-tglu-1: NOTRUN -> [SKIP][212] ([i915#3637]) +3 other tests skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
- shard-rkl: [PASS][213] -> [FAIL][214] ([i915#11989])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-rkl-7/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a2:
- shard-rkl: NOTRUN -> [FAIL][215] ([i915#11989]) +1 other test fail
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a2.html
* igt@kms_flip@flip-vs-absolute-wf_vblank@b-edp1:
- shard-mtlp: [PASS][216] -> [FAIL][217] ([i915#11989])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-mtlp-2/igt@kms_flip@flip-vs-absolute-wf_vblank@b-edp1.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-3/igt@kms_flip@flip-vs-absolute-wf_vblank@b-edp1.html
* igt@kms_flip@flip-vs-suspend:
- shard-dg1: [PASS][218] -> [DMESG-WARN][219] ([i915#4423]) +4 other tests dmesg-warn
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-dg1-18/igt@kms_flip@flip-vs-suspend.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-17/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
- shard-tglu: NOTRUN -> [SKIP][220] ([i915#2672] / [i915#3555]) +3 other tests skip
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-rkl: NOTRUN -> [SKIP][221] ([i915#2672] / [i915#3555]) +2 other tests skip
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][222] ([i915#2672]) +2 other tests skip
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
- shard-tglu-1: NOTRUN -> [SKIP][223] ([i915#2587] / [i915#2672]) +2 other tests skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][224] ([i915#2672] / [i915#3555]) +1 other test skip
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
- shard-dg2: NOTRUN -> [SKIP][225] ([i915#2672] / [i915#3555] / [i915#5190])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][226] ([i915#2672]) +2 other tests skip
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][227] ([i915#2587] / [i915#2672]) +2 other tests skip
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][228] ([i915#2587] / [i915#2672]) +3 other tests skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
- shard-mtlp: NOTRUN -> [SKIP][229] ([i915#3555] / [i915#8813])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][230] ([i915#8810])
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
- shard-tglu-1: NOTRUN -> [SKIP][231] ([i915#2672] / [i915#3555]) +2 other tests skip
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html
- shard-dg1: NOTRUN -> [SKIP][232] ([i915#2672] / [i915#3555]) +2 other tests skip
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-rkl: [PASS][233] -> [DMESG-WARN][234] ([i915#12964]) +1 other test dmesg-warn
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][235] ([i915#8708]) +1 other test skip
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][236] ([i915#5354]) +52 other tests skip
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
- shard-rkl: NOTRUN -> [SKIP][237] ([i915#1825]) +36 other tests skip
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][238] ([i915#5439])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
- shard-tglu: NOTRUN -> [SKIP][239] ([i915#5439]) +1 other test skip
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-5/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][240] ([i915#8708]) +15 other tests skip
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-dg2: NOTRUN -> [SKIP][241] ([i915#10433] / [i915#3458]) +2 other tests skip
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
- shard-dg1: NOTRUN -> [SKIP][242] +53 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][243] ([i915#8708]) +30 other tests skip
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt:
- shard-mtlp: NOTRUN -> [SKIP][244] ([i915#1825]) +3 other tests skip
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-dg2: NOTRUN -> [SKIP][245] ([i915#10055]) +1 other test skip
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-dg2: NOTRUN -> [SKIP][246] ([i915#9766])
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-dg1: NOTRUN -> [SKIP][247] ([i915#3458]) +19 other tests skip
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
- shard-rkl: NOTRUN -> [SKIP][248] ([i915#3023]) +14 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
- shard-dg2: NOTRUN -> [SKIP][249] ([i915#3458]) +24 other tests skip
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
* igt@kms_hdr@bpc-switch:
- shard-tglu-1: NOTRUN -> [SKIP][250] ([i915#3555] / [i915#8228]) +1 other test skip
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_hdr@bpc-switch.html
- shard-dg1: NOTRUN -> [SKIP][251] ([i915#3555] / [i915#8228]) +1 other test skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-dg2: NOTRUN -> [SKIP][252] ([i915#3555] / [i915#8228]) +1 other test skip
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-2/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_hdr@static-toggle:
- shard-rkl: NOTRUN -> [SKIP][253] ([i915#3555] / [i915#8228])
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-3/igt@kms_hdr@static-toggle.html
* igt@kms_hdr@static-toggle-suspend:
- shard-dg2: [PASS][254] -> [SKIP][255] ([i915#3555] / [i915#8228]) +1 other test skip
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-dg2-10/igt@kms_hdr@static-toggle-suspend.html
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-8/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-dg2: NOTRUN -> [SKIP][256] ([i915#12388])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-8/igt@kms_joiner@basic-force-big-joiner.html
- shard-tglu-1: NOTRUN -> [SKIP][257] ([i915#12388])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_joiner@basic-force-big-joiner.html
- shard-dg1: NOTRUN -> [SKIP][258] ([i915#12388])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_joiner@basic-ultra-joiner:
- shard-dg2: NOTRUN -> [SKIP][259] ([i915#12339])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-2/igt@kms_joiner@basic-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-rkl: NOTRUN -> [SKIP][260] ([i915#12388])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-2/igt@kms_joiner@invalid-modeset-force-big-joiner.html
- shard-tglu: NOTRUN -> [SKIP][261] ([i915#12388])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-5/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-dg2: NOTRUN -> [SKIP][262] ([i915#10656] / [i915#13522])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-mtlp: NOTRUN -> [SKIP][263] ([i915#12339])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_panel_fitting@legacy:
- shard-rkl: NOTRUN -> [SKIP][264] ([i915#6301])
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@kms_panel_fitting@legacy.html
- shard-dg1: NOTRUN -> [SKIP][265] ([i915#6301])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_lowres@tiling-yf:
- shard-dg2: NOTRUN -> [SKIP][266] ([i915#3555] / [i915#8821])
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-2/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@2x-scaler-multi-pipe:
- shard-dg2: NOTRUN -> [SKIP][267] ([i915#13046] / [i915#5354] / [i915#9423])
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2: NOTRUN -> [SKIP][268] ([i915#6953] / [i915#9423])
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers:
- shard-dg2: NOTRUN -> [SKIP][269] ([i915#12247] / [i915#9423])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-7/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-c:
- shard-tglu: NOTRUN -> [SKIP][270] ([i915#12247]) +9 other tests skip
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-5/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-c.html
* igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a:
- shard-rkl: NOTRUN -> [SKIP][271] ([i915#12247]) +10 other tests skip
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-2/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html
* igt@kms_plane_scaling@plane-upscale-factor-0-25-with-pixel-format:
- shard-rkl: [PASS][272] -> [DMESG-WARN][273] ([i915#12964] / [i915#1982])
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-rkl-5/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-pixel-format.html
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-1/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-pixel-format.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25:
- shard-dg2: NOTRUN -> [SKIP][274] ([i915#12247] / [i915#6953] / [i915#9423])
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_plane_scaling@planes-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d:
- shard-dg2: NOTRUN -> [SKIP][275] ([i915#12247]) +7 other tests skip
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
- shard-dg1: NOTRUN -> [SKIP][276] ([i915#12247] / [i915#3555])
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
- shard-rkl: NOTRUN -> [SKIP][277] ([i915#12247] / [i915#3555])
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
- shard-dg1: NOTRUN -> [SKIP][278] ([i915#12247] / [i915#6953])
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-17/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b:
- shard-dg1: NOTRUN -> [SKIP][279] ([i915#12247]) +17 other tests skip
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-17/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b.html
* igt@kms_pm_backlight@bad-brightness:
- shard-rkl: NOTRUN -> [SKIP][280] ([i915#5354])
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-7/igt@kms_pm_backlight@bad-brightness.html
- shard-dg1: NOTRUN -> [SKIP][281] ([i915#5354])
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_backlight@basic-brightness:
- shard-tglu: NOTRUN -> [SKIP][282] ([i915#9812])
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-7/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-dg2: NOTRUN -> [SKIP][283] ([i915#9685])
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-2/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc5-retention-flops:
- shard-dg2: NOTRUN -> [SKIP][284] ([i915#3828])
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_pm_dc@dc5-retention-flops.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: NOTRUN -> [FAIL][285] ([i915#9295])
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@kms_pm_dc@dc6-dpms.html
- shard-dg1: NOTRUN -> [SKIP][286] ([i915#3361])
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-tglu: NOTRUN -> [SKIP][287] ([i915#9685])
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-dg2: [PASS][288] -> [SKIP][289] ([i915#9340])
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-dg2-4/igt@kms_pm_lpsp@kms-lpsp.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-7/igt@kms_pm_lpsp@kms-lpsp.html
- shard-tglu-1: NOTRUN -> [SKIP][290] ([i915#3828])
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: [PASS][291] -> [SKIP][292] ([i915#9519]) +1 other test skip
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-rkl-6/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-2/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg1: NOTRUN -> [SKIP][293] ([i915#9519]) +1 other test skip
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-rkl: NOTRUN -> [SKIP][294] ([i915#9519])
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg2: NOTRUN -> [SKIP][295] ([i915#9519])
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_prime@basic-crc-hybrid:
- shard-dg1: NOTRUN -> [SKIP][296] ([i915#6524])
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_prime@basic-crc-vgem:
- shard-dg2: NOTRUN -> [SKIP][297] ([i915#6524] / [i915#6805])
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_prime@basic-crc-vgem.html
* igt@kms_prime@d3hot:
- shard-rkl: NOTRUN -> [SKIP][298] ([i915#6524]) +1 other test skip
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-3/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf:
- shard-tglu: NOTRUN -> [SKIP][299] ([i915#11520]) +6 other tests skip
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
- shard-snb: NOTRUN -> [SKIP][300] ([i915#11520]) +7 other tests skip
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-snb2/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area:
- shard-mtlp: NOTRUN -> [SKIP][301] ([i915#12316])
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
- shard-dg1: NOTRUN -> [SKIP][302] ([i915#11520]) +8 other tests skip
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area:
- shard-rkl: NOTRUN -> [SKIP][303] ([i915#11520]) +5 other tests skip
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-3/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
- shard-tglu-1: NOTRUN -> [SKIP][304] ([i915#11520]) +3 other tests skip
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf:
- shard-dg2: NOTRUN -> [SKIP][305] ([i915#11520]) +11 other tests skip
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-rkl: NOTRUN -> [SKIP][306] ([i915#9683])
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-7/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-p010:
- shard-dg2: NOTRUN -> [SKIP][307] ([i915#9683]) +1 other test skip
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-8/igt@kms_psr2_su@page_flip-p010.html
- shard-tglu-1: NOTRUN -> [SKIP][308] ([i915#9683])
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_psr2_su@page_flip-p010.html
- shard-dg1: NOTRUN -> [SKIP][309] ([i915#9683]) +1 other test skip
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@fbc-pr-cursor-plane-onoff:
- shard-dg1: NOTRUN -> [SKIP][310] ([i915#1072] / [i915#4423] / [i915#9732])
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_psr@fbc-pr-cursor-plane-onoff.html
* igt@kms_psr@fbc-psr-cursor-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][311] ([i915#1072] / [i915#9732]) +31 other tests skip
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_psr@fbc-psr-cursor-mmap-cpu.html
* igt@kms_psr@fbc-psr2-cursor-mmap-cpu:
- shard-tglu: NOTRUN -> [SKIP][312] ([i915#9732]) +15 other tests skip
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@kms_psr@fbc-psr2-cursor-mmap-cpu.html
* igt@kms_psr@fbc-psr2-primary-blt@edp-1:
- shard-mtlp: NOTRUN -> [SKIP][313] ([i915#9688]) +1 other test skip
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_psr@fbc-psr2-primary-blt@edp-1.html
* igt@kms_psr@psr2-cursor-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][314] ([i915#1072] / [i915#9732]) +15 other tests skip
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@kms_psr@psr2-cursor-mmap-gtt.html
* igt@kms_psr@psr2-sprite-mmap-gtt:
- shard-tglu-1: NOTRUN -> [SKIP][315] ([i915#9732]) +9 other tests skip
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@kms_psr@psr2-sprite-mmap-gtt.html
- shard-dg1: NOTRUN -> [SKIP][316] ([i915#1072] / [i915#9732]) +24 other tests skip
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_psr@psr2-sprite-mmap-gtt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-rkl: NOTRUN -> [SKIP][317] ([i915#9685])
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-3/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
- shard-dg2: NOTRUN -> [SKIP][318] ([i915#12755] / [i915#5190]) +1 other test skip
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-8/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-dg1: NOTRUN -> [SKIP][319] ([i915#5289])
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
- shard-dg2: NOTRUN -> [SKIP][320] ([i915#12755]) +3 other tests skip
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
* igt@kms_scaling_modes@scaling-mode-center:
- shard-dg1: NOTRUN -> [SKIP][321] ([i915#3555]) +10 other tests skip
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_scaling_modes@scaling-mode-center.html
* igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free:
- shard-dg2: NOTRUN -> [ABORT][322] ([i915#13179]) +1 other test abort
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free.html
* igt@kms_vrr@flip-basic-fastset:
- shard-dg1: NOTRUN -> [SKIP][323] ([i915#9906])
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-17/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@max-min:
- shard-mtlp: NOTRUN -> [SKIP][324] ([i915#8808] / [i915#9906])
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@kms_vrr@max-min.html
* igt@kms_vrr@negative-basic:
- shard-dg2: NOTRUN -> [SKIP][325] ([i915#3555] / [i915#9906])
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-7/igt@kms_vrr@negative-basic.html
- shard-rkl: NOTRUN -> [SKIP][326] ([i915#3555] / [i915#9906])
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-7/igt@kms_vrr@negative-basic.html
- shard-dg1: NOTRUN -> [SKIP][327] ([i915#3555] / [i915#9906])
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@kms_vrr@negative-basic.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-dg2: NOTRUN -> [SKIP][328] ([i915#9906])
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-4/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-rkl: NOTRUN -> [SKIP][329] ([i915#9906])
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-2/igt@kms_vrr@seamless-rr-switch-vrr.html
- shard-tglu: NOTRUN -> [SKIP][330] ([i915#9906])
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-5/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@kms_writeback@writeback-fb-id:
- shard-tglu: NOTRUN -> [SKIP][331] ([i915#2437])
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-tglu: NOTRUN -> [SKIP][332] ([i915#2437] / [i915#9412])
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-7/igt@kms_writeback@writeback-pixel-formats.html
- shard-dg2: NOTRUN -> [SKIP][333] ([i915#2437] / [i915#9412])
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@blocking@0-rcs0:
- shard-rkl: [PASS][334] -> [FAIL][335] ([i915#10538]) +1 other test fail
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-rkl-4/igt@perf@blocking@0-rcs0.html
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-3/igt@perf@blocking@0-rcs0.html
* igt@perf_pmu@busy-idle@ccs0:
- shard-dg2: NOTRUN -> [FAIL][336] ([i915#4349]) +1 other test fail
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-2/igt@perf_pmu@busy-idle@ccs0.html
* igt@perf_pmu@cpu-hotplug:
- shard-dg2: NOTRUN -> [SKIP][337] ([i915#8850])
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-8/igt@perf_pmu@cpu-hotplug.html
- shard-tglu-1: NOTRUN -> [SKIP][338] ([i915#8850])
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-1/igt@perf_pmu@cpu-hotplug.html
- shard-dg1: NOTRUN -> [SKIP][339] ([i915#8850])
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@perf_pmu@cpu-hotplug.html
* igt@perf_pmu@rc6-all-gts:
- shard-dg2: NOTRUN -> [SKIP][340] ([i915#8516])
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-5/igt@perf_pmu@rc6-all-gts.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-rkl: NOTRUN -> [SKIP][341] ([i915#8516])
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-2/igt@perf_pmu@rc6@other-idle-gt0.html
- shard-tglu: NOTRUN -> [SKIP][342] ([i915#8516])
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-5/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_vgem@basic-fence-flip:
- shard-dg1: NOTRUN -> [SKIP][343] ([i915#3708]) +3 other tests skip
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- shard-dg2: NOTRUN -> [SKIP][344] ([i915#3708] / [i915#4077])
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-2/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- shard-dg2: NOTRUN -> [SKIP][345] ([i915#3291] / [i915#3708]) +1 other test skip
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-7/igt@prime_vgem@basic-fence-read.html
- shard-rkl: NOTRUN -> [SKIP][346] ([i915#3291] / [i915#3708]) +1 other test skip
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-7/igt@prime_vgem@basic-fence-read.html
* igt@sriov_basic@bind-unbind-vf@vf-4:
- shard-tglu: NOTRUN -> [FAIL][347] ([i915#12910]) +9 other tests fail
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-tglu-3/igt@sriov_basic@bind-unbind-vf@vf-4.html
* igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
- shard-dg1: NOTRUN -> [SKIP][348] ([i915#9917])
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-17/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
#### Possible fixes ####
* igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0:
- shard-dg2: [INCOMPLETE][349] ([i915#7297]) -> [PASS][350]
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-dg2-2/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-1/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
* igt@gem_eio@context-create:
- shard-mtlp: [ABORT][351] -> [PASS][352]
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-mtlp-4/igt@gem_eio@context-create.html
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-5/igt@gem_eio@context-create.html
* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][353] -> [PASS][354]
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-snb2/igt@i915_pm_rps@reset.html
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-snb5/igt@i915_pm_rps@reset.html
* igt@kms_cursor_edge_walk@128x128-top-edge@pipe-a-hdmi-a-2:
- shard-rkl: [DMESG-WARN][355] ([i915#12964]) -> [PASS][356] +1 other test pass
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-rkl-1/igt@kms_cursor_edge_walk@128x128-top-edge@pipe-a-hdmi-a-2.html
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-1/igt@kms_cursor_edge_walk@128x128-top-edge@pipe-a-hdmi-a-2.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- shard-glk: [FAIL][357] ([i915#2346]) -> [PASS][358]
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-glk8/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-glk2/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
* igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][359] ([i915#13027]) -> [PASS][360] +1 other test pass
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-snb: [FAIL][361] ([i915#11989]) -> [PASS][362] +9 other tests pass
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-snb7/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-snb1/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a2:
- shard-rkl: [FAIL][363] ([i915#11989]) -> [PASS][364] +1 other test pass
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-rkl-1/igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a2.html
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-1/igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render:
- shard-dg2: [FAIL][365] ([i915#6880]) -> [PASS][366] +1 other test pass
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
* igt@kms_hdr@static-toggle-dpms:
- shard-dg2: [SKIP][367] ([i915#3555] / [i915#8228]) -> [PASS][368]
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-dg2-7/igt@kms_hdr@static-toggle-dpms.html
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-10/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-dg2: [SKIP][369] ([i915#9519]) -> [PASS][370]
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-dg2-10/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-8/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@syncobj_timeline@multi-wait-all-available-submitted:
- shard-dg1: [DMESG-WARN][371] ([i915#4423]) -> [PASS][372]
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-dg1-13/igt@syncobj_timeline@multi-wait-all-available-submitted.html
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@syncobj_timeline@multi-wait-all-available-submitted.html
#### Warnings ####
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg1: [ABORT][373] ([i915#9820]) -> [ABORT][374] ([i915#13493] / [i915#4391] / [i915#4423] / [i915#9820])
[373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-dg1-18/igt@i915_module_load@reload-with-fault-injection.html
[374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-17/igt@i915_module_load@reload-with-fault-injection.html
- shard-mtlp: [ABORT][375] ([i915#10131] / [i915#13493]) -> [ABORT][376] ([i915#10131] / [i915#13493] / [i915#9820])
[375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-mtlp-5/igt@i915_module_load@reload-with-fault-injection.html
[376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-mtlp-6/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_selftest@mock:
- shard-glk: [DMESG-WARN][377] ([i915#9311]) -> [DMESG-WARN][378] ([i915#1982] / [i915#9311])
[377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-glk1/igt@i915_selftest@mock.html
[378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-glk6/igt@i915_selftest@mock.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-dg1: [SKIP][379] ([i915#3638]) -> [SKIP][380] ([i915#3638] / [i915#4423])
[379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-dg1-12/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
[380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-13/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_flip@2x-plain-flip:
- shard-dg1: [SKIP][381] ([i915#9934]) -> [SKIP][382] ([i915#4423] / [i915#9934])
[381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-dg1-13/igt@kms_flip@2x-plain-flip.html
[382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-14/igt@kms_flip@2x-plain-flip.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: [SKIP][383] ([i915#10433] / [i915#3458]) -> [SKIP][384] ([i915#3458]) +1 other test skip
[383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
[384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg2-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw:
- shard-dg1: [SKIP][385] ([i915#3458] / [i915#4423]) -> [SKIP][386] ([i915#3458])
[385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html
[386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: [SKIP][387] ([i915#3361]) -> [SKIP][388] ([i915#4281])
[387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-rkl-7/igt@kms_pm_dc@dc9-dpms.html
[388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-5/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: [SKIP][389] ([i915#3828]) -> [SKIP][390] ([i915#9340])
[389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-rkl-4/igt@kms_pm_lpsp@kms-lpsp.html
[390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-rkl-3/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_psr@fbc-pr-sprite-render:
- shard-dg1: [SKIP][391] ([i915#1072] / [i915#4423] / [i915#9732]) -> [SKIP][392] ([i915#1072] / [i915#9732])
[391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15979/shard-dg1-13/igt@kms_psr@fbc-pr-sprite-render.html
[392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/shard-dg1-18/igt@kms_psr@fbc-pr-sprite-render.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#160]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/160
[i915#10055]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10055
[i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10538
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10887]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10887
[i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11989
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12193
[i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
[i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
[i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
[i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
[i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
[i915#12392]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12392
[i915#12543]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12543
[i915#12549]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12549
[i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
[i915#12739]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12739
[i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
[i915#12817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12817
[i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
[i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
[i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
[i915#12967]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12967
[i915#13027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13027
[i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
[i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
[i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
[i915#13398]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13398
[i915#13475]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13475
[i915#13493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13493
[i915#13522]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13522
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: h
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_143696v1/index.html
[-- Attachment #2: Type: text/html, Size: 119644 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/4] drm/i915/dmc_wl: Pass offset instead of reg to range table iterator
2025-01-17 22:06 ` [PATCH 1/4] drm/i915/dmc_wl: Pass offset instead of reg to range table iterator Gustavo Sousa
@ 2025-01-22 8:23 ` Luca Coelho
0 siblings, 0 replies; 35+ messages in thread
From: Luca Coelho @ 2025-01-22 8:23 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On Fri, 2025-01-17 at 19:06 -0300, Gustavo Sousa wrote:
> We will add another function that checks the offset in an upcoming
> change. Instead of passing the reg variable to only extract the offset
> later, let's extract the offset before so that we do not need to repeat
> ourselves.
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets
2025-01-17 22:06 ` [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets Gustavo Sousa
@ 2025-01-22 9:06 ` Luca Coelho
2025-01-23 14:41 ` Gustavo Sousa
2025-01-23 16:11 ` Vivekanandan, Balasubramani
2025-01-27 9:47 ` Jani Nikula
2 siblings, 1 reply; 35+ messages in thread
From: Luca Coelho @ 2025-01-22 9:06 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On Fri, 2025-01-17 at 19:06 -0300, Gustavo Sousa wrote:
> The DMC wakelock code needs to keep track of register offsets that need
> the wakelock for proper access. If one of the necessary offsets are
> missed, then the failure in asserting the wakelock is very likely to
> cause problems down the road.
>
> A miss could happen for at least two different reasons:
>
> - We might have forgotten to add the offset (or range) to the relevant
> tables tracked by the driver in the first place.
>
> - Or updates to either the DMC firmware or the display IP that require
> new offsets to be tracked and we fail to realize that.
>
> To help capture these cases, let's introduce a debugfs interface for the
> DMC wakelock.
>
> In this part, we export a buffer containing offsets of registers that
> were considered not needing the wakelock by our driver. In an upcoming
> change we will also allow defining an extra set of offset ranges to be
> tracked by our driver.
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
This looks great overall!
A couple of comments below.
[...]
> +static bool untracked_has_recent_offset(struct intel_display *display, u32 offset)
> +{
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> + int look_back = 32;
> + size_t i;
> +
> + if (look_back > dbg->untracked.len)
> + look_back = dbg->untracked.len;
> +
> + i = dbg->untracked.head;
> +
> + while (look_back--) {
> + if (i == 0)
> + i = dbg->untracked.size;
If size < 32, you would check some values twice, right? Probably not a
real case scenario, and it wouldn't matter much, but it took me a bit
to wrap my head around this.
[...]
> +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset)
> +{
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&dbg->lock, flags);
> +
> + if (!dbg->untracked.size)
> + goto out_unlock;
> +
> + /* Save some space by not repeating recent offsets. */
> + if (untracked_has_recent_offset(display, offset))
> + goto out_unlock;
> +
> + dbg->untracked.offsets[dbg->untracked.head] = offset;
> + dbg->untracked.head = (dbg->untracked.head + 1) % dbg->untracked.size;
> + if (dbg->untracked.len < dbg->untracked.size)
> + dbg->untracked.len++;
> +
> + if (dbg->untracked.len == dbg->untracked.size && !dbg->untracked.overflow) {
> + dbg->untracked.overflow = true;
> + drm_warn(display->drm, "Overflow detected in DMC wakelock debugfs untracked offsets\n");
> + }
Couldn't it be useful to print overflows every time they occur? Maybe
convert overflow to a uint to track how many times it happened? (though
maybe this is a bit overkill).
[...]
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 3/4] drm/i915/dmc_wl: Add extra_ranges debugfs
2025-01-17 22:06 ` [PATCH 3/4] drm/i915/dmc_wl: Add extra_ranges debugfs Gustavo Sousa
@ 2025-01-22 10:19 ` Luca Coelho
2025-01-23 15:52 ` Gustavo Sousa
2025-01-30 8:30 ` Vivekanandan, Balasubramani
1 sibling, 1 reply; 35+ messages in thread
From: Luca Coelho @ 2025-01-22 10:19 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On Fri, 2025-01-17 at 19:06 -0300, Gustavo Sousa wrote:
> We already have a way of finding the set of untracked offsets for which
> there has been one or more MMIO operations via the
> "intel_dmc_wl/untracked" debugfs interface.
>
> However, in order to try adding one or more of those registers to the
> set of tracked offsets, one would need to manually change the source
> code and re-compile the driver.
>
> To make debugging easier, also add a "intel_dmc_wl/extra_ranges" debugfs
> interface so that extra offsets to be tracked can be defined during
> runtime, removing the need of re-compilation or even module reloading.
>
> With "intel_dmc_wl/untracked" and "intel_dmc_wl/extra_ranges", one could
> even come up with a search algorithm to find missing offsets when
> debugging a failing test case in a similar fashion to git-bisect. Such
> an algorithm is subject for a future tool, probably implemented in
> another repository (e.g. IGT).
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
Some comments below.
[...]
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> index 41e59d775fe5..1493d296ac98 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
[...]
> +bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
> +{
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> + bool ret = false;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&dbg->lock, flags);
> +
> + if (!dbg->extra_ranges)
> + goto out_unlock;
> +
> + for (int i = 0; dbg->extra_ranges[i].start; i++) {
> + u32 end = dbg->extra_ranges[i].end ?: dbg->extra_ranges[i].start;
> +
> + if (dbg->extra_ranges[i].start <= offset && offset <= end) {
> + ret = true;
> + goto out_unlock;
> + }
> + }
> +
> +out_unlock:
> + spin_unlock_irqrestore(&dbg->lock, flags);
> +
> + return ret;
> +}
This function is probably almost identical than the one used to check
the hard-coded ranges, isn't it? In that case, couldn't you just pass
the ranges array (in this case dbg->extra_ranges) to the same function?
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> index 9437c324966f..ae61217a2789 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> @@ -11,6 +11,11 @@
>
> struct intel_display;
>
> +struct intel_dmc_wl_dbg_extra_range {
> + u32 start;
> + u32 end;
> +};
> +
Why do you need another struct for this?
[...]
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1
2025-01-17 22:06 ` [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1 Gustavo Sousa
@ 2025-01-22 10:24 ` Luca Coelho
2025-01-23 16:10 ` Gustavo Sousa
2025-01-27 12:01 ` Jani Nikula
2025-01-30 8:46 ` Vivekanandan, Balasubramani
2 siblings, 1 reply; 35+ messages in thread
From: Luca Coelho @ 2025-01-22 10:24 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On Fri, 2025-01-17 at 19:06 -0300, Gustavo Sousa wrote:
> We use a spinlock to protect DMC wakelock debugfs data, since it is also
> accessed by the core DMC wakelock logic. Taking the spinlock when the
> debugfs is not in use introduces a small but unnecessary penalty.
>
> Since the debugfs functionality is only expected to be used for, uh,
> debugging sessions, let's protect it behind a module parameter
> enable_dmc_wl_debugfs. That way, we only take the lock if the feature
> was enabled in the first place.
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
Looks good. With a small optional nitpick below.
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
[...]
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
> index c4f1ab43fc0c..bc36d1b0ef87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
> @@ -479,9 +488,14 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
> bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
> {
> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> - bool ret = false;
> + bool ret;
Why not keep this as it was...
> unsigned long flags;
>
> + if (!display->params.enable_dmc_wl_debugfs)
> + return false;
> +
> + ret = false;
> +
...then you don't need to set it here, and can return ret in the if
above for consistency.
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets
2025-01-22 9:06 ` Luca Coelho
@ 2025-01-23 14:41 ` Gustavo Sousa
2025-01-30 9:33 ` Luca Coelho
0 siblings, 1 reply; 35+ messages in thread
From: Gustavo Sousa @ 2025-01-23 14:41 UTC (permalink / raw)
To: Luca Coelho, intel-gfx, intel-xe
Quoting Luca Coelho (2025-01-22 06:06:00-03:00)
>On Fri, 2025-01-17 at 19:06 -0300, Gustavo Sousa wrote:
>> The DMC wakelock code needs to keep track of register offsets that need
>> the wakelock for proper access. If one of the necessary offsets are
>> missed, then the failure in asserting the wakelock is very likely to
>> cause problems down the road.
>>
>> A miss could happen for at least two different reasons:
>>
>> - We might have forgotten to add the offset (or range) to the relevant
>> tables tracked by the driver in the first place.
>>
>> - Or updates to either the DMC firmware or the display IP that require
>> new offsets to be tracked and we fail to realize that.
>>
>> To help capture these cases, let's introduce a debugfs interface for the
>> DMC wakelock.
>>
>> In this part, we export a buffer containing offsets of registers that
>> were considered not needing the wakelock by our driver. In an upcoming
>> change we will also allow defining an extra set of offset ranges to be
>> tracked by our driver.
>>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>
>This looks great overall!
>
>A couple of comments below.
>
>
>[...]
>> +static bool untracked_has_recent_offset(struct intel_display *display, u32 offset)
>> +{
>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> + int look_back = 32;
>> + size_t i;
>> +
>> + if (look_back > dbg->untracked.len)
>> + look_back = dbg->untracked.len;
>> +
>> + i = dbg->untracked.head;
>> +
>> + while (look_back--) {
>> + if (i == 0)
>> + i = dbg->untracked.size;
>
>If size < 32, you would check some values twice, right? Probably not a
>real case scenario, and it wouldn't matter much, but it took me a bit
>to wrap my head around this.
Nope. If look_back is greater than the current number of offsets, it
will be just reset to that count (see the "if (look_back >
dbg->untracked.len)" above).
Note that the number of valid elements in the circular buffer is tracked
with untracked.len, while untracked.size is actually the capacity. Maybe
I should have used that name for the member instead?
>
>[...]
>> +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset)
>> +{
>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&dbg->lock, flags);
>> +
>> + if (!dbg->untracked.size)
>> + goto out_unlock;
>> +
>> + /* Save some space by not repeating recent offsets. */
>> + if (untracked_has_recent_offset(display, offset))
>> + goto out_unlock;
>> +
>> + dbg->untracked.offsets[dbg->untracked.head] = offset;
>> + dbg->untracked.head = (dbg->untracked.head + 1) % dbg->untracked.size;
>> + if (dbg->untracked.len < dbg->untracked.size)
>> + dbg->untracked.len++;
>> +
>> + if (dbg->untracked.len == dbg->untracked.size && !dbg->untracked.overflow) {
>> + dbg->untracked.overflow = true;
>> + drm_warn(display->drm, "Overflow detected in DMC wakelock debugfs untracked offsets\n");
>> + }
>
>Couldn't it be useful to print overflows every time they occur? Maybe
>convert overflow to a uint to track how many times it happened? (though
>maybe this is a bit overkill).
The warning is just to let the user know that the buffer doesn't have
every untracked offset that has been seen since enabling the logging.
The best thing to do in this case is to try a bigger size or try to
reduce the execution to be tracked (maybe a smaller test case).
I'm not sure how providing a count would be useful here.
--
Gustavo Sousa
>
>[...]
>
>--
>Cheers,
>Luca.
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 3/4] drm/i915/dmc_wl: Add extra_ranges debugfs
2025-01-22 10:19 ` Luca Coelho
@ 2025-01-23 15:52 ` Gustavo Sousa
2025-01-30 9:18 ` Luca Coelho
0 siblings, 1 reply; 35+ messages in thread
From: Gustavo Sousa @ 2025-01-23 15:52 UTC (permalink / raw)
To: Luca Coelho, intel-gfx, intel-xe
Quoting Luca Coelho (2025-01-22 07:19:35-03:00)
>On Fri, 2025-01-17 at 19:06 -0300, Gustavo Sousa wrote:
>> We already have a way of finding the set of untracked offsets for which
>> there has been one or more MMIO operations via the
>> "intel_dmc_wl/untracked" debugfs interface.
>>
>> However, in order to try adding one or more of those registers to the
>> set of tracked offsets, one would need to manually change the source
>> code and re-compile the driver.
>>
>> To make debugging easier, also add a "intel_dmc_wl/extra_ranges" debugfs
>> interface so that extra offsets to be tracked can be defined during
>> runtime, removing the need of re-compilation or even module reloading.
>>
>> With "intel_dmc_wl/untracked" and "intel_dmc_wl/extra_ranges", one could
>> even come up with a search algorithm to find missing offsets when
>> debugging a failing test case in a similar fashion to git-bisect. Such
>> an algorithm is subject for a future tool, probably implemented in
>> another repository (e.g. IGT).
>>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>
>Some comments below.
>
>
>[...]
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>> index 41e59d775fe5..1493d296ac98 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>
>[...]
>> +bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
>> +{
>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> + bool ret = false;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&dbg->lock, flags);
>> +
>> + if (!dbg->extra_ranges)
>> + goto out_unlock;
>> +
>> + for (int i = 0; dbg->extra_ranges[i].start; i++) {
>> + u32 end = dbg->extra_ranges[i].end ?: dbg->extra_ranges[i].start;
>> +
>> + if (dbg->extra_ranges[i].start <= offset && offset <= end) {
>> + ret = true;
>> + goto out_unlock;
>> + }
>> + }
>> +
>> +out_unlock:
>> + spin_unlock_irqrestore(&dbg->lock, flags);
>> +
>> + return ret;
>> +}
>
>This function is probably almost identical than the one used to check
>the hard-coded ranges, isn't it? In that case, couldn't you just pass
>the ranges array (in this case dbg->extra_ranges) to the same function?
Yeah. I thought about that when implementing this, but ended up going
with a separate implementation.
If you look at how the current series is done, there is a one-way
dependency between intel_dmc_wl_debugfs and intel_dmc_wl - the latter
depends on the former. I just didn't want to make this a circular
dependency, since the implementation is rather simple anyway...
Let me know if that convinced you :-)
>
>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
>> index 9437c324966f..ae61217a2789 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
>> @@ -11,6 +11,11 @@
>>
>> struct intel_display;
>>
>> +struct intel_dmc_wl_dbg_extra_range {
>> + u32 start;
>> + u32 end;
>> +};
>> +
>
>Why do you need another struct for this?
>
In the same spirit as with my answer above... I think of this much as an
implementation detail that would be better off not exposed in headers.
--
Gustavo Sousa
>[...]
>
>--
>Cheers,
>Luca.
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1
2025-01-22 10:24 ` Luca Coelho
@ 2025-01-23 16:10 ` Gustavo Sousa
2025-01-30 9:28 ` Luca Coelho
0 siblings, 1 reply; 35+ messages in thread
From: Gustavo Sousa @ 2025-01-23 16:10 UTC (permalink / raw)
To: Luca Coelho, intel-gfx, intel-xe
Quoting Luca Coelho (2025-01-22 07:24:43-03:00)
>On Fri, 2025-01-17 at 19:06 -0300, Gustavo Sousa wrote:
>> We use a spinlock to protect DMC wakelock debugfs data, since it is also
>> accessed by the core DMC wakelock logic. Taking the spinlock when the
>> debugfs is not in use introduces a small but unnecessary penalty.
>>
>> Since the debugfs functionality is only expected to be used for, uh,
>> debugging sessions, let's protect it behind a module parameter
>> enable_dmc_wl_debugfs. That way, we only take the lock if the feature
>> was enabled in the first place.
>>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>
>Looks good. With a small optional nitpick below.
>
>Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
>
>[...]
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
>> index c4f1ab43fc0c..bc36d1b0ef87 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
>> @@ -479,9 +488,14 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
>> bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
>> {
>> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> - bool ret = false;
>> + bool ret;
>
>Why not keep this as it was...
Yeah, I suppose that's fine... I think the compiler is going to optimize
it. I can send a v2 with this change.
>
>> unsigned long flags;
>>
>> + if (!display->params.enable_dmc_wl_debugfs)
>> + return false;
>> +
>> + ret = false;
>> +
>
>...then you don't need to set it here, and can return ret in the if
>above for consistency.
In the if above, I guess I prefer the "return false" because it is
explicit.
--
Gustavo Sousa
>
>--
>Cheers,
>Luca.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets
2025-01-17 22:06 ` [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets Gustavo Sousa
2025-01-22 9:06 ` Luca Coelho
@ 2025-01-23 16:11 ` Vivekanandan, Balasubramani
2025-01-23 16:41 ` Gustavo Sousa
2025-01-27 9:47 ` Jani Nikula
2 siblings, 1 reply; 35+ messages in thread
From: Vivekanandan, Balasubramani @ 2025-01-23 16:11 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On 17.01.2025 19:06, Gustavo Sousa wrote:
> The DMC wakelock code needs to keep track of register offsets that need
> the wakelock for proper access. If one of the necessary offsets are
> missed, then the failure in asserting the wakelock is very likely to
> cause problems down the road.
>
> A miss could happen for at least two different reasons:
>
> - We might have forgotten to add the offset (or range) to the relevant
> tables tracked by the driver in the first place.
>
> - Or updates to either the DMC firmware or the display IP that require
> new offsets to be tracked and we fail to realize that.
>
> To help capture these cases, let's introduce a debugfs interface for the
> DMC wakelock.
>
> In this part, we export a buffer containing offsets of registers that
> were considered not needing the wakelock by our driver. In an upcoming
> change we will also allow defining an extra set of offset ranges to be
> tracked by our driver.
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../drm/i915/display/intel_display_debugfs.c | 2 +
> drivers/gpu/drm/i915/display/intel_dmc_wl.c | 5 +-
> drivers/gpu/drm/i915/display/intel_dmc_wl.h | 2 +
> .../drm/i915/display/intel_dmc_wl_debugfs.c | 251 ++++++++++++++++++
> .../drm/i915/display/intel_dmc_wl_debugfs.h | 29 ++
> drivers/gpu/drm/xe/Makefile | 1 +
> 7 files changed, 290 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 3dda9f0eda82..ac1ab79de9c8 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -251,6 +251,7 @@ i915-y += \
> display/intel_display_wa.o \
> display/intel_dmc.o \
> display/intel_dmc_wl.o \
> + display/intel_dmc_wl_debugfs.o \
> display/intel_dpio_phy.o \
> display/intel_dpll.o \
> display/intel_dpll_mgr.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index f1d76484025a..b032535f4830 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -26,6 +26,7 @@
> #include "intel_display_power_well.h"
> #include "intel_display_types.h"
> #include "intel_dmc.h"
> +#include "intel_dmc_wl_debugfs.h"
> #include "intel_dp.h"
> #include "intel_dp_link_training.h"
> #include "intel_dp_mst.h"
> @@ -883,6 +884,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
>
> intel_bios_debugfs_register(display);
> intel_cdclk_debugfs_register(display);
> + intel_dmc_wl_debugfs_register(display);
> intel_dmc_debugfs_register(display);
> intel_dp_test_debugfs_register(display);
> intel_fbc_debugfs_register(display);
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> index 330b43a72e08..3686d4e90167 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> @@ -338,6 +338,7 @@ void intel_dmc_wl_init(struct intel_display *display)
> spin_lock_init(&wl->lock);
> refcount_set(&wl->refcount,
> display->params.enable_dmc_wl == ENABLE_DMC_WL_ALWAYS_LOCKED ? 1 : 0);
> + intel_dmc_wl_debugfs_init(display);
> }
>
> /* Must only be called as part of enabling dynamic DC states. */
> @@ -444,8 +445,10 @@ void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg)
> spin_lock_irqsave(&wl->lock, flags);
>
> if (i915_mmio_reg_valid(reg) &&
> - !intel_dmc_wl_check_range(display, reg, wl->dc_state))
> + !intel_dmc_wl_check_range(display, reg, wl->dc_state)) {
> + intel_dmc_wl_debugfs_log_untracked(display, i915_mmio_reg_offset(reg));
> goto out_unlock;
> + }
>
> if (!wl->enabled) {
> if (!refcount_inc_not_zero(&wl->refcount))
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.h b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
> index 5488fbdf29b8..d11b0ab50b3c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
> @@ -11,6 +11,7 @@
> #include <linux/refcount.h>
>
> #include "i915_reg_defs.h"
> +#include "intel_dmc_wl_debugfs.h"
>
> struct intel_display;
>
> @@ -27,6 +28,7 @@ struct intel_dmc_wl {
> */
> u32 dc_state;
> struct delayed_work work;
> + struct intel_dmc_wl_dbg dbg;
> };
>
> void intel_dmc_wl_init(struct intel_display *display);
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> new file mode 100644
> index 000000000000..41e59d775fe5
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> @@ -0,0 +1,251 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright (C) 2025 Intel Corporation
> + */
> +
> +#include <linux/debugfs.h>
> +
> +#include <drm/drm_device.h>
> +#include <drm/drm_managed.h>
> +#include <drm/drm_print.h>
> +
> +#include "intel_display_core.h"
> +#include "intel_dmc_wl_debugfs.h"
> +
> +#define DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX 65536
This macro is not actually the size but the count of offsets stored in
the buffer. This is used as the array size for drmm_kmalloc_array call.
It makes sense to rename this macro as count
> +
> +/*
> + * DOC: DMC wakelock debugfs
> + *
> + * The DMC wakelock code needs to keep track of register offsets that need the
> + * wakelock for proper access. If one of the necessary offsets are missed, then
> + * the failure in asserting the wakelock is very likely to cause problems down
> + * the road.
> + *
> + * A miss could happen for at least two different reasons:
> + *
> + * - We might have forgotten to add the offset (or range) to the relevant
> + * tables tracked by the driver in the first place.
> + *
> + * - Or updates to either the DMC firmware or the display IP that require new
> + * offsets to be tracked and we fail to realize that.
> + *
> + * To help capture these cases, we provide the intel_dmc_wl/ debugfs directory,
> + * which exports a buffer of untracked register offsets.
> + *
> + * Untracked offsets
> + * -----------------
> + *
> + * This is a buffer that records every register offset that went through the
> + * DMC wakelock check and was deemed not needing the wakelock for MMIO access.
> + *
> + * To activate the logging of offsets into such a buffer, one can do::
> + *
> + * # echo -1 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
This knob is setting the count of offsets to be stored and not the size.
I think this should be renamed to indicate it as count.
> + *
> + * This will create a buffer with the maximum number of entries allowed
> + * (DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX). A positive value can be used instead to
> + * define a different size:
> + *
> + * # echo 1024 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
For me passing negative number doesn't look intuitive. Thinking do we
really need the case of passing default buffer size. We can allow just 0
to disable and any positive number to enable with the buffer size set as
value passed.
> + *
> + * Every write to untracked_size will cause the buffer to be reset.
> + *
> + * It is also possible to read untracked_size in order to get the current
> + * value.
> + *
> + * After enabled, the buffer starts getting filled with offsets as MMIOs are
> + * performed by the driver.
> + *
> + * In order to view the content of the buffer, one can do::
> + *
> + * # cat /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked
> + * 0x000c4000
> + * 0x0016fe50
> + * 0x000c7200
> + * 0x000c7204
> + * 0x00045230
> + * 0x00046440
> + * 0x00045234
> + * 0x0016fa48
> + * 0x0016fa40
> + * 0x0016fa5c
> + * (...)
> + *
> + * The order of those offsets does not reflect the order the checks were done
> + * (some recently seen offsets are skipped to save space).
> + *
> + * Once done with it, the logging can be disabled with::
> + *
> + * # echo 0 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> + */
> +
> +static int untracked_size_get(void *data, u64 *val)
> +{
> + struct intel_display *display = data;
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&dbg->lock, flags);
> + *val = dbg->untracked.size;
> + spin_unlock_irqrestore(&dbg->lock, flags);
> +
> + return 0;
> +}
> +
> +static int untracked_size_set(void *data, u64 val)
> +{
> + struct intel_display *display = data;
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> + s64 new_size;
> + u32 *old_offsets;
> + u32 *new_offsets;
> + unsigned long flags;
> +
> + new_size = (s64)val;
> +
> + if (new_size == -1) {
> + new_size = DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX;
> + } else if (new_size < 0) {
> + drm_err(display->drm,
> + "%lld is invalid for untracked_size, the only negative value allowed is -1\n",
> + new_size);
> + return -EINVAL;
> + } else if (new_size > DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX) {
> + drm_err(display->drm,
> + "%lld too big for untracked_size, maximum allowed value is %d\n",
> + new_size,
> + DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX);
> + return -EINVAL;
> + }
> +
> + if (new_size == 0) {
> + new_offsets = NULL;
> + } else {
> + new_offsets = drmm_kmalloc_array(display->drm, new_size, sizeof(*new_offsets),
> + GFP_KERNEL);
> +
> + if (!new_offsets)
> + return -ENOMEM;
> + }
> +
> + spin_lock_irqsave(&dbg->lock, flags);
> + old_offsets = dbg->untracked.offsets;
> + dbg->untracked.offsets = new_offsets;
> + dbg->untracked.size = new_size;
> + dbg->untracked.head = 0;
> + dbg->untracked.len = 0;
> + dbg->untracked.overflow = false;
> + spin_unlock_irqrestore(&dbg->lock, flags);
> +
> + if (old_offsets)
> + drmm_kfree(display->drm, old_offsets);
> +
> + return 0;
> +}
> +
> +DEFINE_SIMPLE_ATTRIBUTE_SIGNED(untracked_size_fops,
> + untracked_size_get,
> + untracked_size_set,
> + "%lld\n");
> +
> +static int untracked_show(struct seq_file *m, void *data)
> +{
> + struct intel_display *display = m->private;
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> + unsigned long flags;
> + size_t remaining;
> + size_t i;
> +
> + spin_lock_irqsave(&dbg->lock, flags);
> +
> + remaining = dbg->untracked.len;
> + i = dbg->untracked.head;
> +
> + while (remaining--) {
> + if (i == 0)
> + i = dbg->untracked.size;
> +
> + seq_printf(m, "0x%08x\n", dbg->untracked.offsets[--i]);
> + }
> +
> + spin_unlock_irqrestore(&dbg->lock, flags);
> +
> + return 0;
> +}
> +
> +DEFINE_SHOW_ATTRIBUTE(untracked);
> +
> +void intel_dmc_wl_debugfs_init(struct intel_display *display)
> +{
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> +
> + spin_lock_init(&dbg->lock);
> +}
> +
> +void intel_dmc_wl_debugfs_register(struct intel_display *display)
> +{
> + struct dentry *dir;
> +
> + if (!HAS_DMC_WAKELOCK(display))
> + return;
> +
> + dir = debugfs_create_dir("intel_dmc_wl", display->drm->debugfs_root);
> + if (IS_ERR(dir))
> + return;
> +
> + debugfs_create_file("untracked_size", 0644, dir, display,
> + &untracked_size_fops);
> + debugfs_create_file("untracked", 0644, dir, display,
> + &untracked_fops);
> +}
> +
> +static bool untracked_has_recent_offset(struct intel_display *display, u32 offset)
> +{
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> + int look_back = 32;
Define a macro for this magic number
> + size_t i;
> +
> + if (look_back > dbg->untracked.len)
> + look_back = dbg->untracked.len;
> +
> + i = dbg->untracked.head;
> +
> + while (look_back--) {
> + if (i == 0)
> + i = dbg->untracked.size;
> +
> + if (dbg->untracked.offsets[--i] == offset)
> + return true;
> + }
> +
> + return false;
> +}
> +
> +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset)
> +{
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&dbg->lock, flags);
As this code never gets called by an interrupt, we can use just the
spin_lock instead of spin_lock_irqsave. Same applies for all the places
where spin_lock/unlock_irqsave/irqrestore is used.
> +
> + if (!dbg->untracked.size)
> + goto out_unlock;
> +
> + /* Save some space by not repeating recent offsets. */
> + if (untracked_has_recent_offset(display, offset))
> + goto out_unlock;
> +
> + dbg->untracked.offsets[dbg->untracked.head] = offset;
> + dbg->untracked.head = (dbg->untracked.head + 1) % dbg->untracked.size;
> + if (dbg->untracked.len < dbg->untracked.size)
> + dbg->untracked.len++;
> +
> + if (dbg->untracked.len == dbg->untracked.size && !dbg->untracked.overflow) {
> + dbg->untracked.overflow = true;
> + drm_warn(display->drm, "Overflow detected in DMC wakelock debugfs untracked offsets\n");
> + }
> +
> +out_unlock:
> + spin_unlock_irqrestore(&dbg->lock, flags);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> new file mode 100644
> index 000000000000..9437c324966f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright (C) 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_DMC_WL_DEBUGFS_H__
> +#define __INTEL_DMC_WL_DEBUGFS_H__
> +
> +#include <linux/types.h>
> +#include <linux/spinlock.h>
> +
> +struct intel_display;
> +
> +struct intel_dmc_wl_dbg {
> + spinlock_t lock; /* protects everything below */
> + struct {
> + u32 *offsets;
> + size_t head;
> + size_t len;
> + size_t size;
There is no need of both len and size. head will always give the count
of entries in the buffer. During overflow, we are keeping a flag to
indicate a overflow, which indicates the we also have date in the buffer
above head till the end of buffer.
Regards,
Bala
> + bool overflow;
> + } untracked;
> +};
> +
> +void intel_dmc_wl_debugfs_init(struct intel_display *display);
> +void intel_dmc_wl_debugfs_register(struct intel_display *display);
> +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset);
> +
> +#endif /* __INTEL_DMC_WL_DEBUGFS_H__ */
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 81f63258a7e1..f03fbdbcb1a4 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -221,6 +221,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> i915-display/intel_display_wa.o \
> i915-display/intel_dkl_phy.o \
> i915-display/intel_dmc.o \
> + i915-display/intel_dmc_wl_debugfs.o \
> i915-display/intel_dp.o \
> i915-display/intel_dp_aux.o \
> i915-display/intel_dp_aux_backlight.o \
> --
> 2.48.0
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets
2025-01-23 16:11 ` Vivekanandan, Balasubramani
@ 2025-01-23 16:41 ` Gustavo Sousa
2025-01-30 8:54 ` Vivekanandan, Balasubramani
0 siblings, 1 reply; 35+ messages in thread
From: Gustavo Sousa @ 2025-01-23 16:41 UTC (permalink / raw)
To: Vivekanandan, Balasubramani, intel-gfx, intel-xe
Quoting Vivekanandan, Balasubramani (2025-01-23 13:11:03-03:00)
>On 17.01.2025 19:06, Gustavo Sousa wrote:
>> The DMC wakelock code needs to keep track of register offsets that need
>> the wakelock for proper access. If one of the necessary offsets are
>> missed, then the failure in asserting the wakelock is very likely to
>> cause problems down the road.
>>
>> A miss could happen for at least two different reasons:
>>
>> - We might have forgotten to add the offset (or range) to the relevant
>> tables tracked by the driver in the first place.
>>
>> - Or updates to either the DMC firmware or the display IP that require
>> new offsets to be tracked and we fail to realize that.
>>
>> To help capture these cases, let's introduce a debugfs interface for the
>> DMC wakelock.
>>
>> In this part, we export a buffer containing offsets of registers that
>> were considered not needing the wakelock by our driver. In an upcoming
>> change we will also allow defining an extra set of offset ranges to be
>> tracked by our driver.
>>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>> drivers/gpu/drm/i915/Makefile | 1 +
>> .../drm/i915/display/intel_display_debugfs.c | 2 +
>> drivers/gpu/drm/i915/display/intel_dmc_wl.c | 5 +-
>> drivers/gpu/drm/i915/display/intel_dmc_wl.h | 2 +
>> .../drm/i915/display/intel_dmc_wl_debugfs.c | 251 ++++++++++++++++++
>> .../drm/i915/display/intel_dmc_wl_debugfs.h | 29 ++
>> drivers/gpu/drm/xe/Makefile | 1 +
>> 7 files changed, 290 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>> create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>> index 3dda9f0eda82..ac1ab79de9c8 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -251,6 +251,7 @@ i915-y += \
>> display/intel_display_wa.o \
>> display/intel_dmc.o \
>> display/intel_dmc_wl.o \
>> + display/intel_dmc_wl_debugfs.o \
>> display/intel_dpio_phy.o \
>> display/intel_dpll.o \
>> display/intel_dpll_mgr.o \
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index f1d76484025a..b032535f4830 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -26,6 +26,7 @@
>> #include "intel_display_power_well.h"
>> #include "intel_display_types.h"
>> #include "intel_dmc.h"
>> +#include "intel_dmc_wl_debugfs.h"
>> #include "intel_dp.h"
>> #include "intel_dp_link_training.h"
>> #include "intel_dp_mst.h"
>> @@ -883,6 +884,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
>>
>> intel_bios_debugfs_register(display);
>> intel_cdclk_debugfs_register(display);
>> + intel_dmc_wl_debugfs_register(display);
>> intel_dmc_debugfs_register(display);
>> intel_dp_test_debugfs_register(display);
>> intel_fbc_debugfs_register(display);
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
>> index 330b43a72e08..3686d4e90167 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
>> @@ -338,6 +338,7 @@ void intel_dmc_wl_init(struct intel_display *display)
>> spin_lock_init(&wl->lock);
>> refcount_set(&wl->refcount,
>> display->params.enable_dmc_wl == ENABLE_DMC_WL_ALWAYS_LOCKED ? 1 : 0);
>> + intel_dmc_wl_debugfs_init(display);
>> }
>>
>> /* Must only be called as part of enabling dynamic DC states. */
>> @@ -444,8 +445,10 @@ void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg)
>> spin_lock_irqsave(&wl->lock, flags);
>>
>> if (i915_mmio_reg_valid(reg) &&
>> - !intel_dmc_wl_check_range(display, reg, wl->dc_state))
>> + !intel_dmc_wl_check_range(display, reg, wl->dc_state)) {
>> + intel_dmc_wl_debugfs_log_untracked(display, i915_mmio_reg_offset(reg));
>> goto out_unlock;
>> + }
>>
>> if (!wl->enabled) {
>> if (!refcount_inc_not_zero(&wl->refcount))
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.h b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>> index 5488fbdf29b8..d11b0ab50b3c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>> @@ -11,6 +11,7 @@
>> #include <linux/refcount.h>
>>
>> #include "i915_reg_defs.h"
>> +#include "intel_dmc_wl_debugfs.h"
>>
>> struct intel_display;
>>
>> @@ -27,6 +28,7 @@ struct intel_dmc_wl {
>> */
>> u32 dc_state;
>> struct delayed_work work;
>> + struct intel_dmc_wl_dbg dbg;
>> };
>>
>> void intel_dmc_wl_init(struct intel_display *display);
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>> new file mode 100644
>> index 000000000000..41e59d775fe5
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>> @@ -0,0 +1,251 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright (C) 2025 Intel Corporation
>> + */
>> +
>> +#include <linux/debugfs.h>
>> +
>> +#include <drm/drm_device.h>
>> +#include <drm/drm_managed.h>
>> +#include <drm/drm_print.h>
>> +
>> +#include "intel_display_core.h"
>> +#include "intel_dmc_wl_debugfs.h"
>> +
>> +#define DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX 65536
>This macro is not actually the size but the count of offsets stored in
>the buffer. This is used as the array size for drmm_kmalloc_array call.
>It makes sense to rename this macro as count
I think size doesn't really have to mean number of bytes, but, in this
case, I agree, that "buffer size" could be easily thought that way.
However, couldn't "buffer count" be somewhat ambiguous? One might read
as the number of buffers and then only later after reading the code that
it would refer to the number of entries in a single buffer.
Between the two options, I think I would still go with "buffer size"...
>
>> +
>> +/*
>> + * DOC: DMC wakelock debugfs
>> + *
>> + * The DMC wakelock code needs to keep track of register offsets that need the
>> + * wakelock for proper access. If one of the necessary offsets are missed, then
>> + * the failure in asserting the wakelock is very likely to cause problems down
>> + * the road.
>> + *
>> + * A miss could happen for at least two different reasons:
>> + *
>> + * - We might have forgotten to add the offset (or range) to the relevant
>> + * tables tracked by the driver in the first place.
>> + *
>> + * - Or updates to either the DMC firmware or the display IP that require new
>> + * offsets to be tracked and we fail to realize that.
>> + *
>> + * To help capture these cases, we provide the intel_dmc_wl/ debugfs directory,
>> + * which exports a buffer of untracked register offsets.
>> + *
>> + * Untracked offsets
>> + * -----------------
>> + *
>> + * This is a buffer that records every register offset that went through the
>> + * DMC wakelock check and was deemed not needing the wakelock for MMIO access.
>> + *
>> + * To activate the logging of offsets into such a buffer, one can do::
>> + *
>> + * # echo -1 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
>
>This knob is setting the count of offsets to be stored and not the size.
>I think this should be renamed to indicate it as count.
>
>> + *
>> + * This will create a buffer with the maximum number of entries allowed
>> + * (DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX). A positive value can be used instead to
>> + * define a different size:
>> + *
>> + * # echo 1024 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
>
>For me passing negative number doesn't look intuitive. Thinking do we
>really need the case of passing default buffer size. We can allow just 0
>to disable and any positive number to enable with the buffer size set as
>value passed.
Well, this is already supported. The use of -1 is just a convenience,
and the user is not required to use it.
The current interface doesn't provide a way of letting the user know the
maximum value and I think it would be a bit overkill adding another
debugfs file just for that purpose.
As such, I think -1 is a useful way of letting the user use the maximum
size, specially when she doesn't have the up-to-date documentation in
handy to know what value that is. That's certainly better than having
the user finding the maximum via trial and error.
>
>> + *
>> + * Every write to untracked_size will cause the buffer to be reset.
>> + *
>> + * It is also possible to read untracked_size in order to get the current
>> + * value.
>> + *
>> + * After enabled, the buffer starts getting filled with offsets as MMIOs are
>> + * performed by the driver.
>> + *
>> + * In order to view the content of the buffer, one can do::
>> + *
>> + * # cat /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked
>> + * 0x000c4000
>> + * 0x0016fe50
>> + * 0x000c7200
>> + * 0x000c7204
>> + * 0x00045230
>> + * 0x00046440
>> + * 0x00045234
>> + * 0x0016fa48
>> + * 0x0016fa40
>> + * 0x0016fa5c
>> + * (...)
>> + *
>> + * The order of those offsets does not reflect the order the checks were done
>> + * (some recently seen offsets are skipped to save space).
>> + *
>> + * Once done with it, the logging can be disabled with::
>> + *
>> + * # echo 0 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
>> + */
>> +
>> +static int untracked_size_get(void *data, u64 *val)
>> +{
>> + struct intel_display *display = data;
>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&dbg->lock, flags);
>> + *val = dbg->untracked.size;
>> + spin_unlock_irqrestore(&dbg->lock, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static int untracked_size_set(void *data, u64 val)
>> +{
>> + struct intel_display *display = data;
>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> + s64 new_size;
>> + u32 *old_offsets;
>> + u32 *new_offsets;
>> + unsigned long flags;
>> +
>> + new_size = (s64)val;
>> +
>> + if (new_size == -1) {
>> + new_size = DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX;
>> + } else if (new_size < 0) {
>> + drm_err(display->drm,
>> + "%lld is invalid for untracked_size, the only negative value allowed is -1\n",
>> + new_size);
>> + return -EINVAL;
>> + } else if (new_size > DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX) {
>> + drm_err(display->drm,
>> + "%lld too big for untracked_size, maximum allowed value is %d\n",
>> + new_size,
>> + DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX);
>> + return -EINVAL;
>> + }
>> +
>> + if (new_size == 0) {
>> + new_offsets = NULL;
>> + } else {
>> + new_offsets = drmm_kmalloc_array(display->drm, new_size, sizeof(*new_offsets),
>> + GFP_KERNEL);
>> +
>> + if (!new_offsets)
>> + return -ENOMEM;
>> + }
>> +
>> + spin_lock_irqsave(&dbg->lock, flags);
>> + old_offsets = dbg->untracked.offsets;
>> + dbg->untracked.offsets = new_offsets;
>> + dbg->untracked.size = new_size;
>> + dbg->untracked.head = 0;
>> + dbg->untracked.len = 0;
>> + dbg->untracked.overflow = false;
>> + spin_unlock_irqrestore(&dbg->lock, flags);
>> +
>> + if (old_offsets)
>> + drmm_kfree(display->drm, old_offsets);
>> +
>> + return 0;
>> +}
>> +
>> +DEFINE_SIMPLE_ATTRIBUTE_SIGNED(untracked_size_fops,
>> + untracked_size_get,
>> + untracked_size_set,
>> + "%lld\n");
>> +
>> +static int untracked_show(struct seq_file *m, void *data)
>> +{
>> + struct intel_display *display = m->private;
>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> + unsigned long flags;
>> + size_t remaining;
>> + size_t i;
>> +
>> + spin_lock_irqsave(&dbg->lock, flags);
>> +
>> + remaining = dbg->untracked.len;
>> + i = dbg->untracked.head;
>> +
>> + while (remaining--) {
>> + if (i == 0)
>> + i = dbg->untracked.size;
>> +
>> + seq_printf(m, "0x%08x\n", dbg->untracked.offsets[--i]);
>> + }
>> +
>> + spin_unlock_irqrestore(&dbg->lock, flags);
>> +
>> + return 0;
>> +}
>> +
>> +DEFINE_SHOW_ATTRIBUTE(untracked);
>> +
>> +void intel_dmc_wl_debugfs_init(struct intel_display *display)
>> +{
>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> +
>> + spin_lock_init(&dbg->lock);
>> +}
>> +
>> +void intel_dmc_wl_debugfs_register(struct intel_display *display)
>> +{
>> + struct dentry *dir;
>> +
>> + if (!HAS_DMC_WAKELOCK(display))
>> + return;
>> +
>> + dir = debugfs_create_dir("intel_dmc_wl", display->drm->debugfs_root);
>> + if (IS_ERR(dir))
>> + return;
>> +
>> + debugfs_create_file("untracked_size", 0644, dir, display,
>> + &untracked_size_fops);
>> + debugfs_create_file("untracked", 0644, dir, display,
>> + &untracked_fops);
>> +}
>> +
>> +static bool untracked_has_recent_offset(struct intel_display *display, u32 offset)
>> +{
>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> + int look_back = 32;
>Define a macro for this magic number
This is very local to this function and I guess the variable name
already convey it's meaning?
>
>> + size_t i;
>> +
>> + if (look_back > dbg->untracked.len)
>> + look_back = dbg->untracked.len;
>> +
>> + i = dbg->untracked.head;
>> +
>> + while (look_back--) {
>> + if (i == 0)
>> + i = dbg->untracked.size;
>> +
>> + if (dbg->untracked.offsets[--i] == offset)
>> + return true;
>> + }
>> +
>> + return false;
>> +}
>> +
>> +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset)
>> +{
>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&dbg->lock, flags);
>As this code never gets called by an interrupt, we can use just the
>spin_lock instead of spin_lock_irqsave. Same applies for all the places
>where spin_lock/unlock_irqsave/irqrestore is used.
This code does get called in interrupt context. It is called by
intel_dmc_wl_get(), which is called for most of display MMIO access
functions, and that happens both in user and interrupt context.
>
>> +
>> + if (!dbg->untracked.size)
>> + goto out_unlock;
>> +
>> + /* Save some space by not repeating recent offsets. */
>> + if (untracked_has_recent_offset(display, offset))
>> + goto out_unlock;
>> +
>> + dbg->untracked.offsets[dbg->untracked.head] = offset;
>> + dbg->untracked.head = (dbg->untracked.head + 1) % dbg->untracked.size;
>> + if (dbg->untracked.len < dbg->untracked.size)
>> + dbg->untracked.len++;
>> +
>> + if (dbg->untracked.len == dbg->untracked.size && !dbg->untracked.overflow) {
>> + dbg->untracked.overflow = true;
>> + drm_warn(display->drm, "Overflow detected in DMC wakelock debugfs untracked offsets\n");
>> + }
>> +
>> +out_unlock:
>> + spin_unlock_irqrestore(&dbg->lock, flags);
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
>> new file mode 100644
>> index 000000000000..9437c324966f
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
>> @@ -0,0 +1,29 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright (C) 2025 Intel Corporation
>> + */
>> +
>> +#ifndef __INTEL_DMC_WL_DEBUGFS_H__
>> +#define __INTEL_DMC_WL_DEBUGFS_H__
>> +
>> +#include <linux/types.h>
>> +#include <linux/spinlock.h>
>> +
>> +struct intel_display;
>> +
>> +struct intel_dmc_wl_dbg {
>> + spinlock_t lock; /* protects everything below */
>> + struct {
>> + u32 *offsets;
>> + size_t head;
>> + size_t len;
>> + size_t size;
>There is no need of both len and size. head will always give the count
>of entries in the buffer. During overflow, we are keeping a flag to
>indicate a overflow, which indicates the we also have date in the buffer
>above head till the end of buffer.
Ah, right. If overflow==false, then the length equals head, if
overflow==true, then length equals size.
Maybe the inconvenience is that we will need to calculate the length
every time we need it. But maybe that's not too bad...
Thanks! I'll remove the "len" member in v2.
--
Gustavo Sousa
>
>Regards,
>Bala
>
>> + bool overflow;
>> + } untracked;
>> +};
>> +
>> +void intel_dmc_wl_debugfs_init(struct intel_display *display);
>> +void intel_dmc_wl_debugfs_register(struct intel_display *display);
>> +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset);
>> +
>> +#endif /* __INTEL_DMC_WL_DEBUGFS_H__ */
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index 81f63258a7e1..f03fbdbcb1a4 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -221,6 +221,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>> i915-display/intel_display_wa.o \
>> i915-display/intel_dkl_phy.o \
>> i915-display/intel_dmc.o \
>> + i915-display/intel_dmc_wl_debugfs.o \
>> i915-display/intel_dp.o \
>> i915-display/intel_dp_aux.o \
>> i915-display/intel_dp_aux_backlight.o \
>> --
>> 2.48.0
>>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets
2025-01-17 22:06 ` [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets Gustavo Sousa
2025-01-22 9:06 ` Luca Coelho
2025-01-23 16:11 ` Vivekanandan, Balasubramani
@ 2025-01-27 9:47 ` Jani Nikula
2025-01-27 11:17 ` Gustavo Sousa
2 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2025-01-27 9:47 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On Fri, 17 Jan 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.h b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
> index 5488fbdf29b8..d11b0ab50b3c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
> @@ -11,6 +11,7 @@
> #include <linux/refcount.h>
>
> #include "i915_reg_defs.h"
> +#include "intel_dmc_wl_debugfs.h"
>
> struct intel_display;
>
> @@ -27,6 +28,7 @@ struct intel_dmc_wl {
> */
> u32 dc_state;
> struct delayed_work work;
> + struct intel_dmc_wl_dbg dbg;
> };
>
With intel_de.h including intel_dmc_wl.h, we'll have almost all of
display include intel_dmc_wl_debugfs.h, and getting the definition of
struct intel_dmc_wl_dbg, really for no good reason.
I really like to flip this around. You need to have a *good reason* to
expose stuff to the entire display driver all of a sudden. Instead of
requiring a good reason to hide stuff.
BR,
Jani.
> void intel_dmc_wl_init(struct intel_display *display);
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> new file mode 100644
> index 000000000000..41e59d775fe5
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> @@ -0,0 +1,251 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright (C) 2025 Intel Corporation
> + */
> +
> +#include <linux/debugfs.h>
> +
> +#include <drm/drm_device.h>
> +#include <drm/drm_managed.h>
> +#include <drm/drm_print.h>
> +
> +#include "intel_display_core.h"
> +#include "intel_dmc_wl_debugfs.h"
> +
> +#define DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX 65536
> +
> +/*
> + * DOC: DMC wakelock debugfs
> + *
> + * The DMC wakelock code needs to keep track of register offsets that need the
> + * wakelock for proper access. If one of the necessary offsets are missed, then
> + * the failure in asserting the wakelock is very likely to cause problems down
> + * the road.
> + *
> + * A miss could happen for at least two different reasons:
> + *
> + * - We might have forgotten to add the offset (or range) to the relevant
> + * tables tracked by the driver in the first place.
> + *
> + * - Or updates to either the DMC firmware or the display IP that require new
> + * offsets to be tracked and we fail to realize that.
> + *
> + * To help capture these cases, we provide the intel_dmc_wl/ debugfs directory,
> + * which exports a buffer of untracked register offsets.
> + *
> + * Untracked offsets
> + * -----------------
> + *
> + * This is a buffer that records every register offset that went through the
> + * DMC wakelock check and was deemed not needing the wakelock for MMIO access.
> + *
> + * To activate the logging of offsets into such a buffer, one can do::
> + *
> + * # echo -1 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> + *
> + * This will create a buffer with the maximum number of entries allowed
> + * (DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX). A positive value can be used instead to
> + * define a different size:
> + *
> + * # echo 1024 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> + *
> + * Every write to untracked_size will cause the buffer to be reset.
> + *
> + * It is also possible to read untracked_size in order to get the current
> + * value.
> + *
> + * After enabled, the buffer starts getting filled with offsets as MMIOs are
> + * performed by the driver.
> + *
> + * In order to view the content of the buffer, one can do::
> + *
> + * # cat /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked
> + * 0x000c4000
> + * 0x0016fe50
> + * 0x000c7200
> + * 0x000c7204
> + * 0x00045230
> + * 0x00046440
> + * 0x00045234
> + * 0x0016fa48
> + * 0x0016fa40
> + * 0x0016fa5c
> + * (...)
> + *
> + * The order of those offsets does not reflect the order the checks were done
> + * (some recently seen offsets are skipped to save space).
> + *
> + * Once done with it, the logging can be disabled with::
> + *
> + * # echo 0 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> + */
> +
> +static int untracked_size_get(void *data, u64 *val)
> +{
> + struct intel_display *display = data;
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&dbg->lock, flags);
> + *val = dbg->untracked.size;
> + spin_unlock_irqrestore(&dbg->lock, flags);
> +
> + return 0;
> +}
> +
> +static int untracked_size_set(void *data, u64 val)
> +{
> + struct intel_display *display = data;
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> + s64 new_size;
> + u32 *old_offsets;
> + u32 *new_offsets;
> + unsigned long flags;
> +
> + new_size = (s64)val;
> +
> + if (new_size == -1) {
> + new_size = DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX;
> + } else if (new_size < 0) {
> + drm_err(display->drm,
> + "%lld is invalid for untracked_size, the only negative value allowed is -1\n",
> + new_size);
> + return -EINVAL;
> + } else if (new_size > DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX) {
> + drm_err(display->drm,
> + "%lld too big for untracked_size, maximum allowed value is %d\n",
> + new_size,
> + DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX);
> + return -EINVAL;
> + }
> +
> + if (new_size == 0) {
> + new_offsets = NULL;
> + } else {
> + new_offsets = drmm_kmalloc_array(display->drm, new_size, sizeof(*new_offsets),
> + GFP_KERNEL);
> +
> + if (!new_offsets)
> + return -ENOMEM;
> + }
> +
> + spin_lock_irqsave(&dbg->lock, flags);
> + old_offsets = dbg->untracked.offsets;
> + dbg->untracked.offsets = new_offsets;
> + dbg->untracked.size = new_size;
> + dbg->untracked.head = 0;
> + dbg->untracked.len = 0;
> + dbg->untracked.overflow = false;
> + spin_unlock_irqrestore(&dbg->lock, flags);
> +
> + if (old_offsets)
> + drmm_kfree(display->drm, old_offsets);
> +
> + return 0;
> +}
> +
> +DEFINE_SIMPLE_ATTRIBUTE_SIGNED(untracked_size_fops,
> + untracked_size_get,
> + untracked_size_set,
> + "%lld\n");
> +
> +static int untracked_show(struct seq_file *m, void *data)
> +{
> + struct intel_display *display = m->private;
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> + unsigned long flags;
> + size_t remaining;
> + size_t i;
> +
> + spin_lock_irqsave(&dbg->lock, flags);
> +
> + remaining = dbg->untracked.len;
> + i = dbg->untracked.head;
> +
> + while (remaining--) {
> + if (i == 0)
> + i = dbg->untracked.size;
> +
> + seq_printf(m, "0x%08x\n", dbg->untracked.offsets[--i]);
> + }
> +
> + spin_unlock_irqrestore(&dbg->lock, flags);
> +
> + return 0;
> +}
> +
> +DEFINE_SHOW_ATTRIBUTE(untracked);
> +
> +void intel_dmc_wl_debugfs_init(struct intel_display *display)
> +{
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> +
> + spin_lock_init(&dbg->lock);
> +}
> +
> +void intel_dmc_wl_debugfs_register(struct intel_display *display)
> +{
> + struct dentry *dir;
> +
> + if (!HAS_DMC_WAKELOCK(display))
> + return;
> +
> + dir = debugfs_create_dir("intel_dmc_wl", display->drm->debugfs_root);
> + if (IS_ERR(dir))
> + return;
> +
> + debugfs_create_file("untracked_size", 0644, dir, display,
> + &untracked_size_fops);
> + debugfs_create_file("untracked", 0644, dir, display,
> + &untracked_fops);
> +}
> +
> +static bool untracked_has_recent_offset(struct intel_display *display, u32 offset)
> +{
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> + int look_back = 32;
> + size_t i;
> +
> + if (look_back > dbg->untracked.len)
> + look_back = dbg->untracked.len;
> +
> + i = dbg->untracked.head;
> +
> + while (look_back--) {
> + if (i == 0)
> + i = dbg->untracked.size;
> +
> + if (dbg->untracked.offsets[--i] == offset)
> + return true;
> + }
> +
> + return false;
> +}
> +
> +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset)
> +{
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&dbg->lock, flags);
> +
> + if (!dbg->untracked.size)
> + goto out_unlock;
> +
> + /* Save some space by not repeating recent offsets. */
> + if (untracked_has_recent_offset(display, offset))
> + goto out_unlock;
> +
> + dbg->untracked.offsets[dbg->untracked.head] = offset;
> + dbg->untracked.head = (dbg->untracked.head + 1) % dbg->untracked.size;
> + if (dbg->untracked.len < dbg->untracked.size)
> + dbg->untracked.len++;
> +
> + if (dbg->untracked.len == dbg->untracked.size && !dbg->untracked.overflow) {
> + dbg->untracked.overflow = true;
> + drm_warn(display->drm, "Overflow detected in DMC wakelock debugfs untracked offsets\n");
> + }
> +
> +out_unlock:
> + spin_unlock_irqrestore(&dbg->lock, flags);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> new file mode 100644
> index 000000000000..9437c324966f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright (C) 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_DMC_WL_DEBUGFS_H__
> +#define __INTEL_DMC_WL_DEBUGFS_H__
> +
> +#include <linux/types.h>
> +#include <linux/spinlock.h>
> +
> +struct intel_display;
> +
> +struct intel_dmc_wl_dbg {
> + spinlock_t lock; /* protects everything below */
> + struct {
> + u32 *offsets;
> + size_t head;
> + size_t len;
> + size_t size;
> + bool overflow;
> + } untracked;
> +};
> +
> +void intel_dmc_wl_debugfs_init(struct intel_display *display);
> +void intel_dmc_wl_debugfs_register(struct intel_display *display);
> +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset);
> +
> +#endif /* __INTEL_DMC_WL_DEBUGFS_H__ */
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 81f63258a7e1..f03fbdbcb1a4 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -221,6 +221,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> i915-display/intel_display_wa.o \
> i915-display/intel_dkl_phy.o \
> i915-display/intel_dmc.o \
> + i915-display/intel_dmc_wl_debugfs.o \
> i915-display/intel_dp.o \
> i915-display/intel_dp_aux.o \
> i915-display/intel_dp_aux_backlight.o \
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets
2025-01-27 9:47 ` Jani Nikula
@ 2025-01-27 11:17 ` Gustavo Sousa
2025-01-27 11:59 ` Jani Nikula
0 siblings, 1 reply; 35+ messages in thread
From: Gustavo Sousa @ 2025-01-27 11:17 UTC (permalink / raw)
To: Jani Nikula, intel-gfx, intel-xe
Quoting Jani Nikula (2025-01-27 06:47:58-03:00)
>On Fri, 17 Jan 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.h b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>> index 5488fbdf29b8..d11b0ab50b3c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>> @@ -11,6 +11,7 @@
>> #include <linux/refcount.h>
>>
>> #include "i915_reg_defs.h"
>> +#include "intel_dmc_wl_debugfs.h"
>>
>> struct intel_display;
>>
>> @@ -27,6 +28,7 @@ struct intel_dmc_wl {
>> */
>> u32 dc_state;
>> struct delayed_work work;
>> + struct intel_dmc_wl_dbg dbg;
>> };
>>
>
>With intel_de.h including intel_dmc_wl.h, we'll have almost all of
>display include intel_dmc_wl_debugfs.h, and getting the definition of
>struct intel_dmc_wl_dbg, really for no good reason.
>
>I really like to flip this around. You need to have a *good reason* to
>expose stuff to the entire display driver all of a sudden. Instead of
>requiring a good reason to hide stuff.
Maybe make dbg a pointer and have only intel_dmc_wl.c knowing its guts?
Or do you have some other suggestion?
--
Gustavo Sousa
>
>BR,
>Jani.
>
>
>
>> void intel_dmc_wl_init(struct intel_display *display);
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>> new file mode 100644
>> index 000000000000..41e59d775fe5
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>> @@ -0,0 +1,251 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright (C) 2025 Intel Corporation
>> + */
>> +
>> +#include <linux/debugfs.h>
>> +
>> +#include <drm/drm_device.h>
>> +#include <drm/drm_managed.h>
>> +#include <drm/drm_print.h>
>> +
>> +#include "intel_display_core.h"
>> +#include "intel_dmc_wl_debugfs.h"
>> +
>> +#define DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX 65536
>> +
>> +/*
>> + * DOC: DMC wakelock debugfs
>> + *
>> + * The DMC wakelock code needs to keep track of register offsets that need the
>> + * wakelock for proper access. If one of the necessary offsets are missed, then
>> + * the failure in asserting the wakelock is very likely to cause problems down
>> + * the road.
>> + *
>> + * A miss could happen for at least two different reasons:
>> + *
>> + * - We might have forgotten to add the offset (or range) to the relevant
>> + * tables tracked by the driver in the first place.
>> + *
>> + * - Or updates to either the DMC firmware or the display IP that require new
>> + * offsets to be tracked and we fail to realize that.
>> + *
>> + * To help capture these cases, we provide the intel_dmc_wl/ debugfs directory,
>> + * which exports a buffer of untracked register offsets.
>> + *
>> + * Untracked offsets
>> + * -----------------
>> + *
>> + * This is a buffer that records every register offset that went through the
>> + * DMC wakelock check and was deemed not needing the wakelock for MMIO access.
>> + *
>> + * To activate the logging of offsets into such a buffer, one can do::
>> + *
>> + * # echo -1 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
>> + *
>> + * This will create a buffer with the maximum number of entries allowed
>> + * (DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX). A positive value can be used instead to
>> + * define a different size:
>> + *
>> + * # echo 1024 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
>> + *
>> + * Every write to untracked_size will cause the buffer to be reset.
>> + *
>> + * It is also possible to read untracked_size in order to get the current
>> + * value.
>> + *
>> + * After enabled, the buffer starts getting filled with offsets as MMIOs are
>> + * performed by the driver.
>> + *
>> + * In order to view the content of the buffer, one can do::
>> + *
>> + * # cat /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked
>> + * 0x000c4000
>> + * 0x0016fe50
>> + * 0x000c7200
>> + * 0x000c7204
>> + * 0x00045230
>> + * 0x00046440
>> + * 0x00045234
>> + * 0x0016fa48
>> + * 0x0016fa40
>> + * 0x0016fa5c
>> + * (...)
>> + *
>> + * The order of those offsets does not reflect the order the checks were done
>> + * (some recently seen offsets are skipped to save space).
>> + *
>> + * Once done with it, the logging can be disabled with::
>> + *
>> + * # echo 0 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
>> + */
>> +
>> +static int untracked_size_get(void *data, u64 *val)
>> +{
>> + struct intel_display *display = data;
>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&dbg->lock, flags);
>> + *val = dbg->untracked.size;
>> + spin_unlock_irqrestore(&dbg->lock, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static int untracked_size_set(void *data, u64 val)
>> +{
>> + struct intel_display *display = data;
>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> + s64 new_size;
>> + u32 *old_offsets;
>> + u32 *new_offsets;
>> + unsigned long flags;
>> +
>> + new_size = (s64)val;
>> +
>> + if (new_size == -1) {
>> + new_size = DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX;
>> + } else if (new_size < 0) {
>> + drm_err(display->drm,
>> + "%lld is invalid for untracked_size, the only negative value allowed is -1\n",
>> + new_size);
>> + return -EINVAL;
>> + } else if (new_size > DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX) {
>> + drm_err(display->drm,
>> + "%lld too big for untracked_size, maximum allowed value is %d\n",
>> + new_size,
>> + DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX);
>> + return -EINVAL;
>> + }
>> +
>> + if (new_size == 0) {
>> + new_offsets = NULL;
>> + } else {
>> + new_offsets = drmm_kmalloc_array(display->drm, new_size, sizeof(*new_offsets),
>> + GFP_KERNEL);
>> +
>> + if (!new_offsets)
>> + return -ENOMEM;
>> + }
>> +
>> + spin_lock_irqsave(&dbg->lock, flags);
>> + old_offsets = dbg->untracked.offsets;
>> + dbg->untracked.offsets = new_offsets;
>> + dbg->untracked.size = new_size;
>> + dbg->untracked.head = 0;
>> + dbg->untracked.len = 0;
>> + dbg->untracked.overflow = false;
>> + spin_unlock_irqrestore(&dbg->lock, flags);
>> +
>> + if (old_offsets)
>> + drmm_kfree(display->drm, old_offsets);
>> +
>> + return 0;
>> +}
>> +
>> +DEFINE_SIMPLE_ATTRIBUTE_SIGNED(untracked_size_fops,
>> + untracked_size_get,
>> + untracked_size_set,
>> + "%lld\n");
>> +
>> +static int untracked_show(struct seq_file *m, void *data)
>> +{
>> + struct intel_display *display = m->private;
>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> + unsigned long flags;
>> + size_t remaining;
>> + size_t i;
>> +
>> + spin_lock_irqsave(&dbg->lock, flags);
>> +
>> + remaining = dbg->untracked.len;
>> + i = dbg->untracked.head;
>> +
>> + while (remaining--) {
>> + if (i == 0)
>> + i = dbg->untracked.size;
>> +
>> + seq_printf(m, "0x%08x\n", dbg->untracked.offsets[--i]);
>> + }
>> +
>> + spin_unlock_irqrestore(&dbg->lock, flags);
>> +
>> + return 0;
>> +}
>> +
>> +DEFINE_SHOW_ATTRIBUTE(untracked);
>> +
>> +void intel_dmc_wl_debugfs_init(struct intel_display *display)
>> +{
>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> +
>> + spin_lock_init(&dbg->lock);
>> +}
>> +
>> +void intel_dmc_wl_debugfs_register(struct intel_display *display)
>> +{
>> + struct dentry *dir;
>> +
>> + if (!HAS_DMC_WAKELOCK(display))
>> + return;
>> +
>> + dir = debugfs_create_dir("intel_dmc_wl", display->drm->debugfs_root);
>> + if (IS_ERR(dir))
>> + return;
>> +
>> + debugfs_create_file("untracked_size", 0644, dir, display,
>> + &untracked_size_fops);
>> + debugfs_create_file("untracked", 0644, dir, display,
>> + &untracked_fops);
>> +}
>> +
>> +static bool untracked_has_recent_offset(struct intel_display *display, u32 offset)
>> +{
>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> + int look_back = 32;
>> + size_t i;
>> +
>> + if (look_back > dbg->untracked.len)
>> + look_back = dbg->untracked.len;
>> +
>> + i = dbg->untracked.head;
>> +
>> + while (look_back--) {
>> + if (i == 0)
>> + i = dbg->untracked.size;
>> +
>> + if (dbg->untracked.offsets[--i] == offset)
>> + return true;
>> + }
>> +
>> + return false;
>> +}
>> +
>> +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset)
>> +{
>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&dbg->lock, flags);
>> +
>> + if (!dbg->untracked.size)
>> + goto out_unlock;
>> +
>> + /* Save some space by not repeating recent offsets. */
>> + if (untracked_has_recent_offset(display, offset))
>> + goto out_unlock;
>> +
>> + dbg->untracked.offsets[dbg->untracked.head] = offset;
>> + dbg->untracked.head = (dbg->untracked.head + 1) % dbg->untracked.size;
>> + if (dbg->untracked.len < dbg->untracked.size)
>> + dbg->untracked.len++;
>> +
>> + if (dbg->untracked.len == dbg->untracked.size && !dbg->untracked.overflow) {
>> + dbg->untracked.overflow = true;
>> + drm_warn(display->drm, "Overflow detected in DMC wakelock debugfs untracked offsets\n");
>> + }
>> +
>> +out_unlock:
>> + spin_unlock_irqrestore(&dbg->lock, flags);
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
>> new file mode 100644
>> index 000000000000..9437c324966f
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
>> @@ -0,0 +1,29 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright (C) 2025 Intel Corporation
>> + */
>> +
>> +#ifndef __INTEL_DMC_WL_DEBUGFS_H__
>> +#define __INTEL_DMC_WL_DEBUGFS_H__
>> +
>> +#include <linux/types.h>
>> +#include <linux/spinlock.h>
>> +
>> +struct intel_display;
>> +
>> +struct intel_dmc_wl_dbg {
>> + spinlock_t lock; /* protects everything below */
>> + struct {
>> + u32 *offsets;
>> + size_t head;
>> + size_t len;
>> + size_t size;
>> + bool overflow;
>> + } untracked;
>> +};
>> +
>> +void intel_dmc_wl_debugfs_init(struct intel_display *display);
>> +void intel_dmc_wl_debugfs_register(struct intel_display *display);
>> +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset);
>> +
>> +#endif /* __INTEL_DMC_WL_DEBUGFS_H__ */
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index 81f63258a7e1..f03fbdbcb1a4 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -221,6 +221,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>> i915-display/intel_display_wa.o \
>> i915-display/intel_dkl_phy.o \
>> i915-display/intel_dmc.o \
>> + i915-display/intel_dmc_wl_debugfs.o \
>> i915-display/intel_dp.o \
>> i915-display/intel_dp_aux.o \
>> i915-display/intel_dp_aux_backlight.o \
>
>--
>Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets
2025-01-27 11:17 ` Gustavo Sousa
@ 2025-01-27 11:59 ` Jani Nikula
2025-01-27 12:55 ` Gustavo Sousa
0 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2025-01-27 11:59 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On Mon, 27 Jan 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> Quoting Jani Nikula (2025-01-27 06:47:58-03:00)
>>On Fri, 17 Jan 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.h b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>>> index 5488fbdf29b8..d11b0ab50b3c 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>>> @@ -11,6 +11,7 @@
>>> #include <linux/refcount.h>
>>>
>>> #include "i915_reg_defs.h"
>>> +#include "intel_dmc_wl_debugfs.h"
>>>
>>> struct intel_display;
>>>
>>> @@ -27,6 +28,7 @@ struct intel_dmc_wl {
>>> */
>>> u32 dc_state;
>>> struct delayed_work work;
>>> + struct intel_dmc_wl_dbg dbg;
>>> };
>>>
>>
>>With intel_de.h including intel_dmc_wl.h, we'll have almost all of
>>display include intel_dmc_wl_debugfs.h, and getting the definition of
>>struct intel_dmc_wl_dbg, really for no good reason.
>>
>>I really like to flip this around. You need to have a *good reason* to
>>expose stuff to the entire display driver all of a sudden. Instead of
>>requiring a good reason to hide stuff.
>
> Maybe make dbg a pointer and have only intel_dmc_wl.c knowing its guts?
>
> Or do you have some other suggestion?
Yes, using an opaque pointer is usually the way to go.
Lately we've been adding debugfs next to the implementation. Often the
debugfs needs access to the same stuff as the implementation, you can
hide stuff and not have to expose a ton of interfaces. This could work
here too... but I have to say this debugfs looks a bit, uh, bloated for
want of a better word. Maybe having the separate file is worth it.
BR,
Jani.
>
> --
> Gustavo Sousa
>
>>
>>BR,
>>Jani.
>>
>>
>>
>>> void intel_dmc_wl_init(struct intel_display *display);
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>>> new file mode 100644
>>> index 000000000000..41e59d775fe5
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>>> @@ -0,0 +1,251 @@
>>> +// SPDX-License-Identifier: MIT
>>> +/*
>>> + * Copyright (C) 2025 Intel Corporation
>>> + */
>>> +
>>> +#include <linux/debugfs.h>
>>> +
>>> +#include <drm/drm_device.h>
>>> +#include <drm/drm_managed.h>
>>> +#include <drm/drm_print.h>
>>> +
>>> +#include "intel_display_core.h"
>>> +#include "intel_dmc_wl_debugfs.h"
>>> +
>>> +#define DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX 65536
>>> +
>>> +/*
>>> + * DOC: DMC wakelock debugfs
>>> + *
>>> + * The DMC wakelock code needs to keep track of register offsets that need the
>>> + * wakelock for proper access. If one of the necessary offsets are missed, then
>>> + * the failure in asserting the wakelock is very likely to cause problems down
>>> + * the road.
>>> + *
>>> + * A miss could happen for at least two different reasons:
>>> + *
>>> + * - We might have forgotten to add the offset (or range) to the relevant
>>> + * tables tracked by the driver in the first place.
>>> + *
>>> + * - Or updates to either the DMC firmware or the display IP that require new
>>> + * offsets to be tracked and we fail to realize that.
>>> + *
>>> + * To help capture these cases, we provide the intel_dmc_wl/ debugfs directory,
>>> + * which exports a buffer of untracked register offsets.
>>> + *
>>> + * Untracked offsets
>>> + * -----------------
>>> + *
>>> + * This is a buffer that records every register offset that went through the
>>> + * DMC wakelock check and was deemed not needing the wakelock for MMIO access.
>>> + *
>>> + * To activate the logging of offsets into such a buffer, one can do::
>>> + *
>>> + * # echo -1 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
>>> + *
>>> + * This will create a buffer with the maximum number of entries allowed
>>> + * (DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX). A positive value can be used instead to
>>> + * define a different size:
>>> + *
>>> + * # echo 1024 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
>>> + *
>>> + * Every write to untracked_size will cause the buffer to be reset.
>>> + *
>>> + * It is also possible to read untracked_size in order to get the current
>>> + * value.
>>> + *
>>> + * After enabled, the buffer starts getting filled with offsets as MMIOs are
>>> + * performed by the driver.
>>> + *
>>> + * In order to view the content of the buffer, one can do::
>>> + *
>>> + * # cat /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked
>>> + * 0x000c4000
>>> + * 0x0016fe50
>>> + * 0x000c7200
>>> + * 0x000c7204
>>> + * 0x00045230
>>> + * 0x00046440
>>> + * 0x00045234
>>> + * 0x0016fa48
>>> + * 0x0016fa40
>>> + * 0x0016fa5c
>>> + * (...)
>>> + *
>>> + * The order of those offsets does not reflect the order the checks were done
>>> + * (some recently seen offsets are skipped to save space).
>>> + *
>>> + * Once done with it, the logging can be disabled with::
>>> + *
>>> + * # echo 0 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
>>> + */
>>> +
>>> +static int untracked_size_get(void *data, u64 *val)
>>> +{
>>> + struct intel_display *display = data;
>>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>> + unsigned long flags;
>>> +
>>> + spin_lock_irqsave(&dbg->lock, flags);
>>> + *val = dbg->untracked.size;
>>> + spin_unlock_irqrestore(&dbg->lock, flags);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int untracked_size_set(void *data, u64 val)
>>> +{
>>> + struct intel_display *display = data;
>>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>> + s64 new_size;
>>> + u32 *old_offsets;
>>> + u32 *new_offsets;
>>> + unsigned long flags;
>>> +
>>> + new_size = (s64)val;
>>> +
>>> + if (new_size == -1) {
>>> + new_size = DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX;
>>> + } else if (new_size < 0) {
>>> + drm_err(display->drm,
>>> + "%lld is invalid for untracked_size, the only negative value allowed is -1\n",
>>> + new_size);
>>> + return -EINVAL;
>>> + } else if (new_size > DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX) {
>>> + drm_err(display->drm,
>>> + "%lld too big for untracked_size, maximum allowed value is %d\n",
>>> + new_size,
>>> + DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX);
>>> + return -EINVAL;
>>> + }
>>> +
>>> + if (new_size == 0) {
>>> + new_offsets = NULL;
>>> + } else {
>>> + new_offsets = drmm_kmalloc_array(display->drm, new_size, sizeof(*new_offsets),
>>> + GFP_KERNEL);
>>> +
>>> + if (!new_offsets)
>>> + return -ENOMEM;
>>> + }
>>> +
>>> + spin_lock_irqsave(&dbg->lock, flags);
>>> + old_offsets = dbg->untracked.offsets;
>>> + dbg->untracked.offsets = new_offsets;
>>> + dbg->untracked.size = new_size;
>>> + dbg->untracked.head = 0;
>>> + dbg->untracked.len = 0;
>>> + dbg->untracked.overflow = false;
>>> + spin_unlock_irqrestore(&dbg->lock, flags);
>>> +
>>> + if (old_offsets)
>>> + drmm_kfree(display->drm, old_offsets);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +DEFINE_SIMPLE_ATTRIBUTE_SIGNED(untracked_size_fops,
>>> + untracked_size_get,
>>> + untracked_size_set,
>>> + "%lld\n");
>>> +
>>> +static int untracked_show(struct seq_file *m, void *data)
>>> +{
>>> + struct intel_display *display = m->private;
>>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>> + unsigned long flags;
>>> + size_t remaining;
>>> + size_t i;
>>> +
>>> + spin_lock_irqsave(&dbg->lock, flags);
>>> +
>>> + remaining = dbg->untracked.len;
>>> + i = dbg->untracked.head;
>>> +
>>> + while (remaining--) {
>>> + if (i == 0)
>>> + i = dbg->untracked.size;
>>> +
>>> + seq_printf(m, "0x%08x\n", dbg->untracked.offsets[--i]);
>>> + }
>>> +
>>> + spin_unlock_irqrestore(&dbg->lock, flags);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +DEFINE_SHOW_ATTRIBUTE(untracked);
>>> +
>>> +void intel_dmc_wl_debugfs_init(struct intel_display *display)
>>> +{
>>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>> +
>>> + spin_lock_init(&dbg->lock);
>>> +}
>>> +
>>> +void intel_dmc_wl_debugfs_register(struct intel_display *display)
>>> +{
>>> + struct dentry *dir;
>>> +
>>> + if (!HAS_DMC_WAKELOCK(display))
>>> + return;
>>> +
>>> + dir = debugfs_create_dir("intel_dmc_wl", display->drm->debugfs_root);
>>> + if (IS_ERR(dir))
>>> + return;
>>> +
>>> + debugfs_create_file("untracked_size", 0644, dir, display,
>>> + &untracked_size_fops);
>>> + debugfs_create_file("untracked", 0644, dir, display,
>>> + &untracked_fops);
>>> +}
>>> +
>>> +static bool untracked_has_recent_offset(struct intel_display *display, u32 offset)
>>> +{
>>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>> + int look_back = 32;
>>> + size_t i;
>>> +
>>> + if (look_back > dbg->untracked.len)
>>> + look_back = dbg->untracked.len;
>>> +
>>> + i = dbg->untracked.head;
>>> +
>>> + while (look_back--) {
>>> + if (i == 0)
>>> + i = dbg->untracked.size;
>>> +
>>> + if (dbg->untracked.offsets[--i] == offset)
>>> + return true;
>>> + }
>>> +
>>> + return false;
>>> +}
>>> +
>>> +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset)
>>> +{
>>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>> + unsigned long flags;
>>> +
>>> + spin_lock_irqsave(&dbg->lock, flags);
>>> +
>>> + if (!dbg->untracked.size)
>>> + goto out_unlock;
>>> +
>>> + /* Save some space by not repeating recent offsets. */
>>> + if (untracked_has_recent_offset(display, offset))
>>> + goto out_unlock;
>>> +
>>> + dbg->untracked.offsets[dbg->untracked.head] = offset;
>>> + dbg->untracked.head = (dbg->untracked.head + 1) % dbg->untracked.size;
>>> + if (dbg->untracked.len < dbg->untracked.size)
>>> + dbg->untracked.len++;
>>> +
>>> + if (dbg->untracked.len == dbg->untracked.size && !dbg->untracked.overflow) {
>>> + dbg->untracked.overflow = true;
>>> + drm_warn(display->drm, "Overflow detected in DMC wakelock debugfs untracked offsets\n");
>>> + }
>>> +
>>> +out_unlock:
>>> + spin_unlock_irqrestore(&dbg->lock, flags);
>>> +}
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
>>> new file mode 100644
>>> index 000000000000..9437c324966f
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
>>> @@ -0,0 +1,29 @@
>>> +/* SPDX-License-Identifier: MIT */
>>> +/*
>>> + * Copyright (C) 2025 Intel Corporation
>>> + */
>>> +
>>> +#ifndef __INTEL_DMC_WL_DEBUGFS_H__
>>> +#define __INTEL_DMC_WL_DEBUGFS_H__
>>> +
>>> +#include <linux/types.h>
>>> +#include <linux/spinlock.h>
>>> +
>>> +struct intel_display;
>>> +
>>> +struct intel_dmc_wl_dbg {
>>> + spinlock_t lock; /* protects everything below */
>>> + struct {
>>> + u32 *offsets;
>>> + size_t head;
>>> + size_t len;
>>> + size_t size;
>>> + bool overflow;
>>> + } untracked;
>>> +};
>>> +
>>> +void intel_dmc_wl_debugfs_init(struct intel_display *display);
>>> +void intel_dmc_wl_debugfs_register(struct intel_display *display);
>>> +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset);
>>> +
>>> +#endif /* __INTEL_DMC_WL_DEBUGFS_H__ */
>>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>>> index 81f63258a7e1..f03fbdbcb1a4 100644
>>> --- a/drivers/gpu/drm/xe/Makefile
>>> +++ b/drivers/gpu/drm/xe/Makefile
>>> @@ -221,6 +221,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>>> i915-display/intel_display_wa.o \
>>> i915-display/intel_dkl_phy.o \
>>> i915-display/intel_dmc.o \
>>> + i915-display/intel_dmc_wl_debugfs.o \
>>> i915-display/intel_dp.o \
>>> i915-display/intel_dp_aux.o \
>>> i915-display/intel_dp_aux_backlight.o \
>>
>>--
>>Jani Nikula, Intel
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1
2025-01-17 22:06 ` [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1 Gustavo Sousa
2025-01-22 10:24 ` Luca Coelho
@ 2025-01-27 12:01 ` Jani Nikula
2025-01-27 12:02 ` Jani Nikula
2025-01-27 13:24 ` Gustavo Sousa
2025-01-30 8:46 ` Vivekanandan, Balasubramani
2 siblings, 2 replies; 35+ messages in thread
From: Jani Nikula @ 2025-01-27 12:01 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On Fri, 17 Jan 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> We use a spinlock to protect DMC wakelock debugfs data, since it is also
> accessed by the core DMC wakelock logic. Taking the spinlock when the
> debugfs is not in use introduces a small but unnecessary penalty.
>
> Since the debugfs functionality is only expected to be used for, uh,
> debugging sessions, let's protect it behind a module parameter
> enable_dmc_wl_debugfs. That way, we only take the lock if the feature
> was enabled in the first place.
If the debug struct were an opaque pointer, you could check for that
being != NULL. Register the debugfs always, and have that initialize
everything as needed?
BR,
Jani.
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_params.c | 5 +++++
> .../gpu/drm/i915/display/intel_display_params.h | 1 +
> .../gpu/drm/i915/display/intel_dmc_wl_debugfs.c | 16 +++++++++++++++-
> 3 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
> index c4f1ab43fc0c..bc36d1b0ef87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
> @@ -133,6 +133,11 @@ intel_display_param_named_unsafe(enable_dmc_wl, int, 0400,
> "(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register, 3=always locked) "
> "Default: -1");
>
> +intel_display_param_named_unsafe(enable_dmc_wl_debugfs, bool, 0400,
> + "Enable DMC wakelock debugfs"
> + "(0=disabled, 1=enabled) "
> + "Default: 0");
> +
> __maybe_unused
> static void _param_print_bool(struct drm_printer *p, const char *driver_name,
> const char *name, bool val)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
> index 5317138e6044..cb7dc1bc6846 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.h
> @@ -48,6 +48,7 @@ struct drm_printer;
> param(bool, psr_safest_params, false, 0400) \
> param(bool, enable_psr2_sel_fetch, true, 0400) \
> param(int, enable_dmc_wl, -1, 0400) \
> + param(bool, enable_dmc_wl_debugfs, false, 0400) \
>
> #define MEMBER(T, member, ...) T member;
> struct intel_display_params {
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> index 1493d296ac98..f4e4c7a5a730 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> @@ -37,6 +37,9 @@
> * which exports a buffer of untracked register offsets and also allows extra
> * register offsets to be tracked by the driver.
> *
> + * The debugfs directory is only exported if the module parameter
> + * enable_dmc_wl_debugfs=1 is passed.
> + *
> * Untracked offsets
> * -----------------
> *
> @@ -411,6 +414,9 @@ void intel_dmc_wl_debugfs_register(struct intel_display *display)
> {
> struct dentry *dir;
>
> + if (!display->params.enable_dmc_wl_debugfs)
> + return;
> +
> if (!HAS_DMC_WAKELOCK(display))
> return;
>
> @@ -453,6 +459,9 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> unsigned long flags;
>
> + if (!display->params.enable_dmc_wl_debugfs)
> + return;
> +
> spin_lock_irqsave(&dbg->lock, flags);
>
> if (!dbg->untracked.size)
> @@ -479,9 +488,14 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
> bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
> {
> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> - bool ret = false;
> + bool ret;
> unsigned long flags;
>
> + if (!display->params.enable_dmc_wl_debugfs)
> + return false;
> +
> + ret = false;
> +
> spin_lock_irqsave(&dbg->lock, flags);
>
> if (!dbg->extra_ranges)
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1
2025-01-27 12:01 ` Jani Nikula
@ 2025-01-27 12:02 ` Jani Nikula
2025-01-27 13:24 ` Gustavo Sousa
1 sibling, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2025-01-27 12:02 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On Mon, 27 Jan 2025, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Fri, 17 Jan 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> We use a spinlock to protect DMC wakelock debugfs data, since it is also
>> accessed by the core DMC wakelock logic. Taking the spinlock when the
>> debugfs is not in use introduces a small but unnecessary penalty.
>>
>> Since the debugfs functionality is only expected to be used for, uh,
>> debugging sessions, let's protect it behind a module parameter
>> enable_dmc_wl_debugfs. That way, we only take the lock if the feature
>> was enabled in the first place.
>
> If the debug struct were an opaque pointer, you could check for that
> being != NULL. Register the debugfs always, and have that initialize
> everything as needed?
...the underlying point being that I'm generally against adding any new
module parameters.
BR,
Jani.
>
> BR,
> Jani.
>
>>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>> .../gpu/drm/i915/display/intel_display_params.c | 5 +++++
>> .../gpu/drm/i915/display/intel_display_params.h | 1 +
>> .../gpu/drm/i915/display/intel_dmc_wl_debugfs.c | 16 +++++++++++++++-
>> 3 files changed, 21 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
>> index c4f1ab43fc0c..bc36d1b0ef87 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
>> @@ -133,6 +133,11 @@ intel_display_param_named_unsafe(enable_dmc_wl, int, 0400,
>> "(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register, 3=always locked) "
>> "Default: -1");
>>
>> +intel_display_param_named_unsafe(enable_dmc_wl_debugfs, bool, 0400,
>> + "Enable DMC wakelock debugfs"
>> + "(0=disabled, 1=enabled) "
>> + "Default: 0");
>> +
>> __maybe_unused
>> static void _param_print_bool(struct drm_printer *p, const char *driver_name,
>> const char *name, bool val)
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
>> index 5317138e6044..cb7dc1bc6846 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_params.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_params.h
>> @@ -48,6 +48,7 @@ struct drm_printer;
>> param(bool, psr_safest_params, false, 0400) \
>> param(bool, enable_psr2_sel_fetch, true, 0400) \
>> param(int, enable_dmc_wl, -1, 0400) \
>> + param(bool, enable_dmc_wl_debugfs, false, 0400) \
>>
>> #define MEMBER(T, member, ...) T member;
>> struct intel_display_params {
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>> index 1493d296ac98..f4e4c7a5a730 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>> @@ -37,6 +37,9 @@
>> * which exports a buffer of untracked register offsets and also allows extra
>> * register offsets to be tracked by the driver.
>> *
>> + * The debugfs directory is only exported if the module parameter
>> + * enable_dmc_wl_debugfs=1 is passed.
>> + *
>> * Untracked offsets
>> * -----------------
>> *
>> @@ -411,6 +414,9 @@ void intel_dmc_wl_debugfs_register(struct intel_display *display)
>> {
>> struct dentry *dir;
>>
>> + if (!display->params.enable_dmc_wl_debugfs)
>> + return;
>> +
>> if (!HAS_DMC_WAKELOCK(display))
>> return;
>>
>> @@ -453,6 +459,9 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
>> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> unsigned long flags;
>>
>> + if (!display->params.enable_dmc_wl_debugfs)
>> + return;
>> +
>> spin_lock_irqsave(&dbg->lock, flags);
>>
>> if (!dbg->untracked.size)
>> @@ -479,9 +488,14 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
>> bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
>> {
>> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> - bool ret = false;
>> + bool ret;
>> unsigned long flags;
>>
>> + if (!display->params.enable_dmc_wl_debugfs)
>> + return false;
>> +
>> + ret = false;
>> +
>> spin_lock_irqsave(&dbg->lock, flags);
>>
>> if (!dbg->extra_ranges)
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets
2025-01-27 11:59 ` Jani Nikula
@ 2025-01-27 12:55 ` Gustavo Sousa
0 siblings, 0 replies; 35+ messages in thread
From: Gustavo Sousa @ 2025-01-27 12:55 UTC (permalink / raw)
To: Jani Nikula, intel-gfx, intel-xe
Quoting Jani Nikula (2025-01-27 08:59:11-03:00)
>On Mon, 27 Jan 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> Quoting Jani Nikula (2025-01-27 06:47:58-03:00)
>>>On Fri, 17 Jan 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.h b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>>>> index 5488fbdf29b8..d11b0ab50b3c 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>>>> @@ -11,6 +11,7 @@
>>>> #include <linux/refcount.h>
>>>>
>>>> #include "i915_reg_defs.h"
>>>> +#include "intel_dmc_wl_debugfs.h"
>>>>
>>>> struct intel_display;
>>>>
>>>> @@ -27,6 +28,7 @@ struct intel_dmc_wl {
>>>> */
>>>> u32 dc_state;
>>>> struct delayed_work work;
>>>> + struct intel_dmc_wl_dbg dbg;
>>>> };
>>>>
>>>
>>>With intel_de.h including intel_dmc_wl.h, we'll have almost all of
>>>display include intel_dmc_wl_debugfs.h, and getting the definition of
>>>struct intel_dmc_wl_dbg, really for no good reason.
>>>
>>>I really like to flip this around. You need to have a *good reason* to
>>>expose stuff to the entire display driver all of a sudden. Instead of
>>>requiring a good reason to hide stuff.
>>
>> Maybe make dbg a pointer and have only intel_dmc_wl.c knowing its guts?
>>
>> Or do you have some other suggestion?
>
>Yes, using an opaque pointer is usually the way to go.
Okay. I was hoping not to have to have a separate dynamic memory
allocation for it, but that works and helps isolating the definition.
>
>Lately we've been adding debugfs next to the implementation. Often the
>debugfs needs access to the same stuff as the implementation, you can
>hide stuff and not have to expose a ton of interfaces. This could work
>here too... but I have to say this debugfs looks a bit, uh, bloated for
>want of a better word. Maybe having the separate file is worth it.
Yep, I do think it deserves a separate file.
--
Gustavo Sousa
>
>BR,
>Jani.
>
>
>>
>> --
>> Gustavo Sousa
>>
>>>
>>>BR,
>>>Jani.
>>>
>>>
>>>
>>>> void intel_dmc_wl_init(struct intel_display *display);
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>>>> new file mode 100644
>>>> index 000000000000..41e59d775fe5
>>>> --- /dev/null
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>>>> @@ -0,0 +1,251 @@
>>>> +// SPDX-License-Identifier: MIT
>>>> +/*
>>>> + * Copyright (C) 2025 Intel Corporation
>>>> + */
>>>> +
>>>> +#include <linux/debugfs.h>
>>>> +
>>>> +#include <drm/drm_device.h>
>>>> +#include <drm/drm_managed.h>
>>>> +#include <drm/drm_print.h>
>>>> +
>>>> +#include "intel_display_core.h"
>>>> +#include "intel_dmc_wl_debugfs.h"
>>>> +
>>>> +#define DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX 65536
>>>> +
>>>> +/*
>>>> + * DOC: DMC wakelock debugfs
>>>> + *
>>>> + * The DMC wakelock code needs to keep track of register offsets that need the
>>>> + * wakelock for proper access. If one of the necessary offsets are missed, then
>>>> + * the failure in asserting the wakelock is very likely to cause problems down
>>>> + * the road.
>>>> + *
>>>> + * A miss could happen for at least two different reasons:
>>>> + *
>>>> + * - We might have forgotten to add the offset (or range) to the relevant
>>>> + * tables tracked by the driver in the first place.
>>>> + *
>>>> + * - Or updates to either the DMC firmware or the display IP that require new
>>>> + * offsets to be tracked and we fail to realize that.
>>>> + *
>>>> + * To help capture these cases, we provide the intel_dmc_wl/ debugfs directory,
>>>> + * which exports a buffer of untracked register offsets.
>>>> + *
>>>> + * Untracked offsets
>>>> + * -----------------
>>>> + *
>>>> + * This is a buffer that records every register offset that went through the
>>>> + * DMC wakelock check and was deemed not needing the wakelock for MMIO access.
>>>> + *
>>>> + * To activate the logging of offsets into such a buffer, one can do::
>>>> + *
>>>> + * # echo -1 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
>>>> + *
>>>> + * This will create a buffer with the maximum number of entries allowed
>>>> + * (DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX). A positive value can be used instead to
>>>> + * define a different size:
>>>> + *
>>>> + * # echo 1024 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
>>>> + *
>>>> + * Every write to untracked_size will cause the buffer to be reset.
>>>> + *
>>>> + * It is also possible to read untracked_size in order to get the current
>>>> + * value.
>>>> + *
>>>> + * After enabled, the buffer starts getting filled with offsets as MMIOs are
>>>> + * performed by the driver.
>>>> + *
>>>> + * In order to view the content of the buffer, one can do::
>>>> + *
>>>> + * # cat /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked
>>>> + * 0x000c4000
>>>> + * 0x0016fe50
>>>> + * 0x000c7200
>>>> + * 0x000c7204
>>>> + * 0x00045230
>>>> + * 0x00046440
>>>> + * 0x00045234
>>>> + * 0x0016fa48
>>>> + * 0x0016fa40
>>>> + * 0x0016fa5c
>>>> + * (...)
>>>> + *
>>>> + * The order of those offsets does not reflect the order the checks were done
>>>> + * (some recently seen offsets are skipped to save space).
>>>> + *
>>>> + * Once done with it, the logging can be disabled with::
>>>> + *
>>>> + * # echo 0 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
>>>> + */
>>>> +
>>>> +static int untracked_size_get(void *data, u64 *val)
>>>> +{
>>>> + struct intel_display *display = data;
>>>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>>> + unsigned long flags;
>>>> +
>>>> + spin_lock_irqsave(&dbg->lock, flags);
>>>> + *val = dbg->untracked.size;
>>>> + spin_unlock_irqrestore(&dbg->lock, flags);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int untracked_size_set(void *data, u64 val)
>>>> +{
>>>> + struct intel_display *display = data;
>>>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>>> + s64 new_size;
>>>> + u32 *old_offsets;
>>>> + u32 *new_offsets;
>>>> + unsigned long flags;
>>>> +
>>>> + new_size = (s64)val;
>>>> +
>>>> + if (new_size == -1) {
>>>> + new_size = DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX;
>>>> + } else if (new_size < 0) {
>>>> + drm_err(display->drm,
>>>> + "%lld is invalid for untracked_size, the only negative value allowed is -1\n",
>>>> + new_size);
>>>> + return -EINVAL;
>>>> + } else if (new_size > DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX) {
>>>> + drm_err(display->drm,
>>>> + "%lld too big for untracked_size, maximum allowed value is %d\n",
>>>> + new_size,
>>>> + DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX);
>>>> + return -EINVAL;
>>>> + }
>>>> +
>>>> + if (new_size == 0) {
>>>> + new_offsets = NULL;
>>>> + } else {
>>>> + new_offsets = drmm_kmalloc_array(display->drm, new_size, sizeof(*new_offsets),
>>>> + GFP_KERNEL);
>>>> +
>>>> + if (!new_offsets)
>>>> + return -ENOMEM;
>>>> + }
>>>> +
>>>> + spin_lock_irqsave(&dbg->lock, flags);
>>>> + old_offsets = dbg->untracked.offsets;
>>>> + dbg->untracked.offsets = new_offsets;
>>>> + dbg->untracked.size = new_size;
>>>> + dbg->untracked.head = 0;
>>>> + dbg->untracked.len = 0;
>>>> + dbg->untracked.overflow = false;
>>>> + spin_unlock_irqrestore(&dbg->lock, flags);
>>>> +
>>>> + if (old_offsets)
>>>> + drmm_kfree(display->drm, old_offsets);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +DEFINE_SIMPLE_ATTRIBUTE_SIGNED(untracked_size_fops,
>>>> + untracked_size_get,
>>>> + untracked_size_set,
>>>> + "%lld\n");
>>>> +
>>>> +static int untracked_show(struct seq_file *m, void *data)
>>>> +{
>>>> + struct intel_display *display = m->private;
>>>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>>> + unsigned long flags;
>>>> + size_t remaining;
>>>> + size_t i;
>>>> +
>>>> + spin_lock_irqsave(&dbg->lock, flags);
>>>> +
>>>> + remaining = dbg->untracked.len;
>>>> + i = dbg->untracked.head;
>>>> +
>>>> + while (remaining--) {
>>>> + if (i == 0)
>>>> + i = dbg->untracked.size;
>>>> +
>>>> + seq_printf(m, "0x%08x\n", dbg->untracked.offsets[--i]);
>>>> + }
>>>> +
>>>> + spin_unlock_irqrestore(&dbg->lock, flags);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +DEFINE_SHOW_ATTRIBUTE(untracked);
>>>> +
>>>> +void intel_dmc_wl_debugfs_init(struct intel_display *display)
>>>> +{
>>>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>>> +
>>>> + spin_lock_init(&dbg->lock);
>>>> +}
>>>> +
>>>> +void intel_dmc_wl_debugfs_register(struct intel_display *display)
>>>> +{
>>>> + struct dentry *dir;
>>>> +
>>>> + if (!HAS_DMC_WAKELOCK(display))
>>>> + return;
>>>> +
>>>> + dir = debugfs_create_dir("intel_dmc_wl", display->drm->debugfs_root);
>>>> + if (IS_ERR(dir))
>>>> + return;
>>>> +
>>>> + debugfs_create_file("untracked_size", 0644, dir, display,
>>>> + &untracked_size_fops);
>>>> + debugfs_create_file("untracked", 0644, dir, display,
>>>> + &untracked_fops);
>>>> +}
>>>> +
>>>> +static bool untracked_has_recent_offset(struct intel_display *display, u32 offset)
>>>> +{
>>>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>>> + int look_back = 32;
>>>> + size_t i;
>>>> +
>>>> + if (look_back > dbg->untracked.len)
>>>> + look_back = dbg->untracked.len;
>>>> +
>>>> + i = dbg->untracked.head;
>>>> +
>>>> + while (look_back--) {
>>>> + if (i == 0)
>>>> + i = dbg->untracked.size;
>>>> +
>>>> + if (dbg->untracked.offsets[--i] == offset)
>>>> + return true;
>>>> + }
>>>> +
>>>> + return false;
>>>> +}
>>>> +
>>>> +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset)
>>>> +{
>>>> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>>> + unsigned long flags;
>>>> +
>>>> + spin_lock_irqsave(&dbg->lock, flags);
>>>> +
>>>> + if (!dbg->untracked.size)
>>>> + goto out_unlock;
>>>> +
>>>> + /* Save some space by not repeating recent offsets. */
>>>> + if (untracked_has_recent_offset(display, offset))
>>>> + goto out_unlock;
>>>> +
>>>> + dbg->untracked.offsets[dbg->untracked.head] = offset;
>>>> + dbg->untracked.head = (dbg->untracked.head + 1) % dbg->untracked.size;
>>>> + if (dbg->untracked.len < dbg->untracked.size)
>>>> + dbg->untracked.len++;
>>>> +
>>>> + if (dbg->untracked.len == dbg->untracked.size && !dbg->untracked.overflow) {
>>>> + dbg->untracked.overflow = true;
>>>> + drm_warn(display->drm, "Overflow detected in DMC wakelock debugfs untracked offsets\n");
>>>> + }
>>>> +
>>>> +out_unlock:
>>>> + spin_unlock_irqrestore(&dbg->lock, flags);
>>>> +}
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
>>>> new file mode 100644
>>>> index 000000000000..9437c324966f
>>>> --- /dev/null
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
>>>> @@ -0,0 +1,29 @@
>>>> +/* SPDX-License-Identifier: MIT */
>>>> +/*
>>>> + * Copyright (C) 2025 Intel Corporation
>>>> + */
>>>> +
>>>> +#ifndef __INTEL_DMC_WL_DEBUGFS_H__
>>>> +#define __INTEL_DMC_WL_DEBUGFS_H__
>>>> +
>>>> +#include <linux/types.h>
>>>> +#include <linux/spinlock.h>
>>>> +
>>>> +struct intel_display;
>>>> +
>>>> +struct intel_dmc_wl_dbg {
>>>> + spinlock_t lock; /* protects everything below */
>>>> + struct {
>>>> + u32 *offsets;
>>>> + size_t head;
>>>> + size_t len;
>>>> + size_t size;
>>>> + bool overflow;
>>>> + } untracked;
>>>> +};
>>>> +
>>>> +void intel_dmc_wl_debugfs_init(struct intel_display *display);
>>>> +void intel_dmc_wl_debugfs_register(struct intel_display *display);
>>>> +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset);
>>>> +
>>>> +#endif /* __INTEL_DMC_WL_DEBUGFS_H__ */
>>>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>>>> index 81f63258a7e1..f03fbdbcb1a4 100644
>>>> --- a/drivers/gpu/drm/xe/Makefile
>>>> +++ b/drivers/gpu/drm/xe/Makefile
>>>> @@ -221,6 +221,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>>>> i915-display/intel_display_wa.o \
>>>> i915-display/intel_dkl_phy.o \
>>>> i915-display/intel_dmc.o \
>>>> + i915-display/intel_dmc_wl_debugfs.o \
>>>> i915-display/intel_dp.o \
>>>> i915-display/intel_dp_aux.o \
>>>> i915-display/intel_dp_aux_backlight.o \
>>>
>>>--
>>>Jani Nikula, Intel
>
>--
>Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1
2025-01-27 12:01 ` Jani Nikula
2025-01-27 12:02 ` Jani Nikula
@ 2025-01-27 13:24 ` Gustavo Sousa
2025-01-27 13:35 ` Jani Nikula
1 sibling, 1 reply; 35+ messages in thread
From: Gustavo Sousa @ 2025-01-27 13:24 UTC (permalink / raw)
To: Jani Nikula, intel-gfx, intel-xe
Quoting Jani Nikula (2025-01-27 09:01:39-03:00)
>On Fri, 17 Jan 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> We use a spinlock to protect DMC wakelock debugfs data, since it is also
>> accessed by the core DMC wakelock logic. Taking the spinlock when the
>> debugfs is not in use introduces a small but unnecessary penalty.
>>
>> Since the debugfs functionality is only expected to be used for, uh,
>> debugging sessions, let's protect it behind a module parameter
>> enable_dmc_wl_debugfs. That way, we only take the lock if the feature
>> was enabled in the first place.
>
>If the debug struct were an opaque pointer, you could check for that
>being != NULL. Register the debugfs always, and have that initialize
>everything as needed?
Hm... I'm failing to see how this would keep us from having to take the
spinlock once we have the pointer being non-NULL.
The idea of the parameter is to protect us from taking the spinlock when
we are not debugging DMC wakelock offsets.
--
Gustavo Sousa
>
>BR,
>Jani.
>
>>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>> .../gpu/drm/i915/display/intel_display_params.c | 5 +++++
>> .../gpu/drm/i915/display/intel_display_params.h | 1 +
>> .../gpu/drm/i915/display/intel_dmc_wl_debugfs.c | 16 +++++++++++++++-
>> 3 files changed, 21 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
>> index c4f1ab43fc0c..bc36d1b0ef87 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
>> @@ -133,6 +133,11 @@ intel_display_param_named_unsafe(enable_dmc_wl, int, 0400,
>> "(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register, 3=always locked) "
>> "Default: -1");
>>
>> +intel_display_param_named_unsafe(enable_dmc_wl_debugfs, bool, 0400,
>> + "Enable DMC wakelock debugfs"
>> + "(0=disabled, 1=enabled) "
>> + "Default: 0");
>> +
>> __maybe_unused
>> static void _param_print_bool(struct drm_printer *p, const char *driver_name,
>> const char *name, bool val)
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
>> index 5317138e6044..cb7dc1bc6846 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_params.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_params.h
>> @@ -48,6 +48,7 @@ struct drm_printer;
>> param(bool, psr_safest_params, false, 0400) \
>> param(bool, enable_psr2_sel_fetch, true, 0400) \
>> param(int, enable_dmc_wl, -1, 0400) \
>> + param(bool, enable_dmc_wl_debugfs, false, 0400) \
>>
>> #define MEMBER(T, member, ...) T member;
>> struct intel_display_params {
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>> index 1493d296ac98..f4e4c7a5a730 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>> @@ -37,6 +37,9 @@
>> * which exports a buffer of untracked register offsets and also allows extra
>> * register offsets to be tracked by the driver.
>> *
>> + * The debugfs directory is only exported if the module parameter
>> + * enable_dmc_wl_debugfs=1 is passed.
>> + *
>> * Untracked offsets
>> * -----------------
>> *
>> @@ -411,6 +414,9 @@ void intel_dmc_wl_debugfs_register(struct intel_display *display)
>> {
>> struct dentry *dir;
>>
>> + if (!display->params.enable_dmc_wl_debugfs)
>> + return;
>> +
>> if (!HAS_DMC_WAKELOCK(display))
>> return;
>>
>> @@ -453,6 +459,9 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
>> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> unsigned long flags;
>>
>> + if (!display->params.enable_dmc_wl_debugfs)
>> + return;
>> +
>> spin_lock_irqsave(&dbg->lock, flags);
>>
>> if (!dbg->untracked.size)
>> @@ -479,9 +488,14 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
>> bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
>> {
>> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>> - bool ret = false;
>> + bool ret;
>> unsigned long flags;
>>
>> + if (!display->params.enable_dmc_wl_debugfs)
>> + return false;
>> +
>> + ret = false;
>> +
>> spin_lock_irqsave(&dbg->lock, flags);
>>
>> if (!dbg->extra_ranges)
>
>--
>Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1
2025-01-27 13:24 ` Gustavo Sousa
@ 2025-01-27 13:35 ` Jani Nikula
2025-01-27 13:50 ` Gustavo Sousa
0 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2025-01-27 13:35 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On Mon, 27 Jan 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> Quoting Jani Nikula (2025-01-27 09:01:39-03:00)
>>On Fri, 17 Jan 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>>> We use a spinlock to protect DMC wakelock debugfs data, since it is also
>>> accessed by the core DMC wakelock logic. Taking the spinlock when the
>>> debugfs is not in use introduces a small but unnecessary penalty.
>>>
>>> Since the debugfs functionality is only expected to be used for, uh,
>>> debugging sessions, let's protect it behind a module parameter
>>> enable_dmc_wl_debugfs. That way, we only take the lock if the feature
>>> was enabled in the first place.
>>
>>If the debug struct were an opaque pointer, you could check for that
>>being != NULL. Register the debugfs always, and have that initialize
>>everything as needed?
>
> Hm... I'm failing to see how this would keep us from having to take the
> spinlock once we have the pointer being non-NULL.
>
> The idea of the parameter is to protect us from taking the spinlock when
> we are not debugging DMC wakelock offsets.
If you only allocate and assign the pointer when you enable the feature
via debugfs, wouldn't that achieve the goal?
BR,
Jani.
>
> --
> Gustavo Sousa
>
>>
>>BR,
>>Jani.
>>
>>>
>>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>> ---
>>> .../gpu/drm/i915/display/intel_display_params.c | 5 +++++
>>> .../gpu/drm/i915/display/intel_display_params.h | 1 +
>>> .../gpu/drm/i915/display/intel_dmc_wl_debugfs.c | 16 +++++++++++++++-
>>> 3 files changed, 21 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
>>> index c4f1ab43fc0c..bc36d1b0ef87 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
>>> @@ -133,6 +133,11 @@ intel_display_param_named_unsafe(enable_dmc_wl, int, 0400,
>>> "(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register, 3=always locked) "
>>> "Default: -1");
>>>
>>> +intel_display_param_named_unsafe(enable_dmc_wl_debugfs, bool, 0400,
>>> + "Enable DMC wakelock debugfs"
>>> + "(0=disabled, 1=enabled) "
>>> + "Default: 0");
>>> +
>>> __maybe_unused
>>> static void _param_print_bool(struct drm_printer *p, const char *driver_name,
>>> const char *name, bool val)
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
>>> index 5317138e6044..cb7dc1bc6846 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_params.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_params.h
>>> @@ -48,6 +48,7 @@ struct drm_printer;
>>> param(bool, psr_safest_params, false, 0400) \
>>> param(bool, enable_psr2_sel_fetch, true, 0400) \
>>> param(int, enable_dmc_wl, -1, 0400) \
>>> + param(bool, enable_dmc_wl_debugfs, false, 0400) \
>>>
>>> #define MEMBER(T, member, ...) T member;
>>> struct intel_display_params {
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>>> index 1493d296ac98..f4e4c7a5a730 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>>> @@ -37,6 +37,9 @@
>>> * which exports a buffer of untracked register offsets and also allows extra
>>> * register offsets to be tracked by the driver.
>>> *
>>> + * The debugfs directory is only exported if the module parameter
>>> + * enable_dmc_wl_debugfs=1 is passed.
>>> + *
>>> * Untracked offsets
>>> * -----------------
>>> *
>>> @@ -411,6 +414,9 @@ void intel_dmc_wl_debugfs_register(struct intel_display *display)
>>> {
>>> struct dentry *dir;
>>>
>>> + if (!display->params.enable_dmc_wl_debugfs)
>>> + return;
>>> +
>>> if (!HAS_DMC_WAKELOCK(display))
>>> return;
>>>
>>> @@ -453,6 +459,9 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
>>> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>> unsigned long flags;
>>>
>>> + if (!display->params.enable_dmc_wl_debugfs)
>>> + return;
>>> +
>>> spin_lock_irqsave(&dbg->lock, flags);
>>>
>>> if (!dbg->untracked.size)
>>> @@ -479,9 +488,14 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
>>> bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
>>> {
>>> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>> - bool ret = false;
>>> + bool ret;
>>> unsigned long flags;
>>>
>>> + if (!display->params.enable_dmc_wl_debugfs)
>>> + return false;
>>> +
>>> + ret = false;
>>> +
>>> spin_lock_irqsave(&dbg->lock, flags);
>>>
>>> if (!dbg->extra_ranges)
>>
>>--
>>Jani Nikula, Intel
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1
2025-01-27 13:35 ` Jani Nikula
@ 2025-01-27 13:50 ` Gustavo Sousa
2025-01-27 14:40 ` Jani Nikula
0 siblings, 1 reply; 35+ messages in thread
From: Gustavo Sousa @ 2025-01-27 13:50 UTC (permalink / raw)
To: Jani Nikula, intel-gfx, intel-xe
Quoting Jani Nikula (2025-01-27 10:35:57-03:00)
>On Mon, 27 Jan 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> Quoting Jani Nikula (2025-01-27 09:01:39-03:00)
>>>On Fri, 17 Jan 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>>>> We use a spinlock to protect DMC wakelock debugfs data, since it is also
>>>> accessed by the core DMC wakelock logic. Taking the spinlock when the
>>>> debugfs is not in use introduces a small but unnecessary penalty.
>>>>
>>>> Since the debugfs functionality is only expected to be used for, uh,
>>>> debugging sessions, let's protect it behind a module parameter
>>>> enable_dmc_wl_debugfs. That way, we only take the lock if the feature
>>>> was enabled in the first place.
>>>
>>>If the debug struct were an opaque pointer, you could check for that
>>>being != NULL. Register the debugfs always, and have that initialize
>>>everything as needed?
>>
>> Hm... I'm failing to see how this would keep us from having to take the
>> spinlock once we have the pointer being non-NULL.
>>
>> The idea of the parameter is to protect us from taking the spinlock when
>> we are not debugging DMC wakelock offsets.
>
>If you only allocate and assign the pointer when you enable the feature
>via debugfs, wouldn't that achieve the goal?
But then how are we going to protect ourselves from races when checking
the pointer for NULL-ness?
Maybe I'm missing some technical background here...
Is there a way to atomically do that without a lock?
Could RCU (which I still need to learn) help somehow here?
--
Gustavo Sousa
>
>BR,
>Jani.
>
>>
>> --
>> Gustavo Sousa
>>
>>>
>>>BR,
>>>Jani.
>>>
>>>>
>>>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>>> ---
>>>> .../gpu/drm/i915/display/intel_display_params.c | 5 +++++
>>>> .../gpu/drm/i915/display/intel_display_params.h | 1 +
>>>> .../gpu/drm/i915/display/intel_dmc_wl_debugfs.c | 16 +++++++++++++++-
>>>> 3 files changed, 21 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
>>>> index c4f1ab43fc0c..bc36d1b0ef87 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
>>>> @@ -133,6 +133,11 @@ intel_display_param_named_unsafe(enable_dmc_wl, int, 0400,
>>>> "(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register, 3=always locked) "
>>>> "Default: -1");
>>>>
>>>> +intel_display_param_named_unsafe(enable_dmc_wl_debugfs, bool, 0400,
>>>> + "Enable DMC wakelock debugfs"
>>>> + "(0=disabled, 1=enabled) "
>>>> + "Default: 0");
>>>> +
>>>> __maybe_unused
>>>> static void _param_print_bool(struct drm_printer *p, const char *driver_name,
>>>> const char *name, bool val)
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
>>>> index 5317138e6044..cb7dc1bc6846 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display_params.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_params.h
>>>> @@ -48,6 +48,7 @@ struct drm_printer;
>>>> param(bool, psr_safest_params, false, 0400) \
>>>> param(bool, enable_psr2_sel_fetch, true, 0400) \
>>>> param(int, enable_dmc_wl, -1, 0400) \
>>>> + param(bool, enable_dmc_wl_debugfs, false, 0400) \
>>>>
>>>> #define MEMBER(T, member, ...) T member;
>>>> struct intel_display_params {
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>>>> index 1493d296ac98..f4e4c7a5a730 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>>>> @@ -37,6 +37,9 @@
>>>> * which exports a buffer of untracked register offsets and also allows extra
>>>> * register offsets to be tracked by the driver.
>>>> *
>>>> + * The debugfs directory is only exported if the module parameter
>>>> + * enable_dmc_wl_debugfs=1 is passed.
>>>> + *
>>>> * Untracked offsets
>>>> * -----------------
>>>> *
>>>> @@ -411,6 +414,9 @@ void intel_dmc_wl_debugfs_register(struct intel_display *display)
>>>> {
>>>> struct dentry *dir;
>>>>
>>>> + if (!display->params.enable_dmc_wl_debugfs)
>>>> + return;
>>>> +
>>>> if (!HAS_DMC_WAKELOCK(display))
>>>> return;
>>>>
>>>> @@ -453,6 +459,9 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
>>>> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>>> unsigned long flags;
>>>>
>>>> + if (!display->params.enable_dmc_wl_debugfs)
>>>> + return;
>>>> +
>>>> spin_lock_irqsave(&dbg->lock, flags);
>>>>
>>>> if (!dbg->untracked.size)
>>>> @@ -479,9 +488,14 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
>>>> bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
>>>> {
>>>> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>>> - bool ret = false;
>>>> + bool ret;
>>>> unsigned long flags;
>>>>
>>>> + if (!display->params.enable_dmc_wl_debugfs)
>>>> + return false;
>>>> +
>>>> + ret = false;
>>>> +
>>>> spin_lock_irqsave(&dbg->lock, flags);
>>>>
>>>> if (!dbg->extra_ranges)
>>>
>>>--
>>>Jani Nikula, Intel
>
>--
>Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1
2025-01-27 13:50 ` Gustavo Sousa
@ 2025-01-27 14:40 ` Jani Nikula
0 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2025-01-27 14:40 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On Mon, 27 Jan 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> Quoting Jani Nikula (2025-01-27 10:35:57-03:00)
>>On Mon, 27 Jan 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>>> Quoting Jani Nikula (2025-01-27 09:01:39-03:00)
>>>>On Fri, 17 Jan 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>>>>> We use a spinlock to protect DMC wakelock debugfs data, since it is also
>>>>> accessed by the core DMC wakelock logic. Taking the spinlock when the
>>>>> debugfs is not in use introduces a small but unnecessary penalty.
>>>>>
>>>>> Since the debugfs functionality is only expected to be used for, uh,
>>>>> debugging sessions, let's protect it behind a module parameter
>>>>> enable_dmc_wl_debugfs. That way, we only take the lock if the feature
>>>>> was enabled in the first place.
>>>>
>>>>If the debug struct were an opaque pointer, you could check for that
>>>>being != NULL. Register the debugfs always, and have that initialize
>>>>everything as needed?
>>>
>>> Hm... I'm failing to see how this would keep us from having to take the
>>> spinlock once we have the pointer being non-NULL.
>>>
>>> The idea of the parameter is to protect us from taking the spinlock when
>>> we are not debugging DMC wakelock offsets.
>>
>>If you only allocate and assign the pointer when you enable the feature
>>via debugfs, wouldn't that achieve the goal?
>
> But then how are we going to protect ourselves from races when checking
> the pointer for NULL-ness?
If you don't allow dynamically disabling and freeing the stuff, except
at takedown, where's the race?
BR,
Jani.
>
> Maybe I'm missing some technical background here...
>
> Is there a way to atomically do that without a lock?
>
> Could RCU (which I still need to learn) help somehow here?
>
> --
> Gustavo Sousa
>
>>
>>BR,
>>Jani.
>>
>>>
>>> --
>>> Gustavo Sousa
>>>
>>>>
>>>>BR,
>>>>Jani.
>>>>
>>>>>
>>>>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>>>> ---
>>>>> .../gpu/drm/i915/display/intel_display_params.c | 5 +++++
>>>>> .../gpu/drm/i915/display/intel_display_params.h | 1 +
>>>>> .../gpu/drm/i915/display/intel_dmc_wl_debugfs.c | 16 +++++++++++++++-
>>>>> 3 files changed, 21 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
>>>>> index c4f1ab43fc0c..bc36d1b0ef87 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
>>>>> @@ -133,6 +133,11 @@ intel_display_param_named_unsafe(enable_dmc_wl, int, 0400,
>>>>> "(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register, 3=always locked) "
>>>>> "Default: -1");
>>>>>
>>>>> +intel_display_param_named_unsafe(enable_dmc_wl_debugfs, bool, 0400,
>>>>> + "Enable DMC wakelock debugfs"
>>>>> + "(0=disabled, 1=enabled) "
>>>>> + "Default: 0");
>>>>> +
>>>>> __maybe_unused
>>>>> static void _param_print_bool(struct drm_printer *p, const char *driver_name,
>>>>> const char *name, bool val)
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
>>>>> index 5317138e6044..cb7dc1bc6846 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_display_params.h
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_params.h
>>>>> @@ -48,6 +48,7 @@ struct drm_printer;
>>>>> param(bool, psr_safest_params, false, 0400) \
>>>>> param(bool, enable_psr2_sel_fetch, true, 0400) \
>>>>> param(int, enable_dmc_wl, -1, 0400) \
>>>>> + param(bool, enable_dmc_wl_debugfs, false, 0400) \
>>>>>
>>>>> #define MEMBER(T, member, ...) T member;
>>>>> struct intel_display_params {
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>>>>> index 1493d296ac98..f4e4c7a5a730 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
>>>>> @@ -37,6 +37,9 @@
>>>>> * which exports a buffer of untracked register offsets and also allows extra
>>>>> * register offsets to be tracked by the driver.
>>>>> *
>>>>> + * The debugfs directory is only exported if the module parameter
>>>>> + * enable_dmc_wl_debugfs=1 is passed.
>>>>> + *
>>>>> * Untracked offsets
>>>>> * -----------------
>>>>> *
>>>>> @@ -411,6 +414,9 @@ void intel_dmc_wl_debugfs_register(struct intel_display *display)
>>>>> {
>>>>> struct dentry *dir;
>>>>>
>>>>> + if (!display->params.enable_dmc_wl_debugfs)
>>>>> + return;
>>>>> +
>>>>> if (!HAS_DMC_WAKELOCK(display))
>>>>> return;
>>>>>
>>>>> @@ -453,6 +459,9 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
>>>>> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>>>> unsigned long flags;
>>>>>
>>>>> + if (!display->params.enable_dmc_wl_debugfs)
>>>>> + return;
>>>>> +
>>>>> spin_lock_irqsave(&dbg->lock, flags);
>>>>>
>>>>> if (!dbg->untracked.size)
>>>>> @@ -479,9 +488,14 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
>>>>> bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
>>>>> {
>>>>> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
>>>>> - bool ret = false;
>>>>> + bool ret;
>>>>> unsigned long flags;
>>>>>
>>>>> + if (!display->params.enable_dmc_wl_debugfs)
>>>>> + return false;
>>>>> +
>>>>> + ret = false;
>>>>> +
>>>>> spin_lock_irqsave(&dbg->lock, flags);
>>>>>
>>>>> if (!dbg->extra_ranges)
>>>>
>>>>--
>>>>Jani Nikula, Intel
>>
>>--
>>Jani Nikula, Intel
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 3/4] drm/i915/dmc_wl: Add extra_ranges debugfs
2025-01-17 22:06 ` [PATCH 3/4] drm/i915/dmc_wl: Add extra_ranges debugfs Gustavo Sousa
2025-01-22 10:19 ` Luca Coelho
@ 2025-01-30 8:30 ` Vivekanandan, Balasubramani
2025-01-30 8:49 ` Vivekanandan, Balasubramani
1 sibling, 1 reply; 35+ messages in thread
From: Vivekanandan, Balasubramani @ 2025-01-30 8:30 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On 17.01.2025 19:06, Gustavo Sousa wrote:
> We already have a way of finding the set of untracked offsets for which
> there has been one or more MMIO operations via the
> "intel_dmc_wl/untracked" debugfs interface.
>
> However, in order to try adding one or more of those registers to the
> set of tracked offsets, one would need to manually change the source
> code and re-compile the driver.
>
> To make debugging easier, also add a "intel_dmc_wl/extra_ranges" debugfs
> interface so that extra offsets to be tracked can be defined during
> runtime, removing the need of re-compilation or even module reloading.
>
> With "intel_dmc_wl/untracked" and "intel_dmc_wl/extra_ranges", one could
> even come up with a search algorithm to find missing offsets when
> debugging a failing test case in a similar fashion to git-bisect. Such
> an algorithm is subject for a future tool, probably implemented in
> another repository (e.g. IGT).
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Looks good to me.
Regards,
Bala
> ---
> drivers/gpu/drm/i915/display/intel_dmc_wl.c | 7 +
> .../drm/i915/display/intel_dmc_wl_debugfs.c | 254 +++++++++++++++++-
> .../drm/i915/display/intel_dmc_wl_debugfs.h | 7 +
> 3 files changed, 267 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> index 3686d4e90167..c9740250be73 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> @@ -276,6 +276,13 @@ static bool intel_dmc_wl_check_range(struct intel_display *display,
> if (ranges && intel_dmc_wl_offset_in_ranges(offset, ranges))
> return true;
>
> + /*
> + * Call to check extra ranges from debugfs only as last resort to avoid
> + * taking intel_dmc_wl_dbg's spinlock.
> + */
> + if (intel_dmc_wl_debugfs_offset_in_extra_ranges(display, offset))
> + return true;
> +
> return false;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> index 41e59d775fe5..1493d296ac98 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> @@ -3,6 +3,8 @@
> * Copyright (C) 2025 Intel Corporation
> */
>
> +#include <linux/kstrtox.h>
> +#include <linux/ctype.h>
> #include <linux/debugfs.h>
>
> #include <drm/drm_device.h>
> @@ -13,6 +15,7 @@
> #include "intel_dmc_wl_debugfs.h"
>
> #define DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX 65536
> +#define DEBUGFS_EXTRA_RANGES_MAX 255
>
> /*
> * DOC: DMC wakelock debugfs
> @@ -31,7 +34,8 @@
> * offsets to be tracked and we fail to realize that.
> *
> * To help capture these cases, we provide the intel_dmc_wl/ debugfs directory,
> - * which exports a buffer of untracked register offsets.
> + * which exports a buffer of untracked register offsets and also allows extra
> + * register offsets to be tracked by the driver.
> *
> * Untracked offsets
> * -----------------
> @@ -78,6 +82,43 @@
> * Once done with it, the logging can be disabled with::
> *
> * # echo 0 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> + *
> + * Tracking extra ranges
> + * ---------------------
> + *
> + * After looking at a list of untracked offsets via intel_dmc_wl/untracked, it
> + * is likely that one would want to check whether tracking a suspicious
> + * set of register offsets (i.e. asserting the DMC wakelock for them) would
> + * solve a bug.
> + *
> + * Instead of adding the offsets manually in the source code (which would
> + * require re-compiling and reloading the module) the intel_dmc_wl/extra_ranges
> + * debugfs interface allow defining extra ranges during runtime, which can
> + * significantly speed up debugging time.
> + *
> + * Every write to intel_dmc_wl/untracked defines a new set of ranges to be
> + * tracked. The input format is a whitespace-separated list of ranges and each
> + * range is in the format <start_offset>..<end_offset>, with ..<end_offset>
> + * being optional. Note that <end_offset> is inclusive.
> + *
> + * Examples::
> + *
> + * # echo 0x44400..0x4440c \ # Track a single range of 4 registers
> + * > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> + *
> + * # echo 0x44400..0x4440c 0x44410..0x4441c \ # Track 2 ranges
> + * > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> + *
> + * # echo 0x44400 0x44410..0x4441c \ # Track a single register and 1 range
> + * > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> + *
> + * # echo \ # Do not track extra ranges anymore
> + * > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> + *
> + * The new set of extra ranges take effect after the write operation, meaning
> + * that the next MMIOs made by the driver for registers that match those
> + * offsets will assert the wakelock (besides the offsets already hardcoded in
> + * the driver).
> */
>
> static int untracked_size_get(void *data, u64 *val)
> @@ -176,6 +217,189 @@ static int untracked_show(struct seq_file *m, void *data)
>
> DEFINE_SHOW_ATTRIBUTE(untracked);
>
> +static int extra_ranges_show(struct seq_file *m, void *data)
> +{
> + struct intel_display *display = m->private;
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&dbg->lock, flags);
> +
> + if (!dbg->extra_ranges)
> + goto out_unlock;
> +
> + for (int i = 0; dbg->extra_ranges[i].start; i++) {
> + if (dbg->extra_ranges[i].end)
> + seq_printf(m, "0x%08x..0x%08x\n",
> + dbg->extra_ranges[i].start,
> + dbg->extra_ranges[i].end);
> + else
> + seq_printf(m, "0x%08x\n", dbg->extra_ranges[i].start);
> + }
> +
> +out_unlock:
> + spin_unlock_irqrestore(&dbg->lock, flags);
> +
> + return 0;
> +}
> +
> +/*
> + * Parse *p to match the pattern <start_offset>..<end_offset> and store the
> + * offsets into *dest, if dest is not NULL.
> + *
> + * Leading whitespaces are ignored and ..<end_offset> is optional. Both offsets
> + * are expected to be expressed in hexadecimal.
> + *
> + * The pointer *p is updated to point at the next character in the string for
> + * parsing a new range.
> + *
> + * On success, 1 is returned if a valid range was found and 0 is returned if
> + * there is no range left to parse. On error, a negative error number is
> + * returned.
> + */
> +static int parse_single_extra_range(struct intel_display *display,
> + char **p,
> + struct intel_dmc_wl_dbg_extra_range *dest)
> +{
> + char c;
> + char *s;
> + char *range_substr;
> + int err;
> + u32 val;
> +
> + while (isspace(**p))
> + ++*p;
> +
> + if (**p == '\0')
> + return 0;
> +
> + range_substr = *p;
> +
> + /* s is the <start_offset> substr */
> + s = *p;
> + while (!isspace(**p) && **p != '.' && **p != '\0')
> + ++*p;
> + c = **p;
> + **p = '\0';
> + err = kstrtou32(s, 16, &val);
> + **p = c;
> + if (err)
> + goto out_err;
> +
> + if (dest)
> + dest->start = val;
> +
> + if (**p != '.') {
> + /* only the "start offset" was passed */
> + if (dest)
> + dest->end = 0;
> + return 1;
> + }
> +
> + if (*(++*p) != '.') {
> + err = -EINVAL;
> + goto out_err;
> + }
> +
> + /* s is the <end_offset> substr */
> + s = ++*p;
> + while (!isspace(**p) && **p != '\0')
> + ++*p;
> + c = **p;
> + **p = '\0';
> + err = kstrtou32(s, 16, &val);
> + **p = c;
> + if (err)
> + goto out_err;
> +
> + if (dest)
> + dest->end = val;
> +
> + return 1;
> +
> +out_err:
> + while (!isspace(**p) && **p != '\0')
> + ++*p;
> + c = **p;
> + **p = '\0';
> + drm_err(display->drm, "invalid DMC Wakelock extra range: %s\n", range_substr);
> + **p = c;
> +
> + return err;
> +}
> +
> +static struct intel_dmc_wl_dbg_extra_range *
> +parse_extra_ranges(struct intel_display *display, char *s)
> +{
> + struct intel_dmc_wl_dbg_extra_range *ranges;
> + char *p;
> + int num_ranges;
> + int err;
> +
> + /* Do a first pass and validate everything. */
> + p = s;
> + num_ranges = 0;
> + while ((err = parse_single_extra_range(display, &p, NULL)) > 0) {
> + num_ranges++;
> + if (num_ranges > DEBUGFS_EXTRA_RANGES_MAX) {
> + drm_err(display->drm, "Too many DMC wakelock extra ranges, maximum is %d\n",
> + DEBUGFS_EXTRA_RANGES_MAX);
> + return ERR_PTR(-EINVAL);
> + }
> + }
> +
> + if (err < 0)
> + return ERR_PTR(err);
> +
> + /* Now allocate and do a second pass storing the parsed ranges. */
> + ranges = drmm_kmalloc_array(display->drm, num_ranges + 1, sizeof(*ranges), GFP_KERNEL);
> + if (!ranges)
> + return ERR_PTR(-ENOMEM);
> +
> + p = s;
> + num_ranges = 0;
> + while (parse_single_extra_range(display, &p, &ranges[num_ranges]) > 0)
> + num_ranges++;
> +
> + ranges[num_ranges].start = 0; /* Sentinel value. */
> +
> + return ranges;
> +}
> +
> +static ssize_t extra_ranges_write(struct file *file,
> + const char __user *ubuf,
> + size_t len, loff_t *offp)
> +{
> + struct seq_file *m = file->private_data;
> + struct intel_display *display = m->private;
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> + struct intel_dmc_wl_dbg_extra_range *old_extra_ranges;
> + struct intel_dmc_wl_dbg_extra_range *new_extra_ranges;
> + unsigned long flags;
> + char *kbuf;
> +
> + kbuf = memdup_user_nul(ubuf, len);
> + if (IS_ERR(kbuf))
> + return PTR_ERR(kbuf);
> +
> + new_extra_ranges = parse_extra_ranges(display, kbuf);
> + kfree(kbuf);
> + if (IS_ERR(new_extra_ranges))
> + return PTR_ERR(new_extra_ranges);
> +
> + spin_lock_irqsave(&dbg->lock, flags);
> + old_extra_ranges = dbg->extra_ranges;
> + dbg->extra_ranges = new_extra_ranges;
> + spin_unlock_irqrestore(&dbg->lock, flags);
> +
> + if (old_extra_ranges)
> + drmm_kfree(display->drm, old_extra_ranges);
> +
> + return len;
> +}
> +
> +DEFINE_SHOW_STORE_ATTRIBUTE(extra_ranges);
> +
> void intel_dmc_wl_debugfs_init(struct intel_display *display)
> {
> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> @@ -198,6 +422,8 @@ void intel_dmc_wl_debugfs_register(struct intel_display *display)
> &untracked_size_fops);
> debugfs_create_file("untracked", 0644, dir, display,
> &untracked_fops);
> + debugfs_create_file("extra_ranges", 0644, dir, display,
> + &extra_ranges_fops);
> }
>
> static bool untracked_has_recent_offset(struct intel_display *display, u32 offset)
> @@ -249,3 +475,29 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
> out_unlock:
> spin_unlock_irqrestore(&dbg->lock, flags);
> }
> +
> +bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
> +{
> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> + bool ret = false;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&dbg->lock, flags);
> +
> + if (!dbg->extra_ranges)
> + goto out_unlock;
> +
> + for (int i = 0; dbg->extra_ranges[i].start; i++) {
> + u32 end = dbg->extra_ranges[i].end ?: dbg->extra_ranges[i].start;
> +
> + if (dbg->extra_ranges[i].start <= offset && offset <= end) {
> + ret = true;
> + goto out_unlock;
> + }
> + }
> +
> +out_unlock:
> + spin_unlock_irqrestore(&dbg->lock, flags);
> +
> + return ret;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> index 9437c324966f..ae61217a2789 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> @@ -11,6 +11,11 @@
>
> struct intel_display;
>
> +struct intel_dmc_wl_dbg_extra_range {
> + u32 start;
> + u32 end;
> +};
> +
> struct intel_dmc_wl_dbg {
> spinlock_t lock; /* protects everything below */
> struct {
> @@ -20,10 +25,12 @@ struct intel_dmc_wl_dbg {
> size_t size;
> bool overflow;
> } untracked;
> + struct intel_dmc_wl_dbg_extra_range *extra_ranges;
> };
>
> void intel_dmc_wl_debugfs_init(struct intel_display *display);
> void intel_dmc_wl_debugfs_register(struct intel_display *display);
> void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset);
> +bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset);
>
> #endif /* __INTEL_DMC_WL_DEBUGFS_H__ */
> --
> 2.48.0
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1
2025-01-17 22:06 ` [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1 Gustavo Sousa
2025-01-22 10:24 ` Luca Coelho
2025-01-27 12:01 ` Jani Nikula
@ 2025-01-30 8:46 ` Vivekanandan, Balasubramani
2 siblings, 0 replies; 35+ messages in thread
From: Vivekanandan, Balasubramani @ 2025-01-30 8:46 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On 17.01.2025 19:06, Gustavo Sousa wrote:
> We use a spinlock to protect DMC wakelock debugfs data, since it is also
> accessed by the core DMC wakelock logic. Taking the spinlock when the
> debugfs is not in use introduces a small but unnecessary penalty.
>
> Since the debugfs functionality is only expected to be used for, uh,
> debugging sessions, let's protect it behind a module parameter
> enable_dmc_wl_debugfs. That way, we only take the lock if the feature
> was enabled in the first place.
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Looks good to me.
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Regards,
Bala
> ---
> .../gpu/drm/i915/display/intel_display_params.c | 5 +++++
> .../gpu/drm/i915/display/intel_display_params.h | 1 +
> .../gpu/drm/i915/display/intel_dmc_wl_debugfs.c | 16 +++++++++++++++-
> 3 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
> index c4f1ab43fc0c..bc36d1b0ef87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
> @@ -133,6 +133,11 @@ intel_display_param_named_unsafe(enable_dmc_wl, int, 0400,
> "(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register, 3=always locked) "
> "Default: -1");
>
> +intel_display_param_named_unsafe(enable_dmc_wl_debugfs, bool, 0400,
> + "Enable DMC wakelock debugfs"
> + "(0=disabled, 1=enabled) "
> + "Default: 0");
> +
> __maybe_unused
> static void _param_print_bool(struct drm_printer *p, const char *driver_name,
> const char *name, bool val)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
> index 5317138e6044..cb7dc1bc6846 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.h
> @@ -48,6 +48,7 @@ struct drm_printer;
> param(bool, psr_safest_params, false, 0400) \
> param(bool, enable_psr2_sel_fetch, true, 0400) \
> param(int, enable_dmc_wl, -1, 0400) \
> + param(bool, enable_dmc_wl_debugfs, false, 0400) \
>
> #define MEMBER(T, member, ...) T member;
> struct intel_display_params {
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> index 1493d296ac98..f4e4c7a5a730 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> @@ -37,6 +37,9 @@
> * which exports a buffer of untracked register offsets and also allows extra
> * register offsets to be tracked by the driver.
> *
> + * The debugfs directory is only exported if the module parameter
> + * enable_dmc_wl_debugfs=1 is passed.
> + *
> * Untracked offsets
> * -----------------
> *
> @@ -411,6 +414,9 @@ void intel_dmc_wl_debugfs_register(struct intel_display *display)
> {
> struct dentry *dir;
>
> + if (!display->params.enable_dmc_wl_debugfs)
> + return;
> +
> if (!HAS_DMC_WAKELOCK(display))
> return;
>
> @@ -453,6 +459,9 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> unsigned long flags;
>
> + if (!display->params.enable_dmc_wl_debugfs)
> + return;
> +
> spin_lock_irqsave(&dbg->lock, flags);
>
> if (!dbg->untracked.size)
> @@ -479,9 +488,14 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
> bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
> {
> struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> - bool ret = false;
> + bool ret;
> unsigned long flags;
>
> + if (!display->params.enable_dmc_wl_debugfs)
> + return false;
> +
> + ret = false;
> +
> spin_lock_irqsave(&dbg->lock, flags);
>
> if (!dbg->extra_ranges)
> --
> 2.48.0
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 3/4] drm/i915/dmc_wl: Add extra_ranges debugfs
2025-01-30 8:30 ` Vivekanandan, Balasubramani
@ 2025-01-30 8:49 ` Vivekanandan, Balasubramani
0 siblings, 0 replies; 35+ messages in thread
From: Vivekanandan, Balasubramani @ 2025-01-30 8:49 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On 30.01.2025 14:00, Vivekanandan, Balasubramani wrote:
> On 17.01.2025 19:06, Gustavo Sousa wrote:
> > We already have a way of finding the set of untracked offsets for which
> > there has been one or more MMIO operations via the
> > "intel_dmc_wl/untracked" debugfs interface.
> >
> > However, in order to try adding one or more of those registers to the
> > set of tracked offsets, one would need to manually change the source
> > code and re-compile the driver.
> >
> > To make debugging easier, also add a "intel_dmc_wl/extra_ranges" debugfs
> > interface so that extra offsets to be tracked can be defined during
> > runtime, removing the need of re-compilation or even module reloading.
> >
> > With "intel_dmc_wl/untracked" and "intel_dmc_wl/extra_ranges", one could
> > even come up with a search algorithm to find missing offsets when
> > debugging a failing test case in a similar fashion to git-bisect. Such
> > an algorithm is subject for a future tool, probably implemented in
> > another repository (e.g. IGT).
> >
> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>
> Looks good to me.
>
> Regards,
> Bala
Forgot to add
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Regards,
Bala
>
> > ---
> > drivers/gpu/drm/i915/display/intel_dmc_wl.c | 7 +
> > .../drm/i915/display/intel_dmc_wl_debugfs.c | 254 +++++++++++++++++-
> > .../drm/i915/display/intel_dmc_wl_debugfs.h | 7 +
> > 3 files changed, 267 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> > index 3686d4e90167..c9740250be73 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> > @@ -276,6 +276,13 @@ static bool intel_dmc_wl_check_range(struct intel_display *display,
> > if (ranges && intel_dmc_wl_offset_in_ranges(offset, ranges))
> > return true;
> >
> > + /*
> > + * Call to check extra ranges from debugfs only as last resort to avoid
> > + * taking intel_dmc_wl_dbg's spinlock.
> > + */
> > + if (intel_dmc_wl_debugfs_offset_in_extra_ranges(display, offset))
> > + return true;
> > +
> > return false;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> > index 41e59d775fe5..1493d296ac98 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> > @@ -3,6 +3,8 @@
> > * Copyright (C) 2025 Intel Corporation
> > */
> >
> > +#include <linux/kstrtox.h>
> > +#include <linux/ctype.h>
> > #include <linux/debugfs.h>
> >
> > #include <drm/drm_device.h>
> > @@ -13,6 +15,7 @@
> > #include "intel_dmc_wl_debugfs.h"
> >
> > #define DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX 65536
> > +#define DEBUGFS_EXTRA_RANGES_MAX 255
> >
> > /*
> > * DOC: DMC wakelock debugfs
> > @@ -31,7 +34,8 @@
> > * offsets to be tracked and we fail to realize that.
> > *
> > * To help capture these cases, we provide the intel_dmc_wl/ debugfs directory,
> > - * which exports a buffer of untracked register offsets.
> > + * which exports a buffer of untracked register offsets and also allows extra
> > + * register offsets to be tracked by the driver.
> > *
> > * Untracked offsets
> > * -----------------
> > @@ -78,6 +82,43 @@
> > * Once done with it, the logging can be disabled with::
> > *
> > * # echo 0 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> > + *
> > + * Tracking extra ranges
> > + * ---------------------
> > + *
> > + * After looking at a list of untracked offsets via intel_dmc_wl/untracked, it
> > + * is likely that one would want to check whether tracking a suspicious
> > + * set of register offsets (i.e. asserting the DMC wakelock for them) would
> > + * solve a bug.
> > + *
> > + * Instead of adding the offsets manually in the source code (which would
> > + * require re-compiling and reloading the module) the intel_dmc_wl/extra_ranges
> > + * debugfs interface allow defining extra ranges during runtime, which can
> > + * significantly speed up debugging time.
> > + *
> > + * Every write to intel_dmc_wl/untracked defines a new set of ranges to be
> > + * tracked. The input format is a whitespace-separated list of ranges and each
> > + * range is in the format <start_offset>..<end_offset>, with ..<end_offset>
> > + * being optional. Note that <end_offset> is inclusive.
> > + *
> > + * Examples::
> > + *
> > + * # echo 0x44400..0x4440c \ # Track a single range of 4 registers
> > + * > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> > + *
> > + * # echo 0x44400..0x4440c 0x44410..0x4441c \ # Track 2 ranges
> > + * > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> > + *
> > + * # echo 0x44400 0x44410..0x4441c \ # Track a single register and 1 range
> > + * > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> > + *
> > + * # echo \ # Do not track extra ranges anymore
> > + * > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> > + *
> > + * The new set of extra ranges take effect after the write operation, meaning
> > + * that the next MMIOs made by the driver for registers that match those
> > + * offsets will assert the wakelock (besides the offsets already hardcoded in
> > + * the driver).
> > */
> >
> > static int untracked_size_get(void *data, u64 *val)
> > @@ -176,6 +217,189 @@ static int untracked_show(struct seq_file *m, void *data)
> >
> > DEFINE_SHOW_ATTRIBUTE(untracked);
> >
> > +static int extra_ranges_show(struct seq_file *m, void *data)
> > +{
> > + struct intel_display *display = m->private;
> > + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&dbg->lock, flags);
> > +
> > + if (!dbg->extra_ranges)
> > + goto out_unlock;
> > +
> > + for (int i = 0; dbg->extra_ranges[i].start; i++) {
> > + if (dbg->extra_ranges[i].end)
> > + seq_printf(m, "0x%08x..0x%08x\n",
> > + dbg->extra_ranges[i].start,
> > + dbg->extra_ranges[i].end);
> > + else
> > + seq_printf(m, "0x%08x\n", dbg->extra_ranges[i].start);
> > + }
> > +
> > +out_unlock:
> > + spin_unlock_irqrestore(&dbg->lock, flags);
> > +
> > + return 0;
> > +}
> > +
> > +/*
> > + * Parse *p to match the pattern <start_offset>..<end_offset> and store the
> > + * offsets into *dest, if dest is not NULL.
> > + *
> > + * Leading whitespaces are ignored and ..<end_offset> is optional. Both offsets
> > + * are expected to be expressed in hexadecimal.
> > + *
> > + * The pointer *p is updated to point at the next character in the string for
> > + * parsing a new range.
> > + *
> > + * On success, 1 is returned if a valid range was found and 0 is returned if
> > + * there is no range left to parse. On error, a negative error number is
> > + * returned.
> > + */
> > +static int parse_single_extra_range(struct intel_display *display,
> > + char **p,
> > + struct intel_dmc_wl_dbg_extra_range *dest)
> > +{
> > + char c;
> > + char *s;
> > + char *range_substr;
> > + int err;
> > + u32 val;
> > +
> > + while (isspace(**p))
> > + ++*p;
> > +
> > + if (**p == '\0')
> > + return 0;
> > +
> > + range_substr = *p;
> > +
> > + /* s is the <start_offset> substr */
> > + s = *p;
> > + while (!isspace(**p) && **p != '.' && **p != '\0')
> > + ++*p;
> > + c = **p;
> > + **p = '\0';
> > + err = kstrtou32(s, 16, &val);
> > + **p = c;
> > + if (err)
> > + goto out_err;
> > +
> > + if (dest)
> > + dest->start = val;
> > +
> > + if (**p != '.') {
> > + /* only the "start offset" was passed */
> > + if (dest)
> > + dest->end = 0;
> > + return 1;
> > + }
> > +
> > + if (*(++*p) != '.') {
> > + err = -EINVAL;
> > + goto out_err;
> > + }
> > +
> > + /* s is the <end_offset> substr */
> > + s = ++*p;
> > + while (!isspace(**p) && **p != '\0')
> > + ++*p;
> > + c = **p;
> > + **p = '\0';
> > + err = kstrtou32(s, 16, &val);
> > + **p = c;
> > + if (err)
> > + goto out_err;
> > +
> > + if (dest)
> > + dest->end = val;
> > +
> > + return 1;
> > +
> > +out_err:
> > + while (!isspace(**p) && **p != '\0')
> > + ++*p;
> > + c = **p;
> > + **p = '\0';
> > + drm_err(display->drm, "invalid DMC Wakelock extra range: %s\n", range_substr);
> > + **p = c;
> > +
> > + return err;
> > +}
> > +
> > +static struct intel_dmc_wl_dbg_extra_range *
> > +parse_extra_ranges(struct intel_display *display, char *s)
> > +{
> > + struct intel_dmc_wl_dbg_extra_range *ranges;
> > + char *p;
> > + int num_ranges;
> > + int err;
> > +
> > + /* Do a first pass and validate everything. */
> > + p = s;
> > + num_ranges = 0;
> > + while ((err = parse_single_extra_range(display, &p, NULL)) > 0) {
> > + num_ranges++;
> > + if (num_ranges > DEBUGFS_EXTRA_RANGES_MAX) {
> > + drm_err(display->drm, "Too many DMC wakelock extra ranges, maximum is %d\n",
> > + DEBUGFS_EXTRA_RANGES_MAX);
> > + return ERR_PTR(-EINVAL);
> > + }
> > + }
> > +
> > + if (err < 0)
> > + return ERR_PTR(err);
> > +
> > + /* Now allocate and do a second pass storing the parsed ranges. */
> > + ranges = drmm_kmalloc_array(display->drm, num_ranges + 1, sizeof(*ranges), GFP_KERNEL);
> > + if (!ranges)
> > + return ERR_PTR(-ENOMEM);
> > +
> > + p = s;
> > + num_ranges = 0;
> > + while (parse_single_extra_range(display, &p, &ranges[num_ranges]) > 0)
> > + num_ranges++;
> > +
> > + ranges[num_ranges].start = 0; /* Sentinel value. */
> > +
> > + return ranges;
> > +}
> > +
> > +static ssize_t extra_ranges_write(struct file *file,
> > + const char __user *ubuf,
> > + size_t len, loff_t *offp)
> > +{
> > + struct seq_file *m = file->private_data;
> > + struct intel_display *display = m->private;
> > + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> > + struct intel_dmc_wl_dbg_extra_range *old_extra_ranges;
> > + struct intel_dmc_wl_dbg_extra_range *new_extra_ranges;
> > + unsigned long flags;
> > + char *kbuf;
> > +
> > + kbuf = memdup_user_nul(ubuf, len);
> > + if (IS_ERR(kbuf))
> > + return PTR_ERR(kbuf);
> > +
> > + new_extra_ranges = parse_extra_ranges(display, kbuf);
> > + kfree(kbuf);
> > + if (IS_ERR(new_extra_ranges))
> > + return PTR_ERR(new_extra_ranges);
> > +
> > + spin_lock_irqsave(&dbg->lock, flags);
> > + old_extra_ranges = dbg->extra_ranges;
> > + dbg->extra_ranges = new_extra_ranges;
> > + spin_unlock_irqrestore(&dbg->lock, flags);
> > +
> > + if (old_extra_ranges)
> > + drmm_kfree(display->drm, old_extra_ranges);
> > +
> > + return len;
> > +}
> > +
> > +DEFINE_SHOW_STORE_ATTRIBUTE(extra_ranges);
> > +
> > void intel_dmc_wl_debugfs_init(struct intel_display *display)
> > {
> > struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> > @@ -198,6 +422,8 @@ void intel_dmc_wl_debugfs_register(struct intel_display *display)
> > &untracked_size_fops);
> > debugfs_create_file("untracked", 0644, dir, display,
> > &untracked_fops);
> > + debugfs_create_file("extra_ranges", 0644, dir, display,
> > + &extra_ranges_fops);
> > }
> >
> > static bool untracked_has_recent_offset(struct intel_display *display, u32 offset)
> > @@ -249,3 +475,29 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
> > out_unlock:
> > spin_unlock_irqrestore(&dbg->lock, flags);
> > }
> > +
> > +bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
> > +{
> > + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> > + bool ret = false;
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&dbg->lock, flags);
> > +
> > + if (!dbg->extra_ranges)
> > + goto out_unlock;
> > +
> > + for (int i = 0; dbg->extra_ranges[i].start; i++) {
> > + u32 end = dbg->extra_ranges[i].end ?: dbg->extra_ranges[i].start;
> > +
> > + if (dbg->extra_ranges[i].start <= offset && offset <= end) {
> > + ret = true;
> > + goto out_unlock;
> > + }
> > + }
> > +
> > +out_unlock:
> > + spin_unlock_irqrestore(&dbg->lock, flags);
> > +
> > + return ret;
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> > index 9437c324966f..ae61217a2789 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> > @@ -11,6 +11,11 @@
> >
> > struct intel_display;
> >
> > +struct intel_dmc_wl_dbg_extra_range {
> > + u32 start;
> > + u32 end;
> > +};
> > +
> > struct intel_dmc_wl_dbg {
> > spinlock_t lock; /* protects everything below */
> > struct {
> > @@ -20,10 +25,12 @@ struct intel_dmc_wl_dbg {
> > size_t size;
> > bool overflow;
> > } untracked;
> > + struct intel_dmc_wl_dbg_extra_range *extra_ranges;
> > };
> >
> > void intel_dmc_wl_debugfs_init(struct intel_display *display);
> > void intel_dmc_wl_debugfs_register(struct intel_display *display);
> > void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset);
> > +bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset);
> >
> > #endif /* __INTEL_DMC_WL_DEBUGFS_H__ */
> > --
> > 2.48.0
> >
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets
2025-01-23 16:41 ` Gustavo Sousa
@ 2025-01-30 8:54 ` Vivekanandan, Balasubramani
0 siblings, 0 replies; 35+ messages in thread
From: Vivekanandan, Balasubramani @ 2025-01-30 8:54 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On 23.01.2025 13:41, Gustavo Sousa wrote:
> Quoting Vivekanandan, Balasubramani (2025-01-23 13:11:03-03:00)
> >On 17.01.2025 19:06, Gustavo Sousa wrote:
> >> The DMC wakelock code needs to keep track of register offsets that need
> >> the wakelock for proper access. If one of the necessary offsets are
> >> missed, then the failure in asserting the wakelock is very likely to
> >> cause problems down the road.
> >>
> >> A miss could happen for at least two different reasons:
> >>
> >> - We might have forgotten to add the offset (or range) to the relevant
> >> tables tracked by the driver in the first place.
> >>
> >> - Or updates to either the DMC firmware or the display IP that require
> >> new offsets to be tracked and we fail to realize that.
> >>
> >> To help capture these cases, let's introduce a debugfs interface for the
> >> DMC wakelock.
> >>
> >> In this part, we export a buffer containing offsets of registers that
> >> were considered not needing the wakelock by our driver. In an upcoming
> >> change we will also allow defining an extra set of offset ranges to be
> >> tracked by our driver.
> >>
> >> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/Makefile | 1 +
> >> .../drm/i915/display/intel_display_debugfs.c | 2 +
> >> drivers/gpu/drm/i915/display/intel_dmc_wl.c | 5 +-
> >> drivers/gpu/drm/i915/display/intel_dmc_wl.h | 2 +
> >> .../drm/i915/display/intel_dmc_wl_debugfs.c | 251 ++++++++++++++++++
> >> .../drm/i915/display/intel_dmc_wl_debugfs.h | 29 ++
> >> drivers/gpu/drm/xe/Makefile | 1 +
> >> 7 files changed, 290 insertions(+), 1 deletion(-)
> >> create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> >> create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> >>
> >> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> >> index 3dda9f0eda82..ac1ab79de9c8 100644
> >> --- a/drivers/gpu/drm/i915/Makefile
> >> +++ b/drivers/gpu/drm/i915/Makefile
> >> @@ -251,6 +251,7 @@ i915-y += \
> >> display/intel_display_wa.o \
> >> display/intel_dmc.o \
> >> display/intel_dmc_wl.o \
> >> + display/intel_dmc_wl_debugfs.o \
> >> display/intel_dpio_phy.o \
> >> display/intel_dpll.o \
> >> display/intel_dpll_mgr.o \
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >> index f1d76484025a..b032535f4830 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >> @@ -26,6 +26,7 @@
> >> #include "intel_display_power_well.h"
> >> #include "intel_display_types.h"
> >> #include "intel_dmc.h"
> >> +#include "intel_dmc_wl_debugfs.h"
> >> #include "intel_dp.h"
> >> #include "intel_dp_link_training.h"
> >> #include "intel_dp_mst.h"
> >> @@ -883,6 +884,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
> >>
> >> intel_bios_debugfs_register(display);
> >> intel_cdclk_debugfs_register(display);
> >> + intel_dmc_wl_debugfs_register(display);
> >> intel_dmc_debugfs_register(display);
> >> intel_dp_test_debugfs_register(display);
> >> intel_fbc_debugfs_register(display);
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> >> index 330b43a72e08..3686d4e90167 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> >> @@ -338,6 +338,7 @@ void intel_dmc_wl_init(struct intel_display *display)
> >> spin_lock_init(&wl->lock);
> >> refcount_set(&wl->refcount,
> >> display->params.enable_dmc_wl == ENABLE_DMC_WL_ALWAYS_LOCKED ? 1 : 0);
> >> + intel_dmc_wl_debugfs_init(display);
> >> }
> >>
> >> /* Must only be called as part of enabling dynamic DC states. */
> >> @@ -444,8 +445,10 @@ void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg)
> >> spin_lock_irqsave(&wl->lock, flags);
> >>
> >> if (i915_mmio_reg_valid(reg) &&
> >> - !intel_dmc_wl_check_range(display, reg, wl->dc_state))
> >> + !intel_dmc_wl_check_range(display, reg, wl->dc_state)) {
> >> + intel_dmc_wl_debugfs_log_untracked(display, i915_mmio_reg_offset(reg));
> >> goto out_unlock;
> >> + }
> >>
> >> if (!wl->enabled) {
> >> if (!refcount_inc_not_zero(&wl->refcount))
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.h b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
> >> index 5488fbdf29b8..d11b0ab50b3c 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
> >> @@ -11,6 +11,7 @@
> >> #include <linux/refcount.h>
> >>
> >> #include "i915_reg_defs.h"
> >> +#include "intel_dmc_wl_debugfs.h"
> >>
> >> struct intel_display;
> >>
> >> @@ -27,6 +28,7 @@ struct intel_dmc_wl {
> >> */
> >> u32 dc_state;
> >> struct delayed_work work;
> >> + struct intel_dmc_wl_dbg dbg;
> >> };
> >>
> >> void intel_dmc_wl_init(struct intel_display *display);
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> >> new file mode 100644
> >> index 000000000000..41e59d775fe5
> >> --- /dev/null
> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> >> @@ -0,0 +1,251 @@
> >> +// SPDX-License-Identifier: MIT
> >> +/*
> >> + * Copyright (C) 2025 Intel Corporation
> >> + */
> >> +
> >> +#include <linux/debugfs.h>
> >> +
> >> +#include <drm/drm_device.h>
> >> +#include <drm/drm_managed.h>
> >> +#include <drm/drm_print.h>
> >> +
> >> +#include "intel_display_core.h"
> >> +#include "intel_dmc_wl_debugfs.h"
> >> +
> >> +#define DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX 65536
> >This macro is not actually the size but the count of offsets stored in
> >the buffer. This is used as the array size for drmm_kmalloc_array call.
> >It makes sense to rename this macro as count
>
> I think size doesn't really have to mean number of bytes, but, in this
> case, I agree, that "buffer size" could be easily thought that way.
>
> However, couldn't "buffer count" be somewhat ambiguous? One might read
> as the number of buffers and then only later after reading the code that
> it would refer to the number of entries in a single buffer.
>
> Between the two options, I think I would still go with "buffer size"...
I was thinking something like DEBUGFS_UNTRACKED_OFFSET_COUNT
Regards,
Bala
>
> >
> >> +
> >> +/*
> >> + * DOC: DMC wakelock debugfs
> >> + *
> >> + * The DMC wakelock code needs to keep track of register offsets that need the
> >> + * wakelock for proper access. If one of the necessary offsets are missed, then
> >> + * the failure in asserting the wakelock is very likely to cause problems down
> >> + * the road.
> >> + *
> >> + * A miss could happen for at least two different reasons:
> >> + *
> >> + * - We might have forgotten to add the offset (or range) to the relevant
> >> + * tables tracked by the driver in the first place.
> >> + *
> >> + * - Or updates to either the DMC firmware or the display IP that require new
> >> + * offsets to be tracked and we fail to realize that.
> >> + *
> >> + * To help capture these cases, we provide the intel_dmc_wl/ debugfs directory,
> >> + * which exports a buffer of untracked register offsets.
> >> + *
> >> + * Untracked offsets
> >> + * -----------------
> >> + *
> >> + * This is a buffer that records every register offset that went through the
> >> + * DMC wakelock check and was deemed not needing the wakelock for MMIO access.
> >> + *
> >> + * To activate the logging of offsets into such a buffer, one can do::
> >> + *
> >> + * # echo -1 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> >
> >This knob is setting the count of offsets to be stored and not the size.
> >I think this should be renamed to indicate it as count.
> >
> >> + *
> >> + * This will create a buffer with the maximum number of entries allowed
> >> + * (DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX). A positive value can be used instead to
> >> + * define a different size:
> >> + *
> >> + * # echo 1024 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> >
> >For me passing negative number doesn't look intuitive. Thinking do we
> >really need the case of passing default buffer size. We can allow just 0
> >to disable and any positive number to enable with the buffer size set as
> >value passed.
>
> Well, this is already supported. The use of -1 is just a convenience,
> and the user is not required to use it.
>
> The current interface doesn't provide a way of letting the user know the
> maximum value and I think it would be a bit overkill adding another
> debugfs file just for that purpose.
>
> As such, I think -1 is a useful way of letting the user use the maximum
> size, specially when she doesn't have the up-to-date documentation in
> handy to know what value that is. That's certainly better than having
> the user finding the maximum via trial and error.
>
> >
> >> + *
> >> + * Every write to untracked_size will cause the buffer to be reset.
> >> + *
> >> + * It is also possible to read untracked_size in order to get the current
> >> + * value.
> >> + *
> >> + * After enabled, the buffer starts getting filled with offsets as MMIOs are
> >> + * performed by the driver.
> >> + *
> >> + * In order to view the content of the buffer, one can do::
> >> + *
> >> + * # cat /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked
> >> + * 0x000c4000
> >> + * 0x0016fe50
> >> + * 0x000c7200
> >> + * 0x000c7204
> >> + * 0x00045230
> >> + * 0x00046440
> >> + * 0x00045234
> >> + * 0x0016fa48
> >> + * 0x0016fa40
> >> + * 0x0016fa5c
> >> + * (...)
> >> + *
> >> + * The order of those offsets does not reflect the order the checks were done
> >> + * (some recently seen offsets are skipped to save space).
> >> + *
> >> + * Once done with it, the logging can be disabled with::
> >> + *
> >> + * # echo 0 > /sys/kernel/debug/dri/(...)/intel_dmc_wl/untracked_size
> >> + */
> >> +
> >> +static int untracked_size_get(void *data, u64 *val)
> >> +{
> >> + struct intel_display *display = data;
> >> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> >> + unsigned long flags;
> >> +
> >> + spin_lock_irqsave(&dbg->lock, flags);
> >> + *val = dbg->untracked.size;
> >> + spin_unlock_irqrestore(&dbg->lock, flags);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int untracked_size_set(void *data, u64 val)
> >> +{
> >> + struct intel_display *display = data;
> >> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> >> + s64 new_size;
> >> + u32 *old_offsets;
> >> + u32 *new_offsets;
> >> + unsigned long flags;
> >> +
> >> + new_size = (s64)val;
> >> +
> >> + if (new_size == -1) {
> >> + new_size = DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX;
> >> + } else if (new_size < 0) {
> >> + drm_err(display->drm,
> >> + "%lld is invalid for untracked_size, the only negative value allowed is -1\n",
> >> + new_size);
> >> + return -EINVAL;
> >> + } else if (new_size > DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX) {
> >> + drm_err(display->drm,
> >> + "%lld too big for untracked_size, maximum allowed value is %d\n",
> >> + new_size,
> >> + DEBUGFS_UNTRACKED_BUFFER_SIZE_MAX);
> >> + return -EINVAL;
> >> + }
> >> +
> >> + if (new_size == 0) {
> >> + new_offsets = NULL;
> >> + } else {
> >> + new_offsets = drmm_kmalloc_array(display->drm, new_size, sizeof(*new_offsets),
> >> + GFP_KERNEL);
> >> +
> >> + if (!new_offsets)
> >> + return -ENOMEM;
> >> + }
> >> +
> >> + spin_lock_irqsave(&dbg->lock, flags);
> >> + old_offsets = dbg->untracked.offsets;
> >> + dbg->untracked.offsets = new_offsets;
> >> + dbg->untracked.size = new_size;
> >> + dbg->untracked.head = 0;
> >> + dbg->untracked.len = 0;
> >> + dbg->untracked.overflow = false;
> >> + spin_unlock_irqrestore(&dbg->lock, flags);
> >> +
> >> + if (old_offsets)
> >> + drmm_kfree(display->drm, old_offsets);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +DEFINE_SIMPLE_ATTRIBUTE_SIGNED(untracked_size_fops,
> >> + untracked_size_get,
> >> + untracked_size_set,
> >> + "%lld\n");
> >> +
> >> +static int untracked_show(struct seq_file *m, void *data)
> >> +{
> >> + struct intel_display *display = m->private;
> >> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> >> + unsigned long flags;
> >> + size_t remaining;
> >> + size_t i;
> >> +
> >> + spin_lock_irqsave(&dbg->lock, flags);
> >> +
> >> + remaining = dbg->untracked.len;
> >> + i = dbg->untracked.head;
> >> +
> >> + while (remaining--) {
> >> + if (i == 0)
> >> + i = dbg->untracked.size;
> >> +
> >> + seq_printf(m, "0x%08x\n", dbg->untracked.offsets[--i]);
> >> + }
> >> +
> >> + spin_unlock_irqrestore(&dbg->lock, flags);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +DEFINE_SHOW_ATTRIBUTE(untracked);
> >> +
> >> +void intel_dmc_wl_debugfs_init(struct intel_display *display)
> >> +{
> >> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> >> +
> >> + spin_lock_init(&dbg->lock);
> >> +}
> >> +
> >> +void intel_dmc_wl_debugfs_register(struct intel_display *display)
> >> +{
> >> + struct dentry *dir;
> >> +
> >> + if (!HAS_DMC_WAKELOCK(display))
> >> + return;
> >> +
> >> + dir = debugfs_create_dir("intel_dmc_wl", display->drm->debugfs_root);
> >> + if (IS_ERR(dir))
> >> + return;
> >> +
> >> + debugfs_create_file("untracked_size", 0644, dir, display,
> >> + &untracked_size_fops);
> >> + debugfs_create_file("untracked", 0644, dir, display,
> >> + &untracked_fops);
> >> +}
> >> +
> >> +static bool untracked_has_recent_offset(struct intel_display *display, u32 offset)
> >> +{
> >> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> >> + int look_back = 32;
> >Define a macro for this magic number
>
> This is very local to this function and I guess the variable name
> already convey it's meaning?
>
> >
> >> + size_t i;
> >> +
> >> + if (look_back > dbg->untracked.len)
> >> + look_back = dbg->untracked.len;
> >> +
> >> + i = dbg->untracked.head;
> >> +
> >> + while (look_back--) {
> >> + if (i == 0)
> >> + i = dbg->untracked.size;
> >> +
> >> + if (dbg->untracked.offsets[--i] == offset)
> >> + return true;
> >> + }
> >> +
> >> + return false;
> >> +}
> >> +
> >> +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset)
> >> +{
> >> + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> >> + unsigned long flags;
> >> +
> >> + spin_lock_irqsave(&dbg->lock, flags);
> >As this code never gets called by an interrupt, we can use just the
> >spin_lock instead of spin_lock_irqsave. Same applies for all the places
> >where spin_lock/unlock_irqsave/irqrestore is used.
>
> This code does get called in interrupt context. It is called by
> intel_dmc_wl_get(), which is called for most of display MMIO access
> functions, and that happens both in user and interrupt context.
>
> >
> >> +
> >> + if (!dbg->untracked.size)
> >> + goto out_unlock;
> >> +
> >> + /* Save some space by not repeating recent offsets. */
> >> + if (untracked_has_recent_offset(display, offset))
> >> + goto out_unlock;
> >> +
> >> + dbg->untracked.offsets[dbg->untracked.head] = offset;
> >> + dbg->untracked.head = (dbg->untracked.head + 1) % dbg->untracked.size;
> >> + if (dbg->untracked.len < dbg->untracked.size)
> >> + dbg->untracked.len++;
> >> +
> >> + if (dbg->untracked.len == dbg->untracked.size && !dbg->untracked.overflow) {
> >> + dbg->untracked.overflow = true;
> >> + drm_warn(display->drm, "Overflow detected in DMC wakelock debugfs untracked offsets\n");
> >> + }
> >> +
> >> +out_unlock:
> >> + spin_unlock_irqrestore(&dbg->lock, flags);
> >> +}
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> >> new file mode 100644
> >> index 000000000000..9437c324966f
> >> --- /dev/null
> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> >> @@ -0,0 +1,29 @@
> >> +/* SPDX-License-Identifier: MIT */
> >> +/*
> >> + * Copyright (C) 2025 Intel Corporation
> >> + */
> >> +
> >> +#ifndef __INTEL_DMC_WL_DEBUGFS_H__
> >> +#define __INTEL_DMC_WL_DEBUGFS_H__
> >> +
> >> +#include <linux/types.h>
> >> +#include <linux/spinlock.h>
> >> +
> >> +struct intel_display;
> >> +
> >> +struct intel_dmc_wl_dbg {
> >> + spinlock_t lock; /* protects everything below */
> >> + struct {
> >> + u32 *offsets;
> >> + size_t head;
> >> + size_t len;
> >> + size_t size;
> >There is no need of both len and size. head will always give the count
> >of entries in the buffer. During overflow, we are keeping a flag to
> >indicate a overflow, which indicates the we also have date in the buffer
> >above head till the end of buffer.
>
> Ah, right. If overflow==false, then the length equals head, if
> overflow==true, then length equals size.
>
> Maybe the inconvenience is that we will need to calculate the length
> every time we need it. But maybe that's not too bad...
>
> Thanks! I'll remove the "len" member in v2.
>
> --
> Gustavo Sousa
>
> >
> >Regards,
> >Bala
> >
> >> + bool overflow;
> >> + } untracked;
> >> +};
> >> +
> >> +void intel_dmc_wl_debugfs_init(struct intel_display *display);
> >> +void intel_dmc_wl_debugfs_register(struct intel_display *display);
> >> +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset);
> >> +
> >> +#endif /* __INTEL_DMC_WL_DEBUGFS_H__ */
> >> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> >> index 81f63258a7e1..f03fbdbcb1a4 100644
> >> --- a/drivers/gpu/drm/xe/Makefile
> >> +++ b/drivers/gpu/drm/xe/Makefile
> >> @@ -221,6 +221,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> >> i915-display/intel_display_wa.o \
> >> i915-display/intel_dkl_phy.o \
> >> i915-display/intel_dmc.o \
> >> + i915-display/intel_dmc_wl_debugfs.o \
> >> i915-display/intel_dp.o \
> >> i915-display/intel_dp_aux.o \
> >> i915-display/intel_dp_aux_backlight.o \
> >> --
> >> 2.48.0
> >>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 3/4] drm/i915/dmc_wl: Add extra_ranges debugfs
2025-01-23 15:52 ` Gustavo Sousa
@ 2025-01-30 9:18 ` Luca Coelho
0 siblings, 0 replies; 35+ messages in thread
From: Luca Coelho @ 2025-01-30 9:18 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On Thu, 2025-01-23 at 12:52 -0300, Gustavo Sousa wrote:
> Quoting Luca Coelho (2025-01-22 07:19:35-03:00)
> > On Fri, 2025-01-17 at 19:06 -0300, Gustavo Sousa wrote:
> > > We already have a way of finding the set of untracked offsets for which
> > > there has been one or more MMIO operations via the
> > > "intel_dmc_wl/untracked" debugfs interface.
> > >
> > > However, in order to try adding one or more of those registers to the
> > > set of tracked offsets, one would need to manually change the source
> > > code and re-compile the driver.
> > >
> > > To make debugging easier, also add a "intel_dmc_wl/extra_ranges" debugfs
> > > interface so that extra offsets to be tracked can be defined during
> > > runtime, removing the need of re-compilation or even module reloading.
> > >
> > > With "intel_dmc_wl/untracked" and "intel_dmc_wl/extra_ranges", one could
> > > even come up with a search algorithm to find missing offsets when
> > > debugging a failing test case in a similar fashion to git-bisect. Such
> > > an algorithm is subject for a future tool, probably implemented in
> > > another repository (e.g. IGT).
> > >
> > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > > ---
> >
> > Some comments below.
> >
> >
> > [...]
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> > > index 41e59d775fe5..1493d296ac98 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.c
> >
> > [...]
> > > +bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
> > > +{
> > > + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> > > + bool ret = false;
> > > + unsigned long flags;
> > > +
> > > + spin_lock_irqsave(&dbg->lock, flags);
> > > +
> > > + if (!dbg->extra_ranges)
> > > + goto out_unlock;
> > > +
> > > + for (int i = 0; dbg->extra_ranges[i].start; i++) {
> > > + u32 end = dbg->extra_ranges[i].end ?: dbg->extra_ranges[i].start;
> > > +
> > > + if (dbg->extra_ranges[i].start <= offset && offset <= end) {
> > > + ret = true;
> > > + goto out_unlock;
> > > + }
> > > + }
> > > +
> > > +out_unlock:
> > > + spin_unlock_irqrestore(&dbg->lock, flags);
> > > +
> > > + return ret;
> > > +}
> >
> > This function is probably almost identical than the one used to check
> > the hard-coded ranges, isn't it? In that case, couldn't you just pass
> > the ranges array (in this case dbg->extra_ranges) to the same function?
>
> Yeah. I thought about that when implementing this, but ended up going
> with a separate implementation.
>
> If you look at how the current series is done, there is a one-way
> dependency between intel_dmc_wl_debugfs and intel_dmc_wl - the latter
> depends on the former. I just didn't want to make this a circular
> dependency, since the implementation is rather simple anyway...
>
> Let me know if that convinced you :-)
>
> >
> >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> > > index 9437c324966f..ae61217a2789 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl_debugfs.h
> > > @@ -11,6 +11,11 @@
> > >
> > > struct intel_display;
> > >
> > > +struct intel_dmc_wl_dbg_extra_range {
> > > + u32 start;
> > > + u32 end;
> > > +};
> > > +
> >
> > Why do you need another struct for this?
> >
>
> In the same spirit as with my answer above... I think of this much as an
> implementation detail that would be better off not exposed in headers.
Yeah, thanks for the clarification.
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1
2025-01-23 16:10 ` Gustavo Sousa
@ 2025-01-30 9:28 ` Luca Coelho
0 siblings, 0 replies; 35+ messages in thread
From: Luca Coelho @ 2025-01-30 9:28 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On Thu, 2025-01-23 at 13:10 -0300, Gustavo Sousa wrote:
> Quoting Luca Coelho (2025-01-22 07:24:43-03:00)
> > On Fri, 2025-01-17 at 19:06 -0300, Gustavo Sousa wrote:
> > > We use a spinlock to protect DMC wakelock debugfs data, since it is also
> > > accessed by the core DMC wakelock logic. Taking the spinlock when the
> > > debugfs is not in use introduces a small but unnecessary penalty.
> > >
> > > Since the debugfs functionality is only expected to be used for, uh,
> > > debugging sessions, let's protect it behind a module parameter
> > > enable_dmc_wl_debugfs. That way, we only take the lock if the feature
> > > was enabled in the first place.
> > >
> > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > > ---
> >
> > Looks good. With a small optional nitpick below.
> >
> > Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
> >
> > [...]
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
> > > index c4f1ab43fc0c..bc36d1b0ef87 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_params.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
> > > @@ -479,9 +488,14 @@ void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offse
> > > bool intel_dmc_wl_debugfs_offset_in_extra_ranges(struct intel_display *display, u32 offset)
> > > {
> > > struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> > > - bool ret = false;
> > > + bool ret;
> >
> > Why not keep this as it was...
>
> Yeah, I suppose that's fine... I think the compiler is going to optimize
> it. I can send a v2 with this change.
>
> >
> > > unsigned long flags;
> > >
> > > + if (!display->params.enable_dmc_wl_debugfs)
> > > + return false;
> > > +
> > > + ret = false;
> > > +
> >
> > ...then you don't need to set it here, and can return ret in the if
> > above for consistency.
>
> In the if above, I guess I prefer the "return false" because it is
> explicit.
Yeah, fair enough. It's a matter of preference.
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets
2025-01-23 14:41 ` Gustavo Sousa
@ 2025-01-30 9:33 ` Luca Coelho
0 siblings, 0 replies; 35+ messages in thread
From: Luca Coelho @ 2025-01-30 9:33 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On Thu, 2025-01-23 at 11:41 -0300, Gustavo Sousa wrote:
> Quoting Luca Coelho (2025-01-22 06:06:00-03:00)
> > On Fri, 2025-01-17 at 19:06 -0300, Gustavo Sousa wrote:
> > > The DMC wakelock code needs to keep track of register offsets that need
> > > the wakelock for proper access. If one of the necessary offsets are
> > > missed, then the failure in asserting the wakelock is very likely to
> > > cause problems down the road.
> > >
> > > A miss could happen for at least two different reasons:
> > >
> > > - We might have forgotten to add the offset (or range) to the relevant
> > > tables tracked by the driver in the first place.
> > >
> > > - Or updates to either the DMC firmware or the display IP that require
> > > new offsets to be tracked and we fail to realize that.
> > >
> > > To help capture these cases, let's introduce a debugfs interface for the
> > > DMC wakelock.
> > >
> > > In this part, we export a buffer containing offsets of registers that
> > > were considered not needing the wakelock by our driver. In an upcoming
> > > change we will also allow defining an extra set of offset ranges to be
> > > tracked by our driver.
> > >
> > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > > ---
> >
> > This looks great overall!
> >
> > A couple of comments below.
> >
> >
> > [...]
> > > +static bool untracked_has_recent_offset(struct intel_display *display, u32 offset)
> > > +{
> > > + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> > > + int look_back = 32;
> > > + size_t i;
> > > +
> > > + if (look_back > dbg->untracked.len)
> > > + look_back = dbg->untracked.len;
> > > +
> > > + i = dbg->untracked.head;
> > > +
> > > + while (look_back--) {
> > > + if (i == 0)
> > > + i = dbg->untracked.size;
> >
> > If size < 32, you would check some values twice, right? Probably not a
> > real case scenario, and it wouldn't matter much, but it took me a bit
> > to wrap my head around this.
>
> Nope. If look_back is greater than the current number of offsets, it
> will be just reset to that count (see the "if (look_back >
> dbg->untracked.len)" above).
>
> Note that the number of valid elements in the circular buffer is tracked
> with untracked.len, while untracked.size is actually the capacity. Maybe
> I should have used that name for the member instead?
Yeah, maybe untracked.len and untracked.max_len? Dunno, it's also fine
as it is. I was blind focusing on the loop itself and didn't see the
if above it.
> > [...]
> > > +void intel_dmc_wl_debugfs_log_untracked(struct intel_display *display, u32 offset)
> > > +{
> > > + struct intel_dmc_wl_dbg *dbg = &display->wl.dbg;
> > > + unsigned long flags;
> > > +
> > > + spin_lock_irqsave(&dbg->lock, flags);
> > > +
> > > + if (!dbg->untracked.size)
> > > + goto out_unlock;
> > > +
> > > + /* Save some space by not repeating recent offsets. */
> > > + if (untracked_has_recent_offset(display, offset))
> > > + goto out_unlock;
> > > +
> > > + dbg->untracked.offsets[dbg->untracked.head] = offset;
> > > + dbg->untracked.head = (dbg->untracked.head + 1) % dbg->untracked.size;
> > > + if (dbg->untracked.len < dbg->untracked.size)
> > > + dbg->untracked.len++;
> > > +
> > > + if (dbg->untracked.len == dbg->untracked.size && !dbg->untracked.overflow) {
> > > + dbg->untracked.overflow = true;
> > > + drm_warn(display->drm, "Overflow detected in DMC wakelock debugfs untracked offsets\n");
> > > + }
> >
> > Couldn't it be useful to print overflows every time they occur? Maybe
> > convert overflow to a uint to track how many times it happened? (though
> > maybe this is a bit overkill).
>
> The warning is just to let the user know that the buffer doesn't have
> every untracked offset that has been seen since enabling the logging.
> The best thing to do in this case is to try a bigger size or try to
> reduce the execution to be tracked (maybe a smaller test case).
>
> I'm not sure how providing a count would be useful here.
It would at least make it easier to know how to size the buffer for the
next run. ;) But that's moot.
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 35+ messages in thread
end of thread, other threads:[~2025-01-30 9:33 UTC | newest]
Thread overview: 35+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-01-17 22:06 [PATCH 0/4] drm/i915/dmc_wl: Introduce debugfs interface Gustavo Sousa
2025-01-17 22:06 ` [PATCH 1/4] drm/i915/dmc_wl: Pass offset instead of reg to range table iterator Gustavo Sousa
2025-01-22 8:23 ` Luca Coelho
2025-01-17 22:06 ` [PATCH 2/4] drm/i915/dmc_wl: Add debugfs for untracked offsets Gustavo Sousa
2025-01-22 9:06 ` Luca Coelho
2025-01-23 14:41 ` Gustavo Sousa
2025-01-30 9:33 ` Luca Coelho
2025-01-23 16:11 ` Vivekanandan, Balasubramani
2025-01-23 16:41 ` Gustavo Sousa
2025-01-30 8:54 ` Vivekanandan, Balasubramani
2025-01-27 9:47 ` Jani Nikula
2025-01-27 11:17 ` Gustavo Sousa
2025-01-27 11:59 ` Jani Nikula
2025-01-27 12:55 ` Gustavo Sousa
2025-01-17 22:06 ` [PATCH 3/4] drm/i915/dmc_wl: Add extra_ranges debugfs Gustavo Sousa
2025-01-22 10:19 ` Luca Coelho
2025-01-23 15:52 ` Gustavo Sousa
2025-01-30 9:18 ` Luca Coelho
2025-01-30 8:30 ` Vivekanandan, Balasubramani
2025-01-30 8:49 ` Vivekanandan, Balasubramani
2025-01-17 22:06 ` [PATCH 4/4] drm/i915/dmc_wl: Enable the debugfs only with enable_dmc_wl_debugfs=1 Gustavo Sousa
2025-01-22 10:24 ` Luca Coelho
2025-01-23 16:10 ` Gustavo Sousa
2025-01-30 9:28 ` Luca Coelho
2025-01-27 12:01 ` Jani Nikula
2025-01-27 12:02 ` Jani Nikula
2025-01-27 13:24 ` Gustavo Sousa
2025-01-27 13:35 ` Jani Nikula
2025-01-27 13:50 ` Gustavo Sousa
2025-01-27 14:40 ` Jani Nikula
2025-01-30 8:46 ` Vivekanandan, Balasubramani
2025-01-17 23:15 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc_wl: Introduce debugfs interface Patchwork
2025-01-17 23:15 ` ✗ Fi.CI.SPARSE: " Patchwork
2025-01-17 23:28 ` ✓ i915.CI.BAT: success " Patchwork
2025-01-20 12:34 ` ✗ i915.CI.Full: failure " Patchwork
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