* [CI v2 v2 01/12] drm/i915/gmbus: convert to struct intel_display
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
@ 2024-10-28 20:07 ` Jani Nikula
2024-10-28 20:07 ` [CI v2 v2 02/12] drm/i915/cx0: remove unnecessary includes Jani Nikula
` (16 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2024-10-28 20:07 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, Rodrigo Vivi
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch gmbus code over to it.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 6 +-
drivers/gpu/drm/i915/display/intel_crt.c | 6 +-
.../drm/i915/display/intel_display_driver.c | 4 +-
.../gpu/drm/i915/display/intel_display_irq.c | 11 +-
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 5 +-
drivers/gpu/drm/i915/display/intel_dvo.c | 8 +-
drivers/gpu/drm/i915/display/intel_gmbus.c | 290 +++++++++---------
drivers/gpu/drm/i915/display/intel_gmbus.h | 15 +-
.../gpu/drm/i915/display/intel_gmbus_regs.h | 16 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 8 +-
.../gpu/drm/i915/display/intel_hotplug_irq.c | 6 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 9 +-
drivers/gpu/drm/i915/i915_suspend.c | 2 +-
14 files changed, 202 insertions(+), 186 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 9967b65e3cf6..48c010b5b150 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2796,7 +2796,6 @@ static bool child_device_size_valid(struct intel_display *display, int size)
static void
parse_general_definitions(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
const struct bdb_general_definitions *defs;
struct intel_bios_encoder_data *devdata;
const struct child_device_config *child;
@@ -2821,7 +2820,7 @@ parse_general_definitions(struct intel_display *display)
bus_pin = defs->crt_ddc_gmbus_pin;
drm_dbg_kms(display->drm, "crt_ddc_bus_pin: %d\n", bus_pin);
- if (intel_gmbus_is_valid_pin(i915, bus_pin))
+ if (intel_gmbus_is_valid_pin(display, bus_pin))
display->vbt.crt_ddc_pin = bus_pin;
if (!child_device_size_valid(display, defs->child_dev_size))
@@ -3338,7 +3337,6 @@ bool intel_bios_is_tv_present(struct intel_display *display)
*/
bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
const struct intel_bios_encoder_data *devdata;
if (list_empty(&display->vbt.display_devices))
@@ -3355,7 +3353,7 @@ bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin)
child->device_type != DEVICE_TYPE_LFP)
continue;
- if (intel_gmbus_is_valid_pin(i915, child->i2c_pin))
+ if (intel_gmbus_is_valid_pin(display, child->i2c_pin))
*i2c_pin = child->i2c_pin;
/* However, we cannot trust the BIOS writers to populate
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index fd78adbaadbe..8222b1c251db 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -935,6 +935,7 @@ intel_crt_detect(struct drm_connector *connector,
static int intel_crt_get_modes(struct drm_connector *connector)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_device *dev = connector->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
@@ -954,7 +955,7 @@ static int intel_crt_get_modes(struct drm_connector *connector)
goto out;
/* Try to probe digital port for output in DVI-I -> VGA mode. */
- ddc = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
+ ddc = intel_gmbus_get_adapter(display, GMBUS_PIN_DPB);
ret = intel_crt_ddc_get_modes(connector, ddc);
out:
@@ -1009,6 +1010,7 @@ static const struct drm_encoder_funcs intel_crt_enc_funcs = {
void intel_crt_init(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct drm_connector *connector;
struct intel_crt *crt;
struct intel_connector *intel_connector;
@@ -1057,7 +1059,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
drm_connector_init_with_ddc(&dev_priv->drm, connector,
&intel_crt_connector_funcs,
DRM_MODE_CONNECTOR_VGA,
- intel_gmbus_get_adapter(dev_priv, ddc_pin));
+ intel_gmbus_get_adapter(display, ddc_pin));
drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
DRM_MODE_ENCODER_DAC, "CRT");
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 673f9b965494..ae5470078173 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -432,7 +432,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
intel_pps_setup(display);
- intel_gmbus_setup(i915);
+ intel_gmbus_setup(display);
drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
INTEL_NUM_PIPES(i915),
@@ -608,7 +608,7 @@ void intel_display_driver_remove_noirq(struct drm_i915_private *i915)
intel_overlay_cleanup(i915);
- intel_gmbus_teardown(i915);
+ intel_gmbus_teardown(display);
destroy_workqueue(i915->display.wq.flip);
destroy_workqueue(i915->display.wq.modeset);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index a4f42ed3f21a..0478fe3cdd86 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -543,12 +543,13 @@ void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
intel_opregion_asle_intr(display);
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
- intel_gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(display);
}
void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
u32 pipe_stats[I915_MAX_PIPES])
{
+ struct intel_display *display = &dev_priv->display;
enum pipe pipe;
for_each_pipe(dev_priv, pipe) {
@@ -566,7 +567,7 @@ void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
}
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
- intel_gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(display);
}
static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
@@ -588,7 +589,7 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_dp_aux_irq_handler(display);
if (pch_iir & SDE_GMBUS)
- intel_gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(display);
if (pch_iir & SDE_AUDIO_HDCP_MASK)
drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
@@ -677,7 +678,7 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_dp_aux_irq_handler(display);
if (pch_iir & SDE_GMBUS_CPT)
- intel_gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(display);
if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
@@ -1109,7 +1110,7 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
(iir & BXT_DE_PORT_GMBUS)) {
- intel_gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(display);
found = true;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index f0e3be0fe420..e8129a720210 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -323,6 +323,7 @@ enum {
static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
int gpio, bool value)
{
+ struct intel_display *display = &dev_priv->display;
int index;
if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 11 && gpio >= MIPI_RESET_2))
@@ -367,7 +368,7 @@ static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
case MIPI_AVEE_EN_2:
index = gpio == MIPI_AVEE_EN_1 ? 1 : 2;
- intel_de_rmw(dev_priv, GPIO(dev_priv, index),
+ intel_de_rmw(display, GPIO(display, index),
GPIO_CLOCK_VAL_OUT,
GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT |
GPIO_CLOCK_VAL_MASK | (value ? GPIO_CLOCK_VAL_OUT : 0));
@@ -376,7 +377,7 @@ static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
case MIPI_VIO_EN_2:
index = gpio == MIPI_VIO_EN_1 ? 1 : 2;
- intel_de_rmw(dev_priv, GPIO(dev_priv, index),
+ intel_de_rmw(display, GPIO(display, index),
GPIO_DATA_VAL_OUT,
GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT |
GPIO_DATA_VAL_MASK | (value ? GPIO_DATA_VAL_OUT : 0));
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index 9508ceae0d84..2d5ffb37eac9 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -417,6 +417,7 @@ static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv,
struct intel_dvo *intel_dvo,
const struct intel_dvo_device *dvo)
{
+ struct intel_display *display = &dev_priv->display;
struct i2c_adapter *i2c;
u32 dpll[I915_MAX_PIPES];
enum pipe pipe;
@@ -428,7 +429,7 @@ static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv,
* special cases, but otherwise default to what's defined
* in the spec.
*/
- if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio))
+ if (intel_gmbus_is_valid_pin(display, dvo->gpio))
gpio = dvo->gpio;
else if (dvo->type == INTEL_DVO_CHIP_LVDS)
gpio = GMBUS_PIN_SSC;
@@ -440,7 +441,7 @@ static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv,
* It appears that everything is on GPIOE except for panels
* on i830 laptops, which are on GPIOB (DVOA).
*/
- i2c = intel_gmbus_get_adapter(dev_priv, gpio);
+ i2c = intel_gmbus_get_adapter(display, gpio);
intel_dvo->dev = *dvo;
@@ -489,6 +490,7 @@ static bool intel_dvo_probe(struct drm_i915_private *i915,
void intel_dvo_init(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
struct intel_connector *connector;
struct intel_encoder *encoder;
struct intel_dvo *intel_dvo;
@@ -549,7 +551,7 @@ void intel_dvo_init(struct drm_i915_private *i915)
drm_connector_init_with_ddc(&i915->drm, &connector->base,
&intel_dvo_connector_funcs,
intel_dvo_connector_type(&intel_dvo->dev),
- intel_gmbus_get_adapter(i915, GMBUS_PIN_DPC));
+ intel_gmbus_get_adapter(display, GMBUS_PIN_DPC));
drm_connector_helper_add(&connector->base,
&intel_dvo_connector_helper_funcs);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 6470f75106bd..e3d938c7f83e 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -48,7 +48,7 @@ struct intel_gmbus {
u32 reg0;
i915_reg_t gpio_reg;
struct i2c_algo_bit_data bit_algo;
- struct drm_i915_private *i915;
+ struct intel_display *display;
};
enum gmbus_gpio {
@@ -149,9 +149,10 @@ static const struct gmbus_pin gmbus_pins_mtp[] = {
[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
};
-static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
+static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display,
unsigned int pin)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
const struct gmbus_pin *pins;
size_t size;
@@ -173,7 +174,7 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
pins = gmbus_pins_bxt;
size = ARRAY_SIZE(gmbus_pins_bxt);
- } else if (DISPLAY_VER(i915) == 9) {
+ } else if (DISPLAY_VER(display) == 9) {
pins = gmbus_pins_skl;
size = ARRAY_SIZE(gmbus_pins_skl);
} else if (IS_BROADWELL(i915)) {
@@ -190,9 +191,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
return &pins[pin];
}
-bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin)
+bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin)
{
- return get_gmbus_pin(i915, pin);
+ return get_gmbus_pin(display, pin);
}
/* Intel GPIO access functions */
@@ -206,42 +207,45 @@ to_intel_gmbus(struct i2c_adapter *i2c)
}
void
-intel_gmbus_reset(struct drm_i915_private *i915)
+intel_gmbus_reset(struct intel_display *display)
{
- intel_de_write(i915, GMBUS0(i915), 0);
- intel_de_write(i915, GMBUS4(i915), 0);
+ intel_de_write(display, GMBUS0(display), 0);
+ intel_de_write(display, GMBUS4(display), 0);
}
-static void pnv_gmbus_clock_gating(struct drm_i915_private *i915,
+static void pnv_gmbus_clock_gating(struct intel_display *display,
bool enable)
{
/* When using bit bashing for I2C, this bit needs to be set to 1 */
- intel_de_rmw(i915, DSPCLK_GATE_D(i915), PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,
+ intel_de_rmw(display, DSPCLK_GATE_D(display),
+ PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,
!enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
}
-static void pch_gmbus_clock_gating(struct drm_i915_private *i915,
+static void pch_gmbus_clock_gating(struct intel_display *display,
bool enable)
{
- intel_de_rmw(i915, SOUTH_DSPCLK_GATE_D, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE,
+ intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
+ PCH_GMBUSUNIT_CLOCK_GATE_DISABLE,
!enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
}
-static void bxt_gmbus_clock_gating(struct drm_i915_private *i915,
+static void bxt_gmbus_clock_gating(struct intel_display *display,
bool enable)
{
- intel_de_rmw(i915, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS,
+ intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS,
!enable ? BXT_GMBUS_GATING_DIS : 0);
}
static u32 get_reserved(struct intel_gmbus *bus)
{
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
u32 reserved = 0;
/* On most chips, these bits must be preserved in software. */
if (!IS_I830(i915) && !IS_I845G(i915))
- reserved = intel_de_read_notrace(i915, bus->gpio_reg) &
+ reserved = intel_de_read_notrace(display, bus->gpio_reg) &
(GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE);
return reserved;
@@ -250,31 +254,31 @@ static u32 get_reserved(struct intel_gmbus *bus)
static int get_clock(void *data)
{
struct intel_gmbus *bus = data;
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
u32 reserved = get_reserved(bus);
- intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
- intel_de_write_notrace(i915, bus->gpio_reg, reserved);
+ intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
+ intel_de_write_notrace(display, bus->gpio_reg, reserved);
- return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
+ return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
}
static int get_data(void *data)
{
struct intel_gmbus *bus = data;
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
u32 reserved = get_reserved(bus);
- intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
- intel_de_write_notrace(i915, bus->gpio_reg, reserved);
+ intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
+ intel_de_write_notrace(display, bus->gpio_reg, reserved);
- return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
+ return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
}
static void set_clock(void *data, int state_high)
{
struct intel_gmbus *bus = data;
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
u32 reserved = get_reserved(bus);
u32 clock_bits;
@@ -284,14 +288,14 @@ static void set_clock(void *data, int state_high)
clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
GPIO_CLOCK_VAL_MASK;
- intel_de_write_notrace(i915, bus->gpio_reg, reserved | clock_bits);
- intel_de_posting_read(i915, bus->gpio_reg);
+ intel_de_write_notrace(display, bus->gpio_reg, reserved | clock_bits);
+ intel_de_posting_read(display, bus->gpio_reg);
}
static void set_data(void *data, int state_high)
{
struct intel_gmbus *bus = data;
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
u32 reserved = get_reserved(bus);
u32 data_bits;
@@ -301,20 +305,21 @@ static void set_data(void *data, int state_high)
data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
GPIO_DATA_VAL_MASK;
- intel_de_write_notrace(i915, bus->gpio_reg, reserved | data_bits);
- intel_de_posting_read(i915, bus->gpio_reg);
+ intel_de_write_notrace(display, bus->gpio_reg, reserved | data_bits);
+ intel_de_posting_read(display, bus->gpio_reg);
}
static int
intel_gpio_pre_xfer(struct i2c_adapter *adapter)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
- intel_gmbus_reset(i915);
+ intel_gmbus_reset(display);
if (IS_PINEVIEW(i915))
- pnv_gmbus_clock_gating(i915, false);
+ pnv_gmbus_clock_gating(display, false);
set_data(bus, 1);
set_clock(bus, 1);
@@ -326,13 +331,14 @@ static void
intel_gpio_post_xfer(struct i2c_adapter *adapter)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
set_data(bus, 1);
set_clock(bus, 1);
if (IS_PINEVIEW(i915))
- pnv_gmbus_clock_gating(i915, true);
+ pnv_gmbus_clock_gating(display, true);
}
static void
@@ -355,16 +361,17 @@ intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg)
algo->data = bus;
}
-static bool has_gmbus_irq(struct drm_i915_private *i915)
+static bool has_gmbus_irq(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
/*
* encoder->shutdown() may want to use GMBUS
* after irqs have already been disabled.
*/
- return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915);
+ return HAS_GMBUS_IRQ(display) && intel_irqs_enabled(i915);
}
-static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en)
+static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en)
{
DEFINE_WAIT(wait);
u32 gmbus2;
@@ -374,21 +381,21 @@ static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en)
* we also need to check for NAKs besides the hw ready/idle signal, we
* need to wake up periodically and check that ourselves.
*/
- if (!has_gmbus_irq(i915))
+ if (!has_gmbus_irq(display))
irq_en = 0;
- add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
- intel_de_write_fw(i915, GMBUS4(i915), irq_en);
+ add_wait_queue(&display->gmbus.wait_queue, &wait);
+ intel_de_write_fw(display, GMBUS4(display), irq_en);
status |= GMBUS_SATOER;
- ret = wait_for_us((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status,
+ ret = wait_for_us((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status,
2);
if (ret)
- ret = wait_for((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status,
+ ret = wait_for((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status,
50);
- intel_de_write_fw(i915, GMBUS4(i915), 0);
- remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
+ intel_de_write_fw(display, GMBUS4(display), 0);
+ remove_wait_queue(&display->gmbus.wait_queue, &wait);
if (gmbus2 & GMBUS_SATOER)
return -ENXIO;
@@ -397,7 +404,7 @@ static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en)
}
static int
-gmbus_wait_idle(struct drm_i915_private *i915)
+gmbus_wait_idle(struct intel_display *display)
{
DEFINE_WAIT(wait);
u32 irq_enable;
@@ -405,33 +412,33 @@ gmbus_wait_idle(struct drm_i915_private *i915)
/* Important: The hw handles only the first bit, so set only one! */
irq_enable = 0;
- if (has_gmbus_irq(i915))
+ if (has_gmbus_irq(display))
irq_enable = GMBUS_IDLE_EN;
- add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
- intel_de_write_fw(i915, GMBUS4(i915), irq_enable);
+ add_wait_queue(&display->gmbus.wait_queue, &wait);
+ intel_de_write_fw(display, GMBUS4(display), irq_enable);
- ret = intel_de_wait_fw(i915, GMBUS2(i915), GMBUS_ACTIVE, 0, 10);
+ ret = intel_de_wait_fw(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10);
- intel_de_write_fw(i915, GMBUS4(i915), 0);
- remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
+ intel_de_write_fw(display, GMBUS4(display), 0);
+ remove_wait_queue(&display->gmbus.wait_queue, &wait);
return ret;
}
-static unsigned int gmbus_max_xfer_size(struct drm_i915_private *i915)
+static unsigned int gmbus_max_xfer_size(struct intel_display *display)
{
- return DISPLAY_VER(i915) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
+ return DISPLAY_VER(display) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
GMBUS_BYTE_COUNT_MAX;
}
static int
-gmbus_xfer_read_chunk(struct drm_i915_private *i915,
+gmbus_xfer_read_chunk(struct intel_display *display,
unsigned short addr, u8 *buf, unsigned int len,
u32 gmbus0_reg, u32 gmbus1_index)
{
unsigned int size = len;
- bool burst_read = len > gmbus_max_xfer_size(i915);
+ bool burst_read = len > gmbus_max_xfer_size(display);
bool extra_byte_added = false;
if (burst_read) {
@@ -444,21 +451,21 @@ gmbus_xfer_read_chunk(struct drm_i915_private *i915,
len++;
}
size = len % 256 + 256;
- intel_de_write_fw(i915, GMBUS0(i915),
+ intel_de_write_fw(display, GMBUS0(display),
gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
}
- intel_de_write_fw(i915, GMBUS1(i915),
+ intel_de_write_fw(display, GMBUS1(display),
gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
while (len) {
int ret;
u32 val, loop = 0;
- ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
+ ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
if (ret)
return ret;
- val = intel_de_read_fw(i915, GMBUS3(i915));
+ val = intel_de_read_fw(display, GMBUS3(display));
do {
if (extra_byte_added && len == 1)
break;
@@ -469,7 +476,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *i915,
if (burst_read && len == size - 4)
/* Reset the override bit */
- intel_de_write_fw(i915, GMBUS0(i915), gmbus0_reg);
+ intel_de_write_fw(display, GMBUS0(display), gmbus0_reg);
}
return 0;
@@ -486,9 +493,10 @@ gmbus_xfer_read_chunk(struct drm_i915_private *i915,
#define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
static int
-gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg,
+gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg,
u32 gmbus0_reg, u32 gmbus1_index)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
u8 *buf = msg->buf;
unsigned int rx_size = msg->len;
unsigned int len;
@@ -498,9 +506,9 @@ gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg,
if (HAS_GMBUS_BURST_READ(i915))
len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
else
- len = min(rx_size, gmbus_max_xfer_size(i915));
+ len = min(rx_size, gmbus_max_xfer_size(display));
- ret = gmbus_xfer_read_chunk(i915, msg->addr, buf, len,
+ ret = gmbus_xfer_read_chunk(display, msg->addr, buf, len,
gmbus0_reg, gmbus1_index);
if (ret)
return ret;
@@ -513,7 +521,7 @@ gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg,
}
static int
-gmbus_xfer_write_chunk(struct drm_i915_private *i915,
+gmbus_xfer_write_chunk(struct intel_display *display,
unsigned short addr, u8 *buf, unsigned int len,
u32 gmbus1_index)
{
@@ -526,8 +534,8 @@ gmbus_xfer_write_chunk(struct drm_i915_private *i915,
len -= 1;
}
- intel_de_write_fw(i915, GMBUS3(i915), val);
- intel_de_write_fw(i915, GMBUS1(i915),
+ intel_de_write_fw(display, GMBUS3(display), val);
+ intel_de_write_fw(display, GMBUS1(display),
gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
while (len) {
int ret;
@@ -537,9 +545,9 @@ gmbus_xfer_write_chunk(struct drm_i915_private *i915,
val |= *buf++ << (8 * loop);
} while (--len && ++loop < 4);
- intel_de_write_fw(i915, GMBUS3(i915), val);
+ intel_de_write_fw(display, GMBUS3(display), val);
- ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
+ ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
if (ret)
return ret;
}
@@ -548,7 +556,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *i915,
}
static int
-gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg,
+gmbus_xfer_write(struct intel_display *display, struct i2c_msg *msg,
u32 gmbus1_index)
{
u8 *buf = msg->buf;
@@ -557,9 +565,9 @@ gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg,
int ret;
do {
- len = min(tx_size, gmbus_max_xfer_size(i915));
+ len = min(tx_size, gmbus_max_xfer_size(display));
- ret = gmbus_xfer_write_chunk(i915, msg->addr, buf, len,
+ ret = gmbus_xfer_write_chunk(display, msg->addr, buf, len,
gmbus1_index);
if (ret)
return ret;
@@ -586,7 +594,7 @@ gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
}
static int
-gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs,
+gmbus_index_xfer(struct intel_display *display, struct i2c_msg *msgs,
u32 gmbus0_reg)
{
u32 gmbus1_index = 0;
@@ -602,17 +610,17 @@ gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs,
/* GMBUS5 holds 16-bit index */
if (gmbus5)
- intel_de_write_fw(i915, GMBUS5(i915), gmbus5);
+ intel_de_write_fw(display, GMBUS5(display), gmbus5);
if (msgs[1].flags & I2C_M_RD)
- ret = gmbus_xfer_read(i915, &msgs[1], gmbus0_reg,
+ ret = gmbus_xfer_read(display, &msgs[1], gmbus0_reg,
gmbus1_index);
else
- ret = gmbus_xfer_write(i915, &msgs[1], gmbus1_index);
+ ret = gmbus_xfer_write(display, &msgs[1], gmbus1_index);
/* Clear GMBUS5 after each index transfer */
if (gmbus5)
- intel_de_write_fw(i915, GMBUS5(i915), 0);
+ intel_de_write_fw(display, GMBUS5(display), 0);
return ret;
}
@@ -622,34 +630,35 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
u32 gmbus0_source)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
int i = 0, inc, try = 0;
int ret = 0;
/* Display WA #0868: skl,bxt,kbl,cfl,glk */
if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
- bxt_gmbus_clock_gating(i915, false);
+ bxt_gmbus_clock_gating(display, false);
else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915))
- pch_gmbus_clock_gating(i915, false);
+ pch_gmbus_clock_gating(display, false);
retry:
- intel_de_write_fw(i915, GMBUS0(i915), gmbus0_source | bus->reg0);
+ intel_de_write_fw(display, GMBUS0(display), gmbus0_source | bus->reg0);
for (; i < num; i += inc) {
inc = 1;
if (gmbus_is_index_xfer(msgs, i, num)) {
- ret = gmbus_index_xfer(i915, &msgs[i],
+ ret = gmbus_index_xfer(display, &msgs[i],
gmbus0_source | bus->reg0);
inc = 2; /* an index transmission is two msgs */
} else if (msgs[i].flags & I2C_M_RD) {
- ret = gmbus_xfer_read(i915, &msgs[i],
+ ret = gmbus_xfer_read(display, &msgs[i],
gmbus0_source | bus->reg0, 0);
} else {
- ret = gmbus_xfer_write(i915, &msgs[i], 0);
+ ret = gmbus_xfer_write(display, &msgs[i], 0);
}
if (!ret)
- ret = gmbus_wait(i915,
+ ret = gmbus_wait(display,
GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
if (ret == -ETIMEDOUT)
goto timeout;
@@ -661,19 +670,19 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
* a STOP on the very first cycle. To simplify the code we
* unconditionally generate the STOP condition with an additional gmbus
* cycle. */
- intel_de_write_fw(i915, GMBUS1(i915), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
+ intel_de_write_fw(display, GMBUS1(display), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
/* Mark the GMBUS interface as disabled after waiting for idle.
* We will re-enable it at the start of the next xfer,
* till then let it sleep.
*/
- if (gmbus_wait_idle(i915)) {
- drm_dbg_kms(&i915->drm,
+ if (gmbus_wait_idle(display)) {
+ drm_dbg_kms(display->drm,
"GMBUS [%s] timed out waiting for idle\n",
adapter->name);
ret = -ETIMEDOUT;
}
- intel_de_write_fw(i915, GMBUS0(i915), 0);
+ intel_de_write_fw(display, GMBUS0(display), 0);
ret = ret ?: i;
goto out;
@@ -692,8 +701,8 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
* it's slow responding and only answers on the 2nd retry.
*/
ret = -ENXIO;
- if (gmbus_wait_idle(i915)) {
- drm_dbg_kms(&i915->drm,
+ if (gmbus_wait_idle(display)) {
+ drm_dbg_kms(display->drm,
"GMBUS [%s] timed out after NAK\n",
adapter->name);
ret = -ETIMEDOUT;
@@ -703,11 +712,11 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
* of resetting the GMBUS controller and so clearing the
* BUS_ERROR raised by the target's NAK.
*/
- intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT);
- intel_de_write_fw(i915, GMBUS1(i915), 0);
- intel_de_write_fw(i915, GMBUS0(i915), 0);
+ intel_de_write_fw(display, GMBUS1(display), GMBUS_SW_CLR_INT);
+ intel_de_write_fw(display, GMBUS1(display), 0);
+ intel_de_write_fw(display, GMBUS0(display), 0);
- drm_dbg_kms(&i915->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
+ drm_dbg_kms(display->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
adapter->name, msgs[i].addr,
(msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
@@ -718,7 +727,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
* drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
*/
if (ret == -ENXIO && i == 0 && try++ == 0) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"GMBUS [%s] NAK on first message, retry\n",
adapter->name);
goto retry;
@@ -727,10 +736,10 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
goto out;
timeout:
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
bus->adapter.name, bus->reg0 & 0xff);
- intel_de_write_fw(i915, GMBUS0(i915), 0);
+ intel_de_write_fw(display, GMBUS0(display), 0);
/*
* Hardware may not support GMBUS over these pins? Try GPIO bitbanging
@@ -741,9 +750,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
out:
/* Display WA #0868: skl,bxt,kbl,cfl,glk */
if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
- bxt_gmbus_clock_gating(i915, true);
+ bxt_gmbus_clock_gating(display, true);
else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915))
- pch_gmbus_clock_gating(i915, true);
+ pch_gmbus_clock_gating(display, true);
return ret;
}
@@ -752,7 +761,8 @@ static int
gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
intel_wakeref_t wakeref;
int ret;
@@ -776,7 +786,8 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
u8 cmd = DRM_HDCP_DDC_AKSV;
u8 buf[DRM_HDCP_KSV_LEN] = {};
struct i2c_msg msgs[] = {
@@ -797,7 +808,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
int ret;
wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS);
- mutex_lock(&i915->display.gmbus.mutex);
+ mutex_lock(&display->gmbus.mutex);
/*
* In order to output Aksv to the receiver, use an indexed write to
@@ -806,7 +817,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
*/
ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
- mutex_unlock(&i915->display.gmbus.mutex);
+ mutex_unlock(&display->gmbus.mutex);
intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref);
return ret;
@@ -830,27 +841,27 @@ static void gmbus_lock_bus(struct i2c_adapter *adapter,
unsigned int flags)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
- mutex_lock(&i915->display.gmbus.mutex);
+ mutex_lock(&display->gmbus.mutex);
}
static int gmbus_trylock_bus(struct i2c_adapter *adapter,
unsigned int flags)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
- return mutex_trylock(&i915->display.gmbus.mutex);
+ return mutex_trylock(&display->gmbus.mutex);
}
static void gmbus_unlock_bus(struct i2c_adapter *adapter,
unsigned int flags)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
- mutex_unlock(&i915->display.gmbus.mutex);
+ mutex_unlock(&display->gmbus.mutex);
}
static const struct i2c_lock_operations gmbus_lock_ops = {
@@ -861,31 +872,32 @@ static const struct i2c_lock_operations gmbus_lock_ops = {
/**
* intel_gmbus_setup - instantiate all Intel i2c GMBuses
- * @i915: i915 device private
+ * @display: display device
*/
-int intel_gmbus_setup(struct drm_i915_private *i915)
+int intel_gmbus_setup(struct intel_display *display)
{
- struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct drm_i915_private *i915 = to_i915(display->drm);
+ struct pci_dev *pdev = to_pci_dev(display->drm->dev);
unsigned int pin;
int ret;
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
- i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE;
- else if (!HAS_GMCH(i915))
+ display->gmbus.mmio_base = VLV_DISPLAY_BASE;
+ else if (!HAS_GMCH(display))
/*
* Broxton uses the same PCH offsets for South Display Engine,
* even though it doesn't have a PCH.
*/
- i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE;
+ display->gmbus.mmio_base = PCH_DISPLAY_BASE;
- mutex_init(&i915->display.gmbus.mutex);
- init_waitqueue_head(&i915->display.gmbus.wait_queue);
+ mutex_init(&display->gmbus.mutex);
+ init_waitqueue_head(&display->gmbus.wait_queue);
- for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) {
+ for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {
const struct gmbus_pin *gmbus_pin;
struct intel_gmbus *bus;
- gmbus_pin = get_gmbus_pin(i915, pin);
+ gmbus_pin = get_gmbus_pin(display, pin);
if (!gmbus_pin)
continue;
@@ -901,7 +913,7 @@ int intel_gmbus_setup(struct drm_i915_private *i915)
"i915 gmbus %s", gmbus_pin->name);
bus->adapter.dev.parent = &pdev->dev;
- bus->i915 = i915;
+ bus->display = display;
bus->adapter.algo = &gmbus_algorithm;
bus->adapter.lock_ops = &gmbus_lock_ops;
@@ -919,7 +931,7 @@ int intel_gmbus_setup(struct drm_i915_private *i915)
if (IS_I830(i915))
bus->force_bit = 1;
- intel_gpio_setup(bus, GPIO(i915, gmbus_pin->gpio));
+ intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio));
ret = i2c_add_adapter(&bus->adapter);
if (ret) {
@@ -927,43 +939,43 @@ int intel_gmbus_setup(struct drm_i915_private *i915)
goto err;
}
- i915->display.gmbus.bus[pin] = bus;
+ display->gmbus.bus[pin] = bus;
}
- intel_gmbus_reset(i915);
+ intel_gmbus_reset(display);
return 0;
err:
- intel_gmbus_teardown(i915);
+ intel_gmbus_teardown(display);
return ret;
}
-struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *i915,
+struct i2c_adapter *intel_gmbus_get_adapter(struct intel_display *display,
unsigned int pin)
{
- if (drm_WARN_ON(&i915->drm, pin >= ARRAY_SIZE(i915->display.gmbus.bus) ||
- !i915->display.gmbus.bus[pin]))
+ if (drm_WARN_ON(display->drm, pin >= ARRAY_SIZE(display->gmbus.bus) ||
+ !display->gmbus.bus[pin]))
return NULL;
- return &i915->display.gmbus.bus[pin]->adapter;
+ return &display->gmbus.bus[pin]->adapter;
}
void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
- mutex_lock(&i915->display.gmbus.mutex);
+ mutex_lock(&display->gmbus.mutex);
bus->force_bit += force_bit ? 1 : -1;
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"%sabling bit-banging on %s. force bit now %d\n",
force_bit ? "en" : "dis", adapter->name,
bus->force_bit);
- mutex_unlock(&i915->display.gmbus.mutex);
+ mutex_unlock(&display->gmbus.mutex);
}
bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
@@ -973,25 +985,25 @@ bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
return bus->force_bit;
}
-void intel_gmbus_teardown(struct drm_i915_private *i915)
+void intel_gmbus_teardown(struct intel_display *display)
{
unsigned int pin;
- for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) {
+ for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {
struct intel_gmbus *bus;
- bus = i915->display.gmbus.bus[pin];
+ bus = display->gmbus.bus[pin];
if (!bus)
continue;
i2c_del_adapter(&bus->adapter);
kfree(bus);
- i915->display.gmbus.bus[pin] = NULL;
+ display->gmbus.bus[pin] = NULL;
}
}
-void intel_gmbus_irq_handler(struct drm_i915_private *i915)
+void intel_gmbus_irq_handler(struct intel_display *display)
{
- wake_up_all(&i915->display.gmbus.wait_queue);
+ wake_up_all(&display->gmbus.wait_queue);
}
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h b/drivers/gpu/drm/i915/display/intel_gmbus.h
index 8111eb23e2af..35a200a9efc0 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.h
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
@@ -8,8 +8,8 @@
#include <linux/types.h>
-struct drm_i915_private;
struct i2c_adapter;
+struct intel_display;
#define GMBUS_PIN_DISABLED 0
#define GMBUS_PIN_SSC 1
@@ -34,18 +34,17 @@ struct i2c_adapter;
#define GMBUS_NUM_PINS 15 /* including 0 */
-int intel_gmbus_setup(struct drm_i915_private *dev_priv);
-void intel_gmbus_teardown(struct drm_i915_private *dev_priv);
-bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
- unsigned int pin);
+int intel_gmbus_setup(struct intel_display *display);
+void intel_gmbus_teardown(struct intel_display *display);
+bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin);
int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
struct i2c_adapter *
-intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
+intel_gmbus_get_adapter(struct intel_display *display, unsigned int pin);
void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter);
-void intel_gmbus_reset(struct drm_i915_private *dev_priv);
+void intel_gmbus_reset(struct intel_display *display);
-void intel_gmbus_irq_handler(struct drm_i915_private *i915);
+void intel_gmbus_irq_handler(struct intel_display *display);
#endif /* __INTEL_GMBUS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus_regs.h b/drivers/gpu/drm/i915/display/intel_gmbus_regs.h
index 53aacbda983c..59bad1dda6d6 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_gmbus_regs.h
@@ -8,9 +8,9 @@
#include "i915_reg_defs.h"
-#define GMBUS_MMIO_BASE(__i915) ((__i915)->display.gmbus.mmio_base)
+#define __GMBUS_MMIO_BASE(__display) ((__display)->gmbus.mmio_base)
-#define GPIO(__i915, gpio) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5010 + 4 * (gpio))
+#define GPIO(__display, gpio) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5010 + 4 * (gpio))
#define GPIO_CLOCK_DIR_MASK (1 << 0)
#define GPIO_CLOCK_DIR_IN (0 << 1)
#define GPIO_CLOCK_DIR_OUT (1 << 1)
@@ -27,7 +27,7 @@
#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
/* clock/port select */
-#define GMBUS0(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5100)
+#define GMBUS0(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5100)
#define GMBUS_AKSV_SELECT (1 << 11)
#define GMBUS_RATE_100KHZ (0 << 8)
#define GMBUS_RATE_50KHZ (1 << 8)
@@ -37,7 +37,7 @@
#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
/* command/status */
-#define GMBUS1(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5104)
+#define GMBUS1(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5104)
#define GMBUS_SW_CLR_INT (1 << 31)
#define GMBUS_SW_RDY (1 << 30)
#define GMBUS_ENT (1 << 29) /* enable timeout */
@@ -54,7 +54,7 @@
#define GMBUS_SLAVE_WRITE (0 << 0)
/* status */
-#define GMBUS2(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5108)
+#define GMBUS2(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5108)
#define GMBUS_INUSE (1 << 15)
#define GMBUS_HW_WAIT_PHASE (1 << 14)
#define GMBUS_STALL_TIMEOUT (1 << 13)
@@ -64,10 +64,10 @@
#define GMBUS_ACTIVE (1 << 9)
/* data buffer bytes 3-0 */
-#define GMBUS3(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x510c)
+#define GMBUS3(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x510c)
/* interrupt mask (Pineview+) */
-#define GMBUS4(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5110)
+#define GMBUS4(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5110)
#define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
#define GMBUS_NAK_EN (1 << 3)
#define GMBUS_IDLE_EN (1 << 2)
@@ -75,7 +75,7 @@
#define GMBUS_HW_RDY_EN (1 << 0)
/* byte index */
-#define GMBUS5(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5120)
+#define GMBUS5(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5120)
#define GMBUS_2BYTE_INDEX_EN (1 << 31)
#endif /* __INTEL_GMBUS_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 6a16194b1105..37b61f05bd73 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2918,7 +2918,6 @@ static struct intel_encoder *
get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin)
{
struct intel_display *display = to_intel_display(encoder);
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_encoder *other;
for_each_intel_encoder(display->drm, other) {
@@ -2932,7 +2931,7 @@ get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin)
connector = enc_to_dig_port(other)->hdmi.attached_connector;
- if (connector && connector->base.ddc == intel_gmbus_get_adapter(i915, ddc_pin))
+ if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin))
return other;
}
@@ -2942,7 +2941,6 @@ get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin)
static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_encoder *other;
const char *source;
u8 ddc_pin;
@@ -2955,7 +2953,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
source = "platform default";
}
- if (!intel_gmbus_is_valid_pin(i915, ddc_pin)) {
+ if (!intel_gmbus_is_valid_pin(display, ddc_pin)) {
drm_dbg_kms(display->drm,
"[ENCODER:%d:%s] Invalid DDC pin %d\n",
encoder->base.base.id, encoder->base.name, ddc_pin);
@@ -3053,7 +3051,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
drm_connector_init_with_ddc(dev, connector,
&intel_hdmi_connector_funcs,
DRM_MODE_CONNECTOR_HDMIA,
- intel_gmbus_get_adapter(dev_priv, ddc_pin));
+ intel_gmbus_get_adapter(display, ddc_pin));
drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 5d055dc9366f..cb64c6f0ad1b 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -556,6 +556,7 @@ void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
{
+ struct intel_display *display = &dev_priv->display;
u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
u32 pin_mask = 0, long_mask = 0;
@@ -589,11 +590,12 @@ void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
if (pch_iir & SDE_GMBUS_ICP)
- intel_gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(display);
}
void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
{
+ struct intel_display *display = &dev_priv->display;
u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
~SDE_PORTE_HOTPLUG_SPT;
u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
@@ -625,7 +627,7 @@ void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
if (pch_iir & SDE_GMBUS_CPT)
- intel_gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(display);
}
void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 5d022b4215ee..6d7637ad980a 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -901,7 +901,7 @@ void intel_lvds_init(struct drm_i915_private *i915)
drm_connector_init_with_ddc(&i915->drm, &connector->base,
&intel_lvds_connector_funcs,
DRM_MODE_CONNECTOR_LVDS,
- intel_gmbus_get_adapter(i915, ddc_pin));
+ intel_gmbus_get_adapter(display, ddc_pin));
drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs,
DRM_MODE_ENCODER_LVDS, "LVDS");
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index b83bf813677d..7a28104f68ad 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -2082,10 +2082,10 @@ intel_sdvo_get_edid(struct drm_connector *connector)
static const struct drm_edid *
intel_sdvo_get_analog_edid(struct drm_connector *connector)
{
- struct drm_i915_private *i915 = to_i915(connector->dev);
+ struct intel_display *display = to_intel_display(connector->dev);
struct i2c_adapter *ddc;
- ddc = intel_gmbus_get_adapter(i915, i915->display.vbt.crt_ddc_pin);
+ ddc = intel_gmbus_get_adapter(display, display->vbt.crt_ddc_pin);
if (!ddc)
return NULL;
@@ -2638,6 +2638,7 @@ intel_sdvo_select_ddc_bus(struct intel_sdvo *sdvo,
static void
intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
{
+ struct intel_display *display = to_intel_display(&sdvo->base);
struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
const struct sdvo_device_mapping *mapping;
u8 pin;
@@ -2648,7 +2649,7 @@ intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
mapping = &dev_priv->display.vbt.sdvo_mappings[1];
if (mapping->initialized &&
- intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
+ intel_gmbus_is_valid_pin(display, mapping->i2c_pin))
pin = mapping->i2c_pin;
else
pin = GMBUS_PIN_DPB;
@@ -2657,7 +2658,7 @@ intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
sdvo->base.base.base.id, sdvo->base.base.name,
pin, sdvo->target_addr);
- sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
+ sdvo->i2c = intel_gmbus_get_adapter(display, pin);
/*
* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 9d3d9b983032..f18f1acf2158 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -137,5 +137,5 @@ void i915_restore_display(struct drm_i915_private *dev_priv)
intel_vga_redisable(display);
- intel_gmbus_reset(dev_priv);
+ intel_gmbus_reset(display);
}
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [CI v2 v2 02/12] drm/i915/cx0: remove unnecessary includes
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
2024-10-28 20:07 ` [CI v2 v2 01/12] drm/i915/gmbus: convert to struct intel_display Jani Nikula
@ 2024-10-28 20:07 ` Jani Nikula
2024-10-28 20:07 ` [CI v2 v2 03/12] drm/i915/cx0: convert to struct intel_display Jani Nikula
` (15 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2024-10-28 20:07 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, Rodrigo Vivi
There's nothing in the header that requires the bit or bitfield
headers. Remove.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 9004b99bb51f..3555a9bc1de9 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -7,8 +7,6 @@
#define __INTEL_CX0_PHY_H__
#include <linux/types.h>
-#include <linux/bitfield.h>
-#include <linux/bits.h>
enum icl_port_dpll_id;
struct drm_i915_private;
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [CI v2 v2 03/12] drm/i915/cx0: convert to struct intel_display
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
2024-10-28 20:07 ` [CI v2 v2 01/12] drm/i915/gmbus: convert to struct intel_display Jani Nikula
2024-10-28 20:07 ` [CI v2 v2 02/12] drm/i915/cx0: remove unnecessary includes Jani Nikula
@ 2024-10-28 20:07 ` Jani Nikula
2024-10-29 16:08 ` [PATCH] " Jani Nikula
2024-10-28 20:07 ` [CI v2 v2 04/12] drm/i915/dpio: " Jani Nikula
` (14 subsequent siblings)
17 siblings, 1 reply; 22+ messages in thread
From: Jani Nikula @ 2024-10-28 20:07 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, Rodrigo Vivi
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch Cx0 PHY code over to it.
v2: Rebase, split out the include cleanups (Rodrigo)
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 334 ++++++++++---------
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
3 files changed, 186 insertions(+), 160 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 8bd5a4d1b735..666fe6a74347 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -65,22 +65,23 @@ static u8 intel_cx0_get_owned_lane_mask(struct intel_encoder *encoder)
}
static void
-assert_dc_off(struct drm_i915_private *i915)
+assert_dc_off(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
bool enabled;
enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF);
- drm_WARN_ON(&i915->drm, !enabled);
+ drm_WARN_ON(display->drm, !enabled);
}
static void intel_cx0_program_msgbus_timer(struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(encoder);
int lane;
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
for_each_cx0_lane_in_mask(INTEL_CX0_BOTH_LANES, lane)
- intel_de_rmw(i915,
- XELPDP_PORT_MSGBUS_TIMER(i915, encoder->port, lane),
+ intel_de_rmw(display,
+ XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane),
XELPDP_PORT_MSGBUS_TIMER_VAL_MASK,
XELPDP_PORT_MSGBUS_TIMER_VAL);
}
@@ -119,25 +120,28 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_w
static void intel_clear_response_ready_flag(struct intel_encoder *encoder,
int lane)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, encoder->port, lane),
+ intel_de_rmw(display,
+ XELPDP_PORT_P2M_MSGBUS_STATUS(display, encoder->port, lane),
0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET);
}
static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET);
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
- drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
+ drm_err_once(display->drm,
+ "Failed to bring PHY %c to idle.\n",
+ phy_name(phy));
return;
}
@@ -147,22 +151,23 @@ static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
int command, int lane, u32 *val)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
- if (intel_de_wait_custom(i915,
- XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
+ if (intel_de_wait_custom(display,
+ XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_MSGBUS_TIMEOUT_FAST_US,
XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
- drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
+ drm_dbg_kms(display->drm,
+ "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
phy_name(phy), *val);
- if (!(intel_de_read(i915, XELPDP_PORT_MSGBUS_TIMER(i915, port, lane)) &
+ if (!(intel_de_read(display, XELPDP_PORT_MSGBUS_TIMER(display, port, lane)) &
XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT))
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Hardware did not detect a timeout\n",
phy_name(phy));
@@ -171,14 +176,18 @@ static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
}
if (*val & XELPDP_PORT_P2M_ERROR_SET) {
- drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s command. Status: 0x%x\n", phy_name(phy),
+ drm_dbg_kms(display->drm,
+ "PHY %c Error occurred during %s command. Status: 0x%x\n",
+ phy_name(phy),
command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val);
intel_cx0_bus_reset(encoder, lane);
return -EINVAL;
}
if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) != command) {
- drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", phy_name(phy),
+ drm_dbg_kms(display->drm,
+ "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n",
+ phy_name(phy),
command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val);
intel_cx0_bus_reset(encoder, lane);
return -EINVAL;
@@ -190,22 +199,22 @@ static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
static int __intel_cx0_read_once(struct intel_encoder *encoder,
int lane, u16 addr)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
int ack;
u32 val;
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
return -ETIMEDOUT;
}
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
XELPDP_PORT_M2P_COMMAND_READ |
XELPDP_PORT_M2P_ADDRESS(addr));
@@ -229,11 +238,11 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
static u8 __intel_cx0_read(struct intel_encoder *encoder,
int lane, u16 addr)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
int i, status;
- assert_dc_off(i915);
+ assert_dc_off(display);
/* 3 tries is assumed to be enough to read successfully */
for (i = 0; i < 3; i++) {
@@ -243,7 +252,8 @@ static u8 __intel_cx0_read(struct intel_encoder *encoder,
return status;
}
- drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n",
+ drm_err_once(display->drm,
+ "PHY %c Read %04x failed after %d retries.\n",
phy_name(phy), addr, i);
return 0;
@@ -260,32 +270,32 @@ static u8 intel_cx0_read(struct intel_encoder *encoder,
static int __intel_cx0_write_once(struct intel_encoder *encoder,
int lane, u16 addr, u8 data, bool committed)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
int ack;
u32 val;
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for previous transaction to complete. Resetting the bus.\n", phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
return -ETIMEDOUT;
}
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
(committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
XELPDP_PORT_M2P_DATA(data) |
XELPDP_PORT_M2P_ADDRESS(addr));
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for write to complete. Resetting the bus.\n", phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
return -ETIMEDOUT;
@@ -295,9 +305,9 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
if (ack < 0)
return ack;
- } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane)) &
+ } else if ((intel_de_read(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane)) &
XELPDP_PORT_P2M_ERROR_SET)) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Error occurred during write command.\n", phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
return -EINVAL;
@@ -318,11 +328,11 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
static void __intel_cx0_write(struct intel_encoder *encoder,
int lane, u16 addr, u8 data, bool committed)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
int i, status;
- assert_dc_off(i915);
+ assert_dc_off(display);
/* 3 tries is assumed to be enough to write successfully */
for (i = 0; i < 3; i++) {
@@ -332,7 +342,7 @@ static void __intel_cx0_write(struct intel_encoder *encoder,
return;
}
- drm_err_once(&i915->drm,
+ drm_err_once(display->drm,
"PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
}
@@ -348,9 +358,9 @@ static void intel_cx0_write(struct intel_encoder *encoder,
static void intel_c20_sram_write(struct intel_encoder *encoder,
int lane, u16 addr, u16 data)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- assert_dc_off(i915);
+ assert_dc_off(display);
intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0);
intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0);
@@ -362,10 +372,10 @@ static void intel_c20_sram_write(struct intel_encoder *encoder,
static u16 intel_c20_sram_read(struct intel_encoder *encoder,
int lane, u16 addr)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
u16 val;
- assert_dc_off(i915);
+ assert_dc_off(display);
intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0);
intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1);
@@ -429,7 +439,7 @@ static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state)
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
const struct intel_ddi_buf_trans *trans;
u8 owned_lane_mask;
intel_wakeref_t wakeref;
@@ -444,7 +454,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
wakeref = intel_cx0_phy_transaction_begin(encoder);
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
- if (drm_WARN_ON_ONCE(&i915->drm, !trans)) {
+ if (drm_WARN_ON_ONCE(display->drm, !trans)) {
intel_cx0_phy_transaction_end(encoder, wakeref);
return;
}
@@ -2020,7 +2030,6 @@ static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll;
int i;
@@ -2036,7 +2045,7 @@ static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state,
if (pll_state->ssc_enabled)
return;
- drm_WARN_ON(&i915->drm, ARRAY_SIZE(pll_state->c10.pll) < 9);
+ drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 9);
for (i = 4; i < 9; i++)
pll_state->c10.pll[i] = 0;
}
@@ -2090,7 +2099,7 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
intel_cx0_phy_transaction_end(encoder, wakeref);
}
-static void intel_c10_pll_program(struct drm_i915_private *i915,
+static void intel_c10_pll_program(struct intel_display *display,
const struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
@@ -2123,7 +2132,7 @@ static void intel_c10_pll_program(struct drm_i915_private *i915,
MB_WRITE_COMMITTED);
}
-static void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
+static void intel_c10pll_dump_hw_state(struct intel_display *display,
const struct intel_c10pll_state *hw_state)
{
bool fracen;
@@ -2132,29 +2141,31 @@ static void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
unsigned int multiplier, tx_clk_div;
fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
- drm_dbg_kms(&i915->drm, "c10pll_hw_state: fracen: %s, ",
+ drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ",
str_yes_no(fracen));
if (fracen) {
frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13];
frac_den = hw_state->pll[10] << 8 | hw_state->pll[9];
- drm_dbg_kms(&i915->drm, "quot: %u, rem: %u, den: %u,\n",
+ drm_dbg_kms(display->drm, "quot: %u, rem: %u, den: %u,\n",
frac_quot, frac_rem, frac_den);
}
multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 |
hw_state->pll[2]) / 2 + 16;
tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]);
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
- drm_dbg_kms(&i915->drm, "c10pll_rawhw_state:");
- drm_dbg_kms(&i915->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn);
+ drm_dbg_kms(display->drm, "c10pll_rawhw_state:");
+ drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx,
+ hw_state->cmn);
BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4);
for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4)
- drm_dbg_kms(&i915->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
+ drm_dbg_kms(display->drm,
+ "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
}
@@ -2256,17 +2267,17 @@ static const struct intel_c20pll_state * const *
intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(crtc_state);
if (intel_crtc_has_dp_encoder(crtc_state)) {
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
- if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
+ if (DISPLAY_VER_FULL(display) == IP_VER(14, 1))
return xe2hpd_c20_edp_tables;
}
- if (DISPLAY_VER(i915) >= 30)
+ if (DISPLAY_VER(display) >= 30)
return xe3lpd_c20_dp_edp_tables;
- else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
+ else if (DISPLAY_VER_FULL(display) == IP_VER(14, 1))
return xe2hpd_c20_dp_tables;
else
return mtl_c20_dp_tables;
@@ -2368,10 +2379,10 @@ static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_c20pll_state *pll_state)
{
+ struct intel_display *display = to_intel_display(encoder);
bool cntx;
intel_wakeref_t wakeref;
int i;
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
wakeref = intel_cx0_phy_transaction_begin(encoder);
@@ -2383,11 +2394,11 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
if (cntx)
pll_state->tx[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
- PHY_C20_B_TX_CNTX_CFG(i915, i));
+ PHY_C20_B_TX_CNTX_CFG(display, i));
else
pll_state->tx[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
- PHY_C20_A_TX_CNTX_CFG(i915, i));
+ PHY_C20_A_TX_CNTX_CFG(display, i));
}
/* Read common configuration */
@@ -2395,11 +2406,11 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
if (cntx)
pll_state->cmn[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
- PHY_C20_B_CMN_CNTX_CFG(i915, i));
+ PHY_C20_B_CMN_CNTX_CFG(display, i));
else
pll_state->cmn[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
- PHY_C20_A_CMN_CNTX_CFG(i915, i));
+ PHY_C20_A_CMN_CNTX_CFG(display, i));
}
if (intel_c20phy_use_mpllb(pll_state)) {
@@ -2408,11 +2419,11 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
if (cntx)
pll_state->mpllb[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
- PHY_C20_B_MPLLB_CNTX_CFG(i915, i));
+ PHY_C20_B_MPLLB_CNTX_CFG(display, i));
else
pll_state->mpllb[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
- PHY_C20_A_MPLLB_CNTX_CFG(i915, i));
+ PHY_C20_A_MPLLB_CNTX_CFG(display, i));
}
} else {
/* MPLLA configuration */
@@ -2420,11 +2431,11 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
if (cntx)
pll_state->mplla[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
- PHY_C20_B_MPLLA_CNTX_CFG(i915, i));
+ PHY_C20_B_MPLLA_CNTX_CFG(display, i));
else
pll_state->mplla[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
- PHY_C20_A_MPLLA_CNTX_CFG(i915, i));
+ PHY_C20_A_MPLLA_CNTX_CFG(display, i));
}
}
@@ -2433,33 +2444,37 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
intel_cx0_phy_transaction_end(encoder, wakeref);
}
-static void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
+static void intel_c20pll_dump_hw_state(struct intel_display *display,
const struct intel_c20pll_state *hw_state)
{
int i;
- drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n");
- drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
+ drm_dbg_kms(display->drm, "c20pll_hw_state:\n");
+ drm_dbg_kms(display->drm,
+ "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
- drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
+ drm_dbg_kms(display->drm,
+ "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);
if (intel_c20phy_use_mpllb(hw_state)) {
for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++)
- drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
+ drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i,
+ hw_state->mpllb[i]);
} else {
for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
- drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]);
+ drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,
+ hw_state->mplla[i]);
}
}
-void intel_cx0pll_dump_hw_state(struct drm_i915_private *i915,
+void intel_cx0pll_dump_hw_state(struct intel_display *display,
const struct intel_cx0pll_state *hw_state)
{
if (hw_state->use_c10)
- intel_c10pll_dump_hw_state(i915, &hw_state->c10);
+ intel_c10pll_dump_hw_state(display, &hw_state->c10);
else
- intel_c20pll_dump_hw_state(i915, &hw_state->c20);
+ intel_c20pll_dump_hw_state(display, &hw_state->c20);
}
static u8 intel_c20_get_dp_rate(u32 clock)
@@ -2559,7 +2574,7 @@ static int intel_get_c20_custom_width(u32 clock, bool dp)
return 0;
}
-static void intel_c20_pll_program(struct drm_i915_private *i915,
+static void intel_c20_pll_program(struct intel_display *display,
const struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
@@ -2592,11 +2607,11 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_TX_CNTX_CFG(i915, i),
+ PHY_C20_A_TX_CNTX_CFG(display, i),
pll_state->tx[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_TX_CNTX_CFG(i915, i),
+ PHY_C20_B_TX_CNTX_CFG(display, i),
pll_state->tx[i]);
}
@@ -2604,11 +2619,11 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_CMN_CNTX_CFG(i915, i),
+ PHY_C20_A_CMN_CNTX_CFG(display, i),
pll_state->cmn[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_CMN_CNTX_CFG(i915, i),
+ PHY_C20_B_CMN_CNTX_CFG(display, i),
pll_state->cmn[i]);
}
@@ -2617,22 +2632,22 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLB_CNTX_CFG(i915, i),
+ PHY_C20_A_MPLLB_CNTX_CFG(display, i),
pll_state->mpllb[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLB_CNTX_CFG(i915, i),
+ PHY_C20_B_MPLLB_CNTX_CFG(display, i),
pll_state->mpllb[i]);
}
} else {
for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLA_CNTX_CFG(i915, i),
+ PHY_C20_A_MPLLA_CNTX_CFG(display, i),
pll_state->mplla[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLA_CNTX_CFG(i915, i),
+ PHY_C20_B_MPLLA_CNTX_CFG(display, i),
pll_state->mplla[i]);
}
}
@@ -2699,10 +2714,10 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
bool lane_reversal)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
u32 val = 0;
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
XELPDP_PORT_REVERSAL,
lane_reversal ? XELPDP_PORT_REVERSAL : 0);
@@ -2724,7 +2739,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
else
val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA |
XELPDP_SSC_ENABLE_PLLB, val);
@@ -2755,48 +2770,49 @@ static u32 intel_cx0_get_powerdown_state(u8 lane_mask, u8 state)
static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
u8 lane_mask, u8 state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
- i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(i915, port);
+ i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port);
int lane;
- intel_de_rmw(i915, buf_ctl2_reg,
+ intel_de_rmw(display, buf_ctl2_reg,
intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK),
intel_cx0_get_powerdown_state(lane_mask, state));
/* Wait for pending transactions.*/
for_each_cx0_lane_in_mask(lane_mask, lane)
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for previous transaction to complete. Reset the bus.\n",
phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
}
- intel_de_rmw(i915, buf_ctl2_reg,
+ intel_de_rmw(display, buf_ctl2_reg,
intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES),
intel_cx0_get_powerdown_update(lane_mask));
/* Update Timeout Value */
- if (intel_de_wait_custom(i915, buf_ctl2_reg,
+ if (intel_de_wait_custom(display, buf_ctl2_reg,
intel_cx0_get_powerdown_update(lane_mask), 0,
XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
+ drm_warn(display->drm,
+ "PHY %c failed to bring out of Lane reset after %dus.\n",
phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
}
static void intel_cx0_setup_powerdown(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port),
+ intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
XELPDP_POWER_STATE_READY_MASK,
XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(i915, port),
+ intel_de_rmw(display, XELPDP_PORT_BUF_CTL3(display, port),
XELPDP_POWER_STATE_ACTIVE_MASK |
XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
@@ -2828,7 +2844,7 @@ static u32 intel_cx0_get_pclk_refclk_ack(u8 lane_mask)
static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
bool lane_reversal)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
@@ -2841,48 +2857,51 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
XELPDP_LANE_PHY_CURRENT_STATUS(1))
: XELPDP_LANE_PHY_CURRENT_STATUS(0);
- if (intel_de_wait_custom(i915, XELPDP_PORT_BUF_CTL1(i915, port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL1(display, port),
XELPDP_PORT_BUF_SOC_PHY_READY,
XELPDP_PORT_BUF_SOC_PHY_READY,
XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
+ drm_warn(display->drm,
+ "PHY %c failed to bring out of SOC reset after %dus.\n",
phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset,
+ intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset,
lane_pipe_reset);
- if (intel_de_wait_custom(i915, XELPDP_PORT_BUF_CTL2(i915, port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_phy_current_status, lane_phy_current_status,
XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
+ drm_warn(display->drm,
+ "PHY %c failed to bring out of Lane reset after %dus.\n",
phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
intel_cx0_get_pclk_refclk_request(owned_lane_mask),
intel_cx0_get_pclk_refclk_request(lane_mask));
- if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
intel_cx0_get_pclk_refclk_ack(lane_mask),
XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n",
+ drm_warn(display->drm,
+ "PHY %c failed to request refclk after %dus.\n",
phy_name(phy), XELPDP_REFCLK_ENABLE_TIMEOUT_US);
intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
CX0_P2_STATE_RESET);
intel_cx0_setup_powerdown(encoder);
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset, 0);
+ intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 0);
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(i915, port),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_phy_current_status,
XELPDP_PORT_RESET_END_TIMEOUT))
- drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
+ drm_warn(display->drm,
+ "PHY %c failed to bring out of Lane reset after %dms.\n",
phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
}
-static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
- struct intel_encoder *encoder, int lane_count,
+static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_count,
bool lane_reversal)
{
int i;
@@ -2951,7 +2970,7 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
static void intel_cx0pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
@@ -2983,15 +3002,15 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
/* 5. Program PHY internal PLL internal registers. */
if (intel_encoder_is_c10phy(encoder))
- intel_c10_pll_program(i915, crtc_state, encoder);
+ intel_c10_pll_program(display, crtc_state, encoder);
else
- intel_c20_pll_program(i915, crtc_state, encoder);
+ intel_c20_pll_program(display, crtc_state, encoder);
/*
* 6. Program the enabled and disabled owned PHY lane
* transmitters over message bus
*/
- intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal);
+ intel_cx0_program_phy_lane(encoder, crtc_state->lane_count, lane_reversal);
/*
* 7. Follow the Display Voltage Frequency Switching - Sequence
@@ -3002,23 +3021,23 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
* 8. Program DDI_CLK_VALFREQ to match intended DDI
* clock frequency.
*/
- intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
+ intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
crtc_state->port_clock);
/*
* 9. Set PORT_CLOCK_CTL register PCLK PLL Request
* LN<Lane for maxPCLK> to "1" to enable PLL.
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
intel_cx0_get_pclk_pll_request(maxpclk_lane));
/* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
- if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
intel_cx0_get_pclk_pll_ack(maxpclk_lane),
XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "Port %c PLL not locked after %dus.\n",
+ drm_warn(display->drm, "Port %c PLL not locked after %dus.\n",
phy_name(phy), XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US);
/*
@@ -3032,15 +3051,16 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- u32 clock;
- u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
+ struct intel_display *display = to_intel_display(encoder);
+ u32 clock, val;
+
+ val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
- drm_WARN_ON(&i915->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
- drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));
- drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_ACK));
+ drm_WARN_ON(display->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
+ drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));
+ drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_ACK));
switch (clock) {
case XELPDP_DDI_CLOCK_SELECT_TBT_162:
@@ -3057,7 +3077,7 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
}
}
-static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
+static int intel_mtl_tbt_clock_select(int clock)
{
switch (clock) {
case 162000:
@@ -3077,7 +3097,7 @@ static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
u32 val = 0;
@@ -3085,13 +3105,13 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
* 1. Program PORT_CLOCK_CTL REGISTER to configure
* clock muxes, gating and SSC
*/
- val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock));
+ val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(crtc_state->port_clock));
val |= XELPDP_FORWARD_CLOCK_UNGATE;
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);
/* 2. Read back PORT_CLOCK_CTL REGISTER */
- val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
+ val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
/*
* 3. Follow the Display Voltage Frequency Switching - Sequence
@@ -3102,14 +3122,15 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
* 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL.
*/
val |= XELPDP_TBT_CLOCK_REQUEST;
- intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), val);
+ intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val);
/* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
- if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_TBT_CLOCK_ACK,
XELPDP_TBT_CLOCK_ACK,
100, 0, NULL))
- drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n",
+ drm_warn(display->drm,
+ "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n",
encoder->base.base.id, encoder->base.name, phy_name(phy));
/*
@@ -3121,7 +3142,7 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
* 7. Program DDI_CLK_VALFREQ to match intended DDI
* clock frequency.
*/
- intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
+ intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
crtc_state->port_clock);
}
@@ -3138,13 +3159,14 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
if (intel_encoder_is_c10phy(encoder))
return CX0_P2PG_STATE_DISABLE;
if ((IS_BATTLEMAGE(i915) && encoder->port == PORT_A) ||
- (DISPLAY_VER(i915) >= 30 && encoder->type == INTEL_OUTPUT_EDP))
+ (DISPLAY_VER(display) >= 30 && encoder->type == INTEL_OUTPUT_EDP))
return CX0_P2PG_STATE_DISABLE;
return CX0_P4PG_STATE_DISABLE;
@@ -3152,7 +3174,7 @@ static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
static void intel_cx0pll_disable(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
@@ -3169,21 +3191,22 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
* 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
* to "0" to disable PLL.
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
/* 4. Program DDI_CLK_VALFREQ to 0. */
- intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
+ intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
/*
* 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
*/
- if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "Port %c PLL not unlocked after %dus.\n",
+ drm_warn(display->drm,
+ "Port %c PLL not unlocked after %dus.\n",
phy_name(phy), XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US);
/*
@@ -3192,9 +3215,9 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
*/
/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_DDI_CLOCK_SELECT_MASK, 0);
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_FORWARD_CLOCK_UNGATE, 0);
intel_cx0_phy_transaction_end(encoder, wakeref);
@@ -3202,7 +3225,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
/*
@@ -3213,13 +3236,14 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
/*
* 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL.
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_TBT_CLOCK_REQUEST, 0);
/* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
- if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
- drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
+ drm_warn(display->drm,
+ "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
encoder->base.base.id, encoder->base.name, phy_name(phy));
/*
@@ -3230,12 +3254,12 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
/*
* 5. Program PORT CLOCK CTRL register to disable and gate clocks
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_DDI_CLOCK_SELECT_MASK |
XELPDP_FORWARD_CLOCK_UNGATE, 0);
/* 6. Program DDI_CLK_VALFREQ to 0. */
- intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
+ intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
}
void intel_mtl_pll_disable(struct intel_encoder *encoder)
@@ -3252,13 +3276,15 @@ enum icl_port_dpll_id
intel_mtl_port_pll_type(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
+ u32 val, clock;
+
/*
* TODO: Determine the PLL type from the SW state, once MTL PLL
* handling is done via the standard shared DPLL framework.
*/
- u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
- u32 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
+ val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
+ clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
if (clock == XELPDP_DDI_CLOCK_SELECT_MAXPCLK ||
clock == XELPDP_DDI_CLOCK_SELECT_DIV18CLK)
@@ -3430,13 +3456,13 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
void intel_cx0pll_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_encoder *encoder;
struct intel_cx0pll_state mpll_hw_state = {};
- if (DISPLAY_VER(i915) < 14)
+ if (DISPLAY_VER(display) < 14)
return;
if (!new_crtc_state->hw.active)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 3555a9bc1de9..711168882684 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -9,13 +9,13 @@
#include <linux/types.h>
enum icl_port_dpll_id;
-struct drm_i915_private;
struct intel_atomic_state;
struct intel_c10pll_state;
struct intel_c20pll_state;
-struct intel_cx0pll_state;
struct intel_crtc;
struct intel_crtc_state;
+struct intel_cx0pll_state;
+struct intel_display;
struct intel_encoder;
struct intel_hdmi;
@@ -33,7 +33,7 @@ void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
const struct intel_cx0pll_state *pll_state);
-void intel_cx0pll_dump_hw_state(struct drm_i915_private *dev_priv,
+void intel_cx0pll_dump_hw_state(struct intel_display *display,
const struct intel_cx0pll_state *hw_state);
void intel_cx0pll_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ef1436146325..c19f01b63936 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5305,15 +5305,15 @@ pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
const struct intel_cx0pll_state *a,
const struct intel_cx0pll_state *b)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
char *chipname = a->use_c10 ? "C10" : "C20";
pipe_config_mismatch(p, fastset, crtc, name, chipname);
drm_printf(p, "expected:\n");
- intel_cx0pll_dump_hw_state(i915, a);
+ intel_cx0pll_dump_hw_state(display, a);
drm_printf(p, "found:\n");
- intel_cx0pll_dump_hw_state(i915, b);
+ intel_cx0pll_dump_hw_state(display, b);
}
bool
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH] drm/i915/cx0: convert to struct intel_display
2024-10-28 20:07 ` [CI v2 v2 03/12] drm/i915/cx0: convert to struct intel_display Jani Nikula
@ 2024-10-29 16:08 ` Jani Nikula
0 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2024-10-29 16:08 UTC (permalink / raw)
To: Jani Nikula, intel-gfx, intel-xe; +Cc: Rodrigo Vivi
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch Cx0 PHY code over to it.
v2: Rebase, split out the include cleanups (Rodrigo)
v3: Rebase
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 337 ++++++++++---------
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
3 files changed, 187 insertions(+), 162 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 8ad19106fee1..1d50d3963066 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -68,22 +68,23 @@ static u8 intel_cx0_get_owned_lane_mask(struct intel_encoder *encoder)
}
static void
-assert_dc_off(struct drm_i915_private *i915)
+assert_dc_off(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
bool enabled;
enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF);
- drm_WARN_ON(&i915->drm, !enabled);
+ drm_WARN_ON(display->drm, !enabled);
}
static void intel_cx0_program_msgbus_timer(struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(encoder);
int lane;
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
for_each_cx0_lane_in_mask(INTEL_CX0_BOTH_LANES, lane)
- intel_de_rmw(i915,
- XELPDP_PORT_MSGBUS_TIMER(i915, encoder->port, lane),
+ intel_de_rmw(display,
+ XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane),
XELPDP_PORT_MSGBUS_TIMER_VAL_MASK,
XELPDP_PORT_MSGBUS_TIMER_VAL);
}
@@ -122,25 +123,28 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_w
static void intel_clear_response_ready_flag(struct intel_encoder *encoder,
int lane)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, encoder->port, lane),
+ intel_de_rmw(display,
+ XELPDP_PORT_P2M_MSGBUS_STATUS(display, encoder->port, lane),
0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET);
}
static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET);
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
- drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
+ drm_err_once(display->drm,
+ "Failed to bring PHY %c to idle.\n",
+ phy_name(phy));
return;
}
@@ -150,22 +154,23 @@ static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
int command, int lane, u32 *val)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
- if (intel_de_wait_custom(i915,
- XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
+ if (intel_de_wait_custom(display,
+ XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_MSGBUS_TIMEOUT_FAST_US,
XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
- drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
+ drm_dbg_kms(display->drm,
+ "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
phy_name(phy), *val);
- if (!(intel_de_read(i915, XELPDP_PORT_MSGBUS_TIMER(i915, port, lane)) &
+ if (!(intel_de_read(display, XELPDP_PORT_MSGBUS_TIMER(display, port, lane)) &
XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT))
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Hardware did not detect a timeout\n",
phy_name(phy));
@@ -174,14 +179,18 @@ static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
}
if (*val & XELPDP_PORT_P2M_ERROR_SET) {
- drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s command. Status: 0x%x\n", phy_name(phy),
+ drm_dbg_kms(display->drm,
+ "PHY %c Error occurred during %s command. Status: 0x%x\n",
+ phy_name(phy),
command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val);
intel_cx0_bus_reset(encoder, lane);
return -EINVAL;
}
if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) != command) {
- drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", phy_name(phy),
+ drm_dbg_kms(display->drm,
+ "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n",
+ phy_name(phy),
command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val);
intel_cx0_bus_reset(encoder, lane);
return -EINVAL;
@@ -193,22 +202,22 @@ static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
static int __intel_cx0_read_once(struct intel_encoder *encoder,
int lane, u16 addr)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
int ack;
u32 val;
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
return -ETIMEDOUT;
}
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
XELPDP_PORT_M2P_COMMAND_READ |
XELPDP_PORT_M2P_ADDRESS(addr));
@@ -224,7 +233,7 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
* down and let the message bus to end up
* in a known state
*/
- if (DISPLAY_VER(i915) < 30)
+ if (DISPLAY_VER(display) < 30)
intel_cx0_bus_reset(encoder, lane);
return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);
@@ -233,11 +242,11 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
static u8 __intel_cx0_read(struct intel_encoder *encoder,
int lane, u16 addr)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
int i, status;
- assert_dc_off(i915);
+ assert_dc_off(display);
/* 3 tries is assumed to be enough to read successfully */
for (i = 0; i < 3; i++) {
@@ -247,7 +256,8 @@ static u8 __intel_cx0_read(struct intel_encoder *encoder,
return status;
}
- drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n",
+ drm_err_once(display->drm,
+ "PHY %c Read %04x failed after %d retries.\n",
phy_name(phy), addr, i);
return 0;
@@ -264,32 +274,32 @@ static u8 intel_cx0_read(struct intel_encoder *encoder,
static int __intel_cx0_write_once(struct intel_encoder *encoder,
int lane, u16 addr, u8 data, bool committed)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
int ack;
u32 val;
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for previous transaction to complete. Resetting the bus.\n", phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
return -ETIMEDOUT;
}
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
(committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
XELPDP_PORT_M2P_DATA(data) |
XELPDP_PORT_M2P_ADDRESS(addr));
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for write to complete. Resetting the bus.\n", phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
return -ETIMEDOUT;
@@ -299,9 +309,9 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
if (ack < 0)
return ack;
- } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane)) &
+ } else if ((intel_de_read(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane)) &
XELPDP_PORT_P2M_ERROR_SET)) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Error occurred during write command.\n", phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
return -EINVAL;
@@ -314,7 +324,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
* down and let the message bus to end up
* in a known state
*/
- if (DISPLAY_VER(i915) < 30)
+ if (DISPLAY_VER(display) < 30)
intel_cx0_bus_reset(encoder, lane);
return 0;
@@ -323,11 +333,11 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
static void __intel_cx0_write(struct intel_encoder *encoder,
int lane, u16 addr, u8 data, bool committed)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
int i, status;
- assert_dc_off(i915);
+ assert_dc_off(display);
/* 3 tries is assumed to be enough to write successfully */
for (i = 0; i < 3; i++) {
@@ -337,7 +347,7 @@ static void __intel_cx0_write(struct intel_encoder *encoder,
return;
}
- drm_err_once(&i915->drm,
+ drm_err_once(display->drm,
"PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
}
@@ -353,9 +363,9 @@ static void intel_cx0_write(struct intel_encoder *encoder,
static void intel_c20_sram_write(struct intel_encoder *encoder,
int lane, u16 addr, u16 data)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- assert_dc_off(i915);
+ assert_dc_off(display);
intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0);
intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0);
@@ -367,10 +377,10 @@ static void intel_c20_sram_write(struct intel_encoder *encoder,
static u16 intel_c20_sram_read(struct intel_encoder *encoder,
int lane, u16 addr)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
u16 val;
- assert_dc_off(i915);
+ assert_dc_off(display);
intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0);
intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1);
@@ -434,7 +444,7 @@ static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state)
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
const struct intel_ddi_buf_trans *trans;
u8 owned_lane_mask;
intel_wakeref_t wakeref;
@@ -449,7 +459,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
wakeref = intel_cx0_phy_transaction_begin(encoder);
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
- if (drm_WARN_ON_ONCE(&i915->drm, !trans)) {
+ if (drm_WARN_ON_ONCE(display->drm, !trans)) {
intel_cx0_phy_transaction_end(encoder, wakeref);
return;
}
@@ -2025,7 +2035,6 @@ static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll;
int i;
@@ -2041,7 +2050,7 @@ static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state,
if (pll_state->ssc_enabled)
return;
- drm_WARN_ON(&i915->drm, ARRAY_SIZE(pll_state->c10.pll) < 9);
+ drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 9);
for (i = 4; i < 9; i++)
pll_state->c10.pll[i] = 0;
}
@@ -2095,7 +2104,7 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
intel_cx0_phy_transaction_end(encoder, wakeref);
}
-static void intel_c10_pll_program(struct drm_i915_private *i915,
+static void intel_c10_pll_program(struct intel_display *display,
const struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
@@ -2128,7 +2137,7 @@ static void intel_c10_pll_program(struct drm_i915_private *i915,
MB_WRITE_COMMITTED);
}
-static void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
+static void intel_c10pll_dump_hw_state(struct intel_display *display,
const struct intel_c10pll_state *hw_state)
{
bool fracen;
@@ -2137,29 +2146,31 @@ static void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
unsigned int multiplier, tx_clk_div;
fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
- drm_dbg_kms(&i915->drm, "c10pll_hw_state: fracen: %s, ",
+ drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ",
str_yes_no(fracen));
if (fracen) {
frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13];
frac_den = hw_state->pll[10] << 8 | hw_state->pll[9];
- drm_dbg_kms(&i915->drm, "quot: %u, rem: %u, den: %u,\n",
+ drm_dbg_kms(display->drm, "quot: %u, rem: %u, den: %u,\n",
frac_quot, frac_rem, frac_den);
}
multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 |
hw_state->pll[2]) / 2 + 16;
tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]);
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
- drm_dbg_kms(&i915->drm, "c10pll_rawhw_state:");
- drm_dbg_kms(&i915->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn);
+ drm_dbg_kms(display->drm, "c10pll_rawhw_state:");
+ drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx,
+ hw_state->cmn);
BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4);
for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4)
- drm_dbg_kms(&i915->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
+ drm_dbg_kms(display->drm,
+ "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
}
@@ -2269,20 +2280,19 @@ static const struct intel_c20pll_state * const *
intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_display *display = to_intel_display(crtc_state);
if (intel_crtc_has_dp_encoder(crtc_state)) {
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
if (DISPLAY_RUNTIME_INFO(display)->edp_typec_support)
return xe3lpd_c20_dp_edp_tables;
- if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
+ if (DISPLAY_VER_FULL(display) == IP_VER(14, 1))
return xe2hpd_c20_edp_tables;
}
- if (DISPLAY_VER(i915) >= 30)
+ if (DISPLAY_VER(display) >= 30)
return xe3lpd_c20_dp_edp_tables;
- else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
+ else if (DISPLAY_VER_FULL(display) == IP_VER(14, 1))
return xe2hpd_c20_dp_tables;
else
return mtl_c20_dp_tables;
@@ -2383,10 +2393,10 @@ static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_c20pll_state *pll_state)
{
+ struct intel_display *display = to_intel_display(encoder);
bool cntx;
intel_wakeref_t wakeref;
int i;
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
wakeref = intel_cx0_phy_transaction_begin(encoder);
@@ -2398,11 +2408,11 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
if (cntx)
pll_state->tx[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
- PHY_C20_B_TX_CNTX_CFG(i915, i));
+ PHY_C20_B_TX_CNTX_CFG(display, i));
else
pll_state->tx[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
- PHY_C20_A_TX_CNTX_CFG(i915, i));
+ PHY_C20_A_TX_CNTX_CFG(display, i));
}
/* Read common configuration */
@@ -2410,11 +2420,11 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
if (cntx)
pll_state->cmn[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
- PHY_C20_B_CMN_CNTX_CFG(i915, i));
+ PHY_C20_B_CMN_CNTX_CFG(display, i));
else
pll_state->cmn[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
- PHY_C20_A_CMN_CNTX_CFG(i915, i));
+ PHY_C20_A_CMN_CNTX_CFG(display, i));
}
if (intel_c20phy_use_mpllb(pll_state)) {
@@ -2423,11 +2433,11 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
if (cntx)
pll_state->mpllb[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
- PHY_C20_B_MPLLB_CNTX_CFG(i915, i));
+ PHY_C20_B_MPLLB_CNTX_CFG(display, i));
else
pll_state->mpllb[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
- PHY_C20_A_MPLLB_CNTX_CFG(i915, i));
+ PHY_C20_A_MPLLB_CNTX_CFG(display, i));
}
} else {
/* MPLLA configuration */
@@ -2435,11 +2445,11 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
if (cntx)
pll_state->mplla[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
- PHY_C20_B_MPLLA_CNTX_CFG(i915, i));
+ PHY_C20_B_MPLLA_CNTX_CFG(display, i));
else
pll_state->mplla[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
- PHY_C20_A_MPLLA_CNTX_CFG(i915, i));
+ PHY_C20_A_MPLLA_CNTX_CFG(display, i));
}
}
@@ -2448,33 +2458,37 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
intel_cx0_phy_transaction_end(encoder, wakeref);
}
-static void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
+static void intel_c20pll_dump_hw_state(struct intel_display *display,
const struct intel_c20pll_state *hw_state)
{
int i;
- drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n");
- drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
+ drm_dbg_kms(display->drm, "c20pll_hw_state:\n");
+ drm_dbg_kms(display->drm,
+ "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
- drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
+ drm_dbg_kms(display->drm,
+ "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);
if (intel_c20phy_use_mpllb(hw_state)) {
for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++)
- drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
+ drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i,
+ hw_state->mpllb[i]);
} else {
for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
- drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]);
+ drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,
+ hw_state->mplla[i]);
}
}
-void intel_cx0pll_dump_hw_state(struct drm_i915_private *i915,
+void intel_cx0pll_dump_hw_state(struct intel_display *display,
const struct intel_cx0pll_state *hw_state)
{
if (hw_state->use_c10)
- intel_c10pll_dump_hw_state(i915, &hw_state->c10);
+ intel_c10pll_dump_hw_state(display, &hw_state->c10);
else
- intel_c20pll_dump_hw_state(i915, &hw_state->c20);
+ intel_c20pll_dump_hw_state(display, &hw_state->c20);
}
static u8 intel_c20_get_dp_rate(u32 clock)
@@ -2574,7 +2588,7 @@ static int intel_get_c20_custom_width(u32 clock, bool dp)
return 0;
}
-static void intel_c20_pll_program(struct drm_i915_private *i915,
+static void intel_c20_pll_program(struct intel_display *display,
const struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
@@ -2607,11 +2621,11 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_TX_CNTX_CFG(i915, i),
+ PHY_C20_A_TX_CNTX_CFG(display, i),
pll_state->tx[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_TX_CNTX_CFG(i915, i),
+ PHY_C20_B_TX_CNTX_CFG(display, i),
pll_state->tx[i]);
}
@@ -2619,11 +2633,11 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_CMN_CNTX_CFG(i915, i),
+ PHY_C20_A_CMN_CNTX_CFG(display, i),
pll_state->cmn[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_CMN_CNTX_CFG(i915, i),
+ PHY_C20_B_CMN_CNTX_CFG(display, i),
pll_state->cmn[i]);
}
@@ -2632,22 +2646,22 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLB_CNTX_CFG(i915, i),
+ PHY_C20_A_MPLLB_CNTX_CFG(display, i),
pll_state->mpllb[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLB_CNTX_CFG(i915, i),
+ PHY_C20_B_MPLLB_CNTX_CFG(display, i),
pll_state->mpllb[i]);
}
} else {
for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLA_CNTX_CFG(i915, i),
+ PHY_C20_A_MPLLA_CNTX_CFG(display, i),
pll_state->mplla[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLA_CNTX_CFG(i915, i),
+ PHY_C20_B_MPLLA_CNTX_CFG(display, i),
pll_state->mplla[i]);
}
}
@@ -2714,10 +2728,10 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
bool lane_reversal)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
u32 val = 0;
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
XELPDP_PORT_REVERSAL,
lane_reversal ? XELPDP_PORT_REVERSAL : 0);
@@ -2739,7 +2753,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
else
val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA |
XELPDP_SSC_ENABLE_PLLB, val);
@@ -2770,48 +2784,49 @@ static u32 intel_cx0_get_powerdown_state(u8 lane_mask, u8 state)
static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
u8 lane_mask, u8 state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
- i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(i915, port);
+ i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port);
int lane;
- intel_de_rmw(i915, buf_ctl2_reg,
+ intel_de_rmw(display, buf_ctl2_reg,
intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK),
intel_cx0_get_powerdown_state(lane_mask, state));
/* Wait for pending transactions.*/
for_each_cx0_lane_in_mask(lane_mask, lane)
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for previous transaction to complete. Reset the bus.\n",
phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
}
- intel_de_rmw(i915, buf_ctl2_reg,
+ intel_de_rmw(display, buf_ctl2_reg,
intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES),
intel_cx0_get_powerdown_update(lane_mask));
/* Update Timeout Value */
- if (intel_de_wait_custom(i915, buf_ctl2_reg,
+ if (intel_de_wait_custom(display, buf_ctl2_reg,
intel_cx0_get_powerdown_update(lane_mask), 0,
XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
+ drm_warn(display->drm,
+ "PHY %c failed to bring out of Lane reset after %dus.\n",
phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
}
static void intel_cx0_setup_powerdown(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port),
+ intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
XELPDP_POWER_STATE_READY_MASK,
XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(i915, port),
+ intel_de_rmw(display, XELPDP_PORT_BUF_CTL3(display, port),
XELPDP_POWER_STATE_ACTIVE_MASK |
XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
@@ -2843,7 +2858,7 @@ static u32 intel_cx0_get_pclk_refclk_ack(u8 lane_mask)
static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
bool lane_reversal)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
@@ -2856,48 +2871,51 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
XELPDP_LANE_PHY_CURRENT_STATUS(1))
: XELPDP_LANE_PHY_CURRENT_STATUS(0);
- if (intel_de_wait_custom(i915, XELPDP_PORT_BUF_CTL1(i915, port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL1(display, port),
XELPDP_PORT_BUF_SOC_PHY_READY,
XELPDP_PORT_BUF_SOC_PHY_READY,
XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
+ drm_warn(display->drm,
+ "PHY %c failed to bring out of SOC reset after %dus.\n",
phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset,
+ intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset,
lane_pipe_reset);
- if (intel_de_wait_custom(i915, XELPDP_PORT_BUF_CTL2(i915, port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_phy_current_status, lane_phy_current_status,
XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
+ drm_warn(display->drm,
+ "PHY %c failed to bring out of Lane reset after %dus.\n",
phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
intel_cx0_get_pclk_refclk_request(owned_lane_mask),
intel_cx0_get_pclk_refclk_request(lane_mask));
- if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
intel_cx0_get_pclk_refclk_ack(lane_mask),
XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n",
+ drm_warn(display->drm,
+ "PHY %c failed to request refclk after %dus.\n",
phy_name(phy), XELPDP_REFCLK_ENABLE_TIMEOUT_US);
intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
CX0_P2_STATE_RESET);
intel_cx0_setup_powerdown(encoder);
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset, 0);
+ intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 0);
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(i915, port),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_phy_current_status,
XELPDP_PORT_RESET_END_TIMEOUT))
- drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
+ drm_warn(display->drm,
+ "PHY %c failed to bring out of Lane reset after %dms.\n",
phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
}
-static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
- struct intel_encoder *encoder, int lane_count,
+static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_count,
bool lane_reversal)
{
int i;
@@ -2966,7 +2984,7 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
static void intel_cx0pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
@@ -2998,15 +3016,15 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
/* 5. Program PHY internal PLL internal registers. */
if (intel_encoder_is_c10phy(encoder))
- intel_c10_pll_program(i915, crtc_state, encoder);
+ intel_c10_pll_program(display, crtc_state, encoder);
else
- intel_c20_pll_program(i915, crtc_state, encoder);
+ intel_c20_pll_program(display, crtc_state, encoder);
/*
* 6. Program the enabled and disabled owned PHY lane
* transmitters over message bus
*/
- intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal);
+ intel_cx0_program_phy_lane(encoder, crtc_state->lane_count, lane_reversal);
/*
* 7. Follow the Display Voltage Frequency Switching - Sequence
@@ -3017,23 +3035,23 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
* 8. Program DDI_CLK_VALFREQ to match intended DDI
* clock frequency.
*/
- intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
+ intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
crtc_state->port_clock);
/*
* 9. Set PORT_CLOCK_CTL register PCLK PLL Request
* LN<Lane for maxPCLK> to "1" to enable PLL.
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
intel_cx0_get_pclk_pll_request(maxpclk_lane));
/* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
- if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
intel_cx0_get_pclk_pll_ack(maxpclk_lane),
XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "Port %c PLL not locked after %dus.\n",
+ drm_warn(display->drm, "Port %c PLL not locked after %dus.\n",
phy_name(phy), XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US);
/*
@@ -3047,15 +3065,16 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- u32 clock;
- u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
+ struct intel_display *display = to_intel_display(encoder);
+ u32 clock, val;
+
+ val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
- drm_WARN_ON(&i915->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
- drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));
- drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_ACK));
+ drm_WARN_ON(display->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
+ drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));
+ drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_ACK));
switch (clock) {
case XELPDP_DDI_CLOCK_SELECT_TBT_162:
@@ -3072,7 +3091,7 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
}
}
-static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
+static int intel_mtl_tbt_clock_select(int clock)
{
switch (clock) {
case 162000:
@@ -3092,7 +3111,7 @@ static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
u32 val = 0;
@@ -3100,13 +3119,13 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
* 1. Program PORT_CLOCK_CTL REGISTER to configure
* clock muxes, gating and SSC
*/
- val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock));
+ val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(crtc_state->port_clock));
val |= XELPDP_FORWARD_CLOCK_UNGATE;
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);
/* 2. Read back PORT_CLOCK_CTL REGISTER */
- val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
+ val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
/*
* 3. Follow the Display Voltage Frequency Switching - Sequence
@@ -3117,14 +3136,15 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
* 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL.
*/
val |= XELPDP_TBT_CLOCK_REQUEST;
- intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), val);
+ intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val);
/* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
- if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_TBT_CLOCK_ACK,
XELPDP_TBT_CLOCK_ACK,
100, 0, NULL))
- drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n",
+ drm_warn(display->drm,
+ "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n",
encoder->base.base.id, encoder->base.name, phy_name(phy));
/*
@@ -3136,7 +3156,7 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
* 7. Program DDI_CLK_VALFREQ to match intended DDI
* clock frequency.
*/
- intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
+ intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
crtc_state->port_clock);
}
@@ -3153,13 +3173,14 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
if (intel_encoder_is_c10phy(encoder))
return CX0_P2PG_STATE_DISABLE;
if ((IS_BATTLEMAGE(i915) && encoder->port == PORT_A) ||
- (DISPLAY_VER(i915) >= 30 && encoder->type == INTEL_OUTPUT_EDP))
+ (DISPLAY_VER(display) >= 30 && encoder->type == INTEL_OUTPUT_EDP))
return CX0_P2PG_STATE_DISABLE;
return CX0_P4PG_STATE_DISABLE;
@@ -3167,7 +3188,7 @@ static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
static void intel_cx0pll_disable(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
@@ -3184,21 +3205,22 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
* 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
* to "0" to disable PLL.
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
/* 4. Program DDI_CLK_VALFREQ to 0. */
- intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
+ intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
/*
* 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
*/
- if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "Port %c PLL not unlocked after %dus.\n",
+ drm_warn(display->drm,
+ "Port %c PLL not unlocked after %dus.\n",
phy_name(phy), XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US);
/*
@@ -3207,9 +3229,9 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
*/
/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_DDI_CLOCK_SELECT_MASK, 0);
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_FORWARD_CLOCK_UNGATE, 0);
intel_cx0_phy_transaction_end(encoder, wakeref);
@@ -3217,7 +3239,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
/*
@@ -3228,13 +3250,14 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
/*
* 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL.
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_TBT_CLOCK_REQUEST, 0);
/* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
- if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
- drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
+ drm_warn(display->drm,
+ "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
encoder->base.base.id, encoder->base.name, phy_name(phy));
/*
@@ -3245,12 +3268,12 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
/*
* 5. Program PORT CLOCK CTRL register to disable and gate clocks
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_DDI_CLOCK_SELECT_MASK |
XELPDP_FORWARD_CLOCK_UNGATE, 0);
/* 6. Program DDI_CLK_VALFREQ to 0. */
- intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
+ intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
}
void intel_mtl_pll_disable(struct intel_encoder *encoder)
@@ -3267,13 +3290,15 @@ enum icl_port_dpll_id
intel_mtl_port_pll_type(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
+ u32 val, clock;
+
/*
* TODO: Determine the PLL type from the SW state, once MTL PLL
* handling is done via the standard shared DPLL framework.
*/
- u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
- u32 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
+ val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
+ clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
if (clock == XELPDP_DDI_CLOCK_SELECT_MAXPCLK ||
clock == XELPDP_DDI_CLOCK_SELECT_DIV18CLK)
@@ -3445,13 +3470,13 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
void intel_cx0pll_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_encoder *encoder;
struct intel_cx0pll_state mpll_hw_state = {};
- if (DISPLAY_VER(i915) < 14)
+ if (DISPLAY_VER(display) < 14)
return;
if (!new_crtc_state->hw.active)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 3555a9bc1de9..711168882684 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -9,13 +9,13 @@
#include <linux/types.h>
enum icl_port_dpll_id;
-struct drm_i915_private;
struct intel_atomic_state;
struct intel_c10pll_state;
struct intel_c20pll_state;
-struct intel_cx0pll_state;
struct intel_crtc;
struct intel_crtc_state;
+struct intel_cx0pll_state;
+struct intel_display;
struct intel_encoder;
struct intel_hdmi;
@@ -33,7 +33,7 @@ void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
const struct intel_cx0pll_state *pll_state);
-void intel_cx0pll_dump_hw_state(struct drm_i915_private *dev_priv,
+void intel_cx0pll_dump_hw_state(struct intel_display *display,
const struct intel_cx0pll_state *hw_state);
void intel_cx0pll_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0e6d6c8354ef..5d98cdecaa5a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5306,15 +5306,15 @@ pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
const struct intel_cx0pll_state *a,
const struct intel_cx0pll_state *b)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
char *chipname = a->use_c10 ? "C10" : "C20";
pipe_config_mismatch(p, fastset, crtc, name, chipname);
drm_printf(p, "expected:\n");
- intel_cx0pll_dump_hw_state(i915, a);
+ intel_cx0pll_dump_hw_state(display, a);
drm_printf(p, "found:\n");
- intel_cx0pll_dump_hw_state(i915, b);
+ intel_cx0pll_dump_hw_state(display, b);
}
bool
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [CI v2 v2 04/12] drm/i915/dpio: convert to struct intel_display
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (2 preceding siblings ...)
2024-10-28 20:07 ` [CI v2 v2 03/12] drm/i915/cx0: convert to struct intel_display Jani Nikula
@ 2024-10-28 20:07 ` Jani Nikula
2024-10-28 20:07 ` [CI v2 v2 05/12] drm/i915/hdcp: further conversion " Jani Nikula
` (13 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2024-10-28 20:07 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, Rodrigo Vivi
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch DPIO PHY code over to it.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../i915/display/intel_display_power_well.c | 19 ++-
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 158 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpio_phy.h | 22 +--
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 +-
4 files changed, 106 insertions(+), 99 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index adaf7cf3a33b..885bc2e563c5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -919,38 +919,45 @@ static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- bxt_dpio_phy_init(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
+ struct intel_display *display = &dev_priv->display;
+
+ bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy);
}
static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- bxt_dpio_phy_uninit(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
+ struct intel_display *display = &dev_priv->display;
+
+ bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy);
}
static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- return bxt_dpio_phy_is_enabled(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
+ struct intel_display *display = &dev_priv->display;
+
+ return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy);
}
static void bxt_verify_dpio_phy_power_wells(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct i915_power_well *power_well;
power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
if (intel_power_well_refcount(power_well) > 0)
- bxt_dpio_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
+ bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);
power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
if (intel_power_well_refcount(power_well) > 0)
- bxt_dpio_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
+ bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);
if (IS_GEMINILAKE(dev_priv)) {
power_well = lookup_power_well(dev_priv,
GLK_DISP_PW_DPIO_CMN_C);
if (intel_power_well_refcount(power_well) > 0)
- bxt_dpio_phy_verify_state(dev_priv,
+ bxt_dpio_phy_verify_state(display,
i915_power_well_instance(power_well)->bxt.phy);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index d20e4e9cf7f7..0f12f2c3467c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -219,8 +219,10 @@ static const struct bxt_dpio_phy_info glk_dpio_phy_info[] = {
};
static const struct bxt_dpio_phy_info *
-bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
+bxt_get_phy_list(struct intel_display *display, int *count)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
if (IS_GEMINILAKE(dev_priv)) {
*count = ARRAY_SIZE(glk_dpio_phy_info);
return glk_dpio_phy_info;
@@ -231,22 +233,22 @@ bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
}
static const struct bxt_dpio_phy_info *
-bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+bxt_get_phy_info(struct intel_display *display, enum dpio_phy phy)
{
int count;
const struct bxt_dpio_phy_info *phy_list =
- bxt_get_phy_list(dev_priv, &count);
+ bxt_get_phy_list(display, &count);
return &phy_list[phy];
}
-void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
+void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch)
{
const struct bxt_dpio_phy_info *phy_info, *phys;
int i, count;
- phys = bxt_get_phy_list(dev_priv, &count);
+ phys = bxt_get_phy_list(display, &count);
for (i = 0; i < count; i++) {
phy_info = &phys[i];
@@ -265,7 +267,7 @@ void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
}
}
- drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c",
+ drm_WARN(display->drm, 1, "PHY not found for PORT %c",
port_name(port));
*phy = DPIO_PHY0;
*ch = DPIO_CH0;
@@ -275,16 +277,16 @@ void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
* Like intel_de_rmw() but reads from a single per-lane register and
* writes to the group register to write the same value to all the lanes.
*/
-static u32 bxt_dpio_phy_rmw_grp(struct drm_i915_private *i915,
+static u32 bxt_dpio_phy_rmw_grp(struct intel_display *display,
i915_reg_t reg_single,
i915_reg_t reg_group,
u32 clear, u32 set)
{
u32 old, val;
- old = intel_de_read(i915, reg_single);
+ old = intel_de_read(display, reg_single);
val = (old & ~clear) | set;
- intel_de_write(i915, reg_group, val);
+ intel_de_write(display, reg_group, val);
return old;
}
@@ -292,30 +294,30 @@ static u32 bxt_dpio_phy_rmw_grp(struct drm_i915_private *i915,
void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
const struct intel_ddi_buf_trans *trans;
enum dpio_channel ch;
enum dpio_phy phy;
int lane, n_entries;
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
- if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
+ if (drm_WARN_ON_ONCE(display->drm, !trans))
return;
- bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch);
+ bxt_port_to_phy_channel(display, encoder->port, &phy, &ch);
/*
* While we write to the group register to program all lanes at once we
* can read only lane registers and we pick lanes 0/1 for that.
*/
- bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),
+ bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch),
BXT_PORT_PCS_DW10_GRP(phy, ch),
TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT, 0);
for (lane = 0; lane < crtc_state->lane_count; lane++) {
int level = intel_ddi_level(encoder, crtc_state, lane);
- intel_de_rmw(dev_priv, BXT_PORT_TX_DW2_LN(phy, ch, lane),
+ intel_de_rmw(display, BXT_PORT_TX_DW2_LN(phy, ch, lane),
MARGIN_000_MASK | UNIQ_TRANS_SCALE_MASK,
MARGIN_000(trans->entries[level].bxt.margin) |
UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale));
@@ -325,50 +327,50 @@ void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
int level = intel_ddi_level(encoder, crtc_state, lane);
u32 val;
- intel_de_rmw(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane),
+ intel_de_rmw(display, BXT_PORT_TX_DW3_LN(phy, ch, lane),
SCALE_DCOMP_METHOD,
trans->entries[level].bxt.enable ?
SCALE_DCOMP_METHOD : 0);
- val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane));
+ val = intel_de_read(display, BXT_PORT_TX_DW3_LN(phy, ch, lane));
if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"Disabled scaling while ouniqetrangenmethod was set");
}
for (lane = 0; lane < crtc_state->lane_count; lane++) {
int level = intel_ddi_level(encoder, crtc_state, lane);
- intel_de_rmw(dev_priv, BXT_PORT_TX_DW4_LN(phy, ch, lane),
+ intel_de_rmw(display, BXT_PORT_TX_DW4_LN(phy, ch, lane),
DE_EMPHASIS_MASK,
DE_EMPHASIS(trans->entries[level].bxt.deemphasis));
}
- bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),
+ bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch),
BXT_PORT_PCS_DW10_GRP(phy, ch),
0, TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
}
-bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
+bool bxt_dpio_phy_is_enabled(struct intel_display *display,
enum dpio_phy phy)
{
const struct bxt_dpio_phy_info *phy_info;
- phy_info = bxt_get_phy_info(dev_priv, phy);
+ phy_info = bxt_get_phy_info(display, phy);
- if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
+ if (!(intel_de_read(display, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
return false;
- if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) &
+ if ((intel_de_read(display, BXT_PORT_CL1CM_DW0(phy)) &
(PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
- drm_dbg(&dev_priv->drm,
+ drm_dbg(display->drm,
"DDI PHY %d powered, but power hasn't settled\n", phy);
return false;
}
- if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
- drm_dbg(&dev_priv->drm,
+ if (!(intel_de_read(display, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
+ drm_dbg(display->drm,
"DDI PHY %d powered, but still in reset\n", phy);
return false;
@@ -377,47 +379,44 @@ bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
return true;
}
-static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+static u32 bxt_get_grc(struct intel_display *display, enum dpio_phy phy)
{
- u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy));
+ u32 val = intel_de_read(display, BXT_PORT_REF_DW6(phy));
return REG_FIELD_GET(GRC_CODE_MASK, val);
}
-static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
+static void bxt_phy_wait_grc_done(struct intel_display *display,
enum dpio_phy phy)
{
- if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy),
- GRC_DONE, 10))
- drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n",
- phy);
+ if (intel_de_wait_for_set(display, BXT_PORT_REF_DW3(phy), GRC_DONE, 10))
+ drm_err(display->drm, "timeout waiting for PHY%d GRC\n", phy);
}
-static void _bxt_dpio_phy_init(struct drm_i915_private *dev_priv,
- enum dpio_phy phy)
+static void _bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
{
const struct bxt_dpio_phy_info *phy_info;
u32 val;
- phy_info = bxt_get_phy_info(dev_priv, phy);
+ phy_info = bxt_get_phy_info(display, phy);
- if (bxt_dpio_phy_is_enabled(dev_priv, phy)) {
+ if (bxt_dpio_phy_is_enabled(display, phy)) {
/* Still read out the GRC value for state verification */
if (phy_info->rcomp_phy != -1)
- dev_priv->display.state.bxt_phy_grc = bxt_get_grc(dev_priv, phy);
+ display->state.bxt_phy_grc = bxt_get_grc(display, phy);
- if (bxt_dpio_phy_verify_state(dev_priv, phy)) {
- drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, "
+ if (bxt_dpio_phy_verify_state(display, phy)) {
+ drm_dbg(display->drm, "DDI PHY %d already enabled, "
"won't reprogram it\n", phy);
return;
}
- drm_dbg(&dev_priv->drm,
+ drm_dbg(display->drm,
"DDI PHY %d enabled with invalid state, "
"force reprogramming it\n", phy);
}
- intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask);
+ intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask);
/*
* The PHY registers start out inaccessible and respond to reads with
@@ -427,92 +426,91 @@ static void _bxt_dpio_phy_init(struct drm_i915_private *dev_priv,
* The flag should get set in 100us according to the HW team, but
* use 1ms due to occasional timeouts observed with that.
*/
- if (intel_de_wait_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy),
+ if (intel_de_wait_fw(display, BXT_PORT_CL1CM_DW0(phy),
PHY_RESERVED | PHY_POWER_GOOD, PHY_POWER_GOOD, 1))
- drm_err(&dev_priv->drm, "timeout during PHY%d power on\n",
+ drm_err(display->drm, "timeout during PHY%d power on\n",
phy);
/* Program PLL Rcomp code offset */
- intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW9(phy),
+ intel_de_rmw(display, BXT_PORT_CL1CM_DW9(phy),
IREF0RC_OFFSET_MASK, IREF0RC_OFFSET(0xE4));
- intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW10(phy),
+ intel_de_rmw(display, BXT_PORT_CL1CM_DW10(phy),
IREF1RC_OFFSET_MASK, IREF1RC_OFFSET(0xE4));
/* Program power gating */
- intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW28(phy), 0,
+ intel_de_rmw(display, BXT_PORT_CL1CM_DW28(phy), 0,
OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG);
if (phy_info->dual_channel)
- intel_de_rmw(dev_priv, BXT_PORT_CL2CM_DW6(phy), 0,
+ intel_de_rmw(display, BXT_PORT_CL2CM_DW6(phy), 0,
DW6_OLDO_DYN_PWR_DOWN_EN);
if (phy_info->rcomp_phy != -1) {
u32 grc_code;
- bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
+ bxt_phy_wait_grc_done(display, phy_info->rcomp_phy);
/*
* PHY0 isn't connected to an RCOMP resistor so copy over
* the corresponding calibrated value from PHY1, and disable
* the automatic calibration on PHY0.
*/
- val = bxt_get_grc(dev_priv, phy_info->rcomp_phy);
- dev_priv->display.state.bxt_phy_grc = val;
+ val = bxt_get_grc(display, phy_info->rcomp_phy);
+ display->state.bxt_phy_grc = val;
grc_code = GRC_CODE_FAST(val) |
GRC_CODE_SLOW(val) |
GRC_CODE_NOM(val);
- intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code);
- intel_de_rmw(dev_priv, BXT_PORT_REF_DW8(phy),
+ intel_de_write(display, BXT_PORT_REF_DW6(phy), grc_code);
+ intel_de_rmw(display, BXT_PORT_REF_DW8(phy),
0, GRC_DIS | GRC_RDY_OVRD);
}
if (phy_info->reset_delay)
udelay(phy_info->reset_delay);
- intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);
+ intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);
}
-void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)
{
const struct bxt_dpio_phy_info *phy_info;
- phy_info = bxt_get_phy_info(dev_priv, phy);
+ phy_info = bxt_get_phy_info(display, phy);
- intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);
+ intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);
- intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);
+ intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);
}
-void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
{
- const struct bxt_dpio_phy_info *phy_info =
- bxt_get_phy_info(dev_priv, phy);
+ const struct bxt_dpio_phy_info *phy_info = bxt_get_phy_info(display, phy);
enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
bool was_enabled;
- lockdep_assert_held(&dev_priv->display.power.domains.lock);
+ lockdep_assert_held(&display->power.domains.lock);
was_enabled = true;
if (rcomp_phy != -1)
- was_enabled = bxt_dpio_phy_is_enabled(dev_priv, rcomp_phy);
+ was_enabled = bxt_dpio_phy_is_enabled(display, rcomp_phy);
/*
* We need to copy the GRC calibration value from rcomp_phy,
* so make sure it's powered up.
*/
if (!was_enabled)
- _bxt_dpio_phy_init(dev_priv, rcomp_phy);
+ _bxt_dpio_phy_init(display, rcomp_phy);
- _bxt_dpio_phy_init(dev_priv, phy);
+ _bxt_dpio_phy_init(display, phy);
if (!was_enabled)
- bxt_dpio_phy_uninit(dev_priv, rcomp_phy);
+ bxt_dpio_phy_uninit(display, rcomp_phy);
}
static bool __printf(6, 7)
-__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
+__phy_reg_verify_state(struct intel_display *display, enum dpio_phy phy,
i915_reg_t reg, u32 mask, u32 expected,
const char *reg_fmt, ...)
{
@@ -520,7 +518,7 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
va_list args;
u32 val;
- val = intel_de_read(dev_priv, reg);
+ val = intel_de_read(display, reg);
if ((val & mask) == expected)
return true;
@@ -528,7 +526,7 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
vaf.fmt = reg_fmt;
vaf.va = &args;
- drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "
+ drm_dbg(display->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "
"current %08x, expected %08x (mask %08x)\n",
phy, &vaf, reg.reg, val, (val & ~mask) | expected,
mask);
@@ -538,20 +536,20 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
return false;
}
-bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
+bool bxt_dpio_phy_verify_state(struct intel_display *display,
enum dpio_phy phy)
{
const struct bxt_dpio_phy_info *phy_info;
u32 mask;
bool ok;
- phy_info = bxt_get_phy_info(dev_priv, phy);
+ phy_info = bxt_get_phy_info(display, phy);
#define _CHK(reg, mask, exp, fmt, ...) \
- __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
+ __phy_reg_verify_state(display, phy, reg, mask, exp, fmt, \
## __VA_ARGS__)
- if (!bxt_dpio_phy_is_enabled(dev_priv, phy))
+ if (!bxt_dpio_phy_is_enabled(display, phy))
return false;
ok = true;
@@ -575,7 +573,7 @@ bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
"BXT_PORT_CL2CM_DW6(%d)", phy);
if (phy_info->rcomp_phy != -1) {
- u32 grc_code = dev_priv->display.state.bxt_phy_grc;
+ u32 grc_code = display->state.bxt_phy_grc;
grc_code = GRC_CODE_FAST(grc_code) |
GRC_CODE_SLOW(grc_code) |
@@ -614,20 +612,20 @@ bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count)
void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
u8 lane_lat_optim_mask)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum dpio_phy phy;
enum dpio_channel ch;
int lane;
- bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
+ bxt_port_to_phy_channel(display, port, &phy, &ch);
for (lane = 0; lane < 4; lane++) {
/*
* Note that on CHV this flag is called UPAR, but has
* the same function.
*/
- intel_de_rmw(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane),
+ intel_de_rmw(display, BXT_PORT_TX_DW14_LN(phy, ch, lane),
LATENCY_OPTIM,
lane_lat_optim_mask & BIT(lane) ? LATENCY_OPTIM : 0);
}
@@ -636,18 +634,18 @@ void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
u8
bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum dpio_phy phy;
enum dpio_channel ch;
int lane;
u8 mask;
- bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
+ bxt_port_to_phy_channel(display, port, &phy, &ch);
mask = 0;
for (lane = 0; lane < 4; lane++) {
- u32 val = intel_de_read(dev_priv,
+ u32 val = intel_de_read(display,
BXT_PORT_TX_DW14_LN(phy, ch, lane));
if (val & LATENCY_OPTIM)
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
index 226994dcb89b..a82939165546 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
@@ -10,9 +10,9 @@
enum pipe;
enum port;
-struct drm_i915_private;
struct intel_crtc_state;
struct intel_digital_port;
+struct intel_display;
struct intel_encoder;
enum dpio_channel {
@@ -27,15 +27,15 @@ enum dpio_phy {
};
#ifdef I915
-void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
+void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch);
void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
-void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
-void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
-bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
+void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy);
+void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy);
+bool bxt_dpio_phy_is_enabled(struct intel_display *display,
enum dpio_phy phy);
-bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
+bool bxt_dpio_phy_verify_state(struct intel_display *display,
enum dpio_phy phy);
u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count);
void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
@@ -73,7 +73,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
void vlv_phy_reset_lanes(struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state);
#else
-static inline void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
+static inline void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch)
{
}
@@ -81,18 +81,18 @@ static inline void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
}
-static inline void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+static inline void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
{
}
-static inline void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+static inline void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)
{
}
-static inline bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
+static inline bool bxt_dpio_phy_is_enabled(struct intel_display *display,
enum dpio_phy phy)
{
return false;
}
-static inline bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
+static inline bool bxt_dpio_phy_verify_state(struct intel_display *display,
enum dpio_phy phy)
{
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f490b2157828..99962d8cc6b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2035,13 +2035,14 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct intel_display *display = &i915->display;
const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
enum dpio_phy phy;
enum dpio_channel ch;
u32 temp;
- bxt_port_to_phy_channel(i915, port, &phy, &ch);
+ bxt_port_to_phy_channel(display, port, &phy, &ch);
/* Non-SSC reference */
intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
@@ -2157,6 +2158,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct intel_display *display = &i915->display;
struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
intel_wakeref_t wakeref;
@@ -2165,7 +2167,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
u32 val;
bool ret;
- bxt_port_to_phy_channel(i915, port, &phy, &ch);
+ bxt_port_to_phy_channel(display, port, &phy, &ch);
wakeref = intel_display_power_get_if_enabled(i915,
POWER_DOMAIN_DISPLAY_CORE);
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [CI v2 v2 05/12] drm/i915/hdcp: further conversion to struct intel_display
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (3 preceding siblings ...)
2024-10-28 20:07 ` [CI v2 v2 04/12] drm/i915/dpio: " Jani Nikula
@ 2024-10-28 20:07 ` Jani Nikula
2024-10-28 20:07 ` [CI v2 v2 06/12] drm/i915/dp/hdcp: convert " Jani Nikula
` (12 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2024-10-28 20:07 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, Rodrigo Vivi
There are some unconverted stragglers left in the HDCP API still using
struct drm_i915_private. Convert to struct intel_display.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../drm/i915/display/intel_display_driver.c | 7 +++--
drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 5 ++--
drivers/gpu/drm/i915/display/intel_hdcp.c | 30 ++++++++-----------
drivers/gpu/drm/i915/display/intel_hdcp.h | 10 +++----
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +-
drivers/gpu/drm/xe/display/xe_display.c | 4 ++-
7 files changed, 30 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index ae5470078173..3b37a8a69201 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -485,7 +485,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
return 0;
err_hdcp:
- intel_hdcp_component_fini(i915);
+ intel_hdcp_component_fini(display);
err_mode_config:
intel_mode_config_cleanup(i915);
@@ -495,6 +495,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
/* part #3: call after gem init */
int intel_display_driver_probe(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
int ret;
if (!HAS_DISPLAY(i915))
@@ -505,7 +506,7 @@ int intel_display_driver_probe(struct drm_i915_private *i915)
* the BIOS fb takeover and whatever else magic ggtt reservations
* happen during gem/ggtt init.
*/
- intel_hdcp_component_init(i915);
+ intel_hdcp_component_init(display);
/*
* Force all active planes to recompute their states. So that on
@@ -600,7 +601,7 @@ void intel_display_driver_remove_noirq(struct drm_i915_private *i915)
/* flush any delayed tasks or pending work */
flush_workqueue(i915->unordered_wq);
- intel_hdcp_component_fini(i915);
+ intel_hdcp_component_fini(display);
intel_mode_config_cleanup(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7e29619ba040..2c8db21e8612 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6416,6 +6416,7 @@ bool
intel_dp_init_connector(struct intel_digital_port *dig_port,
struct intel_connector *intel_connector)
{
+ struct intel_display *display = to_intel_display(dig_port);
struct drm_connector *connector = &intel_connector->base;
struct intel_dp *intel_dp = &dig_port->dp;
struct intel_encoder *intel_encoder = &dig_port->base;
@@ -6505,7 +6506,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
intel_dp_add_properties(intel_dp, connector);
- if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
+ if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {
int ret = intel_dp_hdcp_init(dig_port, intel_connector);
if (ret)
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index dce645a07cdb..5d77adaaf566 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -873,13 +873,12 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
int intel_dp_hdcp_init(struct intel_digital_port *dig_port,
struct intel_connector *intel_connector)
{
- struct drm_device *dev = intel_connector->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_display *display = to_intel_display(dig_port);
struct intel_encoder *intel_encoder = &dig_port->base;
enum port port = intel_encoder->port;
struct intel_dp *intel_dp = &dig_port->dp;
- if (!is_hdcp_supported(dev_priv, port))
+ if (!is_hdcp_supported(display, port))
return 0;
if (intel_connector->mst_port)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index ed6aa87403e2..870084af92d0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1192,10 +1192,10 @@ static void intel_hdcp_prop_work(struct work_struct *work)
drm_connector_put(&connector->base);
}
-bool is_hdcp_supported(struct drm_i915_private *i915, enum port port)
+bool is_hdcp_supported(struct intel_display *display, enum port port)
{
- return DISPLAY_RUNTIME_INFO(i915)->has_hdcp &&
- (DISPLAY_VER(i915) >= 12 || port < PORT_E);
+ return DISPLAY_RUNTIME_INFO(display)->has_hdcp &&
+ (DISPLAY_VER(display) >= 12 || port < PORT_E);
}
static int
@@ -2301,9 +2301,9 @@ static int initialize_hdcp_port_data(struct intel_connector *connector,
return 0;
}
-static bool is_hdcp2_supported(struct drm_i915_private *i915)
+static bool is_hdcp2_supported(struct intel_display *display)
{
- struct intel_display *display = to_intel_display(&i915->drm);
+ struct drm_i915_private *i915 = to_i915(display->drm);
if (intel_hdcp_gsc_cs_required(display))
return true;
@@ -2317,12 +2317,11 @@ static bool is_hdcp2_supported(struct drm_i915_private *i915)
IS_COMETLAKE(i915));
}
-void intel_hdcp_component_init(struct drm_i915_private *i915)
+void intel_hdcp_component_init(struct intel_display *display)
{
- struct intel_display *display = to_intel_display(&i915->drm);
int ret;
- if (!is_hdcp2_supported(i915))
+ if (!is_hdcp2_supported(display))
return;
mutex_lock(&display->hdcp.hdcp_mutex);
@@ -2367,19 +2366,18 @@ int intel_hdcp_init(struct intel_connector *connector,
struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
if (!shim)
return -EINVAL;
- if (is_hdcp2_supported(i915))
+ if (is_hdcp2_supported(display))
intel_hdcp2_init(connector, dig_port, shim);
- ret =
- drm_connector_attach_content_protection_property(&connector->base,
- hdcp->hdcp2_supported);
+ ret = drm_connector_attach_content_protection_property(&connector->base,
+ hdcp->hdcp2_supported);
if (ret) {
hdcp->hdcp2_supported = false;
kfree(dig_port->hdcp_port_data.streams);
@@ -2432,7 +2430,7 @@ static int _intel_hdcp_enable(struct intel_atomic_state *state,
hdcp->stream_transcoder = INVALID_TRANSCODER;
}
- if (DISPLAY_VER(i915) >= 12)
+ if (DISPLAY_VER(display) >= 12)
dig_port->hdcp_port_data.hdcp_transcoder =
intel_get_hdcp_transcoder(hdcp->cpu_transcoder);
@@ -2583,10 +2581,8 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
_intel_hdcp_enable(state, encoder, crtc_state, conn_state);
}
-void intel_hdcp_component_fini(struct drm_i915_private *i915)
+void intel_hdcp_component_fini(struct intel_display *display)
{
- struct intel_display *display = to_intel_display(&i915->drm);
-
mutex_lock(&display->hdcp.hdcp_mutex);
if (!display->hdcp.comp_added) {
mutex_unlock(&display->hdcp.hdcp_mutex);
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
index 477f2d2bb120..d99830cfb798 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -12,13 +12,13 @@
struct drm_connector;
struct drm_connector_state;
-struct drm_i915_private;
struct intel_atomic_state;
struct intel_connector;
struct intel_crtc_state;
+struct intel_digital_port;
+struct intel_display;
struct intel_encoder;
struct intel_hdcp_shim;
-struct intel_digital_port;
enum port;
enum transcoder;
@@ -37,14 +37,14 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
-bool is_hdcp_supported(struct drm_i915_private *i915, enum port port);
+bool is_hdcp_supported(struct intel_display *display, enum port port);
bool intel_hdcp_get_capability(struct intel_connector *connector);
bool intel_hdcp2_get_capability(struct intel_connector *connector);
void intel_hdcp_get_remote_capability(struct intel_connector *connector,
bool *hdcp_capable,
bool *hdcp2_capable);
-void intel_hdcp_component_init(struct drm_i915_private *i915);
-void intel_hdcp_component_fini(struct drm_i915_private *i915);
+void intel_hdcp_component_init(struct intel_display *display);
+void intel_hdcp_component_fini(struct intel_display *display);
void intel_hdcp_cleanup(struct intel_connector *connector);
void intel_hdcp_handle_cp_irq(struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 37b61f05bd73..e1a1351bc94f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3026,7 +3026,6 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
struct intel_encoder *intel_encoder = &dig_port->base;
struct drm_device *dev = intel_encoder->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
enum port port = intel_encoder->port;
struct cec_connector_info conn_info;
u8 ddc_pin;
@@ -3076,7 +3075,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
intel_connector_attach_encoder(intel_connector, intel_encoder);
intel_hdmi->attached_connector = intel_connector;
- if (is_hdcp_supported(dev_priv, port)) {
+ if (is_hdcp_supported(display, port)) {
int ret = intel_hdcp_init(intel_connector, dig_port,
&intel_hdmi_hdcp_shim);
if (ret)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index 695c27ac6b0f..b5502f335f53 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -202,12 +202,14 @@ int xe_display_init(struct xe_device *xe)
void xe_display_fini(struct xe_device *xe)
{
+ struct intel_display *display = &xe->display;
+
if (!xe->info.probe_display)
return;
intel_hpd_poll_fini(xe);
- intel_hdcp_component_fini(xe);
+ intel_hdcp_component_fini(display);
intel_audio_deinit(xe);
}
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [CI v2 v2 06/12] drm/i915/dp/hdcp: convert to struct intel_display
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (4 preceding siblings ...)
2024-10-28 20:07 ` [CI v2 v2 05/12] drm/i915/hdcp: further conversion " Jani Nikula
@ 2024-10-28 20:07 ` Jani Nikula
2024-10-29 9:04 ` [PATCH] " Jani Nikula
2024-10-28 20:07 ` [CI v2 v2 07/12] drm/i915/crt: " Jani Nikula
` (11 subsequent siblings)
17 siblings, 1 reply; 22+ messages in thread
From: Jani Nikula @ 2024-10-28 20:07 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, Rodrigo Vivi
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch DP HDCP code over to it.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 88 ++++++++++----------
1 file changed, 45 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 5d77adaaf566..e7f9619bccc0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -58,7 +58,7 @@ static
int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
u8 *an)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
u8 aksv[DRM_HDCP_KSV_LEN] = {};
ssize_t dpcd_ret;
@@ -66,7 +66,7 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN,
an, DRM_HDCP_AN_LEN);
if (dpcd_ret != DRM_HDCP_AN_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Failed to write An over DP/AUX (%zd)\n",
dpcd_ret);
return dpcd_ret >= 0 ? -EIO : dpcd_ret;
@@ -82,7 +82,7 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV,
aksv, DRM_HDCP_KSV_LEN);
if (dpcd_ret != DRM_HDCP_KSV_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Failed to write Aksv over DP/AUX (%zd)\n",
dpcd_ret);
return dpcd_ret >= 0 ? -EIO : dpcd_ret;
@@ -93,13 +93,13 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
u8 *bksv)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
DRM_HDCP_KSV_LEN);
if (ret != DRM_HDCP_KSV_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read Bksv from DP/AUX failed (%zd)\n", ret);
return ret >= 0 ? -EIO : ret;
}
@@ -109,7 +109,7 @@ static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
u8 *bstatus)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
/*
@@ -120,7 +120,7 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO,
bstatus, DRM_HDCP_BSTATUS_LEN);
if (ret != DRM_HDCP_BSTATUS_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read bstatus from DP/AUX failed (%zd)\n", ret);
return ret >= 0 ? -EIO : ret;
}
@@ -129,7 +129,7 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
static
int intel_dp_hdcp_read_bcaps(struct drm_dp_aux *aux,
- struct drm_i915_private *i915,
+ struct intel_display *display,
u8 *bcaps)
{
ssize_t ret;
@@ -137,7 +137,7 @@ int intel_dp_hdcp_read_bcaps(struct drm_dp_aux *aux,
ret = drm_dp_dpcd_read(aux, DP_AUX_HDCP_BCAPS,
bcaps, 1);
if (ret != 1) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read bcaps from DP/AUX failed (%zd)\n", ret);
return ret >= 0 ? -EIO : ret;
}
@@ -149,11 +149,11 @@ static
int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port,
bool *repeater_present)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
u8 bcaps;
- ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps);
+ ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);
if (ret)
return ret;
@@ -165,13 +165,14 @@ static
int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
u8 *ri_prime)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
ri_prime, DRM_HDCP_RI_LEN);
if (ret != DRM_HDCP_RI_LEN) {
- drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
+ drm_dbg_kms(display->drm,
+ "Read Ri' from DP/AUX failed (%zd)\n",
ret);
return ret >= 0 ? -EIO : ret;
}
@@ -182,14 +183,14 @@ static
int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
bool *ksv_ready)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
u8 bstatus;
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
&bstatus, 1);
if (ret != 1) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read bstatus from DP/AUX failed (%zd)\n", ret);
return ret >= 0 ? -EIO : ret;
}
@@ -201,7 +202,7 @@ static
int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
int num_downstream, u8 *ksv_fifo)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
int i;
@@ -213,7 +214,7 @@ int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
ksv_fifo + i * DRM_HDCP_KSV_LEN,
len);
if (ret != len) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read ksv[%d] from DP/AUX failed (%zd)\n",
i, ret);
return ret >= 0 ? -EIO : ret;
@@ -226,7 +227,7 @@ static
int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
int i, u32 *part)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
@@ -236,7 +237,7 @@ int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
DP_AUX_HDCP_V_PRIME(i), part,
DRM_HDCP_V_PRIME_PART_LEN);
if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
return ret >= 0 ? -EIO : ret;
}
@@ -256,14 +257,14 @@ static
bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port,
struct intel_connector *connector)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
u8 bstatus;
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
&bstatus, 1);
if (ret != 1) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read bstatus from DP/AUX failed (%zd)\n", ret);
return false;
}
@@ -275,11 +276,11 @@ static
int intel_dp_hdcp_get_capability(struct intel_digital_port *dig_port,
bool *hdcp_capable)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
u8 bcaps;
- ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps);
+ ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);
if (ret)
return ret;
@@ -342,7 +343,7 @@ static int
intel_dp_hdcp2_read_rx_status(struct intel_connector *connector,
u8 *rx_status)
{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_dp_aux *aux = &dig_port->dp.aux;
ssize_t ret;
@@ -351,7 +352,7 @@ intel_dp_hdcp2_read_rx_status(struct intel_connector *connector,
DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
HDCP_2_2_DP_RXSTATUS_LEN);
if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read bstatus from DP/AUX failed (%zd)\n", ret);
return ret >= 0 ? -EIO : ret;
}
@@ -397,7 +398,7 @@ static ssize_t
intel_dp_hdcp2_wait_for_msg(struct intel_connector *connector,
const struct hdcp2_dp_msg_data *hdcp2_msg_data)
{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct intel_dp *dp = &dig_port->dp;
struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
@@ -430,7 +431,7 @@ intel_dp_hdcp2_wait_for_msg(struct intel_connector *connector,
}
if (ret)
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"msg_id %d, ret %d, timeout(mSec): %d\n",
hdcp2_msg_data->msg_id, ret, timeout);
@@ -514,8 +515,8 @@ static
int intel_dp_hdcp2_read_msg(struct intel_connector *connector,
u8 msg_id, void *buf, size_t size)
{
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct drm_dp_aux *aux = &dig_port->dp.aux;
struct intel_dp *dp = &dig_port->dp;
struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
@@ -568,7 +569,7 @@ int intel_dp_hdcp2_read_msg(struct intel_connector *connector,
ret = drm_dp_dpcd_read(aux, offset,
(void *)byte, len);
if (ret < 0) {
- drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
+ drm_dbg_kms(display->drm, "msg_id %d, ret %zd\n",
msg_id, ret);
return ret;
}
@@ -581,7 +582,8 @@ int intel_dp_hdcp2_read_msg(struct intel_connector *connector,
if (hdcp2_msg_data->msg_read_timeout > 0) {
msg_expired = ktime_after(ktime_get_raw(), msg_end);
if (msg_expired) {
- drm_dbg_kms(&i915->drm, "msg_id %d, entire msg read timeout(mSec): %d\n",
+ drm_dbg_kms(display->drm,
+ "msg_id %d, entire msg read timeout(mSec): %d\n",
msg_id, hdcp2_msg_data->msg_read_timeout);
return -ETIMEDOUT;
}
@@ -696,7 +698,7 @@ int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector,
bool *hdcp_capable,
bool *hdcp2_capable)
{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct drm_dp_aux *aux;
u8 bcaps;
int ret;
@@ -709,10 +711,10 @@ int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector,
aux = &connector->port->aux;
ret = _intel_dp_hdcp2_get_capability(aux, hdcp2_capable);
if (ret)
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"HDCP2 DPCD capability read failed err: %d\n", ret);
- ret = intel_dp_hdcp_read_bcaps(aux, i915, &bcaps);
+ ret = intel_dp_hdcp_read_bcaps(aux, display, &bcaps);
if (ret)
return ret;
@@ -745,8 +747,8 @@ static int
intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector,
bool enable)
{
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
@@ -754,7 +756,7 @@ intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector,
hdcp->stream_transcoder, enable,
TRANS_DDI_HDCP_SELECT);
if (ret)
- drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
+ drm_err(display->drm, "%s HDCP stream select failed (%d)\n",
enable ? "Enable" : "Disable", ret);
return ret;
}
@@ -763,8 +765,8 @@ static int
intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
bool enable)
{
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
enum port port = dig_port->base.port;
enum transcoder cpu_transcoder = hdcp->stream_transcoder;
@@ -780,10 +782,10 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
return -EINVAL;
/* Wait for encryption confirmation */
- if (intel_de_wait(i915, HDCP_STATUS(i915, cpu_transcoder, port),
+ if (intel_de_wait(display, HDCP_STATUS(display, cpu_transcoder, port),
stream_enc_status, enable ? stream_enc_status : 0,
HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
- drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
+ drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
return -ETIMEDOUT;
}
@@ -795,8 +797,8 @@ static int
intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
bool enable)
{
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
enum transcoder cpu_transcoder = hdcp->stream_transcoder;
@@ -804,8 +806,8 @@ intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
enum port port = dig_port->base.port;
int ret;
- drm_WARN_ON(&i915->drm, enable &&
- !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
+ drm_WARN_ON(display->drm, enable &&
+ !!(intel_de_read(display, HDCP2_AUTH_STREAM(display, cpu_transcoder, port))
& AUTH_STREAM_TYPE) != data->streams[0].stream_type);
ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
@@ -813,11 +815,11 @@ intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
return ret;
/* Wait for encryption confirmation */
- if (intel_de_wait(i915, HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe),
+ if (intel_de_wait(display, HDCP2_STREAM_STATUS(display, cpu_transcoder, pipe),
STREAM_ENCRYPTION_STATUS,
enable ? STREAM_ENCRYPTION_STATUS : 0,
HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
- drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
+ drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
return -ETIMEDOUT;
}
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH] drm/i915/dp/hdcp: convert to struct intel_display
2024-10-28 20:07 ` [CI v2 v2 06/12] drm/i915/dp/hdcp: convert " Jani Nikula
@ 2024-10-29 9:04 ` Jani Nikula
0 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2024-10-29 9:04 UTC (permalink / raw)
To: Jani Nikula, intel-gfx, intel-xe; +Cc: Rodrigo Vivi
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch DP HDCP code over to it.
v2: Rebase
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 88 ++++++++++----------
1 file changed, 45 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index ed22781c486b..00c493cc8a4b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -58,7 +58,7 @@ static
int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
u8 *an)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
u8 aksv[DRM_HDCP_KSV_LEN] = {};
ssize_t dpcd_ret;
@@ -66,7 +66,7 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN,
an, DRM_HDCP_AN_LEN);
if (dpcd_ret != DRM_HDCP_AN_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Failed to write An over DP/AUX (%zd)\n",
dpcd_ret);
return dpcd_ret >= 0 ? -EIO : dpcd_ret;
@@ -82,7 +82,7 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV,
aksv, DRM_HDCP_KSV_LEN);
if (dpcd_ret != DRM_HDCP_KSV_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Failed to write Aksv over DP/AUX (%zd)\n",
dpcd_ret);
return dpcd_ret >= 0 ? -EIO : dpcd_ret;
@@ -93,13 +93,13 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
u8 *bksv)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
DRM_HDCP_KSV_LEN);
if (ret != DRM_HDCP_KSV_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read Bksv from DP/AUX failed (%zd)\n", ret);
return ret >= 0 ? -EIO : ret;
}
@@ -109,7 +109,7 @@ static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
u8 *bstatus)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
/*
@@ -120,7 +120,7 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO,
bstatus, DRM_HDCP_BSTATUS_LEN);
if (ret != DRM_HDCP_BSTATUS_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read bstatus from DP/AUX failed (%zd)\n", ret);
return ret >= 0 ? -EIO : ret;
}
@@ -129,7 +129,7 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
static
int intel_dp_hdcp_read_bcaps(struct drm_dp_aux *aux,
- struct drm_i915_private *i915,
+ struct intel_display *display,
u8 *bcaps)
{
ssize_t ret;
@@ -137,7 +137,7 @@ int intel_dp_hdcp_read_bcaps(struct drm_dp_aux *aux,
ret = drm_dp_dpcd_read(aux, DP_AUX_HDCP_BCAPS,
bcaps, 1);
if (ret != 1) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read bcaps from DP/AUX failed (%zd)\n", ret);
return ret >= 0 ? -EIO : ret;
}
@@ -149,11 +149,11 @@ static
int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port,
bool *repeater_present)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
u8 bcaps;
- ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps);
+ ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);
if (ret)
return ret;
@@ -165,13 +165,14 @@ static
int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
u8 *ri_prime)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
ri_prime, DRM_HDCP_RI_LEN);
if (ret != DRM_HDCP_RI_LEN) {
- drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
+ drm_dbg_kms(display->drm,
+ "Read Ri' from DP/AUX failed (%zd)\n",
ret);
return ret >= 0 ? -EIO : ret;
}
@@ -182,14 +183,14 @@ static
int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
bool *ksv_ready)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
u8 bstatus;
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
&bstatus, 1);
if (ret != 1) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read bstatus from DP/AUX failed (%zd)\n", ret);
return ret >= 0 ? -EIO : ret;
}
@@ -201,7 +202,7 @@ static
int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
int num_downstream, u8 *ksv_fifo)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
int i;
@@ -213,7 +214,7 @@ int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
ksv_fifo + i * DRM_HDCP_KSV_LEN,
len);
if (ret != len) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read ksv[%d] from DP/AUX failed (%zd)\n",
i, ret);
return ret >= 0 ? -EIO : ret;
@@ -226,7 +227,7 @@ static
int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
int i, u32 *part)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
@@ -236,7 +237,7 @@ int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
DP_AUX_HDCP_V_PRIME(i), part,
DRM_HDCP_V_PRIME_PART_LEN);
if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
return ret >= 0 ? -EIO : ret;
}
@@ -256,14 +257,14 @@ static
bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port,
struct intel_connector *connector)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
u8 bstatus;
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
&bstatus, 1);
if (ret != 1) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read bstatus from DP/AUX failed (%zd)\n", ret);
return false;
}
@@ -275,11 +276,11 @@ static
int intel_dp_hdcp_get_capability(struct intel_digital_port *dig_port,
bool *hdcp_capable)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
u8 bcaps;
- ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps);
+ ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);
if (ret)
return ret;
@@ -342,7 +343,7 @@ static int
intel_dp_hdcp2_read_rx_status(struct intel_connector *connector,
u8 *rx_status)
{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_dp_aux *aux = &dig_port->dp.aux;
ssize_t ret;
@@ -351,7 +352,7 @@ intel_dp_hdcp2_read_rx_status(struct intel_connector *connector,
DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
HDCP_2_2_DP_RXSTATUS_LEN);
if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read bstatus from DP/AUX failed (%zd)\n", ret);
return ret >= 0 ? -EIO : ret;
}
@@ -397,7 +398,7 @@ static ssize_t
intel_dp_hdcp2_wait_for_msg(struct intel_connector *connector,
const struct hdcp2_dp_msg_data *hdcp2_msg_data)
{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct intel_dp *dp = &dig_port->dp;
struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
@@ -430,7 +431,7 @@ intel_dp_hdcp2_wait_for_msg(struct intel_connector *connector,
}
if (ret)
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"msg_id %d, ret %d, timeout(mSec): %d\n",
hdcp2_msg_data->msg_id, ret, timeout);
@@ -514,8 +515,8 @@ static
int intel_dp_hdcp2_read_msg(struct intel_connector *connector,
u8 msg_id, void *buf, size_t size)
{
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct drm_dp_aux *aux = &dig_port->dp.aux;
struct intel_dp *dp = &dig_port->dp;
struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
@@ -568,7 +569,7 @@ int intel_dp_hdcp2_read_msg(struct intel_connector *connector,
ret = drm_dp_dpcd_read(aux, offset,
(void *)byte, len);
if (ret < 0) {
- drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
+ drm_dbg_kms(display->drm, "msg_id %d, ret %zd\n",
msg_id, ret);
return ret;
}
@@ -581,7 +582,8 @@ int intel_dp_hdcp2_read_msg(struct intel_connector *connector,
if (hdcp2_msg_data->msg_read_timeout > 0) {
msg_expired = ktime_after(ktime_get_raw(), msg_end);
if (msg_expired) {
- drm_dbg_kms(&i915->drm, "msg_id %d, entire msg read timeout(mSec): %d\n",
+ drm_dbg_kms(display->drm,
+ "msg_id %d, entire msg read timeout(mSec): %d\n",
msg_id, hdcp2_msg_data->msg_read_timeout);
return -ETIMEDOUT;
}
@@ -696,7 +698,7 @@ int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector,
bool *hdcp_capable,
bool *hdcp2_capable)
{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct drm_dp_aux *aux;
u8 bcaps;
int ret;
@@ -709,10 +711,10 @@ int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector,
aux = &connector->port->aux;
ret = _intel_dp_hdcp2_get_capability(aux, hdcp2_capable);
if (ret)
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"HDCP2 DPCD capability read failed err: %d\n", ret);
- ret = intel_dp_hdcp_read_bcaps(aux, i915, &bcaps);
+ ret = intel_dp_hdcp_read_bcaps(aux, display, &bcaps);
if (ret)
return ret;
@@ -745,8 +747,8 @@ static int
intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector,
bool enable)
{
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
@@ -754,7 +756,7 @@ intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector,
hdcp->stream_transcoder, enable,
TRANS_DDI_HDCP_SELECT);
if (ret)
- drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
+ drm_err(display->drm, "%s HDCP stream select failed (%d)\n",
enable ? "Enable" : "Disable", ret);
return ret;
}
@@ -763,8 +765,8 @@ static int
intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
bool enable)
{
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
enum port port = dig_port->base.port;
enum transcoder cpu_transcoder = hdcp->stream_transcoder;
@@ -780,10 +782,10 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
return -EINVAL;
/* Wait for encryption confirmation */
- if (intel_de_wait(i915, HDCP_STATUS(i915, cpu_transcoder, port),
+ if (intel_de_wait(display, HDCP_STATUS(display, cpu_transcoder, port),
stream_enc_status, enable ? stream_enc_status : 0,
HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
- drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
+ drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
transcoder_name(cpu_transcoder), str_enabled_disabled(enable));
return -ETIMEDOUT;
}
@@ -795,8 +797,8 @@ static int
intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
bool enable)
{
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
enum transcoder cpu_transcoder = hdcp->stream_transcoder;
@@ -804,8 +806,8 @@ intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
enum port port = dig_port->base.port;
int ret;
- drm_WARN_ON(&i915->drm, enable &&
- !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
+ drm_WARN_ON(display->drm, enable &&
+ !!(intel_de_read(display, HDCP2_AUTH_STREAM(display, cpu_transcoder, port))
& AUTH_STREAM_TYPE) != data->streams[0].stream_type);
ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
@@ -813,11 +815,11 @@ intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
return ret;
/* Wait for encryption confirmation */
- if (intel_de_wait(i915, HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe),
+ if (intel_de_wait(display, HDCP2_STREAM_STATUS(display, cpu_transcoder, pipe),
STREAM_ENCRYPTION_STATUS,
enable ? STREAM_ENCRYPTION_STATUS : 0,
HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
- drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
+ drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
transcoder_name(cpu_transcoder), str_enabled_disabled(enable));
return -ETIMEDOUT;
}
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [CI v2 v2 07/12] drm/i915/crt: convert to struct intel_display
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (5 preceding siblings ...)
2024-10-28 20:07 ` [CI v2 v2 06/12] drm/i915/dp/hdcp: convert " Jani Nikula
@ 2024-10-28 20:07 ` Jani Nikula
2024-10-29 10:52 ` [PATCH] " Jani Nikula
2024-10-28 20:07 ` [CI v2 v2 08/12] drm/i915/display: convert vlv_wait_port_ready() " Jani Nikula
` (10 subsequent siblings)
17 siblings, 1 reply; 22+ messages in thread
From: Jani Nikula @ 2024-10-28 20:07 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, Rodrigo Vivi
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch CRT code over to it.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_crt.c | 209 +++++++++---------
drivers/gpu/drm/i915/display/intel_crt.h | 10 +-
drivers/gpu/drm/i915/display/intel_display.c | 12 +-
.../gpu/drm/i915/display/intel_pch_display.c | 3 +-
4 files changed, 123 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 8222b1c251db..74c1983fe07e 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -81,12 +81,13 @@ static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
return intel_encoder_to_crt(intel_attached_encoder(connector));
}
-bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
+bool intel_crt_port_enabled(struct intel_display *display,
i915_reg_t adpa_reg, enum pipe *pipe)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 val;
- val = intel_de_read(dev_priv, adpa_reg);
+ val = intel_de_read(display, adpa_reg);
/* asserts want to know the pipe even if the port is disabled */
if (HAS_PCH_CPT(dev_priv))
@@ -100,6 +101,7 @@ bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crt *crt = intel_encoder_to_crt(encoder);
intel_wakeref_t wakeref;
@@ -110,7 +112,7 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
if (!wakeref)
return false;
- ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
+ ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe);
intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
@@ -119,11 +121,11 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_crt *crt = intel_encoder_to_crt(encoder);
u32 tmp, flags = 0;
- tmp = intel_de_read(dev_priv, crt->adpa_reg);
+ tmp = intel_de_read(display, crt->adpa_reg);
if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
flags |= DRM_MODE_FLAG_PHSYNC;
@@ -168,13 +170,14 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int mode)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crt *crt = intel_encoder_to_crt(encoder);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
u32 adpa;
- if (DISPLAY_VER(dev_priv) >= 5)
+ if (DISPLAY_VER(display) >= 5)
adpa = ADPA_HOTPLUG_BITS;
else
adpa = 0;
@@ -193,7 +196,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
adpa |= ADPA_PIPE_SEL(crtc->pipe);
if (!HAS_PCH_SPLIT(dev_priv))
- intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
+ intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);
switch (mode) {
case DRM_MODE_DPMS_ON:
@@ -210,7 +213,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
break;
}
- intel_de_write(dev_priv, crt->adpa_reg, adpa);
+ intel_de_write(display, crt->adpa_reg, adpa);
}
static void intel_disable_crt(struct intel_atomic_state *state,
@@ -241,9 +244,10 @@ static void hsw_disable_crt(struct intel_atomic_state *state,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state *old_conn_state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
+ drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
}
@@ -253,6 +257,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state *old_conn_state)
{
+ struct intel_display *display = to_intel_display(state);
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -272,7 +277,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
hsw_fdi_disable(encoder);
- drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
+ drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
}
@@ -282,9 +287,10 @@ static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
+ drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
}
@@ -294,11 +300,12 @@ static void hsw_pre_enable_crt(struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
- drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
+ drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
@@ -312,11 +319,12 @@ static void hsw_enable_crt(struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
- drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
+ drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
intel_ddi_enable_transcoder_func(encoder, crtc_state);
@@ -346,9 +354,10 @@ static enum drm_mode_status
intel_crt_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_device *dev = connector->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq;
+ int max_dotclk = display->cdclk.max_dotclk_freq;
enum drm_mode_status status;
int max_clock;
@@ -367,7 +376,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
* DAC limit supposedly 355 MHz.
*/
max_clock = 270000;
- else if (IS_DISPLAY_VER(dev_priv, 3, 4))
+ else if (IS_DISPLAY_VER(display, 3, 4))
max_clock = 400000;
else
max_clock = 350000;
@@ -428,6 +437,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
@@ -450,7 +460,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
if (HAS_PCH_LPT(dev_priv)) {
/* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"LPT only supports 24bpp\n");
return -EINVAL;
}
@@ -470,6 +480,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_device *dev = connector->dev;
struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -483,36 +494,36 @@ static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
crt->force_hotplug_required = false;
- save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
- drm_dbg_kms(&dev_priv->drm,
+ save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
+ drm_dbg_kms(display->drm,
"trigger hotplug detect cycle: adpa=0x%x\n", adpa);
adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
if (turn_off_dac)
adpa &= ~ADPA_DAC_ENABLE;
- intel_de_write(dev_priv, crt->adpa_reg, adpa);
+ intel_de_write(display, crt->adpa_reg, adpa);
- if (intel_de_wait_for_clear(dev_priv,
+ if (intel_de_wait_for_clear(display,
crt->adpa_reg,
ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
1000))
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"timed out waiting for FORCE_TRIGGER");
if (turn_off_dac) {
- intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
- intel_de_posting_read(dev_priv, crt->adpa_reg);
+ intel_de_write(display, crt->adpa_reg, save_adpa);
+ intel_de_posting_read(display, crt->adpa_reg);
}
}
/* Check the status to see if both blue and green are on now */
- adpa = intel_de_read(dev_priv, crt->adpa_reg);
+ adpa = intel_de_read(display, crt->adpa_reg);
if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
ret = true;
else
ret = false;
- drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n",
+ drm_dbg_kms(display->drm, "ironlake hotplug adpa=0x%x, result %d\n",
adpa, ret);
return ret;
@@ -520,6 +531,7 @@ static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_device *dev = connector->dev;
struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -542,29 +554,29 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
*/
reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
- save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
- drm_dbg_kms(&dev_priv->drm,
+ save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
+ drm_dbg_kms(display->drm,
"trigger hotplug detect cycle: adpa=0x%x\n", adpa);
adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
- intel_de_write(dev_priv, crt->adpa_reg, adpa);
+ intel_de_write(display, crt->adpa_reg, adpa);
- if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
+ if (intel_de_wait_for_clear(display, crt->adpa_reg,
ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"timed out waiting for FORCE_TRIGGER");
- intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
+ intel_de_write(display, crt->adpa_reg, save_adpa);
}
/* Check the status to see if both blue and green are on now */
- adpa = intel_de_read(dev_priv, crt->adpa_reg);
+ adpa = intel_de_read(display, crt->adpa_reg);
if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
ret = true;
else
ret = false;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
if (reenable_hpd)
@@ -575,6 +587,7 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
static bool intel_crt_detect_hotplug(struct drm_connector *connector)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_device *dev = connector->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
u32 stat;
@@ -603,18 +616,18 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
CRT_HOTPLUG_FORCE_DETECT,
CRT_HOTPLUG_FORCE_DETECT);
/* wait for FORCE_DETECT to go off */
- if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN(dev_priv),
+ if (intel_de_wait_for_clear(display, PORT_HOTPLUG_EN(display),
CRT_HOTPLUG_FORCE_DETECT, 1000))
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"timed out waiting for FORCE_DETECT to go off");
}
- stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT(dev_priv));
+ stat = intel_de_read(display, PORT_HOTPLUG_STAT(display));
if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
ret = true;
/* clear the interrupt we just generated, if any */
- intel_de_write(dev_priv, PORT_HOTPLUG_STAT(dev_priv),
+ intel_de_write(display, PORT_HOTPLUG_STAT(display),
CRT_HOTPLUG_INT_STATUS);
i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
@@ -660,8 +673,7 @@ static int intel_crt_ddc_get_modes(struct drm_connector *connector,
static bool intel_crt_detect_ddc(struct drm_connector *connector)
{
- struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
- struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
+ struct intel_display *display = to_intel_display(connector->dev);
const struct drm_edid *drm_edid;
bool ret = false;
@@ -674,15 +686,15 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector)
* have to check the EDID input spec of the attached device.
*/
if (drm_edid_is_digital(drm_edid)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
} else {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"CRT detected via DDC:0x50 [EDID]\n");
ret = true;
}
} else {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"CRT not detected via DDC:0x50 [no valid EDID found]\n");
}
@@ -695,8 +707,6 @@ static enum drm_connector_status
intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
{
struct intel_display *display = to_intel_display(&crt->base);
- struct drm_device *dev = crt->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
enum transcoder cpu_transcoder = (enum transcoder)pipe;
u32 save_bclrpat;
u32 save_vtotal;
@@ -707,14 +717,14 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
u8 st00;
enum drm_connector_status status;
- drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
+ drm_dbg_kms(display->drm, "starting load-detect on CRT\n");
- save_bclrpat = intel_de_read(dev_priv,
- BCLRPAT(dev_priv, cpu_transcoder));
- save_vtotal = intel_de_read(dev_priv,
- TRANS_VTOTAL(dev_priv, cpu_transcoder));
- vblank = intel_de_read(dev_priv,
- TRANS_VBLANK(dev_priv, cpu_transcoder));
+ save_bclrpat = intel_de_read(display,
+ BCLRPAT(display, cpu_transcoder));
+ save_vtotal = intel_de_read(display,
+ TRANS_VTOTAL(display, cpu_transcoder));
+ vblank = intel_de_read(display,
+ TRANS_VBLANK(display, cpu_transcoder));
vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
@@ -723,25 +733,25 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
/* Set the border color to purple. */
- intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), 0x500050);
+ intel_de_write(display, BCLRPAT(display, cpu_transcoder), 0x500050);
- if (DISPLAY_VER(dev_priv) != 2) {
- u32 transconf = intel_de_read(dev_priv,
- TRANSCONF(dev_priv, cpu_transcoder));
+ if (DISPLAY_VER(display) != 2) {
+ u32 transconf = intel_de_read(display,
+ TRANSCONF(display, cpu_transcoder));
- intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANSCONF(display, cpu_transcoder),
transconf | TRANSCONF_FORCE_BORDER);
- intel_de_posting_read(dev_priv,
- TRANSCONF(dev_priv, cpu_transcoder));
+ intel_de_posting_read(display,
+ TRANSCONF(display, cpu_transcoder));
/* Wait for next Vblank to substitue
* border color for Color info */
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
- st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
+ st00 = intel_de_read8(display, _VGA_MSR_WRITE);
status = ((st00 & (1 << 4)) != 0) ?
connector_status_connected :
connector_status_disconnected;
- intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANSCONF(display, cpu_transcoder),
transconf);
} else {
bool restore_vblank = false;
@@ -752,13 +762,13 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
* Yes, this will flicker
*/
if (vblank_start <= vactive && vblank_end >= vtotal) {
- u32 vsync = intel_de_read(dev_priv,
- TRANS_VSYNC(dev_priv, cpu_transcoder));
+ u32 vsync = intel_de_read(display,
+ TRANS_VSYNC(display, cpu_transcoder));
u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
vblank_start = vsync_start;
- intel_de_write(dev_priv,
- TRANS_VBLANK(dev_priv, cpu_transcoder),
+ intel_de_write(display,
+ TRANS_VBLANK(display, cpu_transcoder),
VBLANK_START(vblank_start - 1) |
VBLANK_END(vblank_end - 1));
restore_vblank = true;
@@ -772,9 +782,9 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
/*
* Wait for the border to be displayed
*/
- while (intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) >= vactive)
+ while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive)
;
- while ((dsl = intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe))) <= vsample)
+ while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample)
;
/*
* Watch ST00 for an entire scanline
@@ -784,15 +794,15 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
do {
count++;
/* Read the ST00 VGA status register */
- st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
+ st00 = intel_de_read8(display, _VGA_MSR_WRITE);
if (st00 & (1 << 4))
detect++;
- } while ((intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) == dsl));
+ } while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));
/* restore vblank if necessary */
if (restore_vblank)
- intel_de_write(dev_priv,
- TRANS_VBLANK(dev_priv, cpu_transcoder),
+ intel_de_write(display,
+ TRANS_VBLANK(display, cpu_transcoder),
vblank);
/*
* If more than 3/4 of the scanline detected a monitor,
@@ -806,7 +816,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
}
/* Restore previous settings */
- intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder),
+ intel_de_write(display, BCLRPAT(display, cpu_transcoder),
save_bclrpat);
return status;
@@ -843,6 +853,7 @@ intel_crt_detect(struct drm_connector *connector,
struct drm_modeset_acquire_ctx *ctx,
bool force)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
struct intel_encoder *intel_encoder = &crt->base;
@@ -850,7 +861,7 @@ intel_crt_detect(struct drm_connector *connector,
intel_wakeref_t wakeref;
int status;
- drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n",
+ drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",
connector->base.id, connector->name,
force);
@@ -860,7 +871,7 @@ intel_crt_detect(struct drm_connector *connector,
if (!intel_display_driver_check_access(dev_priv))
return connector->status;
- if (dev_priv->display.params.load_detect_test) {
+ if (display->params.load_detect_test) {
wakeref = intel_display_power_get(dev_priv,
intel_encoder->power_domain);
goto load_detect;
@@ -873,18 +884,18 @@ intel_crt_detect(struct drm_connector *connector,
wakeref = intel_display_power_get(dev_priv,
intel_encoder->power_domain);
- if (I915_HAS_HOTPLUG(dev_priv)) {
+ if (I915_HAS_HOTPLUG(display)) {
/* We can not rely on the HPD pin always being correctly wired
* up, for example many KVM do not pass it through, and so
* only trust an assertion that the monitor is connected.
*/
if (intel_crt_detect_hotplug(connector)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"CRT detected via hotplug\n");
status = connector_status_connected;
goto out;
} else
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"CRT not detected via hotplug\n");
}
@@ -897,7 +908,7 @@ intel_crt_detect(struct drm_connector *connector,
* broken monitor (without edid) to work behind a broken kvm (that fails
* to have the right resistors for HP detection) needs to fix this up.
* For now just bail out. */
- if (I915_HAS_HOTPLUG(dev_priv)) {
+ if (I915_HAS_HOTPLUG(display)) {
status = connector_status_disconnected;
goto out;
}
@@ -917,10 +928,10 @@ intel_crt_detect(struct drm_connector *connector,
} else {
if (intel_crt_detect_ddc(connector))
status = connector_status_connected;
- else if (DISPLAY_VER(dev_priv) < 4)
+ else if (DISPLAY_VER(display) < 4)
status = intel_crt_load_detect(crt,
to_intel_crtc(connector->state->crtc)->pipe);
- else if (dev_priv->display.params.load_detect_test)
+ else if (display->params.load_detect_test)
status = connector_status_disconnected;
else
status = connector_status_unknown;
@@ -966,19 +977,19 @@ static int intel_crt_get_modes(struct drm_connector *connector)
void intel_crt_reset(struct drm_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->dev);
+ struct intel_display *display = to_intel_display(encoder->dev);
struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
- if (DISPLAY_VER(dev_priv) >= 5) {
+ if (DISPLAY_VER(display) >= 5) {
u32 adpa;
- adpa = intel_de_read(dev_priv, crt->adpa_reg);
+ adpa = intel_de_read(display, crt->adpa_reg);
adpa &= ~ADPA_CRT_HOTPLUG_MASK;
adpa |= ADPA_HOTPLUG_BITS;
- intel_de_write(dev_priv, crt->adpa_reg, adpa);
- intel_de_posting_read(dev_priv, crt->adpa_reg);
+ intel_de_write(display, crt->adpa_reg, adpa);
+ intel_de_posting_read(display, crt->adpa_reg);
- drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa);
+ drm_dbg_kms(display->drm, "crt adpa set to 0x%x\n", adpa);
crt->force_hotplug_required = true;
}
@@ -1008,9 +1019,9 @@ static const struct drm_encoder_funcs intel_crt_enc_funcs = {
.destroy = intel_encoder_destroy,
};
-void intel_crt_init(struct drm_i915_private *dev_priv)
+void intel_crt_init(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct drm_connector *connector;
struct intel_crt *crt;
struct intel_connector *intel_connector;
@@ -1025,7 +1036,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
else
adpa_reg = ADPA;
- adpa = intel_de_read(dev_priv, adpa_reg);
+ adpa = intel_de_read(display, adpa_reg);
if ((adpa & ADPA_DAC_ENABLE) == 0) {
/*
* On some machines (some IVB at least) CRT can be
@@ -1035,11 +1046,11 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
* take. So the only way to tell is attempt to enable
* it and see what happens.
*/
- intel_de_write(dev_priv, adpa_reg,
+ intel_de_write(display, adpa_reg,
adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
- if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0)
+ if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0)
return;
- intel_de_write(dev_priv, adpa_reg, adpa);
+ intel_de_write(display, adpa_reg, adpa);
}
crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
@@ -1052,16 +1063,16 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
return;
}
- ddc_pin = dev_priv->display.vbt.crt_ddc_pin;
+ ddc_pin = display->vbt.crt_ddc_pin;
connector = &intel_connector->base;
crt->connector = intel_connector;
- drm_connector_init_with_ddc(&dev_priv->drm, connector,
+ drm_connector_init_with_ddc(display->drm, connector,
&intel_crt_connector_funcs,
DRM_MODE_CONNECTOR_VGA,
intel_gmbus_get_adapter(display, ddc_pin));
- drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
+ drm_encoder_init(display->drm, &crt->base.base, &intel_crt_enc_funcs,
DRM_MODE_ENCODER_DAC, "CRT");
intel_connector_attach_encoder(intel_connector, &crt->base);
@@ -1073,14 +1084,14 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
else
crt->base.pipe_mask = ~0;
- if (DISPLAY_VER(dev_priv) != 2)
+ if (DISPLAY_VER(display) != 2)
connector->interlace_allowed = true;
crt->adpa_reg = adpa_reg;
crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
- if (I915_HAS_HOTPLUG(dev_priv) &&
+ if (I915_HAS_HOTPLUG(display) &&
!dmi_check_system(intel_spurious_crt_detect)) {
crt->base.hpd_pin = HPD_CRT;
crt->base.hotplug = intel_encoder_hotplug;
@@ -1090,7 +1101,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
}
intel_connector->base.polled = intel_connector->polled;
- if (HAS_DDI(dev_priv)) {
+ if (HAS_DDI(display)) {
assert_port_valid(dev_priv, PORT_E);
crt->base.port = PORT_E;
@@ -1134,8 +1145,8 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
FDI_RX_LINK_REVERSAL_OVERRIDE;
- dev_priv->display.fdi.rx_config = intel_de_read(dev_priv,
- FDI_RX_CTL(PIPE_A)) & fdi_config;
+ display->fdi.rx_config = intel_de_read(display,
+ FDI_RX_CTL(PIPE_A)) & fdi_config;
}
intel_crt_reset(&crt->base.base);
diff --git a/drivers/gpu/drm/i915/display/intel_crt.h b/drivers/gpu/drm/i915/display/intel_crt.h
index fe7690c2b948..e0abfe96a3d2 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.h
+++ b/drivers/gpu/drm/i915/display/intel_crt.h
@@ -10,20 +10,20 @@
enum pipe;
struct drm_encoder;
-struct drm_i915_private;
+struct intel_display;
#ifdef I915
-bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
+bool intel_crt_port_enabled(struct intel_display *display,
i915_reg_t adpa_reg, enum pipe *pipe);
-void intel_crt_init(struct drm_i915_private *dev_priv);
+void intel_crt_init(struct intel_display *display);
void intel_crt_reset(struct drm_encoder *encoder);
#else
-static inline bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
+static inline bool intel_crt_port_enabled(struct intel_display *display,
i915_reg_t adpa_reg, enum pipe *pipe)
{
return false;
}
-static inline void intel_crt_init(struct drm_i915_private *dev_priv)
+static inline void intel_crt_init(struct intel_display *display)
{
}
static inline void intel_crt_reset(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c19f01b63936..2479ca0a02d9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8147,7 +8147,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (HAS_DDI(dev_priv)) {
if (intel_ddi_crt_present(dev_priv))
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
intel_bios_for_each_encoder(display, intel_ddi_init);
@@ -8162,7 +8162,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
* incorrect sharing of the PPS.
*/
intel_lvds_init(dev_priv);
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
@@ -8193,7 +8193,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
bool has_edp, has_port;
if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
/*
* The DP_DETECTED bit is the latched state of the DDC
@@ -8239,14 +8239,14 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
vlv_dsi_init(dev_priv);
} else if (IS_PINEVIEW(dev_priv)) {
intel_lvds_init(dev_priv);
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
} else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
bool found = false;
if (IS_MOBILE(dev_priv))
intel_lvds_init(dev_priv);
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
@@ -8288,7 +8288,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (IS_I85X(dev_priv))
intel_lvds_init(dev_priv);
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
intel_dvo_init(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index f13ab680c2cf..17739a51fe54 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -76,6 +76,7 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
+ struct intel_display *display = &dev_priv->display;
enum pipe port_pipe;
assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
@@ -83,7 +84,7 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
I915_STATE_WARN(dev_priv,
- intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) && port_pipe == pipe,
+ intel_crt_port_enabled(display, PCH_ADPA, &port_pipe) && port_pipe == pipe,
"PCH VGA enabled on transcoder %c, should be disabled\n",
pipe_name(pipe));
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH] drm/i915/crt: convert to struct intel_display
2024-10-28 20:07 ` [CI v2 v2 07/12] drm/i915/crt: " Jani Nikula
@ 2024-10-29 10:52 ` Jani Nikula
0 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2024-10-29 10:52 UTC (permalink / raw)
To: Jani Nikula, intel-gfx, intel-xe; +Cc: Rodrigo Vivi
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch CRT code over to it.
v2: Rebase
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_crt.c | 209 +++++++++---------
drivers/gpu/drm/i915/display/intel_crt.h | 10 +-
drivers/gpu/drm/i915/display/intel_display.c | 12 +-
.../gpu/drm/i915/display/intel_pch_display.c | 2 +-
4 files changed, 122 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 8222b1c251db..74c1983fe07e 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -81,12 +81,13 @@ static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
return intel_encoder_to_crt(intel_attached_encoder(connector));
}
-bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
+bool intel_crt_port_enabled(struct intel_display *display,
i915_reg_t adpa_reg, enum pipe *pipe)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 val;
- val = intel_de_read(dev_priv, adpa_reg);
+ val = intel_de_read(display, adpa_reg);
/* asserts want to know the pipe even if the port is disabled */
if (HAS_PCH_CPT(dev_priv))
@@ -100,6 +101,7 @@ bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crt *crt = intel_encoder_to_crt(encoder);
intel_wakeref_t wakeref;
@@ -110,7 +112,7 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
if (!wakeref)
return false;
- ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
+ ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe);
intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
@@ -119,11 +121,11 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_crt *crt = intel_encoder_to_crt(encoder);
u32 tmp, flags = 0;
- tmp = intel_de_read(dev_priv, crt->adpa_reg);
+ tmp = intel_de_read(display, crt->adpa_reg);
if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
flags |= DRM_MODE_FLAG_PHSYNC;
@@ -168,13 +170,14 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int mode)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crt *crt = intel_encoder_to_crt(encoder);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
u32 adpa;
- if (DISPLAY_VER(dev_priv) >= 5)
+ if (DISPLAY_VER(display) >= 5)
adpa = ADPA_HOTPLUG_BITS;
else
adpa = 0;
@@ -193,7 +196,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
adpa |= ADPA_PIPE_SEL(crtc->pipe);
if (!HAS_PCH_SPLIT(dev_priv))
- intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
+ intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);
switch (mode) {
case DRM_MODE_DPMS_ON:
@@ -210,7 +213,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
break;
}
- intel_de_write(dev_priv, crt->adpa_reg, adpa);
+ intel_de_write(display, crt->adpa_reg, adpa);
}
static void intel_disable_crt(struct intel_atomic_state *state,
@@ -241,9 +244,10 @@ static void hsw_disable_crt(struct intel_atomic_state *state,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state *old_conn_state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
+ drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
}
@@ -253,6 +257,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state *old_conn_state)
{
+ struct intel_display *display = to_intel_display(state);
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -272,7 +277,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
hsw_fdi_disable(encoder);
- drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
+ drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
}
@@ -282,9 +287,10 @@ static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
+ drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
}
@@ -294,11 +300,12 @@ static void hsw_pre_enable_crt(struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
- drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
+ drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
@@ -312,11 +319,12 @@ static void hsw_enable_crt(struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
- drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
+ drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
intel_ddi_enable_transcoder_func(encoder, crtc_state);
@@ -346,9 +354,10 @@ static enum drm_mode_status
intel_crt_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_device *dev = connector->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq;
+ int max_dotclk = display->cdclk.max_dotclk_freq;
enum drm_mode_status status;
int max_clock;
@@ -367,7 +376,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
* DAC limit supposedly 355 MHz.
*/
max_clock = 270000;
- else if (IS_DISPLAY_VER(dev_priv, 3, 4))
+ else if (IS_DISPLAY_VER(display, 3, 4))
max_clock = 400000;
else
max_clock = 350000;
@@ -428,6 +437,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
@@ -450,7 +460,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
if (HAS_PCH_LPT(dev_priv)) {
/* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"LPT only supports 24bpp\n");
return -EINVAL;
}
@@ -470,6 +480,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_device *dev = connector->dev;
struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -483,36 +494,36 @@ static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
crt->force_hotplug_required = false;
- save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
- drm_dbg_kms(&dev_priv->drm,
+ save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
+ drm_dbg_kms(display->drm,
"trigger hotplug detect cycle: adpa=0x%x\n", adpa);
adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
if (turn_off_dac)
adpa &= ~ADPA_DAC_ENABLE;
- intel_de_write(dev_priv, crt->adpa_reg, adpa);
+ intel_de_write(display, crt->adpa_reg, adpa);
- if (intel_de_wait_for_clear(dev_priv,
+ if (intel_de_wait_for_clear(display,
crt->adpa_reg,
ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
1000))
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"timed out waiting for FORCE_TRIGGER");
if (turn_off_dac) {
- intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
- intel_de_posting_read(dev_priv, crt->adpa_reg);
+ intel_de_write(display, crt->adpa_reg, save_adpa);
+ intel_de_posting_read(display, crt->adpa_reg);
}
}
/* Check the status to see if both blue and green are on now */
- adpa = intel_de_read(dev_priv, crt->adpa_reg);
+ adpa = intel_de_read(display, crt->adpa_reg);
if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
ret = true;
else
ret = false;
- drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n",
+ drm_dbg_kms(display->drm, "ironlake hotplug adpa=0x%x, result %d\n",
adpa, ret);
return ret;
@@ -520,6 +531,7 @@ static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_device *dev = connector->dev;
struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -542,29 +554,29 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
*/
reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
- save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
- drm_dbg_kms(&dev_priv->drm,
+ save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
+ drm_dbg_kms(display->drm,
"trigger hotplug detect cycle: adpa=0x%x\n", adpa);
adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
- intel_de_write(dev_priv, crt->adpa_reg, adpa);
+ intel_de_write(display, crt->adpa_reg, adpa);
- if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
+ if (intel_de_wait_for_clear(display, crt->adpa_reg,
ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"timed out waiting for FORCE_TRIGGER");
- intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
+ intel_de_write(display, crt->adpa_reg, save_adpa);
}
/* Check the status to see if both blue and green are on now */
- adpa = intel_de_read(dev_priv, crt->adpa_reg);
+ adpa = intel_de_read(display, crt->adpa_reg);
if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
ret = true;
else
ret = false;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
if (reenable_hpd)
@@ -575,6 +587,7 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
static bool intel_crt_detect_hotplug(struct drm_connector *connector)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_device *dev = connector->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
u32 stat;
@@ -603,18 +616,18 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
CRT_HOTPLUG_FORCE_DETECT,
CRT_HOTPLUG_FORCE_DETECT);
/* wait for FORCE_DETECT to go off */
- if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN(dev_priv),
+ if (intel_de_wait_for_clear(display, PORT_HOTPLUG_EN(display),
CRT_HOTPLUG_FORCE_DETECT, 1000))
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"timed out waiting for FORCE_DETECT to go off");
}
- stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT(dev_priv));
+ stat = intel_de_read(display, PORT_HOTPLUG_STAT(display));
if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
ret = true;
/* clear the interrupt we just generated, if any */
- intel_de_write(dev_priv, PORT_HOTPLUG_STAT(dev_priv),
+ intel_de_write(display, PORT_HOTPLUG_STAT(display),
CRT_HOTPLUG_INT_STATUS);
i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
@@ -660,8 +673,7 @@ static int intel_crt_ddc_get_modes(struct drm_connector *connector,
static bool intel_crt_detect_ddc(struct drm_connector *connector)
{
- struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
- struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
+ struct intel_display *display = to_intel_display(connector->dev);
const struct drm_edid *drm_edid;
bool ret = false;
@@ -674,15 +686,15 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector)
* have to check the EDID input spec of the attached device.
*/
if (drm_edid_is_digital(drm_edid)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
} else {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"CRT detected via DDC:0x50 [EDID]\n");
ret = true;
}
} else {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"CRT not detected via DDC:0x50 [no valid EDID found]\n");
}
@@ -695,8 +707,6 @@ static enum drm_connector_status
intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
{
struct intel_display *display = to_intel_display(&crt->base);
- struct drm_device *dev = crt->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
enum transcoder cpu_transcoder = (enum transcoder)pipe;
u32 save_bclrpat;
u32 save_vtotal;
@@ -707,14 +717,14 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
u8 st00;
enum drm_connector_status status;
- drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
+ drm_dbg_kms(display->drm, "starting load-detect on CRT\n");
- save_bclrpat = intel_de_read(dev_priv,
- BCLRPAT(dev_priv, cpu_transcoder));
- save_vtotal = intel_de_read(dev_priv,
- TRANS_VTOTAL(dev_priv, cpu_transcoder));
- vblank = intel_de_read(dev_priv,
- TRANS_VBLANK(dev_priv, cpu_transcoder));
+ save_bclrpat = intel_de_read(display,
+ BCLRPAT(display, cpu_transcoder));
+ save_vtotal = intel_de_read(display,
+ TRANS_VTOTAL(display, cpu_transcoder));
+ vblank = intel_de_read(display,
+ TRANS_VBLANK(display, cpu_transcoder));
vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
@@ -723,25 +733,25 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
/* Set the border color to purple. */
- intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), 0x500050);
+ intel_de_write(display, BCLRPAT(display, cpu_transcoder), 0x500050);
- if (DISPLAY_VER(dev_priv) != 2) {
- u32 transconf = intel_de_read(dev_priv,
- TRANSCONF(dev_priv, cpu_transcoder));
+ if (DISPLAY_VER(display) != 2) {
+ u32 transconf = intel_de_read(display,
+ TRANSCONF(display, cpu_transcoder));
- intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANSCONF(display, cpu_transcoder),
transconf | TRANSCONF_FORCE_BORDER);
- intel_de_posting_read(dev_priv,
- TRANSCONF(dev_priv, cpu_transcoder));
+ intel_de_posting_read(display,
+ TRANSCONF(display, cpu_transcoder));
/* Wait for next Vblank to substitue
* border color for Color info */
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
- st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
+ st00 = intel_de_read8(display, _VGA_MSR_WRITE);
status = ((st00 & (1 << 4)) != 0) ?
connector_status_connected :
connector_status_disconnected;
- intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANSCONF(display, cpu_transcoder),
transconf);
} else {
bool restore_vblank = false;
@@ -752,13 +762,13 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
* Yes, this will flicker
*/
if (vblank_start <= vactive && vblank_end >= vtotal) {
- u32 vsync = intel_de_read(dev_priv,
- TRANS_VSYNC(dev_priv, cpu_transcoder));
+ u32 vsync = intel_de_read(display,
+ TRANS_VSYNC(display, cpu_transcoder));
u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
vblank_start = vsync_start;
- intel_de_write(dev_priv,
- TRANS_VBLANK(dev_priv, cpu_transcoder),
+ intel_de_write(display,
+ TRANS_VBLANK(display, cpu_transcoder),
VBLANK_START(vblank_start - 1) |
VBLANK_END(vblank_end - 1));
restore_vblank = true;
@@ -772,9 +782,9 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
/*
* Wait for the border to be displayed
*/
- while (intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) >= vactive)
+ while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive)
;
- while ((dsl = intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe))) <= vsample)
+ while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample)
;
/*
* Watch ST00 for an entire scanline
@@ -784,15 +794,15 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
do {
count++;
/* Read the ST00 VGA status register */
- st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
+ st00 = intel_de_read8(display, _VGA_MSR_WRITE);
if (st00 & (1 << 4))
detect++;
- } while ((intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) == dsl));
+ } while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));
/* restore vblank if necessary */
if (restore_vblank)
- intel_de_write(dev_priv,
- TRANS_VBLANK(dev_priv, cpu_transcoder),
+ intel_de_write(display,
+ TRANS_VBLANK(display, cpu_transcoder),
vblank);
/*
* If more than 3/4 of the scanline detected a monitor,
@@ -806,7 +816,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
}
/* Restore previous settings */
- intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder),
+ intel_de_write(display, BCLRPAT(display, cpu_transcoder),
save_bclrpat);
return status;
@@ -843,6 +853,7 @@ intel_crt_detect(struct drm_connector *connector,
struct drm_modeset_acquire_ctx *ctx,
bool force)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
struct intel_encoder *intel_encoder = &crt->base;
@@ -850,7 +861,7 @@ intel_crt_detect(struct drm_connector *connector,
intel_wakeref_t wakeref;
int status;
- drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n",
+ drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",
connector->base.id, connector->name,
force);
@@ -860,7 +871,7 @@ intel_crt_detect(struct drm_connector *connector,
if (!intel_display_driver_check_access(dev_priv))
return connector->status;
- if (dev_priv->display.params.load_detect_test) {
+ if (display->params.load_detect_test) {
wakeref = intel_display_power_get(dev_priv,
intel_encoder->power_domain);
goto load_detect;
@@ -873,18 +884,18 @@ intel_crt_detect(struct drm_connector *connector,
wakeref = intel_display_power_get(dev_priv,
intel_encoder->power_domain);
- if (I915_HAS_HOTPLUG(dev_priv)) {
+ if (I915_HAS_HOTPLUG(display)) {
/* We can not rely on the HPD pin always being correctly wired
* up, for example many KVM do not pass it through, and so
* only trust an assertion that the monitor is connected.
*/
if (intel_crt_detect_hotplug(connector)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"CRT detected via hotplug\n");
status = connector_status_connected;
goto out;
} else
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"CRT not detected via hotplug\n");
}
@@ -897,7 +908,7 @@ intel_crt_detect(struct drm_connector *connector,
* broken monitor (without edid) to work behind a broken kvm (that fails
* to have the right resistors for HP detection) needs to fix this up.
* For now just bail out. */
- if (I915_HAS_HOTPLUG(dev_priv)) {
+ if (I915_HAS_HOTPLUG(display)) {
status = connector_status_disconnected;
goto out;
}
@@ -917,10 +928,10 @@ intel_crt_detect(struct drm_connector *connector,
} else {
if (intel_crt_detect_ddc(connector))
status = connector_status_connected;
- else if (DISPLAY_VER(dev_priv) < 4)
+ else if (DISPLAY_VER(display) < 4)
status = intel_crt_load_detect(crt,
to_intel_crtc(connector->state->crtc)->pipe);
- else if (dev_priv->display.params.load_detect_test)
+ else if (display->params.load_detect_test)
status = connector_status_disconnected;
else
status = connector_status_unknown;
@@ -966,19 +977,19 @@ static int intel_crt_get_modes(struct drm_connector *connector)
void intel_crt_reset(struct drm_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->dev);
+ struct intel_display *display = to_intel_display(encoder->dev);
struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
- if (DISPLAY_VER(dev_priv) >= 5) {
+ if (DISPLAY_VER(display) >= 5) {
u32 adpa;
- adpa = intel_de_read(dev_priv, crt->adpa_reg);
+ adpa = intel_de_read(display, crt->adpa_reg);
adpa &= ~ADPA_CRT_HOTPLUG_MASK;
adpa |= ADPA_HOTPLUG_BITS;
- intel_de_write(dev_priv, crt->adpa_reg, adpa);
- intel_de_posting_read(dev_priv, crt->adpa_reg);
+ intel_de_write(display, crt->adpa_reg, adpa);
+ intel_de_posting_read(display, crt->adpa_reg);
- drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa);
+ drm_dbg_kms(display->drm, "crt adpa set to 0x%x\n", adpa);
crt->force_hotplug_required = true;
}
@@ -1008,9 +1019,9 @@ static const struct drm_encoder_funcs intel_crt_enc_funcs = {
.destroy = intel_encoder_destroy,
};
-void intel_crt_init(struct drm_i915_private *dev_priv)
+void intel_crt_init(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct drm_connector *connector;
struct intel_crt *crt;
struct intel_connector *intel_connector;
@@ -1025,7 +1036,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
else
adpa_reg = ADPA;
- adpa = intel_de_read(dev_priv, adpa_reg);
+ adpa = intel_de_read(display, adpa_reg);
if ((adpa & ADPA_DAC_ENABLE) == 0) {
/*
* On some machines (some IVB at least) CRT can be
@@ -1035,11 +1046,11 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
* take. So the only way to tell is attempt to enable
* it and see what happens.
*/
- intel_de_write(dev_priv, adpa_reg,
+ intel_de_write(display, adpa_reg,
adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
- if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0)
+ if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0)
return;
- intel_de_write(dev_priv, adpa_reg, adpa);
+ intel_de_write(display, adpa_reg, adpa);
}
crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
@@ -1052,16 +1063,16 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
return;
}
- ddc_pin = dev_priv->display.vbt.crt_ddc_pin;
+ ddc_pin = display->vbt.crt_ddc_pin;
connector = &intel_connector->base;
crt->connector = intel_connector;
- drm_connector_init_with_ddc(&dev_priv->drm, connector,
+ drm_connector_init_with_ddc(display->drm, connector,
&intel_crt_connector_funcs,
DRM_MODE_CONNECTOR_VGA,
intel_gmbus_get_adapter(display, ddc_pin));
- drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
+ drm_encoder_init(display->drm, &crt->base.base, &intel_crt_enc_funcs,
DRM_MODE_ENCODER_DAC, "CRT");
intel_connector_attach_encoder(intel_connector, &crt->base);
@@ -1073,14 +1084,14 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
else
crt->base.pipe_mask = ~0;
- if (DISPLAY_VER(dev_priv) != 2)
+ if (DISPLAY_VER(display) != 2)
connector->interlace_allowed = true;
crt->adpa_reg = adpa_reg;
crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
- if (I915_HAS_HOTPLUG(dev_priv) &&
+ if (I915_HAS_HOTPLUG(display) &&
!dmi_check_system(intel_spurious_crt_detect)) {
crt->base.hpd_pin = HPD_CRT;
crt->base.hotplug = intel_encoder_hotplug;
@@ -1090,7 +1101,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
}
intel_connector->base.polled = intel_connector->polled;
- if (HAS_DDI(dev_priv)) {
+ if (HAS_DDI(display)) {
assert_port_valid(dev_priv, PORT_E);
crt->base.port = PORT_E;
@@ -1134,8 +1145,8 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
FDI_RX_LINK_REVERSAL_OVERRIDE;
- dev_priv->display.fdi.rx_config = intel_de_read(dev_priv,
- FDI_RX_CTL(PIPE_A)) & fdi_config;
+ display->fdi.rx_config = intel_de_read(display,
+ FDI_RX_CTL(PIPE_A)) & fdi_config;
}
intel_crt_reset(&crt->base.base);
diff --git a/drivers/gpu/drm/i915/display/intel_crt.h b/drivers/gpu/drm/i915/display/intel_crt.h
index fe7690c2b948..e0abfe96a3d2 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.h
+++ b/drivers/gpu/drm/i915/display/intel_crt.h
@@ -10,20 +10,20 @@
enum pipe;
struct drm_encoder;
-struct drm_i915_private;
+struct intel_display;
#ifdef I915
-bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
+bool intel_crt_port_enabled(struct intel_display *display,
i915_reg_t adpa_reg, enum pipe *pipe);
-void intel_crt_init(struct drm_i915_private *dev_priv);
+void intel_crt_init(struct intel_display *display);
void intel_crt_reset(struct drm_encoder *encoder);
#else
-static inline bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
+static inline bool intel_crt_port_enabled(struct intel_display *display,
i915_reg_t adpa_reg, enum pipe *pipe)
{
return false;
}
-static inline void intel_crt_init(struct drm_i915_private *dev_priv)
+static inline void intel_crt_init(struct intel_display *display)
{
}
static inline void intel_crt_reset(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 406f9981898d..7b8011781026 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8148,7 +8148,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (HAS_DDI(dev_priv)) {
if (intel_ddi_crt_present(dev_priv))
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
intel_bios_for_each_encoder(display, intel_ddi_init);
@@ -8163,7 +8163,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
* incorrect sharing of the PPS.
*/
intel_lvds_init(dev_priv);
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
@@ -8194,7 +8194,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
bool has_edp, has_port;
if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
/*
* The DP_DETECTED bit is the latched state of the DDC
@@ -8240,14 +8240,14 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
vlv_dsi_init(dev_priv);
} else if (IS_PINEVIEW(dev_priv)) {
intel_lvds_init(dev_priv);
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
} else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
bool found = false;
if (IS_MOBILE(dev_priv))
intel_lvds_init(dev_priv);
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
@@ -8289,7 +8289,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (IS_I85X(dev_priv))
intel_lvds_init(dev_priv);
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
intel_dvo_init(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 5fbcb74aeac1..4210de87a0a2 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -86,7 +86,7 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
INTEL_DISPLAY_STATE_WARN(display,
- intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) && port_pipe == pipe,
+ intel_crt_port_enabled(display, PCH_ADPA, &port_pipe) && port_pipe == pipe,
"PCH VGA enabled on transcoder %c, should be disabled\n",
pipe_name(pipe));
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [CI v2 v2 08/12] drm/i915/display: convert vlv_wait_port_ready() to struct intel_display
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (6 preceding siblings ...)
2024-10-28 20:07 ` [CI v2 v2 07/12] drm/i915/crt: " Jani Nikula
@ 2024-10-28 20:07 ` Jani Nikula
2024-10-28 20:07 ` [CI v2 v2 09/12] drm/i915/power: convert assert_chv_phy_status() " Jani Nikula
` (9 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2024-10-28 20:07 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, Rodrigo Vivi
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch vlv_wait_port_ready() over to
it. The main motivation to do just one function is to stop passing i915
to intel_de_wait(), so its generic wrapper can be removed.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/g4x_dp.c | 3 +--
drivers/gpu/drm/i915/display/g4x_hdmi.c | 9 ++++-----
drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++------
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
4 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 440fb3002f28..a22781d21110 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -706,8 +706,7 @@ static void intel_enable_dp(struct intel_atomic_state *state,
if (IS_CHERRYVIEW(dev_priv))
lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
- vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
- lane_mask);
+ vlv_wait_port_ready(display, dp_to_dig_port(intel_dp), lane_mask);
}
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 46f23bdb4c17..d1a7d0d57c6b 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -480,8 +480,8 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
vlv_phy_pre_encoder_enable(encoder, pipe_config);
@@ -496,7 +496,7 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
g4x_hdmi_enable_port(encoder, pipe_config);
- vlv_wait_port_ready(dev_priv, dig_port, 0x0);
+ vlv_wait_port_ready(display, dig_port, 0x0);
}
static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
@@ -557,9 +557,8 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
chv_phy_pre_encoder_enable(encoder, pipe_config);
@@ -573,7 +572,7 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
g4x_hdmi_enable_port(encoder, pipe_config);
- vlv_wait_port_ready(dev_priv, dig_port, 0x0);
+ vlv_wait_port_ready(display, dig_port, 0x0);
/* Second common lane will stay alive on its own now */
chv_phy_release_cl2_override(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2479ca0a02d9..53e81b0030d4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -474,7 +474,7 @@ static void assert_planes_disabled(struct intel_crtc *crtc)
assert_plane_disabled(plane);
}
-void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
+void vlv_wait_port_ready(struct intel_display *display,
struct intel_digital_port *dig_port,
unsigned int expected_mask)
{
@@ -487,11 +487,11 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
fallthrough;
case PORT_B:
port_mask = DPLL_PORTB_READY_MASK;
- dpll_reg = DPLL(dev_priv, 0);
+ dpll_reg = DPLL(display, 0);
break;
case PORT_C:
port_mask = DPLL_PORTC_READY_MASK;
- dpll_reg = DPLL(dev_priv, 0);
+ dpll_reg = DPLL(display, 0);
expected_mask <<= 4;
break;
case PORT_D:
@@ -500,11 +500,11 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
break;
}
- if (intel_de_wait(dev_priv, dpll_reg, port_mask, expected_mask, 1000))
- drm_WARN(&dev_priv->drm, 1,
+ if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000))
+ drm_WARN(display->drm, 1,
"timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
dig_port->base.base.base.id, dig_port->base.base.name,
- intel_de_read(dev_priv, dpll_reg) & port_mask,
+ intel_de_read(display, dpll_reg) & port_mask,
expected_mask);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 61e1df878de9..51fd8d109f7c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -492,7 +492,7 @@ bool intel_encoder_is_tc(struct intel_encoder *encoder);
enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);
int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
-void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
+void vlv_wait_port_ready(struct intel_display *display,
struct intel_digital_port *dig_port,
unsigned int expected_mask);
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [CI v2 v2 09/12] drm/i915/power: convert assert_chv_phy_status() to struct intel_display
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (7 preceding siblings ...)
2024-10-28 20:07 ` [CI v2 v2 08/12] drm/i915/display: convert vlv_wait_port_ready() " Jani Nikula
@ 2024-10-28 20:07 ` Jani Nikula
2024-10-28 20:07 ` [CI v2 v2 10/12] drm/i915/ips: convert " Jani Nikula
` (8 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2024-10-28 20:07 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, Rodrigo Vivi
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch assert_chv_phy_status() and its
callers to it. Main motivation to do just one function is to stop
passing i915 to intel_de_wait(), so its generic wrapper can be removed.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../i915/display/intel_display_power_well.c | 95 ++++++++++---------
1 file changed, 50 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 885bc2e563c5..f0131dd853de 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1337,13 +1337,14 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
-static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
+static void assert_chv_phy_status(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct i915_power_well *cmn_bc =
lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *cmn_d =
lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
- u32 phy_control = dev_priv->display.power.chv_phy_control;
+ u32 phy_control = display->power.chv_phy_control;
u32 phy_status = 0;
u32 phy_status_mask = 0xffffffff;
@@ -1354,7 +1355,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
* reset (ie. the power well has been disabled at
* least once).
*/
- if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0])
+ if (!display->power.chv_phy_assert[DPIO_PHY0])
phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
@@ -1362,7 +1363,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
- if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY1])
+ if (!display->power.chv_phy_assert[DPIO_PHY1])
phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
@@ -1390,7 +1391,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
*/
if (BITS_SET(phy_control,
PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
- (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & DPLL_VCO_ENABLE) == 0)
+ (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0)
phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
if (BITS_SET(phy_control,
@@ -1433,12 +1434,12 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
* The PHY may be busy with some initial calibration and whatnot,
* so the power state can take a while to actually change.
*/
- if (intel_de_wait(dev_priv, DISPLAY_PHY_STATUS,
+ if (intel_de_wait(display, DISPLAY_PHY_STATUS,
phy_status_mask, phy_status, 10))
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
- intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask,
- phy_status, dev_priv->display.power.chv_phy_control);
+ intel_de_read(display, DISPLAY_PHY_STATUS) & phy_status_mask,
+ phy_status, display->power.chv_phy_control);
}
#undef BITS_SET
@@ -1446,11 +1447,12 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
+ struct intel_display *display = &dev_priv->display;
enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
enum dpio_phy phy;
u32 tmp;
- drm_WARN_ON_ONCE(&dev_priv->drm,
+ drm_WARN_ON_ONCE(display->drm,
id != VLV_DISP_PW_DPIO_CMN_BC &&
id != CHV_DISP_PW_DPIO_CMN_D);
@@ -1464,9 +1466,9 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
vlv_set_power_well(dev_priv, power_well, true);
/* Poll for phypwrgood signal */
- if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS,
+ if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS,
PHY_POWERGOOD(phy), 1))
- drm_err(&dev_priv->drm, "Display PHY %d is not power up\n",
+ drm_err(display->drm, "Display PHY %d is not power up\n",
phy);
vlv_dpio_get(dev_priv);
@@ -1494,24 +1496,25 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
vlv_dpio_put(dev_priv);
- dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
- intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->display.power.chv_phy_control);
+ display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
+ intel_de_write(display, DISPLAY_PHY_CONTROL,
+ display->power.chv_phy_control);
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
- phy, dev_priv->display.power.chv_phy_control);
+ phy, display->power.chv_phy_control);
- assert_chv_phy_status(dev_priv);
+ assert_chv_phy_status(display);
}
static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
+ struct intel_display *display = &dev_priv->display;
enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
enum dpio_phy phy;
- drm_WARN_ON_ONCE(&dev_priv->drm,
+ drm_WARN_ON_ONCE(display->drm,
id != VLV_DISP_PW_DPIO_CMN_BC &&
id != CHV_DISP_PW_DPIO_CMN_D);
@@ -1524,20 +1527,20 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
assert_pll_disabled(dev_priv, PIPE_C);
}
- dev_priv->display.power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
- intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->display.power.chv_phy_control);
+ display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
+ intel_de_write(display, DISPLAY_PHY_CONTROL,
+ display->power.chv_phy_control);
vlv_set_power_well(dev_priv, power_well, false);
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
- phy, dev_priv->display.power.chv_phy_control);
+ phy, display->power.chv_phy_control);
/* PHY is fully reset now, so we can enable the PHY state asserts */
- dev_priv->display.power.chv_phy_assert[phy] = true;
+ display->power.chv_phy_assert[phy] = true;
- assert_chv_phy_status(dev_priv);
+ assert_chv_phy_status(display);
}
static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
@@ -1607,29 +1610,30 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
enum dpio_channel ch, bool override)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct intel_display *display = &dev_priv->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
bool was_override;
mutex_lock(&power_domains->lock);
- was_override = dev_priv->display.power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
if (override == was_override)
goto out;
if (override)
- dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
else
- dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
- intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->display.power.chv_phy_control);
+ intel_de_write(display, DISPLAY_PHY_CONTROL,
+ display->power.chv_phy_control);
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
- phy, ch, dev_priv->display.power.chv_phy_control);
+ phy, ch, display->power.chv_phy_control);
- assert_chv_phy_status(dev_priv);
+ assert_chv_phy_status(display);
out:
mutex_unlock(&power_domains->lock);
@@ -1640,29 +1644,30 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
bool override, unsigned int mask)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct i915_power_domains *power_domains = &display->power.domains;
enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
mutex_lock(&power_domains->lock);
- dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
- dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
+ display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
+ display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
if (override)
- dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
else
- dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
- intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->display.power.chv_phy_control);
+ intel_de_write(display, DISPLAY_PHY_CONTROL,
+ display->power.chv_phy_control);
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
- phy, ch, mask, dev_priv->display.power.chv_phy_control);
+ phy, ch, mask, display->power.chv_phy_control);
- assert_chv_phy_status(dev_priv);
+ assert_chv_phy_status(display);
assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [CI v2 v2 10/12] drm/i915/ips: convert to struct intel_display
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (8 preceding siblings ...)
2024-10-28 20:07 ` [CI v2 v2 09/12] drm/i915/power: convert assert_chv_phy_status() " Jani Nikula
@ 2024-10-28 20:07 ` Jani Nikula
2024-10-28 20:07 ` [CI v2 v2 11/12] drm/i915/dsi: " Jani Nikula
` (7 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2024-10-28 20:07 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, Rodrigo Vivi
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch HSW IPS code over to it.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/hsw_ips.c | 47 ++++++++++++++------------
1 file changed, 26 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index c571c6e76d4a..34c5d28fc866 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -15,6 +15,7 @@
static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
u32 val;
@@ -27,16 +28,16 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
* This function is called from post_plane_update, which is run after
* a vblank wait.
*/
- drm_WARN_ON(&i915->drm,
+ drm_WARN_ON(display->drm,
!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
val = IPS_ENABLE;
- if (i915->display.ips.false_color)
+ if (display->ips.false_color)
val |= IPS_FALSE_COLOR;
if (IS_BROADWELL(i915)) {
- drm_WARN_ON(&i915->drm,
+ drm_WARN_ON(display->drm,
snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,
val | IPS_PCODE_CONTROL));
/*
@@ -46,7 +47,7 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
* so we need to just enable it and continue on.
*/
} else {
- intel_de_write(i915, IPS_CTL, val);
+ intel_de_write(display, IPS_CTL, val);
/*
* The bit only becomes 1 in the next vblank, so this wait here
* is essentially intel_wait_for_vblank. If we don't have this
@@ -54,14 +55,15 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
* the HW state readout code will complain that the expected
* IPS_CTL value is not the one we read.
*/
- if (intel_de_wait_for_set(i915, IPS_CTL, IPS_ENABLE, 50))
- drm_err(&i915->drm,
+ if (intel_de_wait_for_set(display, IPS_CTL, IPS_ENABLE, 50))
+ drm_err(display->drm,
"Timed out waiting for IPS enable\n");
}
}
bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
bool need_vblank_wait = false;
@@ -70,19 +72,19 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
return need_vblank_wait;
if (IS_BROADWELL(i915)) {
- drm_WARN_ON(&i915->drm,
+ drm_WARN_ON(display->drm,
snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0));
/*
* Wait for PCODE to finish disabling IPS. The BSpec specified
* 42ms timeout value leads to occasional timeouts so use 100ms
* instead.
*/
- if (intel_de_wait_for_clear(i915, IPS_CTL, IPS_ENABLE, 100))
- drm_err(&i915->drm,
+ if (intel_de_wait_for_clear(display, IPS_CTL, IPS_ENABLE, 100))
+ drm_err(display->drm,
"Timed out waiting for IPS disable\n");
} else {
- intel_de_write(i915, IPS_CTL, 0);
- intel_de_posting_read(i915, IPS_CTL);
+ intel_de_write(display, IPS_CTL, 0);
+ intel_de_posting_read(display, IPS_CTL);
}
/* We need to wait for a vblank before we can disable the plane. */
@@ -188,6 +190,7 @@ bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
@@ -195,7 +198,7 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
if (!hsw_crtc_supports_ips(crtc))
return false;
- if (!i915->display.params.enable_ips)
+ if (!display->params.enable_ips)
return false;
if (crtc_state->pipe_bpp > 24)
@@ -209,7 +212,7 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
* Should measure whether using a lower cdclk w/o IPS
*/
if (IS_BROADWELL(i915) &&
- crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100)
+ crtc_state->pixel_rate > display->cdclk.max_cdclk_freq * 95 / 100)
return false;
return true;
@@ -259,6 +262,7 @@ int hsw_ips_compute_config(struct intel_atomic_state *state,
void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
@@ -266,7 +270,7 @@ void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
return;
if (IS_HASWELL(i915)) {
- crtc_state->ips_enabled = intel_de_read(i915, IPS_CTL) & IPS_ENABLE;
+ crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;
} else {
/*
* We cannot readout IPS state on broadwell, set to
@@ -280,9 +284,9 @@ void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
static int hsw_ips_debugfs_false_color_get(void *data, u64 *val)
{
struct intel_crtc *crtc = data;
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
- *val = i915->display.ips.false_color;
+ *val = display->ips.false_color;
return 0;
}
@@ -290,7 +294,7 @@ static int hsw_ips_debugfs_false_color_get(void *data, u64 *val)
static int hsw_ips_debugfs_false_color_set(void *data, u64 val)
{
struct intel_crtc *crtc = data;
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
struct intel_crtc_state *crtc_state;
int ret;
@@ -298,7 +302,7 @@ static int hsw_ips_debugfs_false_color_set(void *data, u64 val)
if (ret)
return ret;
- i915->display.ips.false_color = val;
+ display->ips.false_color = val;
crtc_state = to_intel_crtc_state(crtc->base.state);
@@ -325,18 +329,19 @@ DEFINE_DEBUGFS_ATTRIBUTE(hsw_ips_debugfs_false_color_fops,
static int hsw_ips_debugfs_status_show(struct seq_file *m, void *unused)
{
struct intel_crtc *crtc = m->private;
+ struct intel_display *display = to_intel_display(crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
intel_wakeref_t wakeref;
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
seq_printf(m, "Enabled by kernel parameter: %s\n",
- str_yes_no(i915->display.params.enable_ips));
+ str_yes_no(display->params.enable_ips));
- if (DISPLAY_VER(i915) >= 8) {
+ if (DISPLAY_VER(display) >= 8) {
seq_puts(m, "Currently: unknown\n");
} else {
- if (intel_de_read(i915, IPS_CTL) & IPS_ENABLE)
+ if (intel_de_read(display, IPS_CTL) & IPS_ENABLE)
seq_puts(m, "Currently: enabled\n");
else
seq_puts(m, "Currently: disabled\n");
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [CI v2 v2 11/12] drm/i915/dsi: convert to struct intel_display
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (9 preceding siblings ...)
2024-10-28 20:07 ` [CI v2 v2 10/12] drm/i915/ips: convert " Jani Nikula
@ 2024-10-28 20:07 ` Jani Nikula
2024-10-28 20:07 ` [CI v2 v2 12/12] drm/i915/de: remove unnecessary generic wrappers Jani Nikula
` (6 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2024-10-28 20:07 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, Rodrigo Vivi
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch ICL DSI code over to it.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 444 ++++++++++++-----------
drivers/gpu/drm/i915/display/icl_dsi.h | 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
3 files changed, 227 insertions(+), 223 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 115d79c80b9a..8a49f499e3fb 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -52,38 +52,38 @@
#include "skl_scaler.h"
#include "skl_universal_plane.h"
-static int header_credits_available(struct drm_i915_private *dev_priv,
+static int header_credits_available(struct intel_display *display,
enum transcoder dsi_trans)
{
- return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
+ return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
>> FREE_HEADER_CREDIT_SHIFT;
}
-static int payload_credits_available(struct drm_i915_private *dev_priv,
+static int payload_credits_available(struct intel_display *display,
enum transcoder dsi_trans)
{
- return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
+ return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
>> FREE_PLOAD_CREDIT_SHIFT;
}
-static bool wait_for_header_credits(struct drm_i915_private *dev_priv,
+static bool wait_for_header_credits(struct intel_display *display,
enum transcoder dsi_trans, int hdr_credit)
{
- if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
+ if (wait_for_us(header_credits_available(display, dsi_trans) >=
hdr_credit, 100)) {
- drm_err(&dev_priv->drm, "DSI header credits not released\n");
+ drm_err(display->drm, "DSI header credits not released\n");
return false;
}
return true;
}
-static bool wait_for_payload_credits(struct drm_i915_private *dev_priv,
+static bool wait_for_payload_credits(struct intel_display *display,
enum transcoder dsi_trans, int payld_credit)
{
- if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
+ if (wait_for_us(payload_credits_available(display, dsi_trans) >=
payld_credit, 100)) {
- drm_err(&dev_priv->drm, "DSI payload credits not released\n");
+ drm_err(display->drm, "DSI payload credits not released\n");
return false;
}
@@ -100,7 +100,7 @@ static enum transcoder dsi_port_to_transcoder(enum port port)
static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
struct mipi_dsi_device *dsi;
enum port port;
@@ -110,8 +110,8 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
/* wait for header/payload credits to be released */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
- wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT);
+ wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
+ wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT);
}
/* send nop DCS command */
@@ -121,22 +121,22 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
dsi->channel = 0;
ret = mipi_dsi_dcs_nop(dsi);
if (ret < 0)
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"error sending DCS NOP command\n");
}
/* wait for header credits to be released */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
+ wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
}
/* wait for LP TX in progress bit to be cleared */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
+ if (wait_for_us(!(intel_de_read(display, DSI_LP_MSG(dsi_trans)) &
LPTX_IN_PROGRESS), 20))
- drm_err(&dev_priv->drm, "LPTX bit not cleared\n");
+ drm_err(display->drm, "LPTX bit not cleared\n");
}
}
@@ -144,7 +144,7 @@ static int dsi_send_pkt_payld(struct intel_dsi_host *host,
const struct mipi_dsi_packet *packet)
{
struct intel_dsi *intel_dsi = host->intel_dsi;
- struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
+ struct intel_display *display = to_intel_display(&intel_dsi->base);
enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
const u8 *data = packet->payload;
u32 len = packet->payload_length;
@@ -152,20 +152,20 @@ static int dsi_send_pkt_payld(struct intel_dsi_host *host,
/* payload queue can accept *256 bytes*, check limit */
if (len > MAX_PLOAD_CREDIT * 4) {
- drm_err(&i915->drm, "payload size exceeds max queue limit\n");
+ drm_err(display->drm, "payload size exceeds max queue limit\n");
return -EINVAL;
}
for (i = 0; i < len; i += 4) {
u32 tmp = 0;
- if (!wait_for_payload_credits(i915, dsi_trans, 1))
+ if (!wait_for_payload_credits(display, dsi_trans, 1))
return -EBUSY;
for (j = 0; j < min_t(u32, len - i, 4); j++)
tmp |= *data++ << 8 * j;
- intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp);
+ intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp);
}
return 0;
@@ -176,14 +176,14 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
bool enable_lpdt)
{
struct intel_dsi *intel_dsi = host->intel_dsi;
- struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+ struct intel_display *display = to_intel_display(&intel_dsi->base);
enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
u32 tmp;
- if (!wait_for_header_credits(dev_priv, dsi_trans, 1))
+ if (!wait_for_header_credits(display, dsi_trans, 1))
return -EBUSY;
- tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));
+ tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans));
if (packet->payload)
tmp |= PAYLOAD_PRESENT;
@@ -202,15 +202,14 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT);
tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT);
tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT);
- intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp);
+ intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp);
return 0;
}
void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc_state);
u32 mode_flags;
enum port port;
@@ -228,12 +227,13 @@ void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
else
return;
- intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port), 0, DSI_FRAME_UPDATE_REQUEST);
+ intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0,
+ DSI_FRAME_UPDATE_REQUEST);
}
static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum phy phy;
u32 tmp, mask, val;
@@ -247,31 +247,31 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK;
val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE |
RTERM_SELECT(0x6);
- tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
+ tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
tmp &= ~mask;
tmp |= val;
- intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), mask, val);
+ intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
+ intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val);
mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
RCOMP_SCALAR_MASK;
val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) |
RCOMP_SCALAR(0x98);
- tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
+ tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
tmp &= ~mask;
tmp |= val;
- intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), mask, val);
+ intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
+ intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val);
mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
CURSOR_COEFF_MASK;
val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) |
CURSOR_COEFF(0x3f);
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), mask, val);
+ intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val);
/* Bspec: must not use GRP register for write */
for (lane = 0; lane <= 3; lane++)
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy),
+ intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
mask, val);
}
}
@@ -279,13 +279,13 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
static void configure_dual_link_mode(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
u32 dss_ctl1;
/* FIXME: Move all DSS handling to intel_vdsc.c */
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(display) >= 12) {
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
@@ -295,7 +295,7 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
dss_ctl2_reg = DSS_CTL2;
}
- dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg);
+ dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
dss_ctl1 |= SPLITTER_ENABLE;
dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
@@ -310,19 +310,19 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"DL buffer depth exceed max value\n");
dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
- intel_de_rmw(dev_priv, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
+ intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
} else {
/* Interleave */
dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
}
- intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1);
+ intel_de_write(display, dss_ctl1_reg, dss_ctl1);
}
/* aka DSI 8X clock */
@@ -343,6 +343,7 @@ static int afe_clk(struct intel_encoder *encoder,
static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
@@ -362,33 +363,34 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
}
for_each_dsi_port(port, intel_dsi->ports) {
- intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port),
+ intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port),
esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
- intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port));
+ intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port));
}
for_each_dsi_port(port, intel_dsi->ports) {
- intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port),
+ intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port),
esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
- intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port));
+ intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port));
}
if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
for_each_dsi_port(port, intel_dsi->ports) {
- intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8),
+ intel_de_write(display, ADL_MIPIO_DW(port, 8),
esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY);
- intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8));
+ intel_de_posting_read(display, ADL_MIPIO_DW(port, 8));
}
}
}
-static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
- struct intel_dsi *intel_dsi)
+static void get_dsi_io_power_domains(struct intel_dsi *intel_dsi)
{
+ struct intel_display *display = to_intel_display(&intel_dsi->base);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum port port;
for_each_dsi_port(port, intel_dsi->ports) {
- drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]);
+ drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]);
intel_dsi->io_wakeref[port] =
intel_display_power_get(dev_priv,
port == PORT_A ?
@@ -399,15 +401,15 @@ static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port),
+ intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
0, COMBO_PHY_MODE_DSI);
- get_dsi_io_power_domains(dev_priv, intel_dsi);
+ get_dsi_io_power_domains(intel_dsi);
}
static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
@@ -423,6 +425,7 @@ static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum phy phy;
@@ -431,32 +434,33 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
/* Step 4b(i) set loadgen select for transmit and aux lanes */
for_each_dsi_phy(phy, intel_dsi->phys) {
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), LOADGEN_SELECT, 0);
+ intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy),
+ LOADGEN_SELECT, 0);
for (lane = 0; lane <= 3; lane++)
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy),
+ intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0);
}
/* Step 4b(ii) set latency optimization for transmit and aux lanes */
for_each_dsi_phy(phy, intel_dsi->phys) {
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy),
+ intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy),
FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5));
- tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
+ tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
tmp &= ~FRC_LATENCY_OPTIM_MASK;
tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
- intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
+ intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) ||
- (DISPLAY_VER(dev_priv) >= 12)) {
- intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
+ (DISPLAY_VER(display) >= 12)) {
+ intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy),
LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
- tmp = intel_de_read(dev_priv,
+ tmp = intel_de_read(display,
ICL_PORT_PCS_DW1_LN(0, phy));
tmp &= ~LATENCY_OPTIM_MASK;
tmp |= LATENCY_OPTIM_VAL(0x1);
- intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
+ intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy),
tmp);
}
}
@@ -465,17 +469,17 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
u32 tmp;
enum phy phy;
/* clear common keeper enable bit */
for_each_dsi_phy(phy, intel_dsi->phys) {
- tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
+ tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
tmp &= ~COMMON_KEEPER_EN;
- intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
- intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);
+ intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp);
+ intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);
}
/*
@@ -484,14 +488,15 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
* as part of lane phy sequence configuration
*/
for_each_dsi_phy(phy, intel_dsi->phys)
- intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 0, SUS_CLOCK_CONFIG);
+ intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0,
+ SUS_CLOCK_CONFIG);
/* Clear training enable to change swing values */
for_each_dsi_phy(phy, intel_dsi->phys) {
- tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
+ tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
tmp &= ~TX_TRAINING_EN;
- intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);
+ intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
+ intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);
}
/* Program swing and de-emphasis */
@@ -499,26 +504,26 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
/* Set training enable to trigger update */
for_each_dsi_phy(phy, intel_dsi->phys) {
- tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
+ tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
tmp |= TX_TRAINING_EN;
- intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);
+ intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
+ intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);
}
}
static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
for_each_dsi_port(port, intel_dsi->ports) {
- intel_de_rmw(dev_priv, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
+ intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
- if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
+ if (wait_for_us(!(intel_de_read(display, DDI_BUF_CTL(port)) &
DDI_BUF_IS_IDLE),
500))
- drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
+ drm_err(display->drm, "DDI port:%c buffer idle\n",
port_name(port));
}
}
@@ -527,6 +532,7 @@ static void
gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
@@ -534,12 +540,12 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
/* Program DPHY clock lanes timings */
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port),
+ intel_de_write(display, DPHY_CLK_TIMING_PARAM(port),
intel_dsi->dphy_reg);
/* Program DPHY data lanes timings */
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port),
+ intel_de_write(display, DPHY_DATA_TIMING_PARAM(port),
intel_dsi->dphy_data_lane_reg);
/*
@@ -548,10 +554,10 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
* a value '0' inside TA_PARAM_REGISTERS otherwise
* leave all fields at HW default values.
*/
- if (DISPLAY_VER(dev_priv) == 11) {
+ if (DISPLAY_VER(display) == 11) {
if (afe_clk(encoder, crtc_state) <= 800000) {
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_rmw(dev_priv, DPHY_TA_TIMING_PARAM(port),
+ intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port),
TA_SURE_MASK,
TA_SURE_OVERRIDE | TA_SURE(0));
}
@@ -559,7 +565,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
for_each_dsi_phy(phy, intel_dsi->phys)
- intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
+ intel_de_rmw(display, ICL_DPHY_CHKN(phy),
0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
}
}
@@ -568,30 +574,30 @@ static void
gen11_dsi_setup_timings(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
/* Program T-INIT master registers */
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_rmw(dev_priv, ICL_DSI_T_INIT_MASTER(port),
+ intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port),
DSI_T_INIT_MASTER_MASK, intel_dsi->init_count);
/* shadow register inside display core */
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port),
+ intel_de_write(display, DSI_CLK_TIMING_PARAM(port),
intel_dsi->dphy_reg);
/* shadow register inside display core */
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port),
+ intel_de_write(display, DSI_DATA_TIMING_PARAM(port),
intel_dsi->dphy_data_lane_reg);
/* shadow register inside display core */
- if (DISPLAY_VER(dev_priv) == 11) {
+ if (DISPLAY_VER(display) == 11) {
if (afe_clk(encoder, crtc_state) <= 800000) {
for_each_dsi_port(port, intel_dsi->ports) {
- intel_de_rmw(dev_priv, DSI_TA_TIMING_PARAM(port),
+ intel_de_rmw(display, DSI_TA_TIMING_PARAM(port),
TA_SURE_MASK,
TA_SURE_OVERRIDE | TA_SURE(0));
}
@@ -601,45 +607,45 @@ gen11_dsi_setup_timings(struct intel_encoder *encoder,
static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
u32 tmp;
enum phy phy;
- mutex_lock(&dev_priv->display.dpll.lock);
- tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ mutex_lock(&display->dpll.lock);
+ tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys)
tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
- mutex_unlock(&dev_priv->display.dpll.lock);
+ intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
+ mutex_unlock(&display->dpll.lock);
}
static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
u32 tmp;
enum phy phy;
- mutex_lock(&dev_priv->display.dpll.lock);
- tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ mutex_lock(&display->dpll.lock);
+ tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys)
tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
- mutex_unlock(&dev_priv->display.dpll.lock);
+ intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
+ mutex_unlock(&display->dpll.lock);
}
static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
bool clock_enabled = false;
enum phy phy;
u32 tmp;
- tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys) {
if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))
@@ -652,36 +658,36 @@ static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
static void gen11_dsi_map_pll(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum phy phy;
u32 val;
- mutex_lock(&dev_priv->display.dpll.lock);
+ mutex_lock(&display->dpll.lock);
- val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ val = intel_de_read(display, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys) {
val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
}
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+ intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
for_each_dsi_phy(phy, intel_dsi->phys) {
val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
}
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+ intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
- intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ intel_de_posting_read(display, ICL_DPCLKA_CFGCR0);
- mutex_unlock(&dev_priv->display.dpll.lock);
+ mutex_unlock(&display->dpll.lock);
}
static void
gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
enum pipe pipe = crtc->pipe;
@@ -691,7 +697,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
+ tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
if (intel_dsi->eotp_pkt)
tmp &= ~EOTP_DISABLED;
@@ -747,7 +753,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
}
}
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(display) >= 12) {
if (is_vid_mode(intel_dsi))
tmp |= BLANKING_PACKET_ENABLE;
}
@@ -780,15 +786,15 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
tmp |= TE_SOURCE_GPIO;
}
- intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
+ intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
}
/* enable port sync mode if dual link */
if (intel_dsi->dual_link) {
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_rmw(dev_priv,
- TRANS_DDI_FUNC_CTL2(dev_priv, dsi_trans),
+ intel_de_rmw(display,
+ TRANS_DDI_FUNC_CTL2(display, dsi_trans),
0, PORT_SYNC_MODE_ENABLE);
}
@@ -800,8 +806,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
dsi_trans = dsi_port_to_transcoder(port);
/* select data lane width */
- tmp = intel_de_read(dev_priv,
- TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
+ tmp = intel_de_read(display,
+ TRANS_DDI_FUNC_CTL(display, dsi_trans));
tmp &= ~DDI_PORT_WIDTH_MASK;
tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
@@ -827,16 +833,16 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
/* enable DDI buffer */
tmp |= TRANS_DDI_FUNC_ENABLE;
- intel_de_write(dev_priv,
- TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans), tmp);
+ intel_de_write(display,
+ TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp);
}
/* wait for link ready */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) &
+ if (wait_for_us((intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)) &
LINK_READY), 2500))
- drm_err(&dev_priv->drm, "DSI link not ready\n");
+ drm_err(display->drm, "DSI link not ready\n");
}
}
@@ -844,7 +850,7 @@ static void
gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
@@ -911,17 +917,17 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
/* minimum hactive as per bspec: 256 pixels */
if (adjusted_mode->crtc_hdisplay < 256)
- drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n");
+ drm_err(display->drm, "hactive is less then 256 pixels\n");
/* if RGB666 format, then hactive must be multiple of 4 pixels */
if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"hactive pixels are not multiple of 4\n");
/* program TRANS_HTOTAL register */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, dsi_trans),
+ intel_de_write(display, TRANS_HTOTAL(display, dsi_trans),
HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
}
@@ -930,12 +936,12 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) {
/* BSPEC: hsync size should be atleast 16 pixels */
if (hsync_size < 16)
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"hsync size < 16 pixels\n");
}
if (hback_porch < 16)
- drm_err(&dev_priv->drm, "hback porch < 16 pixels\n");
+ drm_err(display->drm, "hback porch < 16 pixels\n");
if (intel_dsi->dual_link) {
hsync_start /= 2;
@@ -944,8 +950,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv,
- TRANS_HSYNC(dev_priv, dsi_trans),
+ intel_de_write(display,
+ TRANS_HSYNC(display, dsi_trans),
HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
}
}
@@ -959,22 +965,22 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
* struct drm_display_mode.
* For interlace mode: program required pixel minus 2
*/
- intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, dsi_trans),
+ intel_de_write(display, TRANS_VTOTAL(display, dsi_trans),
VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
}
if (vsync_end < vsync_start || vsync_end > vtotal)
- drm_err(&dev_priv->drm, "Invalid vsync_end value\n");
+ drm_err(display->drm, "Invalid vsync_end value\n");
if (vsync_start < vactive)
- drm_err(&dev_priv->drm, "vsync_start less than vactive\n");
+ drm_err(display->drm, "vsync_start less than vactive\n");
/* program TRANS_VSYNC register for video mode only */
if (is_vid_mode(intel_dsi)) {
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv,
- TRANS_VSYNC(dev_priv, dsi_trans),
+ intel_de_write(display,
+ TRANS_VSYNC(display, dsi_trans),
VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1));
}
}
@@ -988,8 +994,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
if (is_vid_mode(intel_dsi)) {
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv,
- TRANS_VSYNCSHIFT(dev_priv, dsi_trans),
+ intel_de_write(display,
+ TRANS_VSYNCSHIFT(display, dsi_trans),
vsync_shift);
}
}
@@ -1000,11 +1006,11 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
* FIXME get rid of these local hacks and do it right,
* this will not handle eg. delayed vblank correctly.
*/
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(display) >= 12) {
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv,
- TRANS_VBLANK(dev_priv, dsi_trans),
+ intel_de_write(display,
+ TRANS_VBLANK(display, dsi_trans),
VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
}
}
@@ -1012,20 +1018,20 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
enum transcoder dsi_trans;
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans), 0,
+ intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0,
TRANSCONF_ENABLE);
/* wait for transcoder to be enabled */
- if (intel_de_wait_for_set(dev_priv, TRANSCONF(dev_priv, dsi_trans),
+ if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans),
TRANSCONF_STATE_ENABLE, 10))
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"DSI transcoder not enabled\n");
}
}
@@ -1033,7 +1039,7 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
enum transcoder dsi_trans;
@@ -1057,21 +1063,21 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
dsi_trans = dsi_port_to_transcoder(port);
/* program hst_tx_timeout */
- intel_de_rmw(dev_priv, DSI_HSTX_TO(dsi_trans),
+ intel_de_rmw(display, DSI_HSTX_TO(dsi_trans),
HSTX_TIMEOUT_VALUE_MASK,
HSTX_TIMEOUT_VALUE(hs_tx_timeout));
/* FIXME: DSI_CALIB_TO */
/* program lp_rx_host timeout */
- intel_de_rmw(dev_priv, DSI_LPRX_HOST_TO(dsi_trans),
+ intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans),
LPRX_TIMEOUT_VALUE_MASK,
LPRX_TIMEOUT_VALUE(lp_rx_timeout));
/* FIXME: DSI_PWAIT_TO */
/* program turn around timeout */
- intel_de_rmw(dev_priv, DSI_TA_TO(dsi_trans),
+ intel_de_rmw(display, DSI_TA_TO(dsi_trans),
TA_TIMEOUT_VALUE_MASK,
TA_TIMEOUT_VALUE(ta_timeout));
}
@@ -1080,7 +1086,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
bool enable)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
u32 tmp;
@@ -1092,7 +1098,7 @@ static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
return;
- tmp = intel_de_read(dev_priv, UTIL_PIN_CTL);
+ tmp = intel_de_read(display, UTIL_PIN_CTL);
if (enable) {
tmp |= UTIL_PIN_DIRECTION_INPUT;
@@ -1100,7 +1106,7 @@ static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
} else {
tmp &= ~UTIL_PIN_ENABLE;
}
- intel_de_write(dev_priv, UTIL_PIN_CTL, tmp);
+ intel_de_write(display, UTIL_PIN_CTL, tmp);
}
static void
@@ -1138,7 +1144,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
struct mipi_dsi_device *dsi;
enum port port;
@@ -1154,14 +1160,14 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
* FIXME: This uses the number of DW's currently in the payload
* receive queue. This is probably not what we want here.
*/
- tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans));
+ tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans));
tmp &= NUMBER_RX_PLOAD_DW_MASK;
/* multiply "Number Rx Payload DW" by 4 to get max value */
tmp = tmp * 4;
dsi = intel_dsi->dsi_hosts[port]->device;
ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
if (ret < 0)
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"error setting max return pkt size%d\n", tmp);
}
@@ -1221,10 +1227,10 @@ static void gen11_dsi_pre_enable(struct intel_atomic_state *state,
static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,
enum pipe pipe, bool enable)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B)
- intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
+ if (DISPLAY_VER(display) == 11 && pipe == PIPE_B)
+ intel_de_rmw(display, CHICKEN_PAR1_1,
IGNORE_KVMR_PIPE_A,
enable ? IGNORE_KVMR_PIPE_A : 0);
}
@@ -1237,13 +1243,13 @@ static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,
*/
static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
- if (DISPLAY_VER(i915) == 13) {
+ if (DISPLAY_VER(display) == 13) {
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
+ intel_de_rmw(display, TGL_DSI_CHKN_REG(port),
TGL_DSI_CHKN_LSHS_GB_MASK,
TGL_DSI_CHKN_LSHS_GB(4));
}
@@ -1277,7 +1283,7 @@ static void gen11_dsi_enable(struct intel_atomic_state *state,
static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
enum transcoder dsi_trans;
@@ -1286,13 +1292,13 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
dsi_trans = dsi_port_to_transcoder(port);
/* disable transcoder */
- intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans),
+ intel_de_rmw(display, TRANSCONF(display, dsi_trans),
TRANSCONF_ENABLE, 0);
/* wait for transcoder to be disabled */
- if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, dsi_trans),
+ if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans),
TRANSCONF_STATE_ENABLE, 50))
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"DSI trancoder not disabled\n");
}
}
@@ -1309,7 +1315,7 @@ static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
enum transcoder dsi_trans;
@@ -1318,29 +1324,29 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
/* disable periodic update mode */
if (is_cmd_mode(intel_dsi)) {
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port),
+ intel_de_rmw(display, DSI_CMD_FRMCTL(port),
DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0);
}
/* put dsi link in ULPS */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans));
+ tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans));
tmp |= LINK_ENTER_ULPS;
tmp &= ~LINK_ULPS_TYPE_LP11;
- intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp);
+ intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
- if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
+ if (wait_for_us((intel_de_read(display, DSI_LP_MSG(dsi_trans)) &
LINK_IN_ULPS),
10))
- drm_err(&dev_priv->drm, "DSI link not in ULPS\n");
+ drm_err(display->drm, "DSI link not in ULPS\n");
}
/* disable ddi function */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_rmw(dev_priv,
- TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans),
+ intel_de_rmw(display,
+ TRANS_DDI_FUNC_CTL(display, dsi_trans),
TRANS_DDI_FUNC_ENABLE, 0);
}
@@ -1348,8 +1354,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
if (intel_dsi->dual_link) {
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_rmw(dev_priv,
- TRANS_DDI_FUNC_CTL2(dev_priv, dsi_trans),
+ intel_de_rmw(display,
+ TRANS_DDI_FUNC_CTL2(display, dsi_trans),
PORT_SYNC_MODE_ENABLE, 0);
}
}
@@ -1357,18 +1363,18 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
static void gen11_dsi_disable_port(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
gen11_dsi_ungate_clocks(encoder);
for_each_dsi_port(port, intel_dsi->ports) {
- intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
+ intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
- if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
+ if (wait_for_us((intel_de_read(display, DDI_BUF_CTL(port)) &
DDI_BUF_IS_IDLE),
8))
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"DDI port:%c buffer not idle\n",
port_name(port));
}
@@ -1377,6 +1383,7 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder)
static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
@@ -1394,7 +1401,7 @@ static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
/* set mode to DDI */
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port),
+ intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
COMBO_PHY_MODE_DSI, 0);
}
@@ -1506,8 +1513,7 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
{
- struct drm_device *dev = intel_dsi->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_display *display = to_intel_display(&intel_dsi->base);
enum transcoder dsi_trans;
u32 val;
@@ -1516,7 +1522,7 @@ static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
else
dsi_trans = TRANSCODER_DSI_0;
- val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
+ val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
}
@@ -1559,7 +1565,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
static void gen11_dsi_sync_state(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_crtc *intel_crtc;
enum pipe pipe;
@@ -1570,9 +1576,9 @@ static void gen11_dsi_sync_state(struct intel_encoder *encoder,
pipe = intel_crtc->pipe;
/* wa verify 1409054076:icl,jsl,ehl */
- if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B &&
- !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
- drm_dbg_kms(&dev_priv->drm,
+ if (DISPLAY_VER(display) == 11 && pipe == PIPE_B &&
+ !(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
+ drm_dbg_kms(display->drm,
"[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n",
encoder->base.base.id,
encoder->base.name);
@@ -1581,9 +1587,9 @@ static void gen11_dsi_sync_state(struct intel_encoder *encoder,
static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
- int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10;
+ int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10;
bool use_dsc;
int ret;
@@ -1608,12 +1614,12 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
return ret;
/* DSI specific sanity checks on the common code */
- drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable);
- drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422);
- drm_WARN_ON(&dev_priv->drm,
+ drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable);
+ drm_WARN_ON(display->drm, vdsc_cfg->simple_422);
+ drm_WARN_ON(display->drm,
vdsc_cfg->pic_width % vdsc_cfg->slice_width);
- drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8);
- drm_WARN_ON(&dev_priv->drm,
+ drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8);
+ drm_WARN_ON(display->drm,
vdsc_cfg->pic_height % vdsc_cfg->slice_height);
ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
@@ -1629,7 +1635,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
struct intel_connector *intel_connector = intel_dsi->attached_connector;
struct drm_display_mode *adjusted_mode =
@@ -1663,7 +1669,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
pipe_config->clock_set = true;
if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
- drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n");
+ drm_dbg_kms(display->drm, "Attempting to use DSC failed\n");
pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
@@ -1681,15 +1687,13 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-
- get_dsi_io_power_domains(i915,
- enc_to_intel_dsi(encoder));
+ get_dsi_io_power_domains(enc_to_intel_dsi(encoder));
}
static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum transcoder dsi_trans;
@@ -1705,8 +1709,8 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- tmp = intel_de_read(dev_priv,
- TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
+ tmp = intel_de_read(display,
+ TRANS_DDI_FUNC_CTL(display, dsi_trans));
switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
case TRANS_DDI_EDP_INPUT_A_ON:
*pipe = PIPE_A;
@@ -1721,11 +1725,11 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
*pipe = PIPE_D;
break;
default:
- drm_err(&dev_priv->drm, "Invalid PIPE input\n");
+ drm_err(display->drm, "Invalid PIPE input\n");
goto out;
}
- tmp = intel_de_read(dev_priv, TRANSCONF(dev_priv, dsi_trans));
+ tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));
ret = tmp & TRANSCONF_ENABLE;
}
out:
@@ -1835,8 +1839,7 @@ static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
{
- struct drm_device *dev = intel_dsi->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_display *display = to_intel_display(&intel_dsi->base);
struct intel_connector *connector = intel_dsi->attached_connector;
struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
u32 tlpx_ns;
@@ -1860,7 +1863,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
*/
prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
- drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n",
+ drm_dbg_kms(display->drm, "prepare_cnt out of range (%d)\n",
prepare_cnt);
prepare_cnt = ICL_PREPARE_CNT_MAX;
}
@@ -1869,7 +1872,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
ths_prepare_ns, tlpx_ns);
if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
}
@@ -1877,7 +1880,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
/* trail cnt in escape clocks*/
trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
if (trail_cnt > ICL_TRAIL_CNT_MAX) {
- drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n",
+ drm_dbg_kms(display->drm, "trail_cnt out of range (%d)\n",
trail_cnt);
trail_cnt = ICL_TRAIL_CNT_MAX;
}
@@ -1885,7 +1888,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
/* tclk pre count in escape clocks */
tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
}
@@ -1894,7 +1897,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
ths_prepare_ns, tlpx_ns);
if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
- drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n",
+ drm_dbg_kms(display->drm, "hs_zero_cnt out of range (%d)\n",
hs_zero_cnt);
hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
}
@@ -1902,7 +1905,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
/* hs exit zero cnt in escape clocks */
exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"exit_zero_cnt out of range (%d)\n",
exit_zero_cnt);
exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
@@ -1944,10 +1947,9 @@ static void icl_dsi_add_properties(struct intel_connector *connector)
fixed_mode->vdisplay);
}
-void icl_dsi_init(struct drm_i915_private *dev_priv,
+void icl_dsi_init(struct intel_display *display,
const struct intel_bios_encoder_data *devdata)
{
- struct intel_display *display = &dev_priv->display;
struct intel_dsi *intel_dsi;
struct intel_encoder *encoder;
struct intel_connector *intel_connector;
@@ -1975,7 +1977,8 @@ void icl_dsi_init(struct drm_i915_private *dev_priv,
encoder->devdata = devdata;
/* register DSI encoder with DRM subsystem */
- drm_encoder_init(&dev_priv->drm, &encoder->base, &gen11_dsi_encoder_funcs,
+ drm_encoder_init(display->drm, &encoder->base,
+ &gen11_dsi_encoder_funcs,
DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
@@ -2000,7 +2003,8 @@ void icl_dsi_init(struct drm_i915_private *dev_priv,
encoder->shutdown = intel_dsi_shutdown;
/* register DSI connector with DRM subsystem */
- drm_connector_init(&dev_priv->drm, connector, &gen11_dsi_connector_funcs,
+ drm_connector_init(display->drm, connector,
+ &gen11_dsi_connector_funcs,
DRM_MODE_CONNECTOR_DSI);
drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
@@ -2013,12 +2017,12 @@ void icl_dsi_init(struct drm_i915_private *dev_priv,
intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL);
- mutex_lock(&dev_priv->drm.mode_config.mutex);
+ mutex_lock(&display->drm->mode_config.mutex);
intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
- mutex_unlock(&dev_priv->drm.mode_config.mutex);
+ mutex_unlock(&display->drm->mode_config.mutex);
if (!intel_panel_preferred_fixed_mode(intel_connector)) {
- drm_err(&dev_priv->drm, "DSI fixed mode info missing\n");
+ drm_err(display->drm, "DSI fixed mode info missing\n");
goto err;
}
@@ -2031,10 +2035,10 @@ void icl_dsi_init(struct drm_i915_private *dev_priv,
else
intel_dsi->ports = BIT(port);
- if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
+ if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
- if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
+ if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
for_each_dsi_port(port, intel_dsi->ports) {
@@ -2048,7 +2052,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv,
}
if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
- drm_dbg_kms(&dev_priv->drm, "no device found\n");
+ drm_dbg_kms(display->drm, "no device found\n");
goto err;
}
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.h b/drivers/gpu/drm/i915/display/icl_dsi.h
index 43fa7d72eeb1..099fc50e35b4 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.h
+++ b/drivers/gpu/drm/i915/display/icl_dsi.h
@@ -6,11 +6,11 @@
#ifndef __ICL_DSI_H__
#define __ICL_DSI_H__
-struct drm_i915_private;
struct intel_bios_encoder_data;
struct intel_crtc_state;
+struct intel_display;
-void icl_dsi_init(struct drm_i915_private *dev_priv,
+void icl_dsi_init(struct intel_display *display,
const struct intel_bios_encoder_data *devdata);
void icl_dsi_frame_update(struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ff4c633c8546..2bd14e2134be 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4885,7 +4885,7 @@ void intel_ddi_init(struct intel_display *display,
if (!assert_has_icl_dsi(dev_priv))
return;
- icl_dsi_init(dev_priv, devdata);
+ icl_dsi_init(display, devdata);
return;
}
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [CI v2 v2 12/12] drm/i915/de: remove unnecessary generic wrappers
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (10 preceding siblings ...)
2024-10-28 20:07 ` [CI v2 v2 11/12] drm/i915/dsi: " Jani Nikula
@ 2024-10-28 20:07 ` Jani Nikula
2024-10-29 23:22 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: bunch of struct intel_display conversions (rev6) Patchwork
` (5 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2024-10-28 20:07 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, Rodrigo Vivi
With many of the intel_de_* callers switched over to struct
intel_display, we can remove some of the unnecessary generic wrappers.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_de.h | 46 ++++++++++---------------
1 file changed, 18 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index e017cd4a8168..bb51f974e9e2 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -32,7 +32,7 @@ __intel_de_read(struct intel_display *display, i915_reg_t reg)
#define intel_de_read(p,...) __intel_de_read(__to_intel_display(p), __VA_ARGS__)
static inline u8
-__intel_de_read8(struct intel_display *display, i915_reg_t reg)
+intel_de_read8(struct intel_display *display, i915_reg_t reg)
{
u8 val;
@@ -44,11 +44,10 @@ __intel_de_read8(struct intel_display *display, i915_reg_t reg)
return val;
}
-#define intel_de_read8(p,...) __intel_de_read8(__to_intel_display(p), __VA_ARGS__)
static inline u64
-__intel_de_read64_2x32(struct intel_display *display,
- i915_reg_t lower_reg, i915_reg_t upper_reg)
+intel_de_read64_2x32(struct intel_display *display,
+ i915_reg_t lower_reg, i915_reg_t upper_reg)
{
u64 val;
@@ -63,7 +62,6 @@ __intel_de_read64_2x32(struct intel_display *display,
return val;
}
-#define intel_de_read64_2x32(p,...) __intel_de_read64_2x32(__to_intel_display(p), __VA_ARGS__)
static inline void
__intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
@@ -88,12 +86,11 @@ __intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
#define intel_de_write(p,...) __intel_de_write(__to_intel_display(p), __VA_ARGS__)
static inline u32
-____intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,
- u32 clear, u32 set)
+__intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,
+ u32 clear, u32 set)
{
return intel_uncore_rmw(__to_uncore(display), reg, clear, set);
}
-#define __intel_de_rmw_nowl(p,...) ____intel_de_rmw_nowl(__to_intel_display(p), __VA_ARGS__)
static inline u32
__intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear,
@@ -112,18 +109,17 @@ __intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear,
#define intel_de_rmw(p,...) __intel_de_rmw(__to_intel_display(p), __VA_ARGS__)
static inline int
-____intel_de_wait_for_register_nowl(struct intel_display *display,
- i915_reg_t reg,
- u32 mask, u32 value, unsigned int timeout)
+__intel_de_wait_for_register_nowl(struct intel_display *display,
+ i915_reg_t reg,
+ u32 mask, u32 value, unsigned int timeout)
{
return intel_wait_for_register(__to_uncore(display), reg, mask,
value, timeout);
}
-#define __intel_de_wait_for_register_nowl(p,...) ____intel_de_wait_for_register_nowl(__to_intel_display(p), __VA_ARGS__)
static inline int
-__intel_de_wait(struct intel_display *display, i915_reg_t reg,
- u32 mask, u32 value, unsigned int timeout)
+intel_de_wait(struct intel_display *display, i915_reg_t reg,
+ u32 mask, u32 value, unsigned int timeout)
{
int ret;
@@ -136,11 +132,10 @@ __intel_de_wait(struct intel_display *display, i915_reg_t reg,
return ret;
}
-#define intel_de_wait(p,...) __intel_de_wait(__to_intel_display(p), __VA_ARGS__)
static inline int
-__intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
- u32 mask, u32 value, unsigned int timeout)
+intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
+ u32 mask, u32 value, unsigned int timeout)
{
int ret;
@@ -153,13 +148,12 @@ __intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
return ret;
}
-#define intel_de_wait_fw(p,...) __intel_de_wait_fw(__to_intel_display(p), __VA_ARGS__)
static inline int
-__intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
- u32 mask, u32 value,
- unsigned int fast_timeout_us,
- unsigned int slow_timeout_ms, u32 *out_value)
+intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
+ u32 mask, u32 value,
+ unsigned int fast_timeout_us,
+ unsigned int slow_timeout_ms, u32 *out_value)
{
int ret;
@@ -173,7 +167,6 @@ __intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
return ret;
}
-#define intel_de_wait_custom(p,...) __intel_de_wait_custom(__to_intel_display(p), __VA_ARGS__)
static inline int
__intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,
@@ -220,19 +213,16 @@ __intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)
#define intel_de_write_fw(p,...) __intel_de_write_fw(__to_intel_display(p), __VA_ARGS__)
static inline u32
-__intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
+intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
{
return intel_uncore_read_notrace(__to_uncore(display), reg);
}
-#define intel_de_read_notrace(p,...) __intel_de_read_notrace(__to_intel_display(p), __VA_ARGS__)
static inline void
-__intel_de_write_notrace(struct intel_display *display, i915_reg_t reg,
- u32 val)
+intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val)
{
intel_uncore_write_notrace(__to_uncore(display), reg, val);
}
-#define intel_de_write_notrace(p,...) __intel_de_write_notrace(__to_intel_display(p), __VA_ARGS__)
static __always_inline void
intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb,
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: bunch of struct intel_display conversions (rev6)
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (11 preceding siblings ...)
2024-10-28 20:07 ` [CI v2 v2 12/12] drm/i915/de: remove unnecessary generic wrappers Jani Nikula
@ 2024-10-29 23:22 ` Patchwork
2024-10-29 23:22 ` ✗ Fi.CI.SPARSE: " Patchwork
` (4 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2024-10-29 23:22 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: bunch of struct intel_display conversions (rev6)
URL : https://patchwork.freedesktop.org/series/140324/
State : warning
== Summary ==
Error: dim checkpatch failed
ad128789ff31 drm/i915/gmbus: convert to struct intel_display
c7142960f3a5 drm/i915/cx0: remove unnecessary includes
df827e9677c3 drm/i915/cx0: convert to struct intel_display
-:463: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#463: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2436:
+ PHY_C20_B_MPLLB_CNTX_CFG(display, i));
-:468: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#468: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2440:
+ PHY_C20_A_MPLLB_CNTX_CFG(display, i));
-:477: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#477: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2448:
+ PHY_C20_B_MPLLA_CNTX_CFG(display, i));
-:482: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#482: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2452:
+ PHY_C20_A_MPLLA_CNTX_CFG(display, i));
-:639: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#639: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2799:
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
total: 0 errors, 5 warnings, 0 checks, 1002 lines checked
52d79f2979c0 drm/i915/dpio: convert to struct intel_display
-:565: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#565: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:84:
}
+static inline void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
-:569: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#569: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:87:
}
+static inline void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)
-:573: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#573: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:90:
}
+static inline bool bxt_dpio_phy_is_enabled(struct intel_display *display,
-:579: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#579: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:95:
}
+static inline bool bxt_dpio_phy_verify_state(struct intel_display *display,
total: 0 errors, 0 warnings, 4 checks, 570 lines checked
293faf775a6e drm/i915/hdcp: further conversion to struct intel_display
2c36b8e22ec1 drm/i915/dp/hdcp: convert to struct intel_display
43f7b275058c drm/i915/crt: convert to struct intel_display
-:220: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#220: FILE: drivers/gpu/drm/i915/display/intel_crt.c:497:
+ save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
-:274: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#274: FILE: drivers/gpu/drm/i915/display/intel_crt.c:557:
+ save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
-:706: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#706: FILE: drivers/gpu/drm/i915/display/intel_crt.h:26:
}
+static inline void intel_crt_init(struct intel_display *display)
-:776: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#776: FILE: drivers/gpu/drm/i915/display/intel_pch_display.c:89:
+ intel_crt_port_enabled(display, PCH_ADPA, &port_pipe) && port_pipe == pipe,
total: 0 errors, 1 warnings, 3 checks, 697 lines checked
a0f1db2be274 drm/i915/display: convert vlv_wait_port_ready() to struct intel_display
12892fe486da drm/i915/power: convert assert_chv_phy_status() to struct intel_display
4ec3133642a3 drm/i915/ips: convert to struct intel_display
4bfc289ec3b3 drm/i915/dsi: convert to struct intel_display
-:1366: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#1366: FILE: drivers/gpu/drm/i915/display/icl_dsi.c:2041:
+ if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
total: 0 errors, 1 warnings, 0 checks, 1302 lines checked
a594d4aa014e drm/i915/de: remove unnecessary generic wrappers
^ permalink raw reply [flat|nested] 22+ messages in thread* ✗ Fi.CI.SPARSE: warning for drm/i915/display: bunch of struct intel_display conversions (rev6)
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (12 preceding siblings ...)
2024-10-29 23:22 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: bunch of struct intel_display conversions (rev6) Patchwork
@ 2024-10-29 23:22 ` Patchwork
2024-10-29 23:22 ` ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2024-10-29 23:22 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: bunch of struct intel_display conversions (rev6)
URL : https://patchwork.freedesktop.org/series/140324/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 22+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915/display: bunch of struct intel_display conversions (rev6)
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (13 preceding siblings ...)
2024-10-29 23:22 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2024-10-29 23:22 ` Patchwork
2024-10-30 12:16 ` [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (2 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2024-10-29 23:22 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 2826 bytes --]
== Series Details ==
Series: drm/i915/display: bunch of struct intel_display conversions (rev6)
URL : https://patchwork.freedesktop.org/series/140324/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15607 -> Patchwork_140324v6
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/index.html
Participating hosts (47 -> 46)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_140324v6 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_chamelium_edid@hdmi-edid-read:
- bat-dg2-13: [PASS][1] -> [DMESG-WARN][2] ([i915#12253])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/bat-dg2-13/igt@kms_chamelium_edid@hdmi-edid-read.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/bat-dg2-13/igt@kms_chamelium_edid@hdmi-edid-read.html
#### Possible fixes ####
* igt@i915_selftest@live:
- bat-arls-1: [ABORT][3] ([i915#12133]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/bat-arls-1/igt@i915_selftest@live.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/bat-arls-1/igt@i915_selftest@live.html
* igt@i915_selftest@live@workarounds:
- bat-arls-1: [ABORT][5] ([i915#12061]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/bat-arls-1/igt@i915_selftest@live@workarounds.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/bat-arls-1/igt@i915_selftest@live@workarounds.html
* igt@kms_chamelium_frames@dp-crc-fast:
- bat-dg2-13: [DMESG-WARN][7] ([i915#12253]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/bat-dg2-13/igt@kms_chamelium_frames@dp-crc-fast.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/bat-dg2-13/igt@kms_chamelium_frames@dp-crc-fast.html
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12133]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12133
[i915#12253]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12253
Build changes
-------------
* Linux: CI_DRM_15607 -> Patchwork_140324v6
CI-20190529: 20190529
CI_DRM_15607: fb2691707e2d5a8c704ae5e48bc5a314a308b0e0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8087: 7abd9c49a49a9ff1f3300d7c51a92a5af8a789f1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_140324v6: fb2691707e2d5a8c704ae5e48bc5a314a308b0e0 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/index.html
[-- Attachment #2: Type: text/html, Size: 3579 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (14 preceding siblings ...)
2024-10-29 23:22 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2024-10-30 12:16 ` Jani Nikula
2024-10-30 22:42 ` ✓ Fi.CI.IGT: success for drm/i915/display: bunch of struct intel_display conversions (rev6) Patchwork
2024-10-30 22:49 ` Patchwork
17 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2024-10-30 12:16 UTC (permalink / raw)
To: intel-gfx, intel-xe
On Mon, 28 Oct 2024, Jani Nikula <jani.nikula@intel.com> wrote:
> Just resending [1] because I never got the CI logs for it.
And pushed to din, thanks for the review.
BR,
Jani.
>
> [1] https://lore.kernel.org/r/cover.1729776384.git.jani.nikula@intel.com
>
> Jani Nikula (12):
> drm/i915/gmbus: convert to struct intel_display
> drm/i915/cx0: remove unnecessary includes
> drm/i915/cx0: convert to struct intel_display
> drm/i915/dpio: convert to struct intel_display
> drm/i915/hdcp: further conversion to struct intel_display
> drm/i915/dp/hdcp: convert to struct intel_display
> drm/i915/crt: convert to struct intel_display
> drm/i915/display: convert vlv_wait_port_ready() to struct
> intel_display
> drm/i915/power: convert assert_chv_phy_status() to struct
> intel_display
> drm/i915/ips: convert to struct intel_display
> drm/i915/dsi: convert to struct intel_display
> drm/i915/de: remove unnecessary generic wrappers
>
> drivers/gpu/drm/i915/display/g4x_dp.c | 3 +-
> drivers/gpu/drm/i915/display/g4x_hdmi.c | 9 +-
> drivers/gpu/drm/i915/display/hsw_ips.c | 47 +-
> drivers/gpu/drm/i915/display/icl_dsi.c | 444 +++++++++---------
> drivers/gpu/drm/i915/display/icl_dsi.h | 4 +-
> drivers/gpu/drm/i915/display/intel_bios.c | 6 +-
> drivers/gpu/drm/i915/display/intel_crt.c | 213 +++++----
> drivers/gpu/drm/i915/display/intel_crt.h | 10 +-
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 334 +++++++------
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_de.h | 46 +-
> drivers/gpu/drm/i915/display/intel_display.c | 30 +-
> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
> .../drm/i915/display/intel_display_driver.c | 11 +-
> .../gpu/drm/i915/display/intel_display_irq.c | 11 +-
> .../i915/display/intel_display_power_well.c | 114 +++--
> drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 93 ++--
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 158 +++----
> drivers/gpu/drm/i915/display/intel_dpio_phy.h | 22 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 +-
> drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 5 +-
> drivers/gpu/drm/i915/display/intel_dvo.c | 8 +-
> drivers/gpu/drm/i915/display/intel_gmbus.c | 290 ++++++------
> drivers/gpu/drm/i915/display/intel_gmbus.h | 15 +-
> .../gpu/drm/i915/display/intel_gmbus_regs.h | 16 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 30 +-
> drivers/gpu/drm/i915/display/intel_hdcp.h | 10 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 11 +-
> .../gpu/drm/i915/display/intel_hotplug_irq.c | 6 +-
> drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
> .../gpu/drm/i915/display/intel_pch_display.c | 3 +-
> drivers/gpu/drm/i915/display/intel_sdvo.c | 9 +-
> drivers/gpu/drm/i915/i915_suspend.c | 2 +-
> drivers/gpu/drm/xe/display/xe_display.c | 4 +-
> 36 files changed, 1024 insertions(+), 963 deletions(-)
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 22+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915/display: bunch of struct intel_display conversions (rev6)
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (15 preceding siblings ...)
2024-10-30 12:16 ` [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
@ 2024-10-30 22:42 ` Patchwork
2024-10-30 22:49 ` Patchwork
17 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2024-10-30 22:42 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 100293 bytes --]
== Series Details ==
Series: drm/i915/display: bunch of struct intel_display conversions (rev6)
URL : https://patchwork.freedesktop.org/series/140324/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15607_full -> Patchwork_140324v6_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-glk-0
Known issues
------------
Here are the changes found in Patchwork_140324v6_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@object-reloc-keep-cache:
- shard-dg1: NOTRUN -> [SKIP][1] ([i915#8411])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@debugfs_test@basic-hwmon:
- shard-tglu-1: NOTRUN -> [SKIP][2] ([i915#9318])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@debugfs_test@basic-hwmon.html
* igt@drm_fdinfo@busy@ccs0:
- shard-dg2: NOTRUN -> [SKIP][3] ([i915#8414]) +8 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@drm_fdinfo@busy@ccs0.html
* igt@drm_fdinfo@virtual-busy-idle-all:
- shard-mtlp: NOTRUN -> [SKIP][4] ([i915#8414])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-6/igt@drm_fdinfo@virtual-busy-idle-all.html
* igt@gem_ccs@block-copy-compressed:
- shard-rkl: NOTRUN -> [SKIP][5] ([i915#3555] / [i915#9323])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@suspend-resume:
- shard-rkl: NOTRUN -> [SKIP][6] ([i915#9323])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@gem_ccs@suspend-resume.html
* igt@gem_close_race@multigpu-basic-process:
- shard-tglu-1: NOTRUN -> [SKIP][7] ([i915#7697])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_ctx_persistence@hang:
- shard-dg2: NOTRUN -> [SKIP][8] ([i915#8555])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@gem_ctx_persistence@hang.html
* igt@gem_ctx_persistence@heartbeat-hostile:
- shard-dg1: NOTRUN -> [SKIP][9] ([i915#8555])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@gem_ctx_persistence@heartbeat-hostile.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-dg1: NOTRUN -> [SKIP][10] ([i915#280])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@reset-stress:
- shard-dg1: [PASS][11] -> [FAIL][12] ([i915#12543] / [i915#5784])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-15/igt@gem_eio@reset-stress.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-15/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@bonded-pair:
- shard-dg2: NOTRUN -> [SKIP][13] ([i915#4771])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@gem_exec_balancer@bonded-pair.html
* igt@gem_exec_balancer@nop:
- shard-mtlp: [PASS][14] -> [DMESG-WARN][15] ([i915#12412])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-mtlp-2/igt@gem_exec_balancer@nop.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-5/igt@gem_exec_balancer@nop.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-rkl: NOTRUN -> [SKIP][16] ([i915#4525]) +1 other test skip
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_big@single:
- shard-tglu: NOTRUN -> [ABORT][17] ([i915#11713])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-4/igt@gem_exec_big@single.html
* igt@gem_exec_capture@capture-recoverable:
- shard-tglu-1: NOTRUN -> [SKIP][18] ([i915#6344])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@gem_exec_capture@capture-recoverable.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglu: [PASS][19] -> [FAIL][20] ([i915#2842]) +1 other test fail
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-tglu-6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-rkl: [PASS][21] -> [FAIL][22] ([i915#2842]) +1 other test fail
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-rkl-7/igt@gem_exec_fair@basic-pace@bcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-throttle:
- shard-tglu-1: NOTRUN -> [FAIL][23] ([i915#2842]) +1 other test fail
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@gem_exec_fair@basic-throttle.html
* igt@gem_exec_fence@submit3:
- shard-dg2: NOTRUN -> [SKIP][24] ([i915#4812])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@gem_exec_fence@submit3.html
- shard-dg1: NOTRUN -> [SKIP][25] ([i915#4812])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-19/igt@gem_exec_fence@submit3.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-dg2: NOTRUN -> [SKIP][26] ([i915#3539] / [i915#4852]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_reloc@basic-gtt-cpu:
- shard-rkl: NOTRUN -> [SKIP][27] ([i915#3281]) +3 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_exec_reloc@basic-gtt-cpu.html
* igt@gem_exec_reloc@basic-wc-cpu:
- shard-dg2: NOTRUN -> [SKIP][28] ([i915#3281]) +4 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@gem_exec_reloc@basic-wc-cpu.html
* igt@gem_exec_reloc@basic-write-cpu-noreloc:
- shard-dg1: NOTRUN -> [SKIP][29] ([i915#3281])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-13/igt@gem_exec_reloc@basic-write-cpu-noreloc.html
* igt@gem_exec_schedule@pi-ringfull@rcs0:
- shard-rkl: NOTRUN -> [FAIL][30] ([i915#12296]) +4 other tests fail
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@gem_exec_schedule@pi-ringfull@rcs0.html
* igt@gem_exec_schedule@semaphore-power:
- shard-rkl: NOTRUN -> [SKIP][31] ([i915#7276])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy:
- shard-mtlp: NOTRUN -> [SKIP][32] ([i915#4860])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-6/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html
* igt@gem_fenced_exec_thrash@no-spare-fences-interruptible:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#4860])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-rkl: NOTRUN -> [SKIP][34] ([i915#4613]) +1 other test skip
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-tglu: NOTRUN -> [SKIP][35] ([i915#4613]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@verify-random:
- shard-tglu-1: NOTRUN -> [SKIP][36] ([i915#4613]) +1 other test skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@big-bo:
- shard-dg1: NOTRUN -> [SKIP][37] ([i915#4083])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-15/igt@gem_mmap@big-bo.html
* igt@gem_mmap_gtt@cpuset-big-copy:
- shard-dg2: NOTRUN -> [SKIP][38] ([i915#4077]) +1 other test skip
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@gem_mmap_gtt@cpuset-big-copy.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-dg1: NOTRUN -> [SKIP][39] ([i915#4077]) +2 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-13/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
- shard-mtlp: NOTRUN -> [SKIP][40] ([i915#4077]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-3/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_mmap_wc@read-write-distinct:
- shard-dg2: NOTRUN -> [SKIP][41] ([i915#4083]) +2 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@gem_mmap_wc@read-write-distinct.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-rkl: NOTRUN -> [SKIP][42] ([i915#3282]) +2 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_pread@self:
- shard-dg2: NOTRUN -> [SKIP][43] ([i915#3282])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@gem_pread@self.html
- shard-dg1: NOTRUN -> [SKIP][44] ([i915#3282]) +1 other test skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-19/igt@gem_pread@self.html
* igt@gem_pxp@create-valid-protected-context:
- shard-dg1: NOTRUN -> [SKIP][45] ([i915#4270]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_pxp@protected-raw-src-copy-not-readible:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#4270]) +2 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@gem_pxp@protected-raw-src-copy-not-readible.html
- shard-rkl: NOTRUN -> [SKIP][47] ([i915#4270]) +2 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_pxp@protected-raw-src-copy-not-readible.html
- shard-tglu-1: NOTRUN -> [SKIP][48] ([i915#4270]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@gem_pxp@protected-raw-src-copy-not-readible.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-tglu: NOTRUN -> [SKIP][49] ([i915#4270])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-mtlp: NOTRUN -> [SKIP][50] ([i915#4270])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-6/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_render_copy@y-tiled-to-vebox-linear:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#5190] / [i915#8428]) +1 other test skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@gem_render_copy@y-tiled-to-vebox-linear.html
* igt@gem_softpin@evict-snoop:
- shard-mtlp: NOTRUN -> [SKIP][52] ([i915#4885])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-6/igt@gem_softpin@evict-snoop.html
* igt@gem_userptr_blits@coherency-sync:
- shard-tglu-1: NOTRUN -> [SKIP][53] ([i915#3297]) +2 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@coherency-unsync:
- shard-dg1: NOTRUN -> [SKIP][54] ([i915#3297]) +1 other test skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-13/igt@gem_userptr_blits@coherency-unsync.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-rkl: NOTRUN -> [SKIP][55] ([i915#3297] / [i915#3323])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@readonly-unsync:
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#3297])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@gem_userptr_blits@readonly-unsync.html
- shard-rkl: NOTRUN -> [SKIP][57] ([i915#3297]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_userptr_blits@readonly-unsync.html
* igt@gen9_exec_parse@bb-start-far:
- shard-tglu-1: NOTRUN -> [SKIP][58] ([i915#2527] / [i915#2856]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@gen9_exec_parse@bb-start-far.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#2856]) +1 other test skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@gen9_exec_parse@unaligned-access:
- shard-dg1: NOTRUN -> [SKIP][60] ([i915#2527]) +1 other test skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-15/igt@gen9_exec_parse@unaligned-access.html
* igt@i915_module_load@load:
- shard-dg2: NOTRUN -> [SKIP][61] ([i915#6227])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@i915_module_load@load.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-rkl: [PASS][62] -> [ABORT][63] ([i915#9820])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-rkl-3/igt@i915_module_load@reload-with-fault-injection.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-3/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_api@freq-basic-api:
- shard-rkl: NOTRUN -> [SKIP][64] ([i915#8399])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@i915_pm_freq_api@freq-basic-api.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-dg1: [PASS][65] -> [FAIL][66] ([i915#12548] / [i915#3591])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0:
- shard-dg1: [PASS][67] -> [FAIL][68] ([i915#3591])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-dg2: NOTRUN -> [SKIP][69] +9 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][70] -> [INCOMPLETE][71] ([i915#7790])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-snb2/igt@i915_pm_rps@reset.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-snb4/igt@i915_pm_rps@reset.html
* igt@i915_pm_rps@thresholds-park:
- shard-dg2: NOTRUN -> [SKIP][72] ([i915#11681])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-8/igt@i915_pm_rps@thresholds-park.html
* igt@i915_power@sanity:
- shard-mtlp: [PASS][73] -> [SKIP][74] ([i915#7984])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-mtlp-1/igt@i915_power@sanity.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-1/igt@i915_power@sanity.html
* igt@i915_query@hwconfig_table:
- shard-dg1: NOTRUN -> [SKIP][75] ([i915#6245])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@i915_query@hwconfig_table.html
* igt@intel_hwmon@hwmon-write:
- shard-tglu-1: NOTRUN -> [SKIP][76] ([i915#7707])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@intel_hwmon@hwmon-write.html
* igt@kms_addfb_basic@clobberred-modifier:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#4212]) +2 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_addfb_basic@clobberred-modifier.html
- shard-dg1: NOTRUN -> [SKIP][78] ([i915#4212])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-19/igt@kms_addfb_basic@clobberred-modifier.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][79] ([i915#8709]) +3 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-3/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc.html
* igt@kms_atomic_transition@modeset-transition-nonblocking:
- shard-glk: ([PASS][80], [PASS][81]) -> [FAIL][82] ([i915#12177])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk6/igt@kms_atomic_transition@modeset-transition-nonblocking.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk2/igt@kms_atomic_transition@modeset-transition-nonblocking.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking.html
* igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs:
- shard-glk: ([PASS][83], [PASS][84]) -> [FAIL][85] ([i915#11859])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk6/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk2/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-tglu: NOTRUN -> [SKIP][86] ([i915#1769] / [i915#3555])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-dg2: NOTRUN -> [SKIP][87] ([i915#1769] / [i915#3555])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][88] ([i915#4538] / [i915#5286]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-19/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-0:
- shard-tglu-1: NOTRUN -> [SKIP][89] ([i915#5286]) +3 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-rkl: NOTRUN -> [SKIP][90] ([i915#5286]) +4 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
- shard-dg1: NOTRUN -> [SKIP][91] ([i915#5286])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
- shard-tglu: NOTRUN -> [SKIP][92] ([i915#5286])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][93] ([i915#3638]) +2 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-180:
- shard-rkl: [PASS][94] -> [ABORT][95] ([i915#10354])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-rkl-2/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-1/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-dg2: NOTRUN -> [SKIP][96] ([i915#5190]) +1 other test skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-dg1: NOTRUN -> [SKIP][97] ([i915#4538])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-19/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-dg2: NOTRUN -> [SKIP][98] ([i915#4538] / [i915#5190]) +6 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][99] ([i915#6095]) +54 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][100] ([i915#6095]) +6 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-2/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-c-edp-1.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][101] ([i915#10307] / [i915#10434] / [i915#6095]) +2 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs:
- shard-tglu: NOTRUN -> [SKIP][102] ([i915#6095]) +4 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][103] ([i915#6095]) +76 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][104] ([i915#10307] / [i915#6095]) +157 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-6/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-d-hdmi-a-3.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][105] ([i915#6095]) +112 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-15/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-4.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][106] ([i915#7213]) +3 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html
* igt@kms_cdclk@plane-scaling:
- shard-rkl: NOTRUN -> [SKIP][107] ([i915#3742])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_cdclk@plane-scaling.html
- shard-tglu-1: NOTRUN -> [SKIP][108] ([i915#3742])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_cdclk@plane-scaling.html
* igt@kms_cdclk@plane-scaling@pipe-c-dp-3:
- shard-dg2: NOTRUN -> [SKIP][109] ([i915#4087]) +4 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_cdclk@plane-scaling@pipe-c-dp-3.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-tglu-1: NOTRUN -> [SKIP][110] ([i915#7828]) +5 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_frames@hdmi-aspect-ratio:
- shard-tglu: NOTRUN -> [SKIP][111] ([i915#7828]) +1 other test skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_chamelium_frames@hdmi-aspect-ratio.html
* igt@kms_chamelium_frames@hdmi-crc-multiple:
- shard-dg2: NOTRUN -> [SKIP][112] ([i915#7828]) +2 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_chamelium_frames@hdmi-crc-multiple.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- shard-dg1: NOTRUN -> [SKIP][113] ([i915#7828])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-16/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- shard-rkl: NOTRUN -> [SKIP][114] ([i915#7828]) +4 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_color@deep-color:
- shard-tglu-1: NOTRUN -> [SKIP][115] ([i915#3555] / [i915#9979])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_color@deep-color.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-tglu-1: NOTRUN -> [SKIP][116] ([i915#3116] / [i915#3299])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@mei-interface:
- shard-tglu-1: NOTRUN -> [SKIP][117] ([i915#6944] / [i915#9424])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_content_protection@mei-interface.html
* igt@kms_cursor_crc@cursor-offscreen-max-size:
- shard-dg1: NOTRUN -> [SKIP][118] ([i915#3555]) +1 other test skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@kms_cursor_crc@cursor-offscreen-max-size.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-rkl: NOTRUN -> [SKIP][119] ([i915#11453] / [i915#3359]) +1 other test skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-tglu-1: NOTRUN -> [SKIP][120] ([i915#11453] / [i915#3359]) +1 other test skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-dg1: NOTRUN -> [SKIP][121] ([i915#11453] / [i915#3359])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#3555]) +6 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_cursor_crc@cursor-sliding-32x10.html
- shard-rkl: NOTRUN -> [SKIP][123] ([i915#3555]) +7 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_cursor_crc@cursor-sliding-32x10.html
- shard-tglu-1: NOTRUN -> [SKIP][124] ([i915#3555]) +3 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-32x10.html
* igt@kms_cursor_crc@cursor-sliding-32x32:
- shard-mtlp: NOTRUN -> [SKIP][125] ([i915#3555] / [i915#8814])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-4/igt@kms_cursor_crc@cursor-sliding-32x32.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-mtlp: NOTRUN -> [SKIP][126] ([i915#11453] / [i915#3359])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-6/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-dg2: NOTRUN -> [SKIP][127] ([i915#11453] / [i915#3359])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-8/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-mtlp: NOTRUN -> [SKIP][128] ([i915#9809]) +1 other test skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-2/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-rkl: NOTRUN -> [SKIP][129] +22 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-snb: [PASS][130] -> [FAIL][131] ([i915#2346])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-snb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-snb6/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-tglu-1: NOTRUN -> [SKIP][132] ([i915#9067])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-dg2: NOTRUN -> [SKIP][133] ([i915#4103] / [i915#4213])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
- shard-rkl: NOTRUN -> [SKIP][134] ([i915#4103])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
- shard-tglu-1: NOTRUN -> [SKIP][135] ([i915#4103])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-rkl: NOTRUN -> [SKIP][136] ([i915#8588])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][137] ([i915#3804])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dp_aux_dev:
- shard-tglu-1: NOTRUN -> [SKIP][138] ([i915#1257])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_dp_aux_dev.html
* igt@kms_dsc@dsc-basic:
- shard-dg1: NOTRUN -> [SKIP][139] ([i915#3555] / [i915#3840])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-15/igt@kms_dsc@dsc-basic.html
* igt@kms_fb_coherency@memset-crc:
- shard-dg2: [PASS][140] -> [SKIP][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-7/igt@kms_fb_coherency@memset-crc.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_fb_coherency@memset-crc.html
* igt@kms_fbcon_fbt@psr:
- shard-tglu-1: NOTRUN -> [SKIP][142] ([i915#3469])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_fbcon_fbt@psr.html
* igt@kms_feature_discovery@chamelium:
- shard-dg2: NOTRUN -> [SKIP][143] ([i915#4854])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-3x:
- shard-dg2: NOTRUN -> [SKIP][144] ([i915#1839])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_feature_discovery@display-3x.html
- shard-rkl: NOTRUN -> [SKIP][145] ([i915#1839])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_feature_discovery@display-3x.html
- shard-tglu-1: NOTRUN -> [SKIP][146] ([i915#1839])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_feature_discovery@display-3x.html
* igt@kms_feature_discovery@display-4x:
- shard-dg1: NOTRUN -> [SKIP][147] ([i915#1839])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@kms_feature_discovery@display-4x.html
* igt@kms_feature_discovery@dp-mst:
- shard-mtlp: NOTRUN -> [SKIP][148] ([i915#9337])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-5/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr2:
- shard-tglu-1: NOTRUN -> [SKIP][149] ([i915#658])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_feature_discovery@psr2.html
- shard-dg2: NOTRUN -> [SKIP][150] ([i915#658])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_feature_discovery@psr2.html
- shard-rkl: NOTRUN -> [SKIP][151] ([i915#658])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-tglu: NOTRUN -> [SKIP][152] ([i915#3637])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-4/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-tglu-1: NOTRUN -> [SKIP][153] ([i915#3637]) +3 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset:
- shard-dg1: NOTRUN -> [SKIP][154] ([i915#9934])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible@ab-vga1-hdmi-a1:
- shard-snb: [PASS][155] -> [FAIL][156] ([i915#2122]) +1 other test fail
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-snb6/igt@kms_flip@2x-wf_vblank-ts-check-interruptible@ab-vga1-hdmi-a1.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-snb7/igt@kms_flip@2x-wf_vblank-ts-check-interruptible@ab-vga1-hdmi-a1.html
* igt@kms_flip@flip-vs-blocking-wf-vblank:
- shard-mtlp: [PASS][157] -> [FAIL][158] ([i915#11989] / [i915#2122])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-mtlp-1/igt@kms_flip@flip-vs-blocking-wf-vblank.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-1/igt@kms_flip@flip-vs-blocking-wf-vblank.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
- shard-mtlp: [PASS][159] -> [FAIL][160] ([i915#2122])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-mtlp-1/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-1/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-rkl: NOTRUN -> [FAIL][161] ([i915#2122]) +1 other test fail
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-dg2: [PASS][162] -> [SKIP][163] ([i915#5354]) +5 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-7/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip@wf_vblank-ts-check-interruptible:
- shard-dg2: [PASS][164] -> [FAIL][165] ([i915#2122])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-5/igt@kms_flip@wf_vblank-ts-check-interruptible.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_flip@wf_vblank-ts-check-interruptible.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@a-dp3:
- shard-dg2: NOTRUN -> [FAIL][166] ([i915#2122]) +1 other test fail
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_flip@wf_vblank-ts-check-interruptible@a-dp3.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a1:
- shard-glk: ([PASS][167], [PASS][168]) -> [FAIL][169] ([i915#2122]) +1 other test fail
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk5/igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a1.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk4/igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a1.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk4/igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a1.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@d-hdmi-a1:
- shard-tglu: [PASS][170] -> [FAIL][171] ([i915#2122]) +5 other tests fail
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-tglu-2/igt@kms_flip@wf_vblank-ts-check-interruptible@d-hdmi-a1.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_flip@wf_vblank-ts-check-interruptible@d-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling:
- shard-dg2: [PASS][172] -> [SKIP][173] ([i915#3555]) +2 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-7/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-tglu-1: NOTRUN -> [SKIP][174] ([i915#2587] / [i915#2672] / [i915#3555]) +1 other test skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][175] ([i915#2672]) +5 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
- shard-tglu-1: NOTRUN -> [SKIP][176] ([i915#2587] / [i915#2672]) +2 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling:
- shard-dg2: NOTRUN -> [SKIP][177] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
- shard-tglu-1: NOTRUN -> [SKIP][178] ([i915#2672] / [i915#3555])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][179] ([i915#8708]) +2 other tests skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff:
- shard-mtlp: NOTRUN -> [SKIP][180] ([i915#1825])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
- shard-snb: [PASS][181] -> [SKIP][182] +1 other test skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][183] ([i915#8708]) +7 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
- shard-snb: NOTRUN -> [SKIP][184] +8 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][185] ([i915#3458]) +8 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-tglu: NOTRUN -> [SKIP][186] +12 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render:
- shard-dg1: NOTRUN -> [SKIP][187] +7 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
- shard-rkl: NOTRUN -> [SKIP][188] ([i915#1825]) +24 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
- shard-tglu-1: NOTRUN -> [SKIP][189] +65 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-rkl: NOTRUN -> [SKIP][190] ([i915#9766])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
- shard-tglu-1: NOTRUN -> [SKIP][191] ([i915#9766])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
- shard-dg2: NOTRUN -> [SKIP][192] ([i915#9766])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-rkl: NOTRUN -> [SKIP][193] ([i915#3023]) +15 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
- shard-dg1: NOTRUN -> [SKIP][194] ([i915#3458]) +5 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render:
- shard-dg2: NOTRUN -> [SKIP][195] ([i915#5354]) +25 other tests skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render.html
* igt@kms_hdmi_inject@inject-audio:
- shard-tglu-1: NOTRUN -> [SKIP][196] ([i915#433])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_hdr@bpc-switch:
- shard-dg2: [PASS][197] -> [SKIP][198] ([i915#3555] / [i915#8228]) +1 other test skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-10/igt@kms_hdr@bpc-switch.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@invalid-hdr:
- shard-tglu: NOTRUN -> [SKIP][199] ([i915#3555] / [i915#8228])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-tglu-1: NOTRUN -> [SKIP][200] ([i915#3555] / [i915#8228]) +1 other test skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_hdr@static-toggle:
- shard-rkl: NOTRUN -> [SKIP][201] ([i915#3555] / [i915#8228]) +1 other test skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_hdr@static-toggle.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-tglu-1: NOTRUN -> [SKIP][202] ([i915#12388])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: NOTRUN -> [SKIP][203] ([i915#4070] / [i915#4816])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane@plane-position-covered:
- shard-dg2: [PASS][204] -> [SKIP][205] ([i915#8825])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_plane@plane-position-covered.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_plane@plane-position-covered.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][206] ([i915#8292])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-15/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-d:
- shard-dg1: NOTRUN -> [SKIP][207] ([i915#12247]) +1 other test skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-d.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a:
- shard-rkl: NOTRUN -> [SKIP][208] ([i915#12247]) +2 other tests skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20:
- shard-dg2: NOTRUN -> [SKIP][209] ([i915#12247] / [i915#9423])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b:
- shard-dg2: NOTRUN -> [SKIP][210] ([i915#12247]) +3 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20:
- shard-dg1: [PASS][211] -> [DMESG-WARN][212] ([i915#4423]) +2 other tests dmesg-warn
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-17/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20.html
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25:
- shard-dg2: [PASS][213] -> [SKIP][214] ([i915#6953] / [i915#8152] / [i915#9423])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-a:
- shard-dg2: [PASS][215] -> [SKIP][216] ([i915#12247]) +5 other tests skip
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-a.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-a.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-d:
- shard-dg2: [PASS][217] -> [SKIP][218] ([i915#12247] / [i915#8152]) +1 other test skip
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-d.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-d.html
* igt@kms_plane_scaling@planes-downscale-factor-0-75:
- shard-dg2: [PASS][219] -> [SKIP][220] ([i915#12247] / [i915#3555] / [i915#6953] / [i915#8152] / [i915#9423])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_plane_scaling@planes-downscale-factor-0-75.html
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-75.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
- shard-dg1: NOTRUN -> [SKIP][221] ([i915#12247] / [i915#12504] / [i915#3555])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a:
- shard-dg1: NOTRUN -> [SKIP][222] ([i915#12247] / [i915#12504]) +6 other tests skip
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
- shard-tglu-1: NOTRUN -> [SKIP][223] ([i915#12247] / [i915#6953])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c:
- shard-tglu-1: NOTRUN -> [SKIP][224] ([i915#12247]) +3 other tests skip
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c.html
* igt@kms_pm_backlight@bad-brightness:
- shard-dg1: NOTRUN -> [SKIP][225] ([i915#5354])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_backlight@basic-brightness:
- shard-rkl: NOTRUN -> [SKIP][226] ([i915#5354])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_pm_dc@dc6-psr:
- shard-rkl: NOTRUN -> [SKIP][227] ([i915#9685])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_dc@dc9-dpms:
- shard-tglu: [PASS][228] -> [SKIP][229] ([i915#4281])
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-tglu-3/igt@kms_pm_dc@dc9-dpms.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-8/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_rpm@dpms-mode-unset-lpsp:
- shard-glk: NOTRUN -> [SKIP][230]
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk1/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
- shard-dg1: NOTRUN -> [SKIP][231] ([i915#9519])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-15/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: NOTRUN -> [SKIP][232] ([i915#9519])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
- shard-tglu-1: NOTRUN -> [SKIP][233] ([i915#9519])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-rkl: [PASS][234] -> [SKIP][235] ([i915#9519]) +2 other tests skip
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp.html
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-1/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg2: [PASS][236] -> [SKIP][237] ([i915#9519])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_prime@basic-crc-hybrid:
- shard-tglu: NOTRUN -> [SKIP][238] ([i915#6524])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-dg2: NOTRUN -> [SKIP][239] ([i915#6524] / [i915#6805])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_prime@basic-modeset-hybrid.html
- shard-rkl: NOTRUN -> [SKIP][240] ([i915#6524])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_prime@basic-modeset-hybrid.html
- shard-tglu-1: NOTRUN -> [SKIP][241] ([i915#6524])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
- shard-dg2: NOTRUN -> [SKIP][242] ([i915#11520]) +4 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
- shard-dg1: NOTRUN -> [SKIP][243] ([i915#11520])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html
- shard-mtlp: NOTRUN -> [SKIP][244] ([i915#12316]) +1 other test skip
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-4/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][245] ([i915#9808])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-4/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1.html
* igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf:
- shard-tglu: NOTRUN -> [SKIP][246] ([i915#11520]) +2 other tests skip
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
- shard-tglu-1: NOTRUN -> [SKIP][247] ([i915#11520]) +7 other tests skip
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
- shard-rkl: NOTRUN -> [SKIP][248] ([i915#11520]) +5 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-dg1: NOTRUN -> [SKIP][249] ([i915#9683])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-15/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@fbc-psr-basic:
- shard-rkl: NOTRUN -> [SKIP][250] ([i915#1072] / [i915#9732]) +15 other tests skip
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_psr@fbc-psr-basic.html
* igt@kms_psr@psr-cursor-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][251] ([i915#1072] / [i915#9732]) +12 other tests skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_psr@psr-cursor-mmap-cpu.html
- shard-dg1: NOTRUN -> [SKIP][252] ([i915#1072] / [i915#9732]) +2 other tests skip
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-19/igt@kms_psr@psr-cursor-mmap-cpu.html
* igt@kms_psr@psr-sprite-blt:
- shard-tglu: NOTRUN -> [SKIP][253] ([i915#9732]) +4 other tests skip
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_psr@psr-sprite-blt.html
* igt@kms_psr@psr2-cursor-mmap-gtt:
- shard-tglu-1: NOTRUN -> [SKIP][254] ([i915#9732]) +13 other tests skip
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_psr@psr2-cursor-mmap-gtt.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-rkl: NOTRUN -> [SKIP][255] ([i915#5289])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg1: NOTRUN -> [SKIP][256] ([i915#5289])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][257] ([i915#11131] / [i915#4235])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-rkl: NOTRUN -> [SKIP][258] ([i915#8623])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
- shard-tglu-1: NOTRUN -> [SKIP][259] ([i915#8623])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
- shard-dg2: NOTRUN -> [SKIP][260] ([i915#8623])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_universal_plane@universal-plane-sanity:
- shard-dg2: [PASS][261] -> [SKIP][262] ([i915#9197]) +16 other tests skip
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_universal_plane@universal-plane-sanity.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_universal_plane@universal-plane-sanity.html
* igt@kms_vrr@flip-basic-fastset:
- shard-tglu-1: NOTRUN -> [SKIP][263] ([i915#9906])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@negative-basic:
- shard-mtlp: [PASS][264] -> [FAIL][265] ([i915#10393]) +1 other test fail
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-mtlp-1/igt@kms_vrr@negative-basic.html
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-2/igt@kms_vrr@negative-basic.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-tglu: NOTRUN -> [SKIP][266] ([i915#9906])
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][267] ([i915#2437] / [i915#9412])
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-rkl: NOTRUN -> [SKIP][268] ([i915#2437])
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@per-context-mode-unprivileged:
- shard-rkl: NOTRUN -> [SKIP][269] ([i915#2435])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@perf@per-context-mode-unprivileged.html
* igt@perf_pmu@busy-double-start@vcs1:
- shard-dg2: [PASS][270] -> [FAIL][271] ([i915#4349]) +2 other tests fail
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@perf_pmu@busy-double-start@vcs1.html
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@perf_pmu@busy-double-start@vcs1.html
* igt@perf_pmu@module-unload:
- shard-dg2: NOTRUN -> [FAIL][272] ([i915#11823] / [i915#12555])
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@perf_pmu@module-unload.html
* igt@prime_vgem@basic-fence-flip:
- shard-dg2: NOTRUN -> [SKIP][273] ([i915#3708])
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-write:
- shard-rkl: NOTRUN -> [SKIP][274] ([i915#3291] / [i915#3708])
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@prime_vgem@basic-write.html
* igt@prime_vgem@fence-write-hang:
- shard-rkl: NOTRUN -> [SKIP][275] ([i915#3708])
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@prime_vgem@fence-write-hang.html
* igt@sriov_basic@bind-unbind-vf:
- shard-dg2: NOTRUN -> [SKIP][276] ([i915#9917]) +1 other test skip
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@sriov_basic@bind-unbind-vf.html
- shard-rkl: NOTRUN -> [SKIP][277] ([i915#9917])
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@sriov_basic@bind-unbind-vf.html
- shard-tglu-1: NOTRUN -> [SKIP][278] ([i915#9917])
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@sriov_basic@bind-unbind-vf.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-dg1: NOTRUN -> [SKIP][279] ([i915#9917])
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@sriov_basic@enable-vfs-autoprobe-on.html
#### Possible fixes ####
* igt@fbdev@write:
- shard-dg2: [SKIP][280] ([i915#2582]) -> [PASS][281]
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@fbdev@write.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@fbdev@write.html
* igt@gem_ccs@suspend-resume:
- shard-dg2: [INCOMPLETE][282] ([i915#7297]) -> [PASS][283] +1 other test pass
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-4/igt@gem_ccs@suspend-resume.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-8/igt@gem_ccs@suspend-resume.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: [FAIL][284] ([i915#2842]) -> [PASS][285]
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-rkl-7/igt@gem_exec_fair@basic-pace@rcs0.html
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglu: [ABORT][286] ([i915#10887] / [i915#9820]) -> [PASS][287]
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-tglu-5/igt@i915_module_load@reload-with-fault-injection.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_addfb_basic@bad-pitch-65536:
- shard-dg1: [DMESG-WARN][288] ([i915#4423]) -> [PASS][289] +4 other tests pass
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-13/igt@kms_addfb_basic@bad-pitch-65536.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@kms_addfb_basic@bad-pitch-65536.html
* igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:
- shard-glk: ([FAIL][290], [PASS][291]) ([i915#12238]) -> [PASS][292]
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk9/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk2/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
* igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs:
- shard-glk: ([PASS][293], [FAIL][294]) ([i915#11859]) -> [PASS][295]
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk9/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs.html
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs.html
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk2/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-180:
- shard-dg2: [SKIP][296] ([i915#9197]) -> [PASS][297] +31 other tests pass
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
* igt@kms_color@ctm-0-75:
- shard-dg2: [SKIP][298] ([i915#12655]) -> [PASS][299]
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_color@ctm-0-75.html
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_color@ctm-0-75.html
* igt@kms_dp_aux_dev:
- shard-dg2: [SKIP][300] ([i915#1257]) -> [PASS][301]
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_dp_aux_dev.html
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_dp_aux_dev.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
- shard-glk: ([FAIL][302], [FAIL][303]) ([i915#2122]) -> [PASS][304] +1 other test pass
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk2/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk1/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
* igt@kms_flip@2x-plain-flip-ts-check:
- shard-snb: [FAIL][305] ([i915#2122]) -> [PASS][306] +3 other tests pass
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-snb4/igt@kms_flip@2x-plain-flip-ts-check.html
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-snb2/igt@kms_flip@2x-plain-flip-ts-check.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
- shard-dg2: [SKIP][307] ([i915#5354]) -> [PASS][308] +13 other tests pass
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: ([FAIL][309], [PASS][310]) ([i915#79]) -> [PASS][311] +1 other test pass
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk7/igt@kms_flip@flip-vs-expired-vblank.html
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk2/igt@kms_flip@flip-vs-expired-vblank.html
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk1/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-tglu: [FAIL][312] ([i915#79]) -> [PASS][313] +1 other test pass
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-tglu-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@wf_vblank-ts-check-interruptible:
- shard-dg1: [FAIL][314] ([i915#12517] / [i915#2122]) -> [PASS][315]
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-19/igt@kms_flip@wf_vblank-ts-check-interruptible.html
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@kms_flip@wf_vblank-ts-check-interruptible.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@c-edp1:
- shard-mtlp: [FAIL][316] ([i915#2122]) -> [PASS][317]
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-mtlp-4/igt@kms_flip@wf_vblank-ts-check-interruptible@c-edp1.html
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-6/igt@kms_flip@wf_vblank-ts-check-interruptible@c-edp1.html
* igt@kms_flip@wf_vblank-ts-check@d-hdmi-a1:
- shard-tglu: [FAIL][318] ([i915#2122]) -> [PASS][319] +3 other tests pass
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-tglu-9/igt@kms_flip@wf_vblank-ts-check@d-hdmi-a1.html
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-9/igt@kms_flip@wf_vblank-ts-check@d-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-dg2: [SKIP][320] ([i915#3555]) -> [PASS][321] +2 other tests pass
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt:
- shard-snb: [SKIP][322] -> [PASS][323] +1 other test pass
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-snb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-dg2: [SKIP][324] ([i915#12388]) -> [PASS][325]
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_joiner@basic-force-big-joiner.html
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_plane@plane-panning-top-left:
- shard-dg2: [SKIP][326] ([i915#8825]) -> [PASS][327] +1 other test pass
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane@plane-panning-top-left.html
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_plane@plane-panning-top-left.html
* igt@kms_plane_alpha_blend@alpha-7efc:
- shard-dg2: [SKIP][328] ([i915#7294]) -> [PASS][329]
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_alpha_blend@alpha-7efc.html
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_plane_alpha_blend@alpha-7efc.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers:
- shard-dg2: [SKIP][330] ([i915#8152] / [i915#9423]) -> [PASS][331] +1 other test pass
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers.html
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers@pipe-d:
- shard-dg2: [SKIP][332] ([i915#8152]) -> [PASS][333] +2 other tests pass
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers@pipe-d.html
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers@pipe-d.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-c:
- shard-dg2: [SKIP][334] ([i915#12247]) -> [PASS][335] +11 other tests pass
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-c.html
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-c.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation:
- shard-dg2: [SKIP][336] ([i915#12247] / [i915#8152] / [i915#9423]) -> [PASS][337]
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation.html
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-d:
- shard-dg2: [SKIP][338] ([i915#12247] / [i915#8152]) -> [PASS][339]
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-d.html
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-d.html
* igt@kms_plane_scaling@planes-upscale-20x20:
- shard-dg2: [SKIP][340] ([i915#6953] / [i915#8152] / [i915#9423]) -> [PASS][341]
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-20x20.html
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_plane_scaling@planes-upscale-20x20.html
* igt@kms_pm_dc@dc6-dpms:
- shard-tglu: [FAIL][342] ([i915#9295]) -> [PASS][343]
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-tglu-8/igt@kms_pm_dc@dc6-dpms.html
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-5/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-rkl: [SKIP][344] ([i915#9519]) -> [PASS][345]
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-rkl-1/igt@kms_pm_rpm@dpms-lpsp.html
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-7/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@drm-resources-equal:
- shard-dg2: [SKIP][346] ([i915#3547]) -> [PASS][347]
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_pm_rpm@drm-resources-equal.html
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_pm_rpm@drm-resources-equal.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg2: [SKIP][348] ([i915#9519]) -> [PASS][349] +1 other test pass
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_pm_rpm@modeset-lpsp.html
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_setmode@basic:
- shard-tglu: [FAIL][350] ([i915#5465]) -> [PASS][351] +2 other tests pass
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-tglu-4/igt@kms_setmode@basic.html
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-8/igt@kms_setmode@basic.html
- shard-mtlp: [FAIL][352] ([i915#5465]) -> [PASS][353] +1 other test pass
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-mtlp-4/igt@kms_setmode@basic.html
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-2/igt@kms_setmode@basic.html
* igt@perf_pmu@busy-double-start@ccs0:
- shard-dg2: [FAIL][354] ([i915#4349]) -> [PASS][355]
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@perf_pmu@busy-double-start@ccs0.html
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@perf_pmu@busy-double-start@ccs0.html
#### Warnings ####
* igt@gem_exec_fair@basic-deadline:
- shard-glk: ([PASS][356], [FAIL][357]) ([i915#2846]) -> [FAIL][358] ([i915#2846])
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk8/igt@gem_exec_fair@basic-deadline.html
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk9/igt@gem_exec_fair@basic-deadline.html
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: ([FAIL][359], [PASS][360]) ([i915#2842]) -> [FAIL][361] ([i915#2842]) +1 other test fail
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@i915_selftest@mock:
- shard-glk: ([DMESG-WARN][362], [DMESG-WARN][363]) ([i915#1982] / [i915#9311]) -> [DMESG-WARN][364] ([i915#9311])
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk7/igt@i915_selftest@mock.html
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk2/igt@i915_selftest@mock.html
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk1/igt@i915_selftest@mock.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-dg2: [SKIP][365] ([i915#9197]) -> [SKIP][366] +2 other tests skip
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-dg2: [SKIP][367] ([i915#5190] / [i915#9197]) -> [SKIP][368] ([i915#4538] / [i915#5190]) +4 other tests skip
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-dg2: [SKIP][369] ([i915#5190] / [i915#9197]) -> [SKIP][370] ([i915#5190]) +1 other test skip
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-dg2: [SKIP][371] ([i915#4538] / [i915#5190]) -> [SKIP][372] ([i915#5190] / [i915#9197]) +2 other tests skip
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
- shard-dg2: [SKIP][373] ([i915#9197]) -> [SKIP][374] ([i915#12313]) +3 other tests skip
[373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
[374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs:
- shard-dg2: [SKIP][375] ([i915#9197]) -> [SKIP][376] ([i915#10307] / [i915#6095]) +6 other tests skip
[375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs.html
[376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs:
- shard-dg2: [SKIP][377] ([i915#10307] / [i915#6095]) -> [SKIP][378] ([i915#9197]) +5 other tests skip
[377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-7/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs.html
[378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs.html
* igt@kms_cdclk@mode-transition:
- shard-dg2: [SKIP][379] ([i915#9197]) -> [SKIP][380] ([i915#11616] / [i915#7213])
[379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_cdclk@mode-transition.html
[380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_cdclk@mode-transition.html
* igt@kms_content_protection@atomic:
- shard-dg2: [SKIP][381] ([i915#7118] / [i915#9424]) -> [SKIP][382] ([i915#9197]) +1 other test skip
[381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_content_protection@atomic.html
[382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg2: [SKIP][383] ([i915#9197]) -> [SKIP][384] ([i915#7118] / [i915#9424])
[383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_content_protection@atomic-dpms.html
[384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@mei-interface:
- shard-dg2: [SKIP][385] ([i915#9197]) -> [SKIP][386] ([i915#9424])
[385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_content_protection@mei-interface.html
[386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_content_protection@mei-interface.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-dg2: [SKIP][387] ([i915#11453] / [i915#3359]) -> [SKIP][388] ([i915#9197]) +1 other test skip
[387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_cursor_crc@cursor-random-512x512.html
[388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-dg2: [SKIP][389] ([i915#9197]) -> [SKIP][390] ([i915#11453] / [i915#3359])
[389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_cursor_crc@cursor-sliding-512x170.html
[390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-dg2: [SKIP][391] ([i915#5354]) -> [SKIP][392] ([i915#9197]) +2 other tests skip
[391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-7/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
[392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-dg2: [SKIP][393] ([i915#4103] / [i915#4213]) -> [SKIP][394] ([i915#9197])
[393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-dg2: [SKIP][395] ([i915#9197]) -> [SKIP][396] ([i915#5354])
[395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
[396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: ([PASS][397], [FAIL][398]) ([i915#2346]) -> [FAIL][399] ([i915#2346])
[397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[398]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[399]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-dg2: [SKIP][400] ([i915#9197]) -> [SKIP][401] ([i915#9067])
[400]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
[401]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-dg2: [SKIP][402] ([i915#9197]) -> [SKIP][403] ([i915#3555]) +2 other tests skip
[402]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
[403]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_dsc@dsc-with-bpc:
- shard-dg2: [SKIP][404] ([i915#9197]) -> [SKIP][405] ([i915#3555] / [i915#3840])
[404]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_dsc@dsc-with-bpc.html
[405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-dg2: [SKIP][406] ([i915#9197]) -> [SKIP][407] ([i915#3840] / [i915#9053])
[406]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
[407]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-dg1: [SKIP][408] ([i915#9934]) -> [SKIP][409] ([i915#4423] / [i915#9934])
[408]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-15/igt@kms_flip@2x-dpms-vs-vblank-race.html
[409]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-14/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@2x-flip-vs-panning:
- shard-dg1: [INCOMPLETE][410] -> [SKIP][411] ([i915#9934])
[410]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-17/igt@kms_flip@2x-flip-vs-panning.html
[411]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-19/igt@kms_flip@2x-flip-vs-panning.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
- shard-dg2: [SKIP][412] ([i915#3555]) -> [SKIP][413] ([i915#2672] / [i915#3555]) +1 other test skip
[412]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html
[413]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
- shard-dg2: [SKIP][414] ([i915#3555] / [i915#5190]) -> [SKIP][415] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
[414]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
[415]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc:
- shard-dg1: [SKIP][416] ([i915#8708]) -> [SKIP][417] ([i915#4423] / [i915#8708])
[416]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html
[417]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-14/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt:
- shard-dg2: [SKIP][418] ([i915#5354]) -> [SKIP][419] ([i915#8708]) +6 other tests skip
[418]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt.html
[419]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-dg2: [SKIP][420] ([i915#3458]) -> [SKIP][421] ([i915#10433] / [i915#3458]) +1 other test skip
[420]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-10/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[421]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-dg2: [SKIP][422] ([i915#5354]) -> [SKIP][423] ([i915#10433] / [i915#3458])
[422]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
[423]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu:
- shard-dg2: [SKIP][424] ([i915#5354]) -> [SKIP][425] ([i915#3458]) +16 other tests skip
[424]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
[425]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: [SKIP][426] ([i915#3458]) -> [SKIP][427] ([i915#5354]) +1 other test skip
[426]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
[427]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move:
- shard-dg1: [SKIP][428] ([i915#4423]) -> [SKIP][429]
[428]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-18/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html
[429]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
- shard-dg2: [SKIP][430] ([i915#8708]) -> [SKIP][431] ([i915#5354]) +8 other tests skip
[430]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
[431]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
* igt@kms_hdr@static-swap:
- shard-dg2: [SKIP][432] ([i915#9197]) -> [SKIP][433] ([i915#3555] / [i915#8228]) +1 other test skip
[432]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_hdr@static-swap.html
[433]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_hdr@static-swap.html
* igt@kms_plane_lowres@tiling-yf:
- shard-dg2: [SKIP][434] ([i915#9197]) -> [SKIP][435] ([i915#3555] / [i915#8821])
[434]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_lowres@tiling-yf.html
[435]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
- shard-dg2: [SKIP][436] ([i915#12247] / [i915#6953] / [i915#8152] / [i915#9423]) -> [SKIP][437] ([i915#12247] / [i915#6953] / [i915#9423])
[436]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
[437]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d:
- shard-dg2: [SKIP][438] ([i915#12247] / [i915#8152]) -> [SKIP][439] ([i915#12247])
[438]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d.html
[439]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-dg2: [SKIP][440] ([i915#11131] / [i915#4235]) -> [SKIP][441] ([i915#9197])
[440]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_rotation_crc@bad-pixel-format.html
[441]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-dg2: [SKIP][442] ([i915#11131] / [i915#4235] / [i915#5190]) -> [SKIP][443] ([i915#5190] / [i915#9197])
[442]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
[443]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-dg2: [SKIP][444] ([i915#9197]) -> [SKIP][445] ([i915#11131] / [i915#4235])
[444]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_rotation_crc@sprite-rotation-270.html
[445]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_vrr@flip-basic-fastset:
- shard-dg2: [SKIP][446] ([i915#9197]) -> [SKIP][447] ([i915#9906])
[446]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_vrr@flip-basic-fastset.html
[447]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-dg2: [SKIP][448] ([i915#9906]) -> [SKIP][449] ([i915#9197])
[448]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-7/igt@kms_vrr@seamless-rr-switch-vrr.html
[449]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_vrr@seamless-rr-switch-vrr.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10354
[i915#10393]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10393
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]:
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/index.html
[-- Attachment #2: Type: text/html, Size: 108880 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915/display: bunch of struct intel_display conversions (rev6)
2024-10-28 20:07 [CI v2 v2 00/12] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (16 preceding siblings ...)
2024-10-30 22:42 ` ✓ Fi.CI.IGT: success for drm/i915/display: bunch of struct intel_display conversions (rev6) Patchwork
@ 2024-10-30 22:49 ` Patchwork
17 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2024-10-30 22:49 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 100293 bytes --]
== Series Details ==
Series: drm/i915/display: bunch of struct intel_display conversions (rev6)
URL : https://patchwork.freedesktop.org/series/140324/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15607_full -> Patchwork_140324v6_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-glk-0
Known issues
------------
Here are the changes found in Patchwork_140324v6_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@object-reloc-keep-cache:
- shard-dg1: NOTRUN -> [SKIP][1] ([i915#8411])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@debugfs_test@basic-hwmon:
- shard-tglu-1: NOTRUN -> [SKIP][2] ([i915#9318])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@debugfs_test@basic-hwmon.html
* igt@drm_fdinfo@busy@ccs0:
- shard-dg2: NOTRUN -> [SKIP][3] ([i915#8414]) +8 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@drm_fdinfo@busy@ccs0.html
* igt@drm_fdinfo@virtual-busy-idle-all:
- shard-mtlp: NOTRUN -> [SKIP][4] ([i915#8414])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-6/igt@drm_fdinfo@virtual-busy-idle-all.html
* igt@gem_ccs@block-copy-compressed:
- shard-rkl: NOTRUN -> [SKIP][5] ([i915#3555] / [i915#9323])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@suspend-resume:
- shard-rkl: NOTRUN -> [SKIP][6] ([i915#9323])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@gem_ccs@suspend-resume.html
* igt@gem_close_race@multigpu-basic-process:
- shard-tglu-1: NOTRUN -> [SKIP][7] ([i915#7697])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_ctx_persistence@hang:
- shard-dg2: NOTRUN -> [SKIP][8] ([i915#8555])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@gem_ctx_persistence@hang.html
* igt@gem_ctx_persistence@heartbeat-hostile:
- shard-dg1: NOTRUN -> [SKIP][9] ([i915#8555])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@gem_ctx_persistence@heartbeat-hostile.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-dg1: NOTRUN -> [SKIP][10] ([i915#280])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@reset-stress:
- shard-dg1: [PASS][11] -> [FAIL][12] ([i915#12543] / [i915#5784])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-15/igt@gem_eio@reset-stress.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-15/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@bonded-pair:
- shard-dg2: NOTRUN -> [SKIP][13] ([i915#4771])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@gem_exec_balancer@bonded-pair.html
* igt@gem_exec_balancer@nop:
- shard-mtlp: [PASS][14] -> [DMESG-WARN][15] ([i915#12412])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-mtlp-2/igt@gem_exec_balancer@nop.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-5/igt@gem_exec_balancer@nop.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-rkl: NOTRUN -> [SKIP][16] ([i915#4525]) +1 other test skip
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_big@single:
- shard-tglu: NOTRUN -> [ABORT][17] ([i915#11713])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-4/igt@gem_exec_big@single.html
* igt@gem_exec_capture@capture-recoverable:
- shard-tglu-1: NOTRUN -> [SKIP][18] ([i915#6344])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@gem_exec_capture@capture-recoverable.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglu: [PASS][19] -> [FAIL][20] ([i915#2842]) +1 other test fail
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-tglu-6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-rkl: [PASS][21] -> [FAIL][22] ([i915#2842]) +1 other test fail
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-rkl-7/igt@gem_exec_fair@basic-pace@bcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-throttle:
- shard-tglu-1: NOTRUN -> [FAIL][23] ([i915#2842]) +1 other test fail
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@gem_exec_fair@basic-throttle.html
* igt@gem_exec_fence@submit3:
- shard-dg2: NOTRUN -> [SKIP][24] ([i915#4812])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@gem_exec_fence@submit3.html
- shard-dg1: NOTRUN -> [SKIP][25] ([i915#4812])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-19/igt@gem_exec_fence@submit3.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-dg2: NOTRUN -> [SKIP][26] ([i915#3539] / [i915#4852]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_reloc@basic-gtt-cpu:
- shard-rkl: NOTRUN -> [SKIP][27] ([i915#3281]) +3 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_exec_reloc@basic-gtt-cpu.html
* igt@gem_exec_reloc@basic-wc-cpu:
- shard-dg2: NOTRUN -> [SKIP][28] ([i915#3281]) +4 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@gem_exec_reloc@basic-wc-cpu.html
* igt@gem_exec_reloc@basic-write-cpu-noreloc:
- shard-dg1: NOTRUN -> [SKIP][29] ([i915#3281])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-13/igt@gem_exec_reloc@basic-write-cpu-noreloc.html
* igt@gem_exec_schedule@pi-ringfull@rcs0:
- shard-rkl: NOTRUN -> [FAIL][30] ([i915#12296]) +4 other tests fail
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@gem_exec_schedule@pi-ringfull@rcs0.html
* igt@gem_exec_schedule@semaphore-power:
- shard-rkl: NOTRUN -> [SKIP][31] ([i915#7276])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy:
- shard-mtlp: NOTRUN -> [SKIP][32] ([i915#4860])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-6/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html
* igt@gem_fenced_exec_thrash@no-spare-fences-interruptible:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#4860])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-rkl: NOTRUN -> [SKIP][34] ([i915#4613]) +1 other test skip
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-tglu: NOTRUN -> [SKIP][35] ([i915#4613]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@verify-random:
- shard-tglu-1: NOTRUN -> [SKIP][36] ([i915#4613]) +1 other test skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@big-bo:
- shard-dg1: NOTRUN -> [SKIP][37] ([i915#4083])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-15/igt@gem_mmap@big-bo.html
* igt@gem_mmap_gtt@cpuset-big-copy:
- shard-dg2: NOTRUN -> [SKIP][38] ([i915#4077]) +1 other test skip
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@gem_mmap_gtt@cpuset-big-copy.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-dg1: NOTRUN -> [SKIP][39] ([i915#4077]) +2 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-13/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
- shard-mtlp: NOTRUN -> [SKIP][40] ([i915#4077]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-3/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_mmap_wc@read-write-distinct:
- shard-dg2: NOTRUN -> [SKIP][41] ([i915#4083]) +2 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@gem_mmap_wc@read-write-distinct.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-rkl: NOTRUN -> [SKIP][42] ([i915#3282]) +2 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_pread@self:
- shard-dg2: NOTRUN -> [SKIP][43] ([i915#3282])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@gem_pread@self.html
- shard-dg1: NOTRUN -> [SKIP][44] ([i915#3282]) +1 other test skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-19/igt@gem_pread@self.html
* igt@gem_pxp@create-valid-protected-context:
- shard-dg1: NOTRUN -> [SKIP][45] ([i915#4270]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_pxp@protected-raw-src-copy-not-readible:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#4270]) +2 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@gem_pxp@protected-raw-src-copy-not-readible.html
- shard-rkl: NOTRUN -> [SKIP][47] ([i915#4270]) +2 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_pxp@protected-raw-src-copy-not-readible.html
- shard-tglu-1: NOTRUN -> [SKIP][48] ([i915#4270]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@gem_pxp@protected-raw-src-copy-not-readible.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-tglu: NOTRUN -> [SKIP][49] ([i915#4270])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-mtlp: NOTRUN -> [SKIP][50] ([i915#4270])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-6/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_render_copy@y-tiled-to-vebox-linear:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#5190] / [i915#8428]) +1 other test skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@gem_render_copy@y-tiled-to-vebox-linear.html
* igt@gem_softpin@evict-snoop:
- shard-mtlp: NOTRUN -> [SKIP][52] ([i915#4885])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-6/igt@gem_softpin@evict-snoop.html
* igt@gem_userptr_blits@coherency-sync:
- shard-tglu-1: NOTRUN -> [SKIP][53] ([i915#3297]) +2 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@coherency-unsync:
- shard-dg1: NOTRUN -> [SKIP][54] ([i915#3297]) +1 other test skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-13/igt@gem_userptr_blits@coherency-unsync.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-rkl: NOTRUN -> [SKIP][55] ([i915#3297] / [i915#3323])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@readonly-unsync:
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#3297])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@gem_userptr_blits@readonly-unsync.html
- shard-rkl: NOTRUN -> [SKIP][57] ([i915#3297]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_userptr_blits@readonly-unsync.html
* igt@gen9_exec_parse@bb-start-far:
- shard-tglu-1: NOTRUN -> [SKIP][58] ([i915#2527] / [i915#2856]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@gen9_exec_parse@bb-start-far.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#2856]) +1 other test skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@gen9_exec_parse@unaligned-access:
- shard-dg1: NOTRUN -> [SKIP][60] ([i915#2527]) +1 other test skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-15/igt@gen9_exec_parse@unaligned-access.html
* igt@i915_module_load@load:
- shard-dg2: NOTRUN -> [SKIP][61] ([i915#6227])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@i915_module_load@load.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-rkl: [PASS][62] -> [ABORT][63] ([i915#9820])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-rkl-3/igt@i915_module_load@reload-with-fault-injection.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-3/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_api@freq-basic-api:
- shard-rkl: NOTRUN -> [SKIP][64] ([i915#8399])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@i915_pm_freq_api@freq-basic-api.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-dg1: [PASS][65] -> [FAIL][66] ([i915#12548] / [i915#3591])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0:
- shard-dg1: [PASS][67] -> [FAIL][68] ([i915#3591])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-dg2: NOTRUN -> [SKIP][69] +9 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][70] -> [INCOMPLETE][71] ([i915#7790])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-snb2/igt@i915_pm_rps@reset.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-snb4/igt@i915_pm_rps@reset.html
* igt@i915_pm_rps@thresholds-park:
- shard-dg2: NOTRUN -> [SKIP][72] ([i915#11681])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-8/igt@i915_pm_rps@thresholds-park.html
* igt@i915_power@sanity:
- shard-mtlp: [PASS][73] -> [SKIP][74] ([i915#7984])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-mtlp-1/igt@i915_power@sanity.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-1/igt@i915_power@sanity.html
* igt@i915_query@hwconfig_table:
- shard-dg1: NOTRUN -> [SKIP][75] ([i915#6245])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@i915_query@hwconfig_table.html
* igt@intel_hwmon@hwmon-write:
- shard-tglu-1: NOTRUN -> [SKIP][76] ([i915#7707])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@intel_hwmon@hwmon-write.html
* igt@kms_addfb_basic@clobberred-modifier:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#4212]) +2 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_addfb_basic@clobberred-modifier.html
- shard-dg1: NOTRUN -> [SKIP][78] ([i915#4212])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-19/igt@kms_addfb_basic@clobberred-modifier.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][79] ([i915#8709]) +3 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-3/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc.html
* igt@kms_atomic_transition@modeset-transition-nonblocking:
- shard-glk: ([PASS][80], [PASS][81]) -> [FAIL][82] ([i915#12177])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk6/igt@kms_atomic_transition@modeset-transition-nonblocking.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk2/igt@kms_atomic_transition@modeset-transition-nonblocking.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking.html
* igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs:
- shard-glk: ([PASS][83], [PASS][84]) -> [FAIL][85] ([i915#11859])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk6/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk2/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-tglu: NOTRUN -> [SKIP][86] ([i915#1769] / [i915#3555])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-dg2: NOTRUN -> [SKIP][87] ([i915#1769] / [i915#3555])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][88] ([i915#4538] / [i915#5286]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-19/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-0:
- shard-tglu-1: NOTRUN -> [SKIP][89] ([i915#5286]) +3 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-rkl: NOTRUN -> [SKIP][90] ([i915#5286]) +4 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
- shard-dg1: NOTRUN -> [SKIP][91] ([i915#5286])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
- shard-tglu: NOTRUN -> [SKIP][92] ([i915#5286])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][93] ([i915#3638]) +2 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-180:
- shard-rkl: [PASS][94] -> [ABORT][95] ([i915#10354])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-rkl-2/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-1/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-dg2: NOTRUN -> [SKIP][96] ([i915#5190]) +1 other test skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-dg1: NOTRUN -> [SKIP][97] ([i915#4538])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-19/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-dg2: NOTRUN -> [SKIP][98] ([i915#4538] / [i915#5190]) +6 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][99] ([i915#6095]) +54 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][100] ([i915#6095]) +6 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-2/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-c-edp-1.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][101] ([i915#10307] / [i915#10434] / [i915#6095]) +2 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs:
- shard-tglu: NOTRUN -> [SKIP][102] ([i915#6095]) +4 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][103] ([i915#6095]) +76 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][104] ([i915#10307] / [i915#6095]) +157 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-6/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-d-hdmi-a-3.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][105] ([i915#6095]) +112 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-15/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-4.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][106] ([i915#7213]) +3 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html
* igt@kms_cdclk@plane-scaling:
- shard-rkl: NOTRUN -> [SKIP][107] ([i915#3742])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_cdclk@plane-scaling.html
- shard-tglu-1: NOTRUN -> [SKIP][108] ([i915#3742])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_cdclk@plane-scaling.html
* igt@kms_cdclk@plane-scaling@pipe-c-dp-3:
- shard-dg2: NOTRUN -> [SKIP][109] ([i915#4087]) +4 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_cdclk@plane-scaling@pipe-c-dp-3.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-tglu-1: NOTRUN -> [SKIP][110] ([i915#7828]) +5 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_frames@hdmi-aspect-ratio:
- shard-tglu: NOTRUN -> [SKIP][111] ([i915#7828]) +1 other test skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_chamelium_frames@hdmi-aspect-ratio.html
* igt@kms_chamelium_frames@hdmi-crc-multiple:
- shard-dg2: NOTRUN -> [SKIP][112] ([i915#7828]) +2 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_chamelium_frames@hdmi-crc-multiple.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- shard-dg1: NOTRUN -> [SKIP][113] ([i915#7828])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-16/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- shard-rkl: NOTRUN -> [SKIP][114] ([i915#7828]) +4 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_color@deep-color:
- shard-tglu-1: NOTRUN -> [SKIP][115] ([i915#3555] / [i915#9979])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_color@deep-color.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-tglu-1: NOTRUN -> [SKIP][116] ([i915#3116] / [i915#3299])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@mei-interface:
- shard-tglu-1: NOTRUN -> [SKIP][117] ([i915#6944] / [i915#9424])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_content_protection@mei-interface.html
* igt@kms_cursor_crc@cursor-offscreen-max-size:
- shard-dg1: NOTRUN -> [SKIP][118] ([i915#3555]) +1 other test skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@kms_cursor_crc@cursor-offscreen-max-size.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-rkl: NOTRUN -> [SKIP][119] ([i915#11453] / [i915#3359]) +1 other test skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-tglu-1: NOTRUN -> [SKIP][120] ([i915#11453] / [i915#3359]) +1 other test skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-dg1: NOTRUN -> [SKIP][121] ([i915#11453] / [i915#3359])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#3555]) +6 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_cursor_crc@cursor-sliding-32x10.html
- shard-rkl: NOTRUN -> [SKIP][123] ([i915#3555]) +7 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_cursor_crc@cursor-sliding-32x10.html
- shard-tglu-1: NOTRUN -> [SKIP][124] ([i915#3555]) +3 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-32x10.html
* igt@kms_cursor_crc@cursor-sliding-32x32:
- shard-mtlp: NOTRUN -> [SKIP][125] ([i915#3555] / [i915#8814])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-4/igt@kms_cursor_crc@cursor-sliding-32x32.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-mtlp: NOTRUN -> [SKIP][126] ([i915#11453] / [i915#3359])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-6/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-dg2: NOTRUN -> [SKIP][127] ([i915#11453] / [i915#3359])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-8/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-mtlp: NOTRUN -> [SKIP][128] ([i915#9809]) +1 other test skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-2/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-rkl: NOTRUN -> [SKIP][129] +22 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-snb: [PASS][130] -> [FAIL][131] ([i915#2346])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-snb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-snb6/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-tglu-1: NOTRUN -> [SKIP][132] ([i915#9067])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-dg2: NOTRUN -> [SKIP][133] ([i915#4103] / [i915#4213])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
- shard-rkl: NOTRUN -> [SKIP][134] ([i915#4103])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
- shard-tglu-1: NOTRUN -> [SKIP][135] ([i915#4103])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-rkl: NOTRUN -> [SKIP][136] ([i915#8588])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][137] ([i915#3804])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dp_aux_dev:
- shard-tglu-1: NOTRUN -> [SKIP][138] ([i915#1257])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_dp_aux_dev.html
* igt@kms_dsc@dsc-basic:
- shard-dg1: NOTRUN -> [SKIP][139] ([i915#3555] / [i915#3840])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-15/igt@kms_dsc@dsc-basic.html
* igt@kms_fb_coherency@memset-crc:
- shard-dg2: [PASS][140] -> [SKIP][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-7/igt@kms_fb_coherency@memset-crc.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_fb_coherency@memset-crc.html
* igt@kms_fbcon_fbt@psr:
- shard-tglu-1: NOTRUN -> [SKIP][142] ([i915#3469])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_fbcon_fbt@psr.html
* igt@kms_feature_discovery@chamelium:
- shard-dg2: NOTRUN -> [SKIP][143] ([i915#4854])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-3x:
- shard-dg2: NOTRUN -> [SKIP][144] ([i915#1839])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_feature_discovery@display-3x.html
- shard-rkl: NOTRUN -> [SKIP][145] ([i915#1839])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_feature_discovery@display-3x.html
- shard-tglu-1: NOTRUN -> [SKIP][146] ([i915#1839])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_feature_discovery@display-3x.html
* igt@kms_feature_discovery@display-4x:
- shard-dg1: NOTRUN -> [SKIP][147] ([i915#1839])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@kms_feature_discovery@display-4x.html
* igt@kms_feature_discovery@dp-mst:
- shard-mtlp: NOTRUN -> [SKIP][148] ([i915#9337])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-5/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr2:
- shard-tglu-1: NOTRUN -> [SKIP][149] ([i915#658])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_feature_discovery@psr2.html
- shard-dg2: NOTRUN -> [SKIP][150] ([i915#658])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_feature_discovery@psr2.html
- shard-rkl: NOTRUN -> [SKIP][151] ([i915#658])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-tglu: NOTRUN -> [SKIP][152] ([i915#3637])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-4/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-tglu-1: NOTRUN -> [SKIP][153] ([i915#3637]) +3 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset:
- shard-dg1: NOTRUN -> [SKIP][154] ([i915#9934])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible@ab-vga1-hdmi-a1:
- shard-snb: [PASS][155] -> [FAIL][156] ([i915#2122]) +1 other test fail
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-snb6/igt@kms_flip@2x-wf_vblank-ts-check-interruptible@ab-vga1-hdmi-a1.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-snb7/igt@kms_flip@2x-wf_vblank-ts-check-interruptible@ab-vga1-hdmi-a1.html
* igt@kms_flip@flip-vs-blocking-wf-vblank:
- shard-mtlp: [PASS][157] -> [FAIL][158] ([i915#11989] / [i915#2122])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-mtlp-1/igt@kms_flip@flip-vs-blocking-wf-vblank.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-1/igt@kms_flip@flip-vs-blocking-wf-vblank.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
- shard-mtlp: [PASS][159] -> [FAIL][160] ([i915#2122])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-mtlp-1/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-1/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-rkl: NOTRUN -> [FAIL][161] ([i915#2122]) +1 other test fail
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-dg2: [PASS][162] -> [SKIP][163] ([i915#5354]) +5 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-7/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip@wf_vblank-ts-check-interruptible:
- shard-dg2: [PASS][164] -> [FAIL][165] ([i915#2122])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-5/igt@kms_flip@wf_vblank-ts-check-interruptible.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_flip@wf_vblank-ts-check-interruptible.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@a-dp3:
- shard-dg2: NOTRUN -> [FAIL][166] ([i915#2122]) +1 other test fail
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_flip@wf_vblank-ts-check-interruptible@a-dp3.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a1:
- shard-glk: ([PASS][167], [PASS][168]) -> [FAIL][169] ([i915#2122]) +1 other test fail
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk5/igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a1.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk4/igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a1.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk4/igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a1.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@d-hdmi-a1:
- shard-tglu: [PASS][170] -> [FAIL][171] ([i915#2122]) +5 other tests fail
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-tglu-2/igt@kms_flip@wf_vblank-ts-check-interruptible@d-hdmi-a1.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_flip@wf_vblank-ts-check-interruptible@d-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling:
- shard-dg2: [PASS][172] -> [SKIP][173] ([i915#3555]) +2 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-7/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-tglu-1: NOTRUN -> [SKIP][174] ([i915#2587] / [i915#2672] / [i915#3555]) +1 other test skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][175] ([i915#2672]) +5 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
- shard-tglu-1: NOTRUN -> [SKIP][176] ([i915#2587] / [i915#2672]) +2 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling:
- shard-dg2: NOTRUN -> [SKIP][177] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
- shard-tglu-1: NOTRUN -> [SKIP][178] ([i915#2672] / [i915#3555])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][179] ([i915#8708]) +2 other tests skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff:
- shard-mtlp: NOTRUN -> [SKIP][180] ([i915#1825])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
- shard-snb: [PASS][181] -> [SKIP][182] +1 other test skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][183] ([i915#8708]) +7 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
- shard-snb: NOTRUN -> [SKIP][184] +8 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][185] ([i915#3458]) +8 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-tglu: NOTRUN -> [SKIP][186] +12 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render:
- shard-dg1: NOTRUN -> [SKIP][187] +7 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
- shard-rkl: NOTRUN -> [SKIP][188] ([i915#1825]) +24 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
- shard-tglu-1: NOTRUN -> [SKIP][189] +65 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-rkl: NOTRUN -> [SKIP][190] ([i915#9766])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
- shard-tglu-1: NOTRUN -> [SKIP][191] ([i915#9766])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
- shard-dg2: NOTRUN -> [SKIP][192] ([i915#9766])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-rkl: NOTRUN -> [SKIP][193] ([i915#3023]) +15 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
- shard-dg1: NOTRUN -> [SKIP][194] ([i915#3458]) +5 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render:
- shard-dg2: NOTRUN -> [SKIP][195] ([i915#5354]) +25 other tests skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render.html
* igt@kms_hdmi_inject@inject-audio:
- shard-tglu-1: NOTRUN -> [SKIP][196] ([i915#433])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_hdr@bpc-switch:
- shard-dg2: [PASS][197] -> [SKIP][198] ([i915#3555] / [i915#8228]) +1 other test skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-10/igt@kms_hdr@bpc-switch.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@invalid-hdr:
- shard-tglu: NOTRUN -> [SKIP][199] ([i915#3555] / [i915#8228])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-tglu-1: NOTRUN -> [SKIP][200] ([i915#3555] / [i915#8228]) +1 other test skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_hdr@static-toggle:
- shard-rkl: NOTRUN -> [SKIP][201] ([i915#3555] / [i915#8228]) +1 other test skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_hdr@static-toggle.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-tglu-1: NOTRUN -> [SKIP][202] ([i915#12388])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: NOTRUN -> [SKIP][203] ([i915#4070] / [i915#4816])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane@plane-position-covered:
- shard-dg2: [PASS][204] -> [SKIP][205] ([i915#8825])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_plane@plane-position-covered.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_plane@plane-position-covered.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][206] ([i915#8292])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-15/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-d:
- shard-dg1: NOTRUN -> [SKIP][207] ([i915#12247]) +1 other test skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-d.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a:
- shard-rkl: NOTRUN -> [SKIP][208] ([i915#12247]) +2 other tests skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20:
- shard-dg2: NOTRUN -> [SKIP][209] ([i915#12247] / [i915#9423])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b:
- shard-dg2: NOTRUN -> [SKIP][210] ([i915#12247]) +3 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20:
- shard-dg1: [PASS][211] -> [DMESG-WARN][212] ([i915#4423]) +2 other tests dmesg-warn
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-17/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20.html
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25:
- shard-dg2: [PASS][213] -> [SKIP][214] ([i915#6953] / [i915#8152] / [i915#9423])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-a:
- shard-dg2: [PASS][215] -> [SKIP][216] ([i915#12247]) +5 other tests skip
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-a.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-a.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-d:
- shard-dg2: [PASS][217] -> [SKIP][218] ([i915#12247] / [i915#8152]) +1 other test skip
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-d.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-d.html
* igt@kms_plane_scaling@planes-downscale-factor-0-75:
- shard-dg2: [PASS][219] -> [SKIP][220] ([i915#12247] / [i915#3555] / [i915#6953] / [i915#8152] / [i915#9423])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_plane_scaling@planes-downscale-factor-0-75.html
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-75.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
- shard-dg1: NOTRUN -> [SKIP][221] ([i915#12247] / [i915#12504] / [i915#3555])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a:
- shard-dg1: NOTRUN -> [SKIP][222] ([i915#12247] / [i915#12504]) +6 other tests skip
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
- shard-tglu-1: NOTRUN -> [SKIP][223] ([i915#12247] / [i915#6953])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c:
- shard-tglu-1: NOTRUN -> [SKIP][224] ([i915#12247]) +3 other tests skip
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c.html
* igt@kms_pm_backlight@bad-brightness:
- shard-dg1: NOTRUN -> [SKIP][225] ([i915#5354])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_backlight@basic-brightness:
- shard-rkl: NOTRUN -> [SKIP][226] ([i915#5354])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_pm_dc@dc6-psr:
- shard-rkl: NOTRUN -> [SKIP][227] ([i915#9685])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_dc@dc9-dpms:
- shard-tglu: [PASS][228] -> [SKIP][229] ([i915#4281])
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-tglu-3/igt@kms_pm_dc@dc9-dpms.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-8/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_rpm@dpms-mode-unset-lpsp:
- shard-glk: NOTRUN -> [SKIP][230]
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk1/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
- shard-dg1: NOTRUN -> [SKIP][231] ([i915#9519])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-15/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: NOTRUN -> [SKIP][232] ([i915#9519])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
- shard-tglu-1: NOTRUN -> [SKIP][233] ([i915#9519])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-rkl: [PASS][234] -> [SKIP][235] ([i915#9519]) +2 other tests skip
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp.html
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-1/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg2: [PASS][236] -> [SKIP][237] ([i915#9519])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_prime@basic-crc-hybrid:
- shard-tglu: NOTRUN -> [SKIP][238] ([i915#6524])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-dg2: NOTRUN -> [SKIP][239] ([i915#6524] / [i915#6805])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_prime@basic-modeset-hybrid.html
- shard-rkl: NOTRUN -> [SKIP][240] ([i915#6524])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_prime@basic-modeset-hybrid.html
- shard-tglu-1: NOTRUN -> [SKIP][241] ([i915#6524])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
- shard-dg2: NOTRUN -> [SKIP][242] ([i915#11520]) +4 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
- shard-dg1: NOTRUN -> [SKIP][243] ([i915#11520])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html
- shard-mtlp: NOTRUN -> [SKIP][244] ([i915#12316]) +1 other test skip
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-4/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][245] ([i915#9808])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-4/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1.html
* igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf:
- shard-tglu: NOTRUN -> [SKIP][246] ([i915#11520]) +2 other tests skip
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
- shard-tglu-1: NOTRUN -> [SKIP][247] ([i915#11520]) +7 other tests skip
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
- shard-rkl: NOTRUN -> [SKIP][248] ([i915#11520]) +5 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-dg1: NOTRUN -> [SKIP][249] ([i915#9683])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-15/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@fbc-psr-basic:
- shard-rkl: NOTRUN -> [SKIP][250] ([i915#1072] / [i915#9732]) +15 other tests skip
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_psr@fbc-psr-basic.html
* igt@kms_psr@psr-cursor-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][251] ([i915#1072] / [i915#9732]) +12 other tests skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_psr@psr-cursor-mmap-cpu.html
- shard-dg1: NOTRUN -> [SKIP][252] ([i915#1072] / [i915#9732]) +2 other tests skip
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-19/igt@kms_psr@psr-cursor-mmap-cpu.html
* igt@kms_psr@psr-sprite-blt:
- shard-tglu: NOTRUN -> [SKIP][253] ([i915#9732]) +4 other tests skip
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_psr@psr-sprite-blt.html
* igt@kms_psr@psr2-cursor-mmap-gtt:
- shard-tglu-1: NOTRUN -> [SKIP][254] ([i915#9732]) +13 other tests skip
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_psr@psr2-cursor-mmap-gtt.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-rkl: NOTRUN -> [SKIP][255] ([i915#5289])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg1: NOTRUN -> [SKIP][256] ([i915#5289])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][257] ([i915#11131] / [i915#4235])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-rkl: NOTRUN -> [SKIP][258] ([i915#8623])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
- shard-tglu-1: NOTRUN -> [SKIP][259] ([i915#8623])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
- shard-dg2: NOTRUN -> [SKIP][260] ([i915#8623])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_universal_plane@universal-plane-sanity:
- shard-dg2: [PASS][261] -> [SKIP][262] ([i915#9197]) +16 other tests skip
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_universal_plane@universal-plane-sanity.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_universal_plane@universal-plane-sanity.html
* igt@kms_vrr@flip-basic-fastset:
- shard-tglu-1: NOTRUN -> [SKIP][263] ([i915#9906])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@negative-basic:
- shard-mtlp: [PASS][264] -> [FAIL][265] ([i915#10393]) +1 other test fail
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-mtlp-1/igt@kms_vrr@negative-basic.html
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-2/igt@kms_vrr@negative-basic.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-tglu: NOTRUN -> [SKIP][266] ([i915#9906])
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][267] ([i915#2437] / [i915#9412])
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-rkl: NOTRUN -> [SKIP][268] ([i915#2437])
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@per-context-mode-unprivileged:
- shard-rkl: NOTRUN -> [SKIP][269] ([i915#2435])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-5/igt@perf@per-context-mode-unprivileged.html
* igt@perf_pmu@busy-double-start@vcs1:
- shard-dg2: [PASS][270] -> [FAIL][271] ([i915#4349]) +2 other tests fail
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@perf_pmu@busy-double-start@vcs1.html
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@perf_pmu@busy-double-start@vcs1.html
* igt@perf_pmu@module-unload:
- shard-dg2: NOTRUN -> [FAIL][272] ([i915#11823] / [i915#12555])
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@perf_pmu@module-unload.html
* igt@prime_vgem@basic-fence-flip:
- shard-dg2: NOTRUN -> [SKIP][273] ([i915#3708])
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-1/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-write:
- shard-rkl: NOTRUN -> [SKIP][274] ([i915#3291] / [i915#3708])
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@prime_vgem@basic-write.html
* igt@prime_vgem@fence-write-hang:
- shard-rkl: NOTRUN -> [SKIP][275] ([i915#3708])
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@prime_vgem@fence-write-hang.html
* igt@sriov_basic@bind-unbind-vf:
- shard-dg2: NOTRUN -> [SKIP][276] ([i915#9917]) +1 other test skip
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@sriov_basic@bind-unbind-vf.html
- shard-rkl: NOTRUN -> [SKIP][277] ([i915#9917])
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@sriov_basic@bind-unbind-vf.html
- shard-tglu-1: NOTRUN -> [SKIP][278] ([i915#9917])
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-1/igt@sriov_basic@bind-unbind-vf.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-dg1: NOTRUN -> [SKIP][279] ([i915#9917])
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@sriov_basic@enable-vfs-autoprobe-on.html
#### Possible fixes ####
* igt@fbdev@write:
- shard-dg2: [SKIP][280] ([i915#2582]) -> [PASS][281]
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@fbdev@write.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@fbdev@write.html
* igt@gem_ccs@suspend-resume:
- shard-dg2: [INCOMPLETE][282] ([i915#7297]) -> [PASS][283] +1 other test pass
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-4/igt@gem_ccs@suspend-resume.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-8/igt@gem_ccs@suspend-resume.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: [FAIL][284] ([i915#2842]) -> [PASS][285]
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-rkl-7/igt@gem_exec_fair@basic-pace@rcs0.html
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-2/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglu: [ABORT][286] ([i915#10887] / [i915#9820]) -> [PASS][287]
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-tglu-5/igt@i915_module_load@reload-with-fault-injection.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_addfb_basic@bad-pitch-65536:
- shard-dg1: [DMESG-WARN][288] ([i915#4423]) -> [PASS][289] +4 other tests pass
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-13/igt@kms_addfb_basic@bad-pitch-65536.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-18/igt@kms_addfb_basic@bad-pitch-65536.html
* igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:
- shard-glk: ([FAIL][290], [PASS][291]) ([i915#12238]) -> [PASS][292]
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk9/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk2/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
* igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs:
- shard-glk: ([PASS][293], [FAIL][294]) ([i915#11859]) -> [PASS][295]
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk9/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs.html
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs.html
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk2/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-180:
- shard-dg2: [SKIP][296] ([i915#9197]) -> [PASS][297] +31 other tests pass
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
* igt@kms_color@ctm-0-75:
- shard-dg2: [SKIP][298] ([i915#12655]) -> [PASS][299]
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_color@ctm-0-75.html
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_color@ctm-0-75.html
* igt@kms_dp_aux_dev:
- shard-dg2: [SKIP][300] ([i915#1257]) -> [PASS][301]
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_dp_aux_dev.html
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_dp_aux_dev.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
- shard-glk: ([FAIL][302], [FAIL][303]) ([i915#2122]) -> [PASS][304] +1 other test pass
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk2/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk1/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
* igt@kms_flip@2x-plain-flip-ts-check:
- shard-snb: [FAIL][305] ([i915#2122]) -> [PASS][306] +3 other tests pass
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-snb4/igt@kms_flip@2x-plain-flip-ts-check.html
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-snb2/igt@kms_flip@2x-plain-flip-ts-check.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
- shard-dg2: [SKIP][307] ([i915#5354]) -> [PASS][308] +13 other tests pass
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: ([FAIL][309], [PASS][310]) ([i915#79]) -> [PASS][311] +1 other test pass
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk7/igt@kms_flip@flip-vs-expired-vblank.html
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk2/igt@kms_flip@flip-vs-expired-vblank.html
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk1/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-tglu: [FAIL][312] ([i915#79]) -> [PASS][313] +1 other test pass
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-tglu-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@wf_vblank-ts-check-interruptible:
- shard-dg1: [FAIL][314] ([i915#12517] / [i915#2122]) -> [PASS][315]
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-19/igt@kms_flip@wf_vblank-ts-check-interruptible.html
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-12/igt@kms_flip@wf_vblank-ts-check-interruptible.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@c-edp1:
- shard-mtlp: [FAIL][316] ([i915#2122]) -> [PASS][317]
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-mtlp-4/igt@kms_flip@wf_vblank-ts-check-interruptible@c-edp1.html
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-6/igt@kms_flip@wf_vblank-ts-check-interruptible@c-edp1.html
* igt@kms_flip@wf_vblank-ts-check@d-hdmi-a1:
- shard-tglu: [FAIL][318] ([i915#2122]) -> [PASS][319] +3 other tests pass
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-tglu-9/igt@kms_flip@wf_vblank-ts-check@d-hdmi-a1.html
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-9/igt@kms_flip@wf_vblank-ts-check@d-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-dg2: [SKIP][320] ([i915#3555]) -> [PASS][321] +2 other tests pass
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt:
- shard-snb: [SKIP][322] -> [PASS][323] +1 other test pass
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-snb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-dg2: [SKIP][324] ([i915#12388]) -> [PASS][325]
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_joiner@basic-force-big-joiner.html
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_plane@plane-panning-top-left:
- shard-dg2: [SKIP][326] ([i915#8825]) -> [PASS][327] +1 other test pass
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane@plane-panning-top-left.html
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_plane@plane-panning-top-left.html
* igt@kms_plane_alpha_blend@alpha-7efc:
- shard-dg2: [SKIP][328] ([i915#7294]) -> [PASS][329]
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_alpha_blend@alpha-7efc.html
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_plane_alpha_blend@alpha-7efc.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers:
- shard-dg2: [SKIP][330] ([i915#8152] / [i915#9423]) -> [PASS][331] +1 other test pass
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers.html
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers@pipe-d:
- shard-dg2: [SKIP][332] ([i915#8152]) -> [PASS][333] +2 other tests pass
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers@pipe-d.html
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers@pipe-d.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-c:
- shard-dg2: [SKIP][334] ([i915#12247]) -> [PASS][335] +11 other tests pass
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-c.html
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-c.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation:
- shard-dg2: [SKIP][336] ([i915#12247] / [i915#8152] / [i915#9423]) -> [PASS][337]
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation.html
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-d:
- shard-dg2: [SKIP][338] ([i915#12247] / [i915#8152]) -> [PASS][339]
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-d.html
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-d.html
* igt@kms_plane_scaling@planes-upscale-20x20:
- shard-dg2: [SKIP][340] ([i915#6953] / [i915#8152] / [i915#9423]) -> [PASS][341]
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-20x20.html
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_plane_scaling@planes-upscale-20x20.html
* igt@kms_pm_dc@dc6-dpms:
- shard-tglu: [FAIL][342] ([i915#9295]) -> [PASS][343]
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-tglu-8/igt@kms_pm_dc@dc6-dpms.html
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-5/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-rkl: [SKIP][344] ([i915#9519]) -> [PASS][345]
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-rkl-1/igt@kms_pm_rpm@dpms-lpsp.html
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-rkl-7/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@drm-resources-equal:
- shard-dg2: [SKIP][346] ([i915#3547]) -> [PASS][347]
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_pm_rpm@drm-resources-equal.html
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_pm_rpm@drm-resources-equal.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg2: [SKIP][348] ([i915#9519]) -> [PASS][349] +1 other test pass
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_pm_rpm@modeset-lpsp.html
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_setmode@basic:
- shard-tglu: [FAIL][350] ([i915#5465]) -> [PASS][351] +2 other tests pass
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-tglu-4/igt@kms_setmode@basic.html
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-tglu-8/igt@kms_setmode@basic.html
- shard-mtlp: [FAIL][352] ([i915#5465]) -> [PASS][353] +1 other test pass
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-mtlp-4/igt@kms_setmode@basic.html
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-mtlp-2/igt@kms_setmode@basic.html
* igt@perf_pmu@busy-double-start@ccs0:
- shard-dg2: [FAIL][354] ([i915#4349]) -> [PASS][355]
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@perf_pmu@busy-double-start@ccs0.html
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@perf_pmu@busy-double-start@ccs0.html
#### Warnings ####
* igt@gem_exec_fair@basic-deadline:
- shard-glk: ([PASS][356], [FAIL][357]) ([i915#2846]) -> [FAIL][358] ([i915#2846])
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk8/igt@gem_exec_fair@basic-deadline.html
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk9/igt@gem_exec_fair@basic-deadline.html
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: ([FAIL][359], [PASS][360]) ([i915#2842]) -> [FAIL][361] ([i915#2842]) +1 other test fail
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@i915_selftest@mock:
- shard-glk: ([DMESG-WARN][362], [DMESG-WARN][363]) ([i915#1982] / [i915#9311]) -> [DMESG-WARN][364] ([i915#9311])
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk7/igt@i915_selftest@mock.html
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk2/igt@i915_selftest@mock.html
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk1/igt@i915_selftest@mock.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-dg2: [SKIP][365] ([i915#9197]) -> [SKIP][366] +2 other tests skip
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-dg2: [SKIP][367] ([i915#5190] / [i915#9197]) -> [SKIP][368] ([i915#4538] / [i915#5190]) +4 other tests skip
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-dg2: [SKIP][369] ([i915#5190] / [i915#9197]) -> [SKIP][370] ([i915#5190]) +1 other test skip
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-dg2: [SKIP][371] ([i915#4538] / [i915#5190]) -> [SKIP][372] ([i915#5190] / [i915#9197]) +2 other tests skip
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
- shard-dg2: [SKIP][373] ([i915#9197]) -> [SKIP][374] ([i915#12313]) +3 other tests skip
[373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
[374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs:
- shard-dg2: [SKIP][375] ([i915#9197]) -> [SKIP][376] ([i915#10307] / [i915#6095]) +6 other tests skip
[375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs.html
[376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs:
- shard-dg2: [SKIP][377] ([i915#10307] / [i915#6095]) -> [SKIP][378] ([i915#9197]) +5 other tests skip
[377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-7/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs.html
[378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs.html
* igt@kms_cdclk@mode-transition:
- shard-dg2: [SKIP][379] ([i915#9197]) -> [SKIP][380] ([i915#11616] / [i915#7213])
[379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_cdclk@mode-transition.html
[380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_cdclk@mode-transition.html
* igt@kms_content_protection@atomic:
- shard-dg2: [SKIP][381] ([i915#7118] / [i915#9424]) -> [SKIP][382] ([i915#9197]) +1 other test skip
[381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_content_protection@atomic.html
[382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg2: [SKIP][383] ([i915#9197]) -> [SKIP][384] ([i915#7118] / [i915#9424])
[383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_content_protection@atomic-dpms.html
[384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@mei-interface:
- shard-dg2: [SKIP][385] ([i915#9197]) -> [SKIP][386] ([i915#9424])
[385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_content_protection@mei-interface.html
[386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_content_protection@mei-interface.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-dg2: [SKIP][387] ([i915#11453] / [i915#3359]) -> [SKIP][388] ([i915#9197]) +1 other test skip
[387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_cursor_crc@cursor-random-512x512.html
[388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-dg2: [SKIP][389] ([i915#9197]) -> [SKIP][390] ([i915#11453] / [i915#3359])
[389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_cursor_crc@cursor-sliding-512x170.html
[390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-dg2: [SKIP][391] ([i915#5354]) -> [SKIP][392] ([i915#9197]) +2 other tests skip
[391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-7/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
[392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-dg2: [SKIP][393] ([i915#4103] / [i915#4213]) -> [SKIP][394] ([i915#9197])
[393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-dg2: [SKIP][395] ([i915#9197]) -> [SKIP][396] ([i915#5354])
[395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
[396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: ([PASS][397], [FAIL][398]) ([i915#2346]) -> [FAIL][399] ([i915#2346])
[397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[398]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[399]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-dg2: [SKIP][400] ([i915#9197]) -> [SKIP][401] ([i915#9067])
[400]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
[401]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-dg2: [SKIP][402] ([i915#9197]) -> [SKIP][403] ([i915#3555]) +2 other tests skip
[402]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
[403]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_dsc@dsc-with-bpc:
- shard-dg2: [SKIP][404] ([i915#9197]) -> [SKIP][405] ([i915#3555] / [i915#3840])
[404]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_dsc@dsc-with-bpc.html
[405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-dg2: [SKIP][406] ([i915#9197]) -> [SKIP][407] ([i915#3840] / [i915#9053])
[406]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
[407]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-dg1: [SKIP][408] ([i915#9934]) -> [SKIP][409] ([i915#4423] / [i915#9934])
[408]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-15/igt@kms_flip@2x-dpms-vs-vblank-race.html
[409]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-14/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@2x-flip-vs-panning:
- shard-dg1: [INCOMPLETE][410] -> [SKIP][411] ([i915#9934])
[410]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-17/igt@kms_flip@2x-flip-vs-panning.html
[411]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-19/igt@kms_flip@2x-flip-vs-panning.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
- shard-dg2: [SKIP][412] ([i915#3555]) -> [SKIP][413] ([i915#2672] / [i915#3555]) +1 other test skip
[412]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html
[413]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
- shard-dg2: [SKIP][414] ([i915#3555] / [i915#5190]) -> [SKIP][415] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
[414]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
[415]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc:
- shard-dg1: [SKIP][416] ([i915#8708]) -> [SKIP][417] ([i915#4423] / [i915#8708])
[416]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html
[417]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-14/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt:
- shard-dg2: [SKIP][418] ([i915#5354]) -> [SKIP][419] ([i915#8708]) +6 other tests skip
[418]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt.html
[419]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-dg2: [SKIP][420] ([i915#3458]) -> [SKIP][421] ([i915#10433] / [i915#3458]) +1 other test skip
[420]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-10/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[421]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-dg2: [SKIP][422] ([i915#5354]) -> [SKIP][423] ([i915#10433] / [i915#3458])
[422]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
[423]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu:
- shard-dg2: [SKIP][424] ([i915#5354]) -> [SKIP][425] ([i915#3458]) +16 other tests skip
[424]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
[425]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: [SKIP][426] ([i915#3458]) -> [SKIP][427] ([i915#5354]) +1 other test skip
[426]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
[427]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move:
- shard-dg1: [SKIP][428] ([i915#4423]) -> [SKIP][429]
[428]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg1-18/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html
[429]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
- shard-dg2: [SKIP][430] ([i915#8708]) -> [SKIP][431] ([i915#5354]) +8 other tests skip
[430]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
[431]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
* igt@kms_hdr@static-swap:
- shard-dg2: [SKIP][432] ([i915#9197]) -> [SKIP][433] ([i915#3555] / [i915#8228]) +1 other test skip
[432]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_hdr@static-swap.html
[433]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_hdr@static-swap.html
* igt@kms_plane_lowres@tiling-yf:
- shard-dg2: [SKIP][434] ([i915#9197]) -> [SKIP][435] ([i915#3555] / [i915#8821])
[434]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_lowres@tiling-yf.html
[435]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-4/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
- shard-dg2: [SKIP][436] ([i915#12247] / [i915#6953] / [i915#8152] / [i915#9423]) -> [SKIP][437] ([i915#12247] / [i915#6953] / [i915#9423])
[436]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
[437]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d:
- shard-dg2: [SKIP][438] ([i915#12247] / [i915#8152]) -> [SKIP][439] ([i915#12247])
[438]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d.html
[439]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-dg2: [SKIP][440] ([i915#11131] / [i915#4235]) -> [SKIP][441] ([i915#9197])
[440]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_rotation_crc@bad-pixel-format.html
[441]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-dg2: [SKIP][442] ([i915#11131] / [i915#4235] / [i915#5190]) -> [SKIP][443] ([i915#5190] / [i915#9197])
[442]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
[443]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-dg2: [SKIP][444] ([i915#9197]) -> [SKIP][445] ([i915#11131] / [i915#4235])
[444]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_rotation_crc@sprite-rotation-270.html
[445]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-7/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_vrr@flip-basic-fastset:
- shard-dg2: [SKIP][446] ([i915#9197]) -> [SKIP][447] ([i915#9906])
[446]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-2/igt@kms_vrr@flip-basic-fastset.html
[447]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-10/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-dg2: [SKIP][448] ([i915#9906]) -> [SKIP][449] ([i915#9197])
[448]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15607/shard-dg2-7/igt@kms_vrr@seamless-rr-switch-vrr.html
[449]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/shard-dg2-2/igt@kms_vrr@seamless-rr-switch-vrr.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10354
[i915#10393]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10393
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]:
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140324v6/index.html
[-- Attachment #2: Type: text/html, Size: 108880 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread