* [PATCH 0/6] drm/i915: Some intel_display conversions
@ 2024-09-06 14:33 Ville Syrjala
2024-09-06 14:33 ` [PATCH 1/6] drm/i915/cdclk: Add missing braces Ville Syrjala
` (10 more replies)
0 siblings, 11 replies; 23+ messages in thread
From: Ville Syrjala @ 2024-09-06 14:33 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
I somehow ended up in the power domains code and decided
to see how much of it could be converted to use struct
intel_display. The result was still too messy but at least
I managed to convert some of the dependecies in somewhat
decent way. Here they are.
Ville Syrjälä (6):
drm/i915/cdclk: Add missing braces
drm/i915/cdclk: Convert CDCLK code to intel_display
drm/i915/power: Convert low level DC state code to intel_display
drm/i915/vga: Convert VGA code to intel_display
drm/i915/power: Convert "i830 power well" code to intel_display
drm/i915/dmc: Convert DMC code to intel_display
drivers/gpu/drm/i915/display/intel_cdclk.c | 1171 +++++++++--------
drivers/gpu/drm/i915/display/intel_cdclk.h | 24 +-
drivers/gpu/drm/i915/display/intel_display.c | 86 +-
drivers/gpu/drm/i915/display/intel_display.h | 5 +-
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../drm/i915/display/intel_display_device.c | 2 +-
.../drm/i915/display/intel_display_driver.c | 34 +-
.../drm/i915/display/intel_display_power.c | 93 +-
.../i915/display/intel_display_power_well.c | 238 ++--
.../i915/display/intel_display_power_well.h | 15 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 391 +++---
drivers/gpu/drm/i915/display/intel_dmc.h | 26 +-
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 4 +-
.../drm/i915/display/intel_modeset_setup.c | 3 +-
drivers/gpu/drm/i915/display/intel_vga.c | 45 +-
drivers/gpu/drm/i915/display/intel_vga.h | 14 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 3 +-
drivers/gpu/drm/i915/i915_driver.c | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/i915_suspend.c | 3 +-
drivers/gpu/drm/xe/display/xe_display.c | 4 +-
21 files changed, 1137 insertions(+), 1036 deletions(-)
--
2.44.2
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 1/6] drm/i915/cdclk: Add missing braces
2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala
@ 2024-09-06 14:33 ` Ville Syrjala
2024-09-06 15:10 ` Rodrigo Vivi
2024-09-06 15:19 ` Jani Nikula
2024-09-06 14:33 ` [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display Ville Syrjala
` (9 subsequent siblings)
10 siblings, 2 replies; 23+ messages in thread
From: Ville Syrjala @ 2024-09-06 14:33 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
CodingStyle says when one branch of an if ladder is braced
then all of them should be. Make it so.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 66964c7d2a2c..9d870d15d888 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2053,8 +2053,9 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
dg2_cdclk_squash_program(dev_priv, 0);
icl_cdclk_pll_update(dev_priv, vco);
- } else
+ } else {
bxt_cdclk_pll_update(dev_priv, vco);
+ }
if (HAS_CDCLK_SQUASH(dev_priv)) {
u16 waveform = cdclk_squash_waveform(dev_priv, cdclk);
--
2.44.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display
2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala
2024-09-06 14:33 ` [PATCH 1/6] drm/i915/cdclk: Add missing braces Ville Syrjala
@ 2024-09-06 14:33 ` Ville Syrjala
2024-09-06 15:09 ` Rodrigo Vivi
2024-09-06 15:18 ` Jani Nikula
2024-09-06 14:33 ` [PATCH 3/6] drm/i915/power: Convert low level DC state " Ville Syrjala
` (8 subsequent siblings)
10 siblings, 2 replies; 23+ messages in thread
From: Ville Syrjala @ 2024-09-06 14:33 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert the CDCLK code to
use it (as much as possible at this stage).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 1168 +++++++++--------
drivers/gpu/drm/i915/display/intel_cdclk.h | 24 +-
.../drm/i915/display/intel_display_debugfs.c | 2 +-
.../drm/i915/display/intel_display_device.c | 2 +-
.../drm/i915/display/intel_display_driver.c | 17 +-
.../drm/i915/display/intel_display_power.c | 35 +-
.../i915/display/intel_display_power_well.c | 9 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 3 +-
8 files changed, 657 insertions(+), 603 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9d870d15d888..b4eda0a2a45d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -113,81 +113,81 @@
*/
struct intel_cdclk_funcs {
- void (*get_cdclk)(struct drm_i915_private *i915,
+ void (*get_cdclk)(struct intel_display *display,
struct intel_cdclk_config *cdclk_config);
- void (*set_cdclk)(struct drm_i915_private *i915,
+ void (*set_cdclk)(struct intel_display *display,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe);
int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
u8 (*calc_voltage_level)(int cdclk);
};
-void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
+void intel_cdclk_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
- dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config);
+ display->funcs.cdclk->get_cdclk(display, cdclk_config);
}
-static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
+static void intel_cdclk_set_cdclk(struct intel_display *display,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe);
+ display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe);
}
static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
- return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(state);
+ return display->funcs.cdclk->modeset_calc_cdclk(state);
}
-static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
+static u8 intel_cdclk_calc_voltage_level(struct intel_display *display,
int cdclk)
{
- return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk);
+ return display->funcs.cdclk->calc_voltage_level(cdclk);
}
-static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
+static void fixed_133mhz_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
cdclk_config->cdclk = 133333;
}
-static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
+static void fixed_200mhz_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
cdclk_config->cdclk = 200000;
}
-static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
+static void fixed_266mhz_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
cdclk_config->cdclk = 266667;
}
-static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
+static void fixed_333mhz_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
cdclk_config->cdclk = 333333;
}
-static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
+static void fixed_400mhz_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
cdclk_config->cdclk = 400000;
}
-static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
+static void fixed_450mhz_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
cdclk_config->cdclk = 450000;
}
-static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
+static void i85x_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
- struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct pci_dev *pdev = to_pci_dev(display->drm->dev);
u16 hpllcc = 0;
/*
@@ -226,10 +226,10 @@ static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
}
}
-static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
+static void i915gm_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
- struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct pci_dev *pdev = to_pci_dev(display->drm->dev);
u16 gcfgc = 0;
pci_read_config_word(pdev, GCFGC, &gcfgc);
@@ -250,10 +250,10 @@ static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
}
}
-static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
+static void i945gm_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
- struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct pci_dev *pdev = to_pci_dev(display->drm->dev);
u16 gcfgc = 0;
pci_read_config_word(pdev, GCFGC, &gcfgc);
@@ -274,7 +274,7 @@ static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
}
}
-static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
+static unsigned int intel_hpll_vco(struct intel_display *display)
{
static const unsigned int blb_vco[8] = {
[0] = 3200000,
@@ -313,6 +313,7 @@ static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
[4] = 2666667,
[5] = 4266667,
};
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
const unsigned int *vco_table;
unsigned int vco;
u8 tmp = 0;
@@ -331,23 +332,23 @@ static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
else
return 0;
- tmp = intel_de_read(dev_priv,
+ tmp = intel_de_read(display,
IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
vco = vco_table[tmp & 0x7];
if (vco == 0)
- drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
+ drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
tmp);
else
- drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco);
+ drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco);
return vco;
}
-static void g33_get_cdclk(struct drm_i915_private *dev_priv,
+static void g33_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
- struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct pci_dev *pdev = to_pci_dev(display->drm->dev);
static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
@@ -356,7 +357,7 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv,
unsigned int cdclk_sel;
u16 tmp = 0;
- cdclk_config->vco = intel_hpll_vco(dev_priv);
+ cdclk_config->vco = intel_hpll_vco(display);
pci_read_config_word(pdev, GCFGC, &tmp);
@@ -387,16 +388,16 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv,
return;
fail:
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
cdclk_config->vco, tmp);
cdclk_config->cdclk = 190476;
}
-static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
+static void pnv_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
- struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct pci_dev *pdev = to_pci_dev(display->drm->dev);
u16 gcfgc = 0;
pci_read_config_word(pdev, GCFGC, &gcfgc);
@@ -415,7 +416,7 @@ static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
cdclk_config->cdclk = 200000;
break;
default:
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"Unknown pnv display core clock 0x%04x\n", gcfgc);
fallthrough;
case GC_DISPLAY_CLOCK_133_MHZ_PNV:
@@ -427,10 +428,10 @@ static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
}
}
-static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
+static void i965gm_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
- struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct pci_dev *pdev = to_pci_dev(display->drm->dev);
static const u8 div_3200[] = { 16, 10, 8 };
static const u8 div_4000[] = { 20, 12, 10 };
static const u8 div_5333[] = { 24, 16, 14 };
@@ -438,7 +439,7 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
unsigned int cdclk_sel;
u16 tmp = 0;
- cdclk_config->vco = intel_hpll_vco(dev_priv);
+ cdclk_config->vco = intel_hpll_vco(display);
pci_read_config_word(pdev, GCFGC, &tmp);
@@ -466,20 +467,20 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
return;
fail:
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
cdclk_config->vco, tmp);
cdclk_config->cdclk = 200000;
}
-static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
+static void gm45_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
- struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct pci_dev *pdev = to_pci_dev(display->drm->dev);
unsigned int cdclk_sel;
u16 tmp = 0;
- cdclk_config->vco = intel_hpll_vco(dev_priv);
+ cdclk_config->vco = intel_hpll_vco(display);
pci_read_config_word(pdev, GCFGC, &tmp);
@@ -495,7 +496,7 @@ static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
break;
default:
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
cdclk_config->vco, tmp);
cdclk_config->cdclk = 222222;
@@ -503,15 +504,16 @@ static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
}
}
-static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
+static void hsw_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
- u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+ u32 lcpll = intel_de_read(display, LCPLL_CTL);
u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
if (lcpll & LCPLL_CD_SOURCE_FCLK)
cdclk_config->cdclk = 800000;
- else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
+ else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
cdclk_config->cdclk = 450000;
else if (freq == LCPLL_CLK_FREQ_450)
cdclk_config->cdclk = 450000;
@@ -521,8 +523,9 @@ static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
cdclk_config->cdclk = 540000;
}
-static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
+static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
333333 : 320000;
@@ -541,8 +544,10 @@ static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
return 200000;
}
-static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
+static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
if (IS_VALLEYVIEW(dev_priv)) {
if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
return 2;
@@ -560,9 +565,10 @@ static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
}
}
-static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
+static void vlv_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 val;
vlv_iosf_sb_get(dev_priv,
@@ -586,8 +592,9 @@ static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
DSPFREQGUAR_SHIFT_CHV;
}
-static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
+static void vlv_program_pfi_credits(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
unsigned int credits, default_credits;
if (IS_CHERRYVIEW(dev_priv))
@@ -595,7 +602,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
else
default_credits = PFI_CREDIT(8);
- if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) {
+ if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
/* CHV suggested value is 31 or 63 */
if (IS_CHERRYVIEW(dev_priv))
credits = PFI_CREDIT_63;
@@ -609,24 +616,25 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
* WA - write default credits before re-programming
* FIXME: should we also set the resend bit here?
*/
- intel_de_write(dev_priv, GCI_CONTROL,
+ intel_de_write(display, GCI_CONTROL,
VGA_FAST_MODE_DISABLE | default_credits);
- intel_de_write(dev_priv, GCI_CONTROL,
+ intel_de_write(display, GCI_CONTROL,
VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
/*
* FIXME is this guaranteed to clear
* immediately or should we poll for it?
*/
- drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);
+ drm_WARN_ON(display->drm,
+ intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND);
}
-static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
+static void vlv_set_cdclk(struct intel_display *display,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
int cdclk = cdclk_config->cdclk;
u32 val, cmd = cdclk_config->voltage_level;
intel_wakeref_t wakeref;
@@ -663,7 +671,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
50)) {
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"timed out waiting for CDclk change\n");
}
@@ -682,7 +690,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
50))
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"timed out waiting for CDclk change\n");
}
@@ -705,17 +713,18 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
BIT(VLV_IOSF_SB_BUNIT) |
BIT(VLV_IOSF_SB_PUNIT));
- intel_update_cdclk(dev_priv);
+ intel_update_cdclk(display);
- vlv_program_pfi_credits(dev_priv);
+ vlv_program_pfi_credits(display);
intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
}
-static void chv_set_cdclk(struct drm_i915_private *dev_priv,
+static void chv_set_cdclk(struct intel_display *display,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
int cdclk = cdclk_config->cdclk;
u32 val, cmd = cdclk_config->voltage_level;
intel_wakeref_t wakeref;
@@ -747,15 +756,15 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
50)) {
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"timed out waiting for CDclk change\n");
}
vlv_punit_put(dev_priv);
- intel_update_cdclk(dev_priv);
+ intel_update_cdclk(display);
- vlv_program_pfi_credits(dev_priv);
+ vlv_program_pfi_credits(display);
intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
}
@@ -787,15 +796,15 @@ static u8 bdw_calc_voltage_level(int cdclk)
}
}
-static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
+static void bdw_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
- u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
+ u32 lcpll = intel_de_read(display, LCPLL_CTL);
u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
if (lcpll & LCPLL_CD_SOURCE_FCLK)
cdclk_config->cdclk = 800000;
- else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
+ else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
cdclk_config->cdclk = 450000;
else if (freq == LCPLL_CLK_FREQ_450)
cdclk_config->cdclk = 450000;
@@ -831,15 +840,16 @@ static u32 bdw_cdclk_freq_sel(int cdclk)
}
}
-static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
+static void bdw_set_cdclk(struct intel_display *display,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
int cdclk = cdclk_config->cdclk;
int ret;
- if (drm_WARN(&dev_priv->drm,
- (intel_de_read(dev_priv, LCPLL_CTL) &
+ if (drm_WARN(display->drm,
+ (intel_de_read(display, LCPLL_CTL) &
(LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
@@ -849,39 +859,39 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
if (ret) {
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"failed to inform pcode about cdclk change\n");
return;
}
- intel_de_rmw(dev_priv, LCPLL_CTL,
+ intel_de_rmw(display, LCPLL_CTL,
0, LCPLL_CD_SOURCE_FCLK);
/*
* According to the spec, it should be enough to poll for this 1 us.
* However, extensive testing shows that this can take longer.
*/
- if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
+ if (wait_for_us(intel_de_read(display, LCPLL_CTL) &
LCPLL_CD_SOURCE_FCLK_DONE, 100))
- drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
+ drm_err(display->drm, "Switching to FCLK failed\n");
- intel_de_rmw(dev_priv, LCPLL_CTL,
+ intel_de_rmw(display, LCPLL_CTL,
LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk));
- intel_de_rmw(dev_priv, LCPLL_CTL,
+ intel_de_rmw(display, LCPLL_CTL,
LCPLL_CD_SOURCE_FCLK, 0);
- if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
+ if (wait_for_us((intel_de_read(display, LCPLL_CTL) &
LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
- drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
+ drm_err(display->drm, "Switching back to LCPLL failed\n");
snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ,
cdclk_config->voltage_level);
- intel_de_write(dev_priv, CDCLK_FREQ,
+ intel_de_write(display, CDCLK_FREQ,
DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
- intel_update_cdclk(dev_priv);
+ intel_update_cdclk(display);
}
static int skl_calc_cdclk(int min_cdclk, int vco)
@@ -919,7 +929,7 @@ static u8 skl_calc_voltage_level(int cdclk)
return 0;
}
-static void skl_dpll0_update(struct drm_i915_private *dev_priv,
+static void skl_dpll0_update(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
u32 val;
@@ -927,16 +937,16 @@ static void skl_dpll0_update(struct drm_i915_private *dev_priv,
cdclk_config->ref = 24000;
cdclk_config->vco = 0;
- val = intel_de_read(dev_priv, LCPLL1_CTL);
+ val = intel_de_read(display, LCPLL1_CTL);
if ((val & LCPLL_PLL_ENABLE) == 0)
return;
- if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0))
+ if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0))
return;
- val = intel_de_read(dev_priv, DPLL_CTRL1);
+ val = intel_de_read(display, DPLL_CTRL1);
- if (drm_WARN_ON(&dev_priv->drm,
+ if (drm_WARN_ON(display->drm,
(val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
DPLL_CTRL1_SSC(SKL_DPLL0) |
DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
@@ -960,19 +970,19 @@ static void skl_dpll0_update(struct drm_i915_private *dev_priv,
}
}
-static void skl_get_cdclk(struct drm_i915_private *dev_priv,
+static void skl_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
u32 cdctl;
- skl_dpll0_update(dev_priv, cdclk_config);
+ skl_dpll0_update(display, cdclk_config);
cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
if (cdclk_config->vco == 0)
goto out;
- cdctl = intel_de_read(dev_priv, CDCLK_CTL);
+ cdctl = intel_de_read(display, CDCLK_CTL);
if (cdclk_config->vco == 8640000) {
switch (cdctl & CDCLK_FREQ_SEL_MASK) {
@@ -1027,19 +1037,19 @@ static int skl_cdclk_decimal(int cdclk)
return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
}
-static void skl_set_preferred_cdclk_vco(struct drm_i915_private *i915, int vco)
+static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco)
{
- bool changed = i915->display.cdclk.skl_preferred_vco_freq != vco;
+ bool changed = display->cdclk.skl_preferred_vco_freq != vco;
- i915->display.cdclk.skl_preferred_vco_freq = vco;
+ display->cdclk.skl_preferred_vco_freq = vco;
if (changed)
- intel_update_max_cdclk(i915);
+ intel_update_max_cdclk(display);
}
-static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco)
+static u32 skl_dpll0_link_rate(struct intel_display *display, int vco)
{
- drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
+ drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
/*
* We always enable DPLL0 with the lowest link rate possible, but still
@@ -1056,47 +1066,47 @@ static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco)
return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0);
}
-static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
+static void skl_dpll0_enable(struct intel_display *display, int vco)
{
- intel_de_rmw(dev_priv, DPLL_CTRL1,
+ intel_de_rmw(display, DPLL_CTRL1,
DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
DPLL_CTRL1_SSC(SKL_DPLL0) |
DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0),
DPLL_CTRL1_OVERRIDE(SKL_DPLL0) |
- skl_dpll0_link_rate(dev_priv, vco));
- intel_de_posting_read(dev_priv, DPLL_CTRL1);
+ skl_dpll0_link_rate(display, vco));
+ intel_de_posting_read(display, DPLL_CTRL1);
- intel_de_rmw(dev_priv, LCPLL1_CTL,
+ intel_de_rmw(display, LCPLL1_CTL,
0, LCPLL_PLL_ENABLE);
- if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
- drm_err(&dev_priv->drm, "DPLL0 not locked\n");
+ if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
+ drm_err(display->drm, "DPLL0 not locked\n");
- dev_priv->display.cdclk.hw.vco = vco;
+ display->cdclk.hw.vco = vco;
/* We'll want to keep using the current vco from now on. */
- skl_set_preferred_cdclk_vco(dev_priv, vco);
+ skl_set_preferred_cdclk_vco(display, vco);
}
-static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
+static void skl_dpll0_disable(struct intel_display *display)
{
- intel_de_rmw(dev_priv, LCPLL1_CTL,
+ intel_de_rmw(display, LCPLL1_CTL,
LCPLL_PLL_ENABLE, 0);
- if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
- drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
+ if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
+ drm_err(display->drm, "Couldn't disable DPLL0\n");
- dev_priv->display.cdclk.hw.vco = 0;
+ display->cdclk.hw.vco = 0;
}
-static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
+static u32 skl_cdclk_freq_sel(struct intel_display *display,
int cdclk, int vco)
{
switch (cdclk) {
default:
- drm_WARN_ON(&dev_priv->drm,
- cdclk != dev_priv->display.cdclk.hw.bypass);
- drm_WARN_ON(&dev_priv->drm, vco != 0);
+ drm_WARN_ON(display->drm,
+ cdclk != display->cdclk.hw.bypass);
+ drm_WARN_ON(display->drm, vco != 0);
fallthrough;
case 308571:
case 337500:
@@ -1112,10 +1122,11 @@ static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
}
}
-static void skl_set_cdclk(struct drm_i915_private *dev_priv,
+static void skl_set_cdclk(struct intel_display *display,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
int cdclk = cdclk_config->cdclk;
int vco = cdclk_config->vco;
u32 freq_select, cdclk_ctl;
@@ -1129,7 +1140,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
* use the corresponding VCO freq as that always leads to using the
* minimum 308MHz CDCLK.
*/
- drm_WARN_ON_ONCE(&dev_priv->drm,
+ drm_WARN_ON_ONCE(display->drm,
IS_SKYLAKE(dev_priv) && vco == 8640000);
ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
@@ -1137,54 +1148,54 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
SKL_CDCLK_READY_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE, 3);
if (ret) {
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"Failed to inform PCU about cdclk change (%d)\n", ret);
return;
}
- freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco);
+ freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
- if (dev_priv->display.cdclk.hw.vco != 0 &&
- dev_priv->display.cdclk.hw.vco != vco)
- skl_dpll0_disable(dev_priv);
+ if (display->cdclk.hw.vco != 0 &&
+ display->cdclk.hw.vco != vco)
+ skl_dpll0_disable(display);
- cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);
+ cdclk_ctl = intel_de_read(display, CDCLK_CTL);
- if (dev_priv->display.cdclk.hw.vco != vco) {
+ if (display->cdclk.hw.vco != vco) {
/* Wa Display #1183: skl,kbl,cfl */
cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
- intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
+ intel_de_write(display, CDCLK_CTL, cdclk_ctl);
}
/* Wa Display #1183: skl,kbl,cfl */
cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
- intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
- intel_de_posting_read(dev_priv, CDCLK_CTL);
+ intel_de_write(display, CDCLK_CTL, cdclk_ctl);
+ intel_de_posting_read(display, CDCLK_CTL);
- if (dev_priv->display.cdclk.hw.vco != vco)
- skl_dpll0_enable(dev_priv, vco);
+ if (display->cdclk.hw.vco != vco)
+ skl_dpll0_enable(display, vco);
/* Wa Display #1183: skl,kbl,cfl */
cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
- intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
+ intel_de_write(display, CDCLK_CTL, cdclk_ctl);
cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
- intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
+ intel_de_write(display, CDCLK_CTL, cdclk_ctl);
/* Wa Display #1183: skl,kbl,cfl */
cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
- intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
- intel_de_posting_read(dev_priv, CDCLK_CTL);
+ intel_de_write(display, CDCLK_CTL, cdclk_ctl);
+ intel_de_posting_read(display, CDCLK_CTL);
/* inform PCU of the change */
snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
cdclk_config->voltage_level);
- intel_update_cdclk(dev_priv);
+ intel_update_cdclk(display);
}
-static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
+static void skl_sanitize_cdclk(struct intel_display *display)
{
u32 cdctl, expected;
@@ -1193,15 +1204,15 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
* There is SWF18 scratchpad register defined which is set by the
* pre-os which can be used by the OS drivers to check the status
*/
- if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
+ if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
goto sanitize;
- intel_update_cdclk(dev_priv);
- intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
+ intel_update_cdclk(display);
+ intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
/* Is PLL enabled and locked ? */
- if (dev_priv->display.cdclk.hw.vco == 0 ||
- dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
+ if (display->cdclk.hw.vco == 0 ||
+ display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
goto sanitize;
/* DPLL okay; verify the cdclock
@@ -1210,60 +1221,60 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
* decimal part is programmed wrong from BIOS where pre-os does not
* enable display. Verify the same as well.
*/
- cdctl = intel_de_read(dev_priv, CDCLK_CTL);
+ cdctl = intel_de_read(display, CDCLK_CTL);
expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
- skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk);
+ skl_cdclk_decimal(display->cdclk.hw.cdclk);
if (cdctl == expected)
/* All well; nothing to sanitize */
return;
sanitize:
- drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
+ drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
/* force cdclk programming */
- dev_priv->display.cdclk.hw.cdclk = 0;
+ display->cdclk.hw.cdclk = 0;
/* force full PLL disable + enable */
- dev_priv->display.cdclk.hw.vco = ~0;
+ display->cdclk.hw.vco = ~0;
}
-static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
+static void skl_cdclk_init_hw(struct intel_display *display)
{
struct intel_cdclk_config cdclk_config;
- skl_sanitize_cdclk(dev_priv);
+ skl_sanitize_cdclk(display);
- if (dev_priv->display.cdclk.hw.cdclk != 0 &&
- dev_priv->display.cdclk.hw.vco != 0) {
+ if (display->cdclk.hw.cdclk != 0 &&
+ display->cdclk.hw.vco != 0) {
/*
* Use the current vco as our initial
* guess as to what the preferred vco is.
*/
- if (dev_priv->display.cdclk.skl_preferred_vco_freq == 0)
- skl_set_preferred_cdclk_vco(dev_priv,
- dev_priv->display.cdclk.hw.vco);
+ if (display->cdclk.skl_preferred_vco_freq == 0)
+ skl_set_preferred_cdclk_vco(display,
+ display->cdclk.hw.vco);
return;
}
- cdclk_config = dev_priv->display.cdclk.hw;
+ cdclk_config = display->cdclk.hw;
- cdclk_config.vco = dev_priv->display.cdclk.skl_preferred_vco_freq;
+ cdclk_config.vco = display->cdclk.skl_preferred_vco_freq;
if (cdclk_config.vco == 0)
cdclk_config.vco = 8100000;
cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
- skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
+ skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
}
-static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
+static void skl_cdclk_uninit_hw(struct intel_display *display)
{
- struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
+ struct intel_cdclk_config cdclk_config = display->cdclk.hw;
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
- skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
+ skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
}
struct intel_cdclk_vals {
@@ -1471,37 +1482,37 @@ static int cdclk_divider(int cdclk, int vco, u16 waveform)
cdclk * cdclk_squash_len);
}
-static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
+static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk)
{
- const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
+ const struct intel_cdclk_vals *table = display->cdclk.table;
int i;
for (i = 0; table[i].refclk; i++)
- if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
+ if (table[i].refclk == display->cdclk.hw.ref &&
table[i].cdclk >= min_cdclk)
return table[i].cdclk;
- drm_WARN(&dev_priv->drm, 1,
+ drm_WARN(display->drm, 1,
"Cannot satisfy minimum cdclk %d with refclk %u\n",
- min_cdclk, dev_priv->display.cdclk.hw.ref);
+ min_cdclk, display->cdclk.hw.ref);
return 0;
}
-static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
+static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk)
{
- const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
+ const struct intel_cdclk_vals *table = display->cdclk.table;
int i;
- if (cdclk == dev_priv->display.cdclk.hw.bypass)
+ if (cdclk == display->cdclk.hw.bypass)
return 0;
for (i = 0; table[i].refclk; i++)
- if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
+ if (table[i].refclk == display->cdclk.hw.ref &&
table[i].cdclk == cdclk)
- return dev_priv->display.cdclk.hw.ref * table[i].ratio;
+ return display->cdclk.hw.ref * table[i].ratio;
- drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
- cdclk, dev_priv->display.cdclk.hw.ref);
+ drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
+ cdclk, display->cdclk.hw.ref);
return 0;
}
@@ -1583,10 +1594,10 @@ static u8 rplu_calc_voltage_level(int cdclk)
rplu_voltage_level_max_cdclk);
}
-static void icl_readout_refclk(struct drm_i915_private *dev_priv,
+static void icl_readout_refclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
- u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
+ u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
switch (dssm) {
default:
@@ -1604,19 +1615,20 @@ static void icl_readout_refclk(struct drm_i915_private *dev_priv,
}
}
-static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
+static void bxt_de_pll_readout(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 val, ratio;
if (IS_DG2(dev_priv))
cdclk_config->ref = 38400;
- else if (DISPLAY_VER(dev_priv) >= 11)
- icl_readout_refclk(dev_priv, cdclk_config);
+ else if (DISPLAY_VER(display) >= 11)
+ icl_readout_refclk(display, cdclk_config);
else
cdclk_config->ref = 19200;
- val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);
+ val = intel_de_read(display, BXT_DE_PLL_ENABLE);
if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
(val & BXT_DE_PLL_LOCK) == 0) {
/*
@@ -1631,26 +1643,26 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
* DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
* gen9lp had it in a separate PLL control register.
*/
- if (DISPLAY_VER(dev_priv) >= 11)
+ if (DISPLAY_VER(display) >= 11)
ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
else
- ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
+ ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
cdclk_config->vco = ratio * cdclk_config->ref;
}
-static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
+static void bxt_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config)
{
u32 squash_ctl = 0;
u32 divider;
int div;
- bxt_de_pll_readout(dev_priv, cdclk_config);
+ bxt_de_pll_readout(display, cdclk_config);
- if (DISPLAY_VER(dev_priv) >= 12)
+ if (DISPLAY_VER(display) >= 12)
cdclk_config->bypass = cdclk_config->ref / 2;
- else if (DISPLAY_VER(dev_priv) >= 11)
+ else if (DISPLAY_VER(display) >= 11)
cdclk_config->bypass = 50000;
else
cdclk_config->bypass = cdclk_config->ref;
@@ -1660,7 +1672,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
goto out;
}
- divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
+ divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
switch (divider) {
case BXT_CDCLK_CD2X_DIV_SEL_1:
@@ -1680,8 +1692,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
return;
}
- if (HAS_CDCLK_SQUASH(dev_priv))
- squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
+ if (HAS_CDCLK_SQUASH(display))
+ squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL);
if (squash_ctl & CDCLK_SQUASH_ENABLE) {
u16 waveform;
@@ -1697,107 +1709,107 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
}
out:
- if (DISPLAY_VER(dev_priv) >= 20)
- cdclk_config->joined_mbus = intel_de_read(dev_priv, MBUS_CTL) & MBUS_JOIN;
+ if (DISPLAY_VER(display) >= 20)
+ cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;
/*
* Can't read this out :( Let's assume it's
* at least what the CDCLK frequency requires.
*/
cdclk_config->voltage_level =
- intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk);
+ intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk);
}
-static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
+static void bxt_de_pll_disable(struct intel_display *display)
{
- intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0);
+ intel_de_write(display, BXT_DE_PLL_ENABLE, 0);
/* Timeout 200us */
- if (intel_de_wait_for_clear(dev_priv,
+ if (intel_de_wait_for_clear(display,
BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
- drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");
+ drm_err(display->drm, "timeout waiting for DE PLL unlock\n");
- dev_priv->display.cdclk.hw.vco = 0;
+ display->cdclk.hw.vco = 0;
}
-static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
+static void bxt_de_pll_enable(struct intel_display *display, int vco)
{
- int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
+ int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
- intel_de_rmw(dev_priv, BXT_DE_PLL_CTL,
+ intel_de_rmw(display, BXT_DE_PLL_CTL,
BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
- intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
+ intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
/* Timeout 200us */
- if (intel_de_wait_for_set(dev_priv,
+ if (intel_de_wait_for_set(display,
BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
- drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");
+ drm_err(display->drm, "timeout waiting for DE PLL lock\n");
- dev_priv->display.cdclk.hw.vco = vco;
+ display->cdclk.hw.vco = vco;
}
-static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
+static void icl_cdclk_pll_disable(struct intel_display *display)
{
- intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE,
+ intel_de_rmw(display, BXT_DE_PLL_ENABLE,
BXT_DE_PLL_PLL_ENABLE, 0);
/* Timeout 200us */
- if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
- drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n");
+ if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
+ drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n");
- dev_priv->display.cdclk.hw.vco = 0;
+ display->cdclk.hw.vco = 0;
}
-static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
+static void icl_cdclk_pll_enable(struct intel_display *display, int vco)
{
- int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
+ int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
u32 val;
val = ICL_CDCLK_PLL_RATIO(ratio);
- intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+ intel_de_write(display, BXT_DE_PLL_ENABLE, val);
val |= BXT_DE_PLL_PLL_ENABLE;
- intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+ intel_de_write(display, BXT_DE_PLL_ENABLE, val);
/* Timeout 200us */
- if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
- drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n");
+ if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
+ drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n");
- dev_priv->display.cdclk.hw.vco = vco;
+ display->cdclk.hw.vco = vco;
}
-static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
+static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco)
{
- int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
+ int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
u32 val;
/* Write PLL ratio without disabling */
val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
- intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+ intel_de_write(display, BXT_DE_PLL_ENABLE, val);
/* Submit freq change request */
val |= BXT_DE_PLL_FREQ_REQ;
- intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+ intel_de_write(display, BXT_DE_PLL_ENABLE, val);
/* Timeout 200us */
- if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
+ if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE,
BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
- drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n");
+ drm_err(display->drm, "timeout waiting for FREQ change request ack\n");
val &= ~BXT_DE_PLL_FREQ_REQ;
- intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+ intel_de_write(display, BXT_DE_PLL_ENABLE, val);
- dev_priv->display.cdclk.hw.vco = vco;
+ display->cdclk.hw.vco = vco;
}
-static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
+static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe)
{
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(display) >= 12) {
if (pipe == INVALID_PIPE)
return TGL_CDCLK_CD2X_PIPE_NONE;
else
return TGL_CDCLK_CD2X_PIPE(pipe);
- } else if (DISPLAY_VER(dev_priv) >= 11) {
+ } else if (DISPLAY_VER(display) >= 11) {
if (pipe == INVALID_PIPE)
return ICL_CDCLK_CD2X_PIPE_NONE;
else
@@ -1810,15 +1822,15 @@ static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe
}
}
-static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
+static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display,
int cdclk, int vco, u16 waveform)
{
/* cdclk = vco / 2 / div{1,1.5,2,4} */
switch (cdclk_divider(cdclk, vco, waveform)) {
default:
- drm_WARN_ON(&dev_priv->drm,
- cdclk != dev_priv->display.cdclk.hw.bypass);
- drm_WARN_ON(&dev_priv->drm, vco != 0);
+ drm_WARN_ON(display->drm,
+ cdclk != display->cdclk.hw.bypass);
+ drm_WARN_ON(display->drm, vco != 0);
fallthrough;
case 2:
return BXT_CDCLK_CD2X_DIV_SEL_1;
@@ -1831,47 +1843,47 @@ static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
}
}
-static u16 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
+static u16 cdclk_squash_waveform(struct intel_display *display,
int cdclk)
{
- const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
+ const struct intel_cdclk_vals *table = display->cdclk.table;
int i;
- if (cdclk == dev_priv->display.cdclk.hw.bypass)
+ if (cdclk == display->cdclk.hw.bypass)
return 0;
for (i = 0; table[i].refclk; i++)
- if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
+ if (table[i].refclk == display->cdclk.hw.ref &&
table[i].cdclk == cdclk)
return table[i].waveform;
- drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
- cdclk, dev_priv->display.cdclk.hw.ref);
+ drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
+ cdclk, display->cdclk.hw.ref);
return 0xffff;
}
-static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco)
+static void icl_cdclk_pll_update(struct intel_display *display, int vco)
{
- if (i915->display.cdclk.hw.vco != 0 &&
- i915->display.cdclk.hw.vco != vco)
- icl_cdclk_pll_disable(i915);
+ if (display->cdclk.hw.vco != 0 &&
+ display->cdclk.hw.vco != vco)
+ icl_cdclk_pll_disable(display);
- if (i915->display.cdclk.hw.vco != vco)
- icl_cdclk_pll_enable(i915, vco);
+ if (display->cdclk.hw.vco != vco)
+ icl_cdclk_pll_enable(display, vco);
}
-static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
+static void bxt_cdclk_pll_update(struct intel_display *display, int vco)
{
- if (i915->display.cdclk.hw.vco != 0 &&
- i915->display.cdclk.hw.vco != vco)
- bxt_de_pll_disable(i915);
+ if (display->cdclk.hw.vco != 0 &&
+ display->cdclk.hw.vco != vco)
+ bxt_de_pll_disable(display);
- if (i915->display.cdclk.hw.vco != vco)
- bxt_de_pll_enable(i915, vco);
+ if (display->cdclk.hw.vco != vco)
+ bxt_de_pll_enable(display, vco);
}
-static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
+static void dg2_cdclk_squash_program(struct intel_display *display,
u16 waveform)
{
u32 squash_ctl = 0;
@@ -1880,7 +1892,7 @@ static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
squash_ctl = CDCLK_SQUASH_ENABLE |
CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
- intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
+ intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl);
}
static bool cdclk_pll_is_unknown(unsigned int vco)
@@ -1893,38 +1905,40 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
return vco == ~0;
}
-static bool mdclk_source_is_cdclk_pll(struct drm_i915_private *i915)
+static bool mdclk_source_is_cdclk_pll(struct intel_display *display)
{
- return DISPLAY_VER(i915) >= 20;
+ return DISPLAY_VER(display) >= 20;
}
-static u32 xe2lpd_mdclk_source_sel(struct drm_i915_private *i915)
+static u32 xe2lpd_mdclk_source_sel(struct intel_display *display)
{
- if (mdclk_source_is_cdclk_pll(i915))
+ if (mdclk_source_is_cdclk_pll(display))
return MDCLK_SOURCE_SEL_CDCLK_PLL;
return MDCLK_SOURCE_SEL_CD2XCLK;
}
-int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+int intel_mdclk_cdclk_ratio(struct intel_display *display,
const struct intel_cdclk_config *cdclk_config)
{
- if (mdclk_source_is_cdclk_pll(i915))
+ if (mdclk_source_is_cdclk_pll(display))
return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
/* Otherwise, source for MDCLK is CD2XCLK. */
return 2;
}
-static void xe2lpd_mdclk_cdclk_ratio_program(struct drm_i915_private *i915,
+static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display,
const struct intel_cdclk_config *cdclk_config)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
intel_dbuf_mdclk_cdclk_ratio_update(i915,
- intel_mdclk_cdclk_ratio(i915, cdclk_config),
+ intel_mdclk_cdclk_ratio(display, cdclk_config),
cdclk_config->joined_mbus);
}
-static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915,
+static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display,
const struct intel_cdclk_config *old_cdclk_config,
const struct intel_cdclk_config *new_cdclk_config,
struct intel_cdclk_config *mid_cdclk_config)
@@ -1937,11 +1951,11 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
return false;
/* Return if both Squash and Crawl are not present */
- if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
+ if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
return false;
- old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
- new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
+ old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk);
+ new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk);
/* Return if Squash only or Crawl only is the desired action */
if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||
@@ -1958,7 +1972,7 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
* Should not happen currently. We might need more midpoint
* transitions if we need to also change the cd2x divider.
*/
- if (drm_WARN_ON(&i915->drm, old_div != new_div))
+ if (drm_WARN_ON(display->drm, old_div != new_div))
return false;
*mid_cdclk_config = *new_cdclk_config;
@@ -1987,37 +2001,40 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
/* make sure the mid clock came out sane */
- drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk <
+ drm_WARN_ON(display->drm, mid_cdclk_config->cdclk <
min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
- drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk >
- i915->display.cdclk.max_cdclk_freq);
- drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) !=
+ drm_WARN_ON(display->drm, mid_cdclk_config->cdclk >
+ display->cdclk.max_cdclk_freq);
+ drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) !=
mid_waveform);
return true;
}
-static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
+static bool pll_enable_wa_needed(struct intel_display *display)
{
- return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) ||
- DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) ||
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
+ return (DISPLAY_VER_FULL(display) == IP_VER(20, 0) ||
+ DISPLAY_VER_FULL(display) == IP_VER(14, 0) ||
IS_DG2(dev_priv)) &&
- dev_priv->display.cdclk.hw.vco > 0;
+ display->cdclk.hw.vco > 0;
}
-static u32 bxt_cdclk_ctl(struct drm_i915_private *i915,
+static u32 bxt_cdclk_ctl(struct intel_display *display,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
int cdclk = cdclk_config->cdclk;
int vco = cdclk_config->vco;
u16 waveform;
u32 val;
- waveform = cdclk_squash_waveform(i915, cdclk);
+ waveform = cdclk_squash_waveform(display, cdclk);
- val = bxt_cdclk_cd2x_div_sel(i915, cdclk, vco, waveform) |
- bxt_cdclk_cd2x_pipe(i915, pipe);
+ val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) |
+ bxt_cdclk_cd2x_pipe(display, pipe);
/*
* Disable SSA Precharge when CD clock frequency < 500 MHz,
@@ -2027,52 +2044,52 @@ static u32 bxt_cdclk_ctl(struct drm_i915_private *i915,
cdclk >= 500000)
val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
- if (DISPLAY_VER(i915) >= 20)
- val |= xe2lpd_mdclk_source_sel(i915);
+ if (DISPLAY_VER(display) >= 20)
+ val |= xe2lpd_mdclk_source_sel(display);
else
val |= skl_cdclk_decimal(cdclk);
return val;
}
-static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
+static void _bxt_set_cdclk(struct intel_display *display,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- struct intel_display *display = &dev_priv->display;
int cdclk = cdclk_config->cdclk;
int vco = cdclk_config->vco;
- if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 &&
- !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
- if (dev_priv->display.cdclk.hw.vco != vco)
- adlp_cdclk_pll_crawl(dev_priv, vco);
- } else if (DISPLAY_VER(dev_priv) >= 11) {
+ if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 &&
+ !cdclk_pll_is_unknown(display->cdclk.hw.vco)) {
+ if (display->cdclk.hw.vco != vco)
+ adlp_cdclk_pll_crawl(display, vco);
+ } else if (DISPLAY_VER(display) >= 11) {
/* wa_15010685871: dg2, mtl */
- if (pll_enable_wa_needed(dev_priv))
- dg2_cdclk_squash_program(dev_priv, 0);
+ if (pll_enable_wa_needed(display))
+ dg2_cdclk_squash_program(display, 0);
- icl_cdclk_pll_update(dev_priv, vco);
+ icl_cdclk_pll_update(display, vco);
} else {
- bxt_cdclk_pll_update(dev_priv, vco);
+ bxt_cdclk_pll_update(display, vco);
}
- if (HAS_CDCLK_SQUASH(dev_priv)) {
- u16 waveform = cdclk_squash_waveform(dev_priv, cdclk);
+ if (HAS_CDCLK_SQUASH(display)) {
+ u16 waveform = cdclk_squash_waveform(display, cdclk);
- dg2_cdclk_squash_program(dev_priv, waveform);
+ dg2_cdclk_squash_program(display, waveform);
}
- intel_de_write(dev_priv, CDCLK_CTL, bxt_cdclk_ctl(dev_priv, cdclk_config, pipe));
+ intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe));
if (pipe != INVALID_PIPE)
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
}
-static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
+static void bxt_set_cdclk(struct intel_display *display,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_cdclk_config mid_cdclk_config;
int cdclk = cdclk_config->cdclk;
int ret = 0;
@@ -2083,9 +2100,9 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
* mailbox communication, skip
* this step.
*/
- if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv))
+ if (DISPLAY_VER(display) >= 14 || IS_DG2(dev_priv))
/* NOOP */;
- else if (DISPLAY_VER(dev_priv) >= 11)
+ else if (DISPLAY_VER(display) >= 11)
ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
SKL_CDCLK_PREPARE_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE,
@@ -2100,35 +2117,35 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
0x80000000, 150, 2);
if (ret) {
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"Failed to inform PCU about cdclk change (err %d, freq %d)\n",
ret, cdclk);
return;
}
- if (DISPLAY_VER(dev_priv) >= 20 && cdclk < dev_priv->display.cdclk.hw.cdclk)
- xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config);
+ if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)
+ xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
- if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw,
+ if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw,
cdclk_config, &mid_cdclk_config)) {
- _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe);
- _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
+ _bxt_set_cdclk(display, &mid_cdclk_config, pipe);
+ _bxt_set_cdclk(display, cdclk_config, pipe);
} else {
- _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
+ _bxt_set_cdclk(display, cdclk_config, pipe);
}
- if (DISPLAY_VER(dev_priv) >= 20 && cdclk > dev_priv->display.cdclk.hw.cdclk)
- xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config);
+ if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
+ xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
- if (DISPLAY_VER(dev_priv) >= 14)
+ if (DISPLAY_VER(display) >= 14)
/*
* NOOP - No Pcode communication needed for
* Display versions 14 and beyond
*/;
- else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv))
+ else if (DISPLAY_VER(display) >= 11 && !IS_DG2(dev_priv))
ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
cdclk_config->voltage_level);
- if (DISPLAY_VER(dev_priv) < 11) {
+ if (DISPLAY_VER(display) < 11) {
/*
* The timeout isn't specified, the 2ms used here is based on
* experiment.
@@ -2141,42 +2158,42 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
150, 2);
}
if (ret) {
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"PCode CDCLK freq set failed, (err %d, freq %d)\n",
ret, cdclk);
return;
}
- intel_update_cdclk(dev_priv);
+ intel_update_cdclk(display);
- if (DISPLAY_VER(dev_priv) >= 11)
+ if (DISPLAY_VER(display) >= 11)
/*
* Can't read out the voltage level :(
* Let's just assume everything is as expected.
*/
- dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level;
+ display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
}
-static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
+static void bxt_sanitize_cdclk(struct intel_display *display)
{
u32 cdctl, expected;
int cdclk, vco;
- intel_update_cdclk(dev_priv);
- intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
+ intel_update_cdclk(display);
+ intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
- if (dev_priv->display.cdclk.hw.vco == 0 ||
- dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
+ if (display->cdclk.hw.vco == 0 ||
+ display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
goto sanitize;
/* Make sure this is a legal cdclk value for the platform */
- cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk);
- if (cdclk != dev_priv->display.cdclk.hw.cdclk)
+ cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk);
+ if (cdclk != display->cdclk.hw.cdclk)
goto sanitize;
/* Make sure the VCO is correct for the cdclk */
- vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
- if (vco != dev_priv->display.cdclk.hw.vco)
+ vco = bxt_calc_cdclk_pll_vco(display, cdclk);
+ if (vco != display->cdclk.hw.vco)
goto sanitize;
/*
@@ -2184,129 +2201,133 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
* set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
* so sanitize this register.
*/
- cdctl = intel_de_read(dev_priv, CDCLK_CTL);
- expected = bxt_cdclk_ctl(dev_priv, &dev_priv->display.cdclk.hw, INVALID_PIPE);
+ cdctl = intel_de_read(display, CDCLK_CTL);
+ expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE);
/*
* Let's ignore the pipe field, since BIOS could have configured the
* dividers both synching to an active pipe, or asynchronously
* (PIPE_NONE).
*/
- cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
- expected &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
+ cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
+ expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
if (cdctl == expected)
/* All well; nothing to sanitize */
return;
sanitize:
- drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
+ drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
/* force cdclk programming */
- dev_priv->display.cdclk.hw.cdclk = 0;
+ display->cdclk.hw.cdclk = 0;
/* force full PLL disable + enable */
- dev_priv->display.cdclk.hw.vco = ~0;
+ display->cdclk.hw.vco = ~0;
}
-static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
+static void bxt_cdclk_init_hw(struct intel_display *display)
{
struct intel_cdclk_config cdclk_config;
- bxt_sanitize_cdclk(dev_priv);
+ bxt_sanitize_cdclk(display);
- if (dev_priv->display.cdclk.hw.cdclk != 0 &&
- dev_priv->display.cdclk.hw.vco != 0)
+ if (display->cdclk.hw.cdclk != 0 &&
+ display->cdclk.hw.vco != 0)
return;
- cdclk_config = dev_priv->display.cdclk.hw;
+ cdclk_config = display->cdclk.hw;
/*
* FIXME:
* - The initial CDCLK needs to be read from VBT.
* Need to make this change after VBT has changes for BXT.
*/
- cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
- cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
+ cdclk_config.cdclk = bxt_calc_cdclk(display, 0);
+ cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk);
cdclk_config.voltage_level =
- intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
+ intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
- bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
+ bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
}
-static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
+static void bxt_cdclk_uninit_hw(struct intel_display *display)
{
- struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
+ struct intel_cdclk_config cdclk_config = display->cdclk.hw;
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
cdclk_config.voltage_level =
- intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
+ intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
- bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
+ bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
}
/**
* intel_cdclk_init_hw - Initialize CDCLK hardware
- * @i915: i915 device
+ * @display: display instance
*
- * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
+ * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and
* sanitizing the state of the hardware if needed. This is generally done only
* during the display core initialization sequence, after which the DMC will
* take care of turning CDCLK off/on as needed.
*/
-void intel_cdclk_init_hw(struct drm_i915_private *i915)
+void intel_cdclk_init_hw(struct intel_display *display)
{
- if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
- bxt_cdclk_init_hw(i915);
- else if (DISPLAY_VER(i915) == 9)
- skl_cdclk_init_hw(i915);
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
+ if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915))
+ bxt_cdclk_init_hw(display);
+ else if (DISPLAY_VER(display) == 9)
+ skl_cdclk_init_hw(display);
}
/**
* intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
- * @i915: i915 device
+ * @display: display instance
*
* Uninitialize CDCLK. This is done only during the display core
* uninitialization sequence.
*/
-void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
+void intel_cdclk_uninit_hw(struct intel_display *display)
{
- if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
- bxt_cdclk_uninit_hw(i915);
- else if (DISPLAY_VER(i915) == 9)
- skl_cdclk_uninit_hw(i915);
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
+ if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915))
+ bxt_cdclk_uninit_hw(display);
+ else if (DISPLAY_VER(display) == 9)
+ skl_cdclk_uninit_hw(display);
}
-static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915,
+static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display,
const struct intel_cdclk_config *a,
const struct intel_cdclk_config *b)
{
u16 old_waveform;
u16 new_waveform;
- drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco));
+ drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco));
if (a->vco == 0 || b->vco == 0)
return false;
- if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
+ if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
return false;
- old_waveform = cdclk_squash_waveform(i915, a->cdclk);
- new_waveform = cdclk_squash_waveform(i915, b->cdclk);
+ old_waveform = cdclk_squash_waveform(display, a->cdclk);
+ new_waveform = cdclk_squash_waveform(display, b->cdclk);
return a->vco != b->vco &&
old_waveform != new_waveform;
}
-static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
+static bool intel_cdclk_can_crawl(struct intel_display *display,
const struct intel_cdclk_config *a,
const struct intel_cdclk_config *b)
{
int a_div, b_div;
- if (!HAS_CDCLK_CRAWL(dev_priv))
+ if (!HAS_CDCLK_CRAWL(display))
return false;
/*
@@ -2322,7 +2343,7 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
a->ref == b->ref;
}
-static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
+static bool intel_cdclk_can_squash(struct intel_display *display,
const struct intel_cdclk_config *a,
const struct intel_cdclk_config *b)
{
@@ -2332,7 +2353,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
* the moment all platforms with squasher use a fixed cd2x
* divider.
*/
- if (!HAS_CDCLK_SQUASH(dev_priv))
+ if (!HAS_CDCLK_SQUASH(display))
return false;
return a->cdclk != b->cdclk &&
@@ -2361,7 +2382,7 @@ bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
/**
* intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
* configurations requires only a cd2x divider update
- * @dev_priv: i915 device
+ * @display: display instance
* @a: first CDCLK configuration
* @b: second CDCLK configuration
*
@@ -2369,12 +2390,14 @@ bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
* True if changing between the two CDCLK configurations
* can be done with just a cd2x divider update, false if not.
*/
-static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
+static bool intel_cdclk_can_cd2x_update(struct intel_display *display,
const struct intel_cdclk_config *a,
const struct intel_cdclk_config *b)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
/* Older hw doesn't have the capability */
- if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv))
+ if (DISPLAY_VER(display) < 10 && !IS_BROXTON(dev_priv))
return false;
/*
@@ -2383,7 +2406,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
* the moment all platforms with squasher use a fixed cd2x
* divider.
*/
- if (HAS_CDCLK_SQUASH(dev_priv))
+ if (HAS_CDCLK_SQUASH(display))
return false;
return a->cdclk != b->cdclk &&
@@ -2407,23 +2430,24 @@ static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
a->voltage_level != b->voltage_level;
}
-void intel_cdclk_dump_config(struct drm_i915_private *i915,
+void intel_cdclk_dump_config(struct intel_display *display,
const struct intel_cdclk_config *cdclk_config,
const char *context)
{
- drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
+ drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
context, cdclk_config->cdclk, cdclk_config->vco,
cdclk_config->ref, cdclk_config->bypass,
cdclk_config->voltage_level);
}
-static void intel_pcode_notify(struct drm_i915_private *i915,
+static void intel_pcode_notify(struct intel_display *display,
u8 voltage_level,
u8 active_pipe_count,
u16 cdclk,
bool cdclk_update_valid,
bool pipe_count_update_valid)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
int ret;
u32 update_mask = 0;
@@ -2444,26 +2468,27 @@ static void intel_pcode_notify(struct drm_i915_private *i915,
SKL_CDCLK_READY_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE, 3);
if (ret)
- drm_err(&i915->drm,
+ drm_err(display->drm,
"Failed to inform PCU about display config (err %d)\n",
ret);
}
-static void intel_set_cdclk(struct drm_i915_private *dev_priv,
+static void intel_set_cdclk(struct intel_display *display,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe, const char *context)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_encoder *encoder;
- if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config))
+ if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config))
return;
- if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk))
+ if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk))
return;
- intel_cdclk_dump_config(dev_priv, cdclk_config, context);
+ intel_cdclk_dump_config(display, cdclk_config, context);
- for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+ for_each_intel_encoder_with_psr(display->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
intel_psr_pause(intel_dp);
@@ -2476,24 +2501,24 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
* functions use cdclk. Not all platforms/ports do,
* but we'll lock them all for simplicity.
*/
- mutex_lock(&dev_priv->display.gmbus.mutex);
- for_each_intel_dp(&dev_priv->drm, encoder) {
+ mutex_lock(&display->gmbus.mutex);
+ for_each_intel_dp(display->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
- &dev_priv->display.gmbus.mutex);
+ &display->gmbus.mutex);
}
- intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
+ intel_cdclk_set_cdclk(display, cdclk_config, pipe);
- for_each_intel_dp(&dev_priv->drm, encoder) {
+ for_each_intel_dp(display->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
mutex_unlock(&intel_dp->aux.hw_mutex);
}
- mutex_unlock(&dev_priv->display.gmbus.mutex);
+ mutex_unlock(&display->gmbus.mutex);
- for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+ for_each_intel_encoder_with_psr(display->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
intel_psr_resume(intel_dp);
@@ -2501,17 +2526,17 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
intel_audio_cdclk_change_post(dev_priv);
- if (drm_WARN(&dev_priv->drm,
- intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config),
+ if (drm_WARN(display->drm,
+ intel_cdclk_changed(&display->cdclk.hw, cdclk_config),
"cdclk state doesn't match!\n")) {
- intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]");
- intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]");
+ intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]");
+ intel_cdclk_dump_config(display, cdclk_config, "[sw state]");
}
}
static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
const struct intel_cdclk_state *old_cdclk_state =
intel_atomic_get_old_cdclk_state(state);
const struct intel_cdclk_state *new_cdclk_state =
@@ -2550,13 +2575,13 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
if (update_pipe_count)
num_active_pipes = hweight8(new_cdclk_state->active_pipes);
- intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk,
+ intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
change_cdclk, update_pipe_count);
}
static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
const struct intel_cdclk_state *new_cdclk_state =
intel_atomic_get_new_cdclk_state(state);
const struct intel_cdclk_state *old_cdclk_state =
@@ -2587,7 +2612,7 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
if (update_pipe_count)
num_active_pipes = hweight8(new_cdclk_state->active_pipes);
- intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk,
+ intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
update_cdclk, update_pipe_count);
}
@@ -2612,7 +2637,8 @@ bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
void
intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
+ struct drm_i915_private *i915 = to_i915(display->drm);
const struct intel_cdclk_state *old_cdclk_state =
intel_atomic_get_old_cdclk_state(state);
const struct intel_cdclk_state *new_cdclk_state =
@@ -2649,9 +2675,9 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
*/
cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus;
- drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
+ drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
- intel_set_cdclk(i915, &cdclk_config, pipe,
+ intel_set_cdclk(display, &cdclk_config, pipe,
"Pre changing CDCLK to");
}
@@ -2665,7 +2691,8 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
void
intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
+ struct drm_i915_private *i915 = to_i915(display->drm);
const struct intel_cdclk_state *old_cdclk_state =
intel_atomic_get_old_cdclk_state(state);
const struct intel_cdclk_state *new_cdclk_state =
@@ -2685,20 +2712,21 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
else
pipe = INVALID_PIPE;
- drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
+ drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
- intel_set_cdclk(i915, &new_cdclk_state->actual, pipe,
+ intel_set_cdclk(display, &new_cdclk_state->actual, pipe,
"Post changing CDCLK to");
}
static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state->uapi.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
int pixel_rate = crtc_state->pixel_rate;
- if (DISPLAY_VER(dev_priv) >= 10)
+ if (DISPLAY_VER(display) >= 10)
return DIV_ROUND_UP(pixel_rate, 2);
- else if (DISPLAY_VER(dev_priv) == 9 ||
+ else if (DISPLAY_VER(display) == 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
return pixel_rate;
else if (IS_CHERRYVIEW(dev_priv))
@@ -2712,11 +2740,11 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
struct intel_plane *plane;
int min_cdclk = 0;
- for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
+ for_each_intel_plane_on_crtc(display->drm, crtc, plane)
min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk);
return min_cdclk;
@@ -2725,7 +2753,7 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
int min_cdclk = 0;
@@ -2754,7 +2782,7 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
* Since PPC = 2 with bigjoiner
* => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
*/
- int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
+ int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24;
int min_cdclk_bj =
(fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
pixel_clock) / (2 * bigjoiner_interface_bits);
@@ -2767,8 +2795,9 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv =
- to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display =
+ to_intel_display(crtc_state->uapi.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
int min_cdclk;
if (!crtc_state->hw.enable)
@@ -2789,10 +2818,10 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
crtc_state->has_audio &&
crtc_state->port_clock >= 540000 &&
crtc_state->lane_count == 4) {
- if (DISPLAY_VER(dev_priv) == 10) {
+ if (DISPLAY_VER(display) == 10) {
/* Display WA #1145: glk */
min_cdclk = max(316800, min_cdclk);
- } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
+ } else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) {
/* Display WA #1144: skl,bxt */
min_cdclk = max(432000, min_cdclk);
}
@@ -2802,7 +2831,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
* According to BSpec, "The CD clock frequency must be at least twice
* the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
*/
- if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9)
+ if (crtc_state->has_audio && DISPLAY_VER(display) >= 9)
min_cdclk = max(2 * 96000, min_cdclk);
/*
@@ -2844,7 +2873,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
static int intel_compute_min_cdclk(struct intel_atomic_state *state)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_cdclk_state *cdclk_state =
intel_atomic_get_new_cdclk_state(state);
const struct intel_bw_state *bw_state;
@@ -2887,7 +2917,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
min_cdclk = max(cdclk_state->force_min_cdclk,
cdclk_state->bw_min_cdclk);
- for_each_pipe(dev_priv, pipe)
+ for_each_pipe(display, pipe)
min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
/*
@@ -2902,10 +2932,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
!is_power_of_2(cdclk_state->active_pipes))
min_cdclk = max(2 * 96000, min_cdclk);
- if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) {
- drm_dbg_kms(&dev_priv->drm,
+ if (min_cdclk > display->cdclk.max_cdclk_freq) {
+ drm_dbg_kms(display->drm,
"required cdclk (%d kHz) exceeds max (%d kHz)\n",
- min_cdclk, dev_priv->display.cdclk.max_cdclk_freq);
+ min_cdclk, display->cdclk.max_cdclk_freq);
return -EINVAL;
}
@@ -2927,7 +2957,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
*/
static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
struct intel_cdclk_state *cdclk_state =
intel_atomic_get_new_cdclk_state(state);
struct intel_crtc *crtc;
@@ -2955,7 +2985,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
}
min_voltage_level = 0;
- for_each_pipe(dev_priv, pipe)
+ for_each_pipe(display, pipe)
min_voltage_level = max(cdclk_state->min_voltage_level[pipe],
min_voltage_level);
@@ -2964,7 +2994,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
struct intel_cdclk_state *cdclk_state =
intel_atomic_get_new_cdclk_state(state);
int min_cdclk, cdclk;
@@ -2973,18 +3003,18 @@ static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
if (min_cdclk < 0)
return min_cdclk;
- cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
+ cdclk = vlv_calc_cdclk(display, min_cdclk);
cdclk_state->logical.cdclk = cdclk;
cdclk_state->logical.voltage_level =
- vlv_calc_voltage_level(dev_priv, cdclk);
+ vlv_calc_voltage_level(display, cdclk);
if (!cdclk_state->active_pipes) {
- cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
+ cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk);
cdclk_state->actual.cdclk = cdclk;
cdclk_state->actual.voltage_level =
- vlv_calc_voltage_level(dev_priv, cdclk);
+ vlv_calc_voltage_level(display, cdclk);
} else {
cdclk_state->actual = cdclk_state->logical;
}
@@ -3023,7 +3053,7 @@ static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
static int skl_dpll0_vco(struct intel_atomic_state *state)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
struct intel_cdclk_state *cdclk_state =
intel_atomic_get_new_cdclk_state(state);
struct intel_crtc *crtc;
@@ -3032,7 +3062,7 @@ static int skl_dpll0_vco(struct intel_atomic_state *state)
vco = cdclk_state->logical.vco;
if (!vco)
- vco = dev_priv->display.cdclk.skl_preferred_vco_freq;
+ vco = display->cdclk.skl_preferred_vco_freq;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
if (!crtc_state->hw.enable)
@@ -3094,7 +3124,7 @@ static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
struct intel_cdclk_state *cdclk_state =
intel_atomic_get_new_cdclk_state(state);
int min_cdclk, min_voltage_level, cdclk, vco;
@@ -3107,23 +3137,23 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
if (min_voltage_level < 0)
return min_voltage_level;
- cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
- vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
+ cdclk = bxt_calc_cdclk(display, min_cdclk);
+ vco = bxt_calc_cdclk_pll_vco(display, cdclk);
cdclk_state->logical.vco = vco;
cdclk_state->logical.cdclk = cdclk;
cdclk_state->logical.voltage_level =
max_t(int, min_voltage_level,
- intel_cdclk_calc_voltage_level(dev_priv, cdclk));
+ intel_cdclk_calc_voltage_level(display, cdclk));
if (!cdclk_state->active_pipes) {
- cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
- vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
+ cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk);
+ vco = bxt_calc_cdclk_pll_vco(display, cdclk);
cdclk_state->actual.vco = vco;
cdclk_state->actual.cdclk = cdclk;
cdclk_state->actual.voltage_level =
- intel_cdclk_calc_voltage_level(dev_priv, cdclk);
+ intel_cdclk_calc_voltage_level(display, cdclk);
} else {
cdclk_state->actual = cdclk_state->logical;
}
@@ -3175,10 +3205,10 @@ static const struct intel_global_state_funcs intel_cdclk_funcs = {
struct intel_cdclk_state *
intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
struct intel_global_state *cdclk_state;
- cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj);
+ cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj);
if (IS_ERR(cdclk_state))
return ERR_CAST(cdclk_state);
@@ -3234,24 +3264,26 @@ int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joi
return intel_atomic_lock_global_state(&cdclk_state->base);
}
-int intel_cdclk_init(struct drm_i915_private *dev_priv)
+int intel_cdclk_init(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_cdclk_state *cdclk_state;
cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
if (!cdclk_state)
return -ENOMEM;
- intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
+ intel_atomic_global_obj_init(dev_priv, &display->cdclk.obj,
&cdclk_state->base, &intel_cdclk_funcs);
return 0;
}
-static bool intel_cdclk_need_serialize(struct drm_i915_private *i915,
+static bool intel_cdclk_need_serialize(struct intel_display *display,
const struct intel_cdclk_state *old_cdclk_state,
const struct intel_cdclk_state *new_cdclk_state)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) !=
hweight8(new_cdclk_state->active_pipes);
bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual,
@@ -3266,7 +3298,6 @@ static bool intel_cdclk_need_serialize(struct drm_i915_private *i915,
int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
const struct intel_cdclk_state *old_cdclk_state;
struct intel_cdclk_state *new_cdclk_state;
enum pipe pipe = INVALID_PIPE;
@@ -3285,7 +3316,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
if (ret)
return ret;
- if (intel_cdclk_need_serialize(dev_priv, old_cdclk_state, new_cdclk_state)) {
+ if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) {
/*
* Also serialize commits across all crtcs
* if the actual hw needs to be poked.
@@ -3305,7 +3336,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
}
if (is_power_of_2(new_cdclk_state->active_pipes) &&
- intel_cdclk_can_cd2x_update(dev_priv,
+ intel_cdclk_can_cd2x_update(display,
&old_cdclk_state->actual,
&new_cdclk_state->actual)) {
struct intel_crtc *crtc;
@@ -3322,25 +3353,25 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
pipe = INVALID_PIPE;
}
- if (intel_cdclk_can_crawl_and_squash(dev_priv,
+ if (intel_cdclk_can_crawl_and_squash(display,
&old_cdclk_state->actual,
&new_cdclk_state->actual)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Can change cdclk via crawling and squashing\n");
- } else if (intel_cdclk_can_squash(dev_priv,
+ } else if (intel_cdclk_can_squash(display,
&old_cdclk_state->actual,
&new_cdclk_state->actual)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Can change cdclk via squashing\n");
- } else if (intel_cdclk_can_crawl(dev_priv,
+ } else if (intel_cdclk_can_crawl(display,
&old_cdclk_state->actual,
&new_cdclk_state->actual)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Can change cdclk via crawling\n");
} else if (pipe != INVALID_PIPE) {
new_cdclk_state->pipe = pipe;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Can change cdclk cd2x divider with pipe %c active\n",
pipe_name(pipe));
} else if (intel_cdclk_clock_changed(&old_cdclk_state->actual,
@@ -3352,24 +3383,24 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
new_cdclk_state->disable_pipes = true;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Modeset required for cdclk change\n");
}
- if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) !=
- intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) {
- int ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual);
+ if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) !=
+ intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) {
+ int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual);
ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
if (ret)
return ret;
}
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"New cdclk calculated to be logical %u kHz, actual %u kHz\n",
new_cdclk_state->logical.cdclk,
new_cdclk_state->actual.cdclk);
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"New voltage level calculated to be logical %u, actual %u\n",
new_cdclk_state->logical.voltage_level,
new_cdclk_state->actual.voltage_level);
@@ -3377,18 +3408,19 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
return 0;
}
-static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
+static int intel_compute_max_dotclk(struct intel_display *display)
{
- int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+ int max_cdclk_freq = display->cdclk.max_cdclk_freq;
- if (DISPLAY_VER(dev_priv) >= 10)
+ if (DISPLAY_VER(display) >= 10)
return 2 * max_cdclk_freq;
- else if (DISPLAY_VER(dev_priv) == 9 ||
+ else if (DISPLAY_VER(display) == 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
return max_cdclk_freq;
else if (IS_CHERRYVIEW(dev_priv))
return max_cdclk_freq*95/100;
- else if (DISPLAY_VER(dev_priv) < 4)
+ else if (DISPLAY_VER(display) < 4)
return 2*max_cdclk_freq*90/100;
else
return max_cdclk_freq*90/100;
@@ -3396,34 +3428,36 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
/**
* intel_update_max_cdclk - Determine the maximum support CDCLK frequency
- * @dev_priv: i915 device
+ * @display: display instance
*
* Determine the maximum CDCLK frequency the platform supports, and also
* derive the maximum dot clock frequency the maximum CDCLK frequency
* allows.
*/
-void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
+void intel_update_max_cdclk(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
- if (dev_priv->display.cdclk.hw.ref == 24000)
- dev_priv->display.cdclk.max_cdclk_freq = 552000;
+ if (display->cdclk.hw.ref == 24000)
+ display->cdclk.max_cdclk_freq = 552000;
else
- dev_priv->display.cdclk.max_cdclk_freq = 556800;
- } else if (DISPLAY_VER(dev_priv) >= 11) {
- if (dev_priv->display.cdclk.hw.ref == 24000)
- dev_priv->display.cdclk.max_cdclk_freq = 648000;
+ display->cdclk.max_cdclk_freq = 556800;
+ } else if (DISPLAY_VER(display) >= 11) {
+ if (display->cdclk.hw.ref == 24000)
+ display->cdclk.max_cdclk_freq = 648000;
else
- dev_priv->display.cdclk.max_cdclk_freq = 652800;
+ display->cdclk.max_cdclk_freq = 652800;
} else if (IS_GEMINILAKE(dev_priv)) {
- dev_priv->display.cdclk.max_cdclk_freq = 316800;
+ display->cdclk.max_cdclk_freq = 316800;
} else if (IS_BROXTON(dev_priv)) {
- dev_priv->display.cdclk.max_cdclk_freq = 624000;
- } else if (DISPLAY_VER(dev_priv) == 9) {
- u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
+ display->cdclk.max_cdclk_freq = 624000;
+ } else if (DISPLAY_VER(display) == 9) {
+ u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
int max_cdclk, vco;
- vco = dev_priv->display.cdclk.skl_preferred_vco_freq;
- drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
+ vco = display->cdclk.skl_preferred_vco_freq;
+ drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
/*
* Use the lower (vco 8640) cdclk values as a
@@ -3439,7 +3473,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
else
max_cdclk = 308571;
- dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
+ display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
} else if (IS_BROADWELL(dev_priv)) {
/*
* FIXME with extra cooling we can allow
@@ -3447,41 +3481,43 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
* How can we know if extra cooling is
* available? PCI ID, VTB, something else?
*/
- if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
- dev_priv->display.cdclk.max_cdclk_freq = 450000;
+ if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
+ display->cdclk.max_cdclk_freq = 450000;
else if (IS_BROADWELL_ULX(dev_priv))
- dev_priv->display.cdclk.max_cdclk_freq = 450000;
+ display->cdclk.max_cdclk_freq = 450000;
else if (IS_BROADWELL_ULT(dev_priv))
- dev_priv->display.cdclk.max_cdclk_freq = 540000;
+ display->cdclk.max_cdclk_freq = 540000;
else
- dev_priv->display.cdclk.max_cdclk_freq = 675000;
+ display->cdclk.max_cdclk_freq = 675000;
} else if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.cdclk.max_cdclk_freq = 320000;
+ display->cdclk.max_cdclk_freq = 320000;
} else if (IS_VALLEYVIEW(dev_priv)) {
- dev_priv->display.cdclk.max_cdclk_freq = 400000;
+ display->cdclk.max_cdclk_freq = 400000;
} else {
/* otherwise assume cdclk is fixed */
- dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk;
+ display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk;
}
- dev_priv->display.cdclk.max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
+ display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display);
- drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
- dev_priv->display.cdclk.max_cdclk_freq);
+ drm_dbg(display->drm, "Max CD clock rate: %d kHz\n",
+ display->cdclk.max_cdclk_freq);
- drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
- dev_priv->display.cdclk.max_dotclk_freq);
+ drm_dbg(display->drm, "Max dotclock rate: %d kHz\n",
+ display->cdclk.max_dotclk_freq);
}
/**
* intel_update_cdclk - Determine the current CDCLK frequency
- * @dev_priv: i915 device
+ * @display: display instance
*
* Determine the current CDCLK frequency.
*/
-void intel_update_cdclk(struct drm_i915_private *dev_priv)
+void intel_update_cdclk(struct intel_display *display)
{
- intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
+ intel_cdclk_get_cdclk(display, &display->cdclk.hw);
/*
* 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
@@ -3490,28 +3526,29 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
* generate GMBus clock. This will vary with the cdclk freq.
*/
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- intel_de_write(dev_priv, GMBUSFREQ_VLV,
- DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000));
+ intel_de_write(display, GMBUSFREQ_VLV,
+ DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000));
}
-static int dg1_rawclk(struct drm_i915_private *dev_priv)
+static int dg1_rawclk(struct intel_display *display)
{
/*
* DG1 always uses a 38.4 MHz rawclk. The bspec tells us
* "Program Numerator=2, Denominator=4, Divider=37 decimal."
*/
- intel_de_write(dev_priv, PCH_RAWCLK_FREQ,
+ intel_de_write(display, PCH_RAWCLK_FREQ,
CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
return 38400;
}
-static int cnp_rawclk(struct drm_i915_private *dev_priv)
+static int cnp_rawclk(struct intel_display *display)
{
- u32 rawclk;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
int divider, fraction;
+ u32 rawclk;
- if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
+ if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
/* 24 MHz */
divider = 24000;
fraction = 0;
@@ -3531,37 +3568,42 @@ static int cnp_rawclk(struct drm_i915_private *dev_priv)
rawclk |= ICP_RAWCLK_NUM(numerator);
}
- intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk);
+ intel_de_write(display, PCH_RAWCLK_FREQ, rawclk);
return divider + fraction;
}
-static int pch_rawclk(struct drm_i915_private *dev_priv)
+static int pch_rawclk(struct intel_display *display)
{
- return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
+ return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
}
-static int vlv_hrawclk(struct drm_i915_private *dev_priv)
+static int vlv_hrawclk(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
/* RAWCLK_FREQ_VLV register updated from power well code */
return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
CCK_DISPLAY_REF_CLOCK_CONTROL);
}
-static int i9xx_hrawclk(struct drm_i915_private *i915)
+static int i9xx_hrawclk(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
/* hrawclock is 1/4 the FSB frequency */
return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
}
/**
* intel_read_rawclk - Determine the current RAWCLK frequency
- * @dev_priv: i915 device
+ * @display: display instance
*
* Determine the current RAWCLK frequency. RAWCLK is a fixed
* frequency clock so this needs to done only once.
*/
-u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
+u32 intel_read_rawclk(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 freq;
if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
@@ -3572,15 +3614,15 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
*/
freq = 38400;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
- freq = dg1_rawclk(dev_priv);
+ freq = dg1_rawclk(display);
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
- freq = cnp_rawclk(dev_priv);
+ freq = cnp_rawclk(display);
else if (HAS_PCH_SPLIT(dev_priv))
- freq = pch_rawclk(dev_priv);
+ freq = pch_rawclk(display);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- freq = vlv_hrawclk(dev_priv);
- else if (DISPLAY_VER(dev_priv) >= 3)
- freq = i9xx_hrawclk(dev_priv);
+ freq = vlv_hrawclk(display);
+ else if (DISPLAY_VER(display) >= 3)
+ freq = i9xx_hrawclk(display);
else
/* no rawclk on other platforms, or no need to know it */
return 0;
@@ -3590,23 +3632,23 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
static int i915_cdclk_info_show(struct seq_file *m, void *unused)
{
- struct drm_i915_private *i915 = m->private;
+ struct intel_display *display = m->private;
- seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk);
- seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq);
- seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->display.cdclk.max_dotclk_freq);
+ seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk);
+ seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq);
+ seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info);
-void intel_cdclk_debugfs_register(struct drm_i915_private *i915)
+void intel_cdclk_debugfs_register(struct intel_display *display)
{
- struct drm_minor *minor = i915->drm.primary;
+ struct drm_minor *minor = display->drm->primary;
debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root,
- i915, &i915_cdclk_info_fops);
+ display, &i915_cdclk_info_fops);
}
static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
@@ -3747,97 +3789,99 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
/**
* intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
- * @dev_priv: i915 device
+ * @display: display instance
*/
-void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
+void intel_init_cdclk_hooks(struct intel_display *display)
{
- if (DISPLAY_VER(dev_priv) >= 20) {
- dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
- dev_priv->display.cdclk.table = xe2lpd_cdclk_table;
- } else if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1)) {
- dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
- dev_priv->display.cdclk.table = xe2hpd_cdclk_table;
- } else if (DISPLAY_VER(dev_priv) >= 14) {
- dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
- dev_priv->display.cdclk.table = mtl_cdclk_table;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
+ if (DISPLAY_VER(display) >= 20) {
+ display->funcs.cdclk = &rplu_cdclk_funcs;
+ display->cdclk.table = xe2lpd_cdclk_table;
+ } else if (DISPLAY_VER_FULL(display) >= IP_VER(14, 1)) {
+ display->funcs.cdclk = &rplu_cdclk_funcs;
+ display->cdclk.table = xe2hpd_cdclk_table;
+ } else if (DISPLAY_VER(display) >= 14) {
+ display->funcs.cdclk = &rplu_cdclk_funcs;
+ display->cdclk.table = mtl_cdclk_table;
} else if (IS_DG2(dev_priv)) {
- dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
- dev_priv->display.cdclk.table = dg2_cdclk_table;
+ display->funcs.cdclk = &tgl_cdclk_funcs;
+ display->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
/* Wa_22011320316:adl-p[a0] */
if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
- dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
- dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
+ display->cdclk.table = adlp_a_step_cdclk_table;
+ display->funcs.cdclk = &tgl_cdclk_funcs;
} else if (IS_RAPTORLAKE_U(dev_priv)) {
- dev_priv->display.cdclk.table = rplu_cdclk_table;
- dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
+ display->cdclk.table = rplu_cdclk_table;
+ display->funcs.cdclk = &rplu_cdclk_funcs;
} else {
- dev_priv->display.cdclk.table = adlp_cdclk_table;
- dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
+ display->cdclk.table = adlp_cdclk_table;
+ display->funcs.cdclk = &tgl_cdclk_funcs;
}
} else if (IS_ROCKETLAKE(dev_priv)) {
- dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
- dev_priv->display.cdclk.table = rkl_cdclk_table;
- } else if (DISPLAY_VER(dev_priv) >= 12) {
- dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
- dev_priv->display.cdclk.table = icl_cdclk_table;
+ display->funcs.cdclk = &tgl_cdclk_funcs;
+ display->cdclk.table = rkl_cdclk_table;
+ } else if (DISPLAY_VER(display) >= 12) {
+ display->funcs.cdclk = &tgl_cdclk_funcs;
+ display->cdclk.table = icl_cdclk_table;
} else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
- dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
- dev_priv->display.cdclk.table = icl_cdclk_table;
- } else if (DISPLAY_VER(dev_priv) >= 11) {
- dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
- dev_priv->display.cdclk.table = icl_cdclk_table;
+ display->funcs.cdclk = &ehl_cdclk_funcs;
+ display->cdclk.table = icl_cdclk_table;
+ } else if (DISPLAY_VER(display) >= 11) {
+ display->funcs.cdclk = &icl_cdclk_funcs;
+ display->cdclk.table = icl_cdclk_table;
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
- dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
+ display->funcs.cdclk = &bxt_cdclk_funcs;
if (IS_GEMINILAKE(dev_priv))
- dev_priv->display.cdclk.table = glk_cdclk_table;
+ display->cdclk.table = glk_cdclk_table;
else
- dev_priv->display.cdclk.table = bxt_cdclk_table;
- } else if (DISPLAY_VER(dev_priv) == 9) {
- dev_priv->display.funcs.cdclk = &skl_cdclk_funcs;
+ display->cdclk.table = bxt_cdclk_table;
+ } else if (DISPLAY_VER(display) == 9) {
+ display->funcs.cdclk = &skl_cdclk_funcs;
} else if (IS_BROADWELL(dev_priv)) {
- dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs;
+ display->funcs.cdclk = &bdw_cdclk_funcs;
} else if (IS_HASWELL(dev_priv)) {
- dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs;
+ display->funcs.cdclk = &hsw_cdclk_funcs;
} else if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.funcs.cdclk = &chv_cdclk_funcs;
+ display->funcs.cdclk = &chv_cdclk_funcs;
} else if (IS_VALLEYVIEW(dev_priv)) {
- dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs;
+ display->funcs.cdclk = &vlv_cdclk_funcs;
} else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
- dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
+ display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
} else if (IS_IRONLAKE(dev_priv)) {
- dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs;
+ display->funcs.cdclk = &ilk_cdclk_funcs;
} else if (IS_GM45(dev_priv)) {
- dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs;
+ display->funcs.cdclk = &gm45_cdclk_funcs;
} else if (IS_G45(dev_priv)) {
- dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
+ display->funcs.cdclk = &g33_cdclk_funcs;
} else if (IS_I965GM(dev_priv)) {
- dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs;
+ display->funcs.cdclk = &i965gm_cdclk_funcs;
} else if (IS_I965G(dev_priv)) {
- dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
+ display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
} else if (IS_PINEVIEW(dev_priv)) {
- dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs;
+ display->funcs.cdclk = &pnv_cdclk_funcs;
} else if (IS_G33(dev_priv)) {
- dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
+ display->funcs.cdclk = &g33_cdclk_funcs;
} else if (IS_I945GM(dev_priv)) {
- dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs;
+ display->funcs.cdclk = &i945gm_cdclk_funcs;
} else if (IS_I945G(dev_priv)) {
- dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
+ display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
} else if (IS_I915GM(dev_priv)) {
- dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs;
+ display->funcs.cdclk = &i915gm_cdclk_funcs;
} else if (IS_I915G(dev_priv)) {
- dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs;
+ display->funcs.cdclk = &i915g_cdclk_funcs;
} else if (IS_I865G(dev_priv)) {
- dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs;
+ display->funcs.cdclk = &i865g_cdclk_funcs;
} else if (IS_I85X(dev_priv)) {
- dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs;
+ display->funcs.cdclk = &i85x_cdclk_funcs;
} else if (IS_I845G(dev_priv)) {
- dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs;
+ display->funcs.cdclk = &i845g_cdclk_funcs;
} else if (IS_I830(dev_priv)) {
- dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
+ display->funcs.cdclk = &i830_cdclk_funcs;
}
- if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
+ if (drm_WARN(display->drm, !display->funcs.cdclk,
"Unknown platform. Assuming i830\n"))
- dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
+ display->funcs.cdclk = &i830_cdclk_funcs;
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 1fe445a3a30b..6b0e7a41eba3 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -11,9 +11,9 @@
#include "intel_display_limits.h"
#include "intel_global_state.h"
-struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc_state;
+struct intel_display;
struct intel_cdclk_config {
unsigned int cdclk, vco, ref, bypass;
@@ -59,24 +59,24 @@ struct intel_cdclk_state {
};
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
-void intel_cdclk_init_hw(struct drm_i915_private *i915);
-void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
-void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
-void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
-void intel_update_cdclk(struct drm_i915_private *dev_priv);
-u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
+void intel_cdclk_init_hw(struct intel_display *display);
+void intel_cdclk_uninit_hw(struct intel_display *display);
+void intel_init_cdclk_hooks(struct intel_display *display);
+void intel_update_max_cdclk(struct intel_display *display);
+void intel_update_cdclk(struct intel_display *display);
+u32 intel_read_rawclk(struct intel_display *display);
bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
const struct intel_cdclk_config *b);
-int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+int intel_mdclk_cdclk_ratio(struct intel_display *display,
const struct intel_cdclk_config *cdclk_config);
bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state);
void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
-void intel_cdclk_dump_config(struct drm_i915_private *i915,
+void intel_cdclk_dump_config(struct intel_display *display,
const struct intel_cdclk_config *cdclk_config,
const char *context);
int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
-void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
+void intel_cdclk_get_cdclk(struct intel_display *display,
struct intel_cdclk_config *cdclk_config);
int intel_cdclk_atomic_check(struct intel_atomic_state *state,
bool *need_cdclk_calc);
@@ -92,7 +92,7 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
#define intel_atomic_get_new_cdclk_state(state) \
to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->cdclk.obj))
-int intel_cdclk_init(struct drm_i915_private *dev_priv);
-void intel_cdclk_debugfs_register(struct drm_i915_private *i915);
+int intel_cdclk_init(struct intel_display *display);
+void intel_cdclk_debugfs_register(struct intel_display *display);
#endif /* __INTEL_CDCLK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 830b9eb60976..c1bef34d1ffd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1068,7 +1068,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
minor->debugfs_root, minor);
intel_bios_debugfs_register(display);
- intel_cdclk_debugfs_register(i915);
+ intel_cdclk_debugfs_register(display);
intel_dmc_debugfs_register(i915);
intel_fbc_debugfs_register(display);
intel_hpd_debugfs_register(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 408c76852495..9ff08dbefc76 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1678,7 +1678,7 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9
}
}
- display_runtime->rawclk_freq = intel_read_rawclk(i915);
+ display_runtime->rawclk_freq = intel_read_rawclk(&i915->display);
drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq);
return;
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index e7670774ecd0..434e52f450ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -82,16 +82,17 @@ bool intel_display_driver_probe_defer(struct pci_dev *pdev)
void intel_display_driver_init_hw(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
struct intel_cdclk_state *cdclk_state;
if (!HAS_DISPLAY(i915))
return;
- cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state);
+ cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state);
- intel_update_cdclk(i915);
- intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK");
- cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
+ intel_update_cdclk(display);
+ intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
+ cdclk_state->logical = cdclk_state->actual = display->cdclk.hw;
intel_display_wa_apply(i915);
}
@@ -194,7 +195,7 @@ void intel_display_driver_early_probe(struct drm_i915_private *i915)
intel_display_irq_init(i915);
intel_dkl_phy_init(i915);
intel_color_init_hooks(i915);
- intel_init_cdclk_hooks(i915);
+ intel_init_cdclk_hooks(&i915->display);
intel_audio_hooks_init(i915);
intel_dpll_init_clock_hook(i915);
intel_init_display_hooks(i915);
@@ -244,7 +245,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
intel_mode_config_init(i915);
- ret = intel_cdclk_init(i915);
+ ret = intel_cdclk_init(display);
if (ret)
goto cleanup_vga_client_pw_domain_dmc;
@@ -451,8 +452,8 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
intel_display_driver_init_hw(i915);
intel_dpll_update_ref_clks(i915);
- if (i915->display.cdclk.max_cdclk_freq == 0)
- intel_update_max_cdclk(i915);
+ if (display->cdclk.max_cdclk_freq == 0)
+ intel_update_max_cdclk(display);
intel_hti_init(display);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index ef2fdbf97346..eb3e2a56af1d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1300,6 +1300,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
*/
static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
u32 val;
val = intel_de_read(dev_priv, LCPLL_CTL);
@@ -1343,8 +1344,8 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
- intel_update_cdclk(dev_priv);
- intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
+ intel_update_cdclk(display);
+ intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
}
/*
@@ -1416,7 +1417,8 @@ static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
static void skl_display_core_init(struct drm_i915_private *dev_priv,
bool resume)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct intel_display *display = &dev_priv->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *well;
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
@@ -1438,7 +1440,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
mutex_unlock(&power_domains->lock);
- intel_cdclk_init_hw(dev_priv);
+ intel_cdclk_init_hw(display);
gen9_dbuf_enable(dev_priv);
@@ -1448,7 +1450,8 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct intel_display *display = &dev_priv->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *well;
if (!HAS_DISPLAY(dev_priv))
@@ -1459,7 +1462,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_dbuf_disable(dev_priv);
- intel_cdclk_uninit_hw(dev_priv);
+ intel_cdclk_uninit_hw(display);
/* The spec doesn't call for removing the reset handshake flag */
/* disable PG1 and Misc I/O */
@@ -1482,7 +1485,8 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct intel_display *display = &dev_priv->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *well;
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
@@ -1506,7 +1510,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
mutex_unlock(&power_domains->lock);
- intel_cdclk_init_hw(dev_priv);
+ intel_cdclk_init_hw(display);
gen9_dbuf_enable(dev_priv);
@@ -1516,7 +1520,8 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct intel_display *display = &dev_priv->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *well;
if (!HAS_DISPLAY(dev_priv))
@@ -1527,7 +1532,7 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_dbuf_disable(dev_priv);
- intel_cdclk_uninit_hw(dev_priv);
+ intel_cdclk_uninit_hw(display);
/* The spec doesn't call for removing the reset handshake flag */
@@ -1623,7 +1628,8 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
static void icl_display_core_init(struct drm_i915_private *dev_priv,
bool resume)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct intel_display *display = &dev_priv->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *well;
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
@@ -1657,7 +1663,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0);
/* 4. Enable CDCLK. */
- intel_cdclk_init_hw(dev_priv);
+ intel_cdclk_init_hw(display);
if (DISPLAY_VER(dev_priv) >= 12)
gen12_dbuf_slices_config(dev_priv);
@@ -1704,7 +1710,8 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct intel_display *display = &dev_priv->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *well;
if (!HAS_DISPLAY(dev_priv))
@@ -1719,7 +1726,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_dbuf_disable(dev_priv);
/* 3. Disable CD clock */
- intel_cdclk_uninit_hw(dev_priv);
+ intel_cdclk_uninit_hw(display);
if (DISPLAY_VER(dev_priv) == 14)
intel_de_rmw(dev_priv, DC_STATE_EN, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 46e9eff12c23..7b40a5b88214 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -967,7 +967,8 @@ static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct intel_display *display = &dev_priv->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
struct intel_cdclk_config cdclk_config = {};
if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) {
@@ -982,10 +983,10 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
intel_dmc_wl_disable(&dev_priv->display);
- intel_cdclk_get_cdclk(dev_priv, &cdclk_config);
+ intel_cdclk_get_cdclk(display, &cdclk_config);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
- drm_WARN_ON(&dev_priv->drm,
- intel_cdclk_clock_changed(&dev_priv->display.cdclk.hw,
+ drm_WARN_ON(display->drm,
+ intel_cdclk_clock_changed(&display->cdclk.hw,
&cdclk_config));
gen9_assert_dbuf_enabled(dev_priv);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 29835b638495..6e1f04d5ef47 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2973,6 +2973,7 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
static void skl_wm_get_hw_state(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
struct intel_dbuf_state *dbuf_state =
to_intel_dbuf_state(i915->display.dbuf.obj.state);
struct intel_crtc *crtc;
@@ -2980,7 +2981,7 @@ static void skl_wm_get_hw_state(struct drm_i915_private *i915)
if (HAS_MBUS_JOINING(i915))
dbuf_state->joined_mbus = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN;
- dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(i915, &i915->display.cdclk.hw);
+ dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw);
for_each_intel_crtc(&i915->drm, crtc) {
struct intel_crtc_state *crtc_state =
--
2.44.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 3/6] drm/i915/power: Convert low level DC state code to intel_display
2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala
2024-09-06 14:33 ` [PATCH 1/6] drm/i915/cdclk: Add missing braces Ville Syrjala
2024-09-06 14:33 ` [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display Ville Syrjala
@ 2024-09-06 14:33 ` Ville Syrjala
2024-09-06 15:10 ` Rodrigo Vivi
2024-09-06 14:33 ` [PATCH 4/6] drm/i915/vga: Convert VGA " Ville Syrjala
` (7 subsequent siblings)
10 siblings, 1 reply; 23+ messages in thread
From: Ville Syrjala @ 2024-09-06 14:33 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert the lower level
DC state code to use it (as much as possible at this stage).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_display_power.c | 41 ++--
.../i915/display/intel_display_power_well.c | 199 ++++++++++--------
.../i915/display/intel_display_power_well.h | 15 +-
3 files changed, 139 insertions(+), 116 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index eb3e2a56af1d..86ac494ed33b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1421,7 +1421,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *well;
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ gen9_set_dc_state(display, DC_STATE_DISABLE);
/* enable PCH reset handshake */
intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
@@ -1457,7 +1457,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- gen9_disable_dc_states(dev_priv);
+ gen9_disable_dc_states(display);
/* TODO: disable DMC program */
gen9_dbuf_disable(dev_priv);
@@ -1489,7 +1489,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *well;
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ gen9_set_dc_state(display, DC_STATE_DISABLE);
/*
* NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
@@ -1527,7 +1527,7 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- gen9_disable_dc_states(dev_priv);
+ gen9_disable_dc_states(display);
/* TODO: disable DMC program */
gen9_dbuf_disable(dev_priv);
@@ -1632,7 +1632,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
struct i915_power_domains *power_domains = &display->power.domains;
struct i915_power_well *well;
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ gen9_set_dc_state(display, DC_STATE_DISABLE);
/* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
@@ -1717,7 +1717,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- gen9_disable_dc_states(dev_priv);
+ gen9_disable_dc_states(display);
intel_dmc_disable_program(dev_priv);
/* 1. Disable all display engine functions -> aready done */
@@ -2232,9 +2232,11 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
void intel_display_power_suspend_late(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
+
if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
IS_BROXTON(i915)) {
- bxt_enable_dc9(i915);
+ bxt_enable_dc9(display);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
hsw_enable_pc8(i915);
}
@@ -2246,10 +2248,12 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915)
void intel_display_power_resume_early(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
+
if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
IS_BROXTON(i915)) {
- gen9_sanitize_dc_state(i915);
- bxt_disable_dc9(i915);
+ gen9_sanitize_dc_state(display);
+ bxt_disable_dc9(display);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
hsw_disable_pc8(i915);
}
@@ -2261,12 +2265,14 @@ void intel_display_power_resume_early(struct drm_i915_private *i915)
void intel_display_power_suspend(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
+
if (DISPLAY_VER(i915) >= 11) {
icl_display_core_uninit(i915);
- bxt_enable_dc9(i915);
+ bxt_enable_dc9(display);
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
bxt_display_core_uninit(i915);
- bxt_enable_dc9(i915);
+ bxt_enable_dc9(display);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
hsw_enable_pc8(i915);
}
@@ -2274,23 +2280,24 @@ void intel_display_power_suspend(struct drm_i915_private *i915)
void intel_display_power_resume(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->display.power.domains;
+ struct intel_display *display = &i915->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
if (DISPLAY_VER(i915) >= 11) {
- bxt_disable_dc9(i915);
+ bxt_disable_dc9(display);
icl_display_core_init(i915, true);
if (intel_dmc_has_payload(i915)) {
if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
- skl_enable_dc6(i915);
+ skl_enable_dc6(display);
else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
- gen9_enable_dc5(i915);
+ gen9_enable_dc5(display);
}
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
- bxt_disable_dc9(i915);
+ bxt_disable_dc9(display);
bxt_display_core_init(i915, true);
if (intel_dmc_has_payload(i915) &&
(power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
- gen9_enable_dc5(i915);
+ gen9_enable_dc5(display);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
hsw_disable_pc8(i915);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 7b40a5b88214..1f0084ca6248 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -601,20 +601,22 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
return (val & mask) == mask;
}
-static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
+static void assert_can_enable_dc9(struct intel_display *display)
{
- drm_WARN_ONCE(&dev_priv->drm,
- (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9),
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
+ drm_WARN_ONCE(display->drm,
+ (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9),
"DC9 already programmed to be enabled.\n");
- drm_WARN_ONCE(&dev_priv->drm,
- intel_de_read(dev_priv, DC_STATE_EN) &
+ drm_WARN_ONCE(display->drm,
+ intel_de_read(display, DC_STATE_EN) &
DC_STATE_EN_UPTO_DC5,
"DC5 still not disabled to enable DC9.\n");
- drm_WARN_ONCE(&dev_priv->drm,
- intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) &
+ drm_WARN_ONCE(display->drm,
+ intel_de_read(display, HSW_PWR_WELL_CTL2) &
HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),
"Power well 2 on.\n");
- drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
+ drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv),
"Interrupts not disabled yet.\n");
/*
@@ -626,12 +628,14 @@ static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
*/
}
-static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
+static void assert_can_disable_dc9(struct intel_display *display)
{
- drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
+ drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv),
"Interrupts not disabled yet.\n");
- drm_WARN_ONCE(&dev_priv->drm,
- intel_de_read(dev_priv, DC_STATE_EN) &
+ drm_WARN_ONCE(display->drm,
+ intel_de_read(display, DC_STATE_EN) &
DC_STATE_EN_UPTO_DC5,
"DC5 still not disabled.\n");
@@ -644,14 +648,14 @@ static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
*/
}
-static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
+static void gen9_write_dc_state(struct intel_display *display,
u32 state)
{
int rewrites = 0;
int rereads = 0;
u32 v;
- intel_de_write(dev_priv, DC_STATE_EN, state);
+ intel_de_write(display, DC_STATE_EN, state);
/* It has been observed that disabling the dc6 state sometimes
* doesn't stick and dmc keeps returning old value. Make sure
@@ -659,10 +663,10 @@ static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
* we are confident that state is exactly what we want.
*/
do {
- v = intel_de_read(dev_priv, DC_STATE_EN);
+ v = intel_de_read(display, DC_STATE_EN);
if (v != state) {
- intel_de_write(dev_priv, DC_STATE_EN, state);
+ intel_de_write(display, DC_STATE_EN, state);
rewrites++;
rereads = 0;
} else if (rereads++ > 5) {
@@ -672,27 +676,28 @@ static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
} while (rewrites < 100);
if (v != state)
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"Writing dc state to 0x%x failed, now 0x%x\n",
state, v);
/* Most of the times we need one retry, avoid spam */
if (rewrites > 1)
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Rewrote dc state to 0x%x %d times\n",
state, rewrites);
}
-static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
+static u32 gen9_dc_mask(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 mask;
mask = DC_STATE_EN_UPTO_DC5;
- if (DISPLAY_VER(dev_priv) >= 12)
+ if (DISPLAY_VER(display) >= 12)
mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
| DC_STATE_EN_DC9;
- else if (DISPLAY_VER(dev_priv) == 11)
+ else if (DISPLAY_VER(display) == 11)
mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
mask |= DC_STATE_EN_DC9;
@@ -702,17 +707,17 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
return mask;
}
-void gen9_sanitize_dc_state(struct drm_i915_private *i915)
+void gen9_sanitize_dc_state(struct intel_display *display)
{
- struct i915_power_domains *power_domains = &i915->display.power.domains;
+ struct i915_power_domains *power_domains = &display->power.domains;
u32 val;
- if (!HAS_DISPLAY(i915))
+ if (!HAS_DISPLAY(display))
return;
- val = intel_de_read(i915, DC_STATE_EN) & gen9_dc_mask(i915);
+ val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display);
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Resetting DC state tracking from %02x to %02x\n",
power_domains->dc_state, val);
power_domains->dc_state = val;
@@ -720,7 +725,7 @@ void gen9_sanitize_dc_state(struct drm_i915_private *i915)
/**
* gen9_set_dc_state - set target display C power state
- * @dev_priv: i915 device instance
+ * @display: display instance
* @state: target DC power state
* - DC_STATE_DISABLE
* - DC_STATE_EN_UPTO_DC5
@@ -741,70 +746,71 @@ void gen9_sanitize_dc_state(struct drm_i915_private *i915)
* back on and register state is restored. This is guaranteed by the MMIO write
* to DC_STATE_EN blocking until the state is restored.
*/
-void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
+void gen9_set_dc_state(struct intel_display *display, u32 state)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct i915_power_domains *power_domains = &display->power.domains;
u32 val;
u32 mask;
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(display))
return;
- if (drm_WARN_ON_ONCE(&dev_priv->drm,
+ if (drm_WARN_ON_ONCE(display->drm,
state & ~power_domains->allowed_dc_mask))
state &= power_domains->allowed_dc_mask;
- val = intel_de_read(dev_priv, DC_STATE_EN);
- mask = gen9_dc_mask(dev_priv);
- drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to %02x\n",
+ val = intel_de_read(display, DC_STATE_EN);
+ mask = gen9_dc_mask(display);
+ drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n",
val & mask, state);
/* Check if DMC is ignoring our DC state requests */
if ((val & mask) != power_domains->dc_state)
- drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
+ drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
power_domains->dc_state, val & mask);
val &= ~mask;
val |= state;
- gen9_write_dc_state(dev_priv, val);
+ gen9_write_dc_state(display, val);
power_domains->dc_state = val & mask;
}
-static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
+static void tgl_enable_dc3co(struct intel_display *display)
{
- drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n");
- gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+ drm_dbg_kms(display->drm, "Enabling DC3CO\n");
+ gen9_set_dc_state(display, DC_STATE_EN_DC3CO);
}
-static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)
+static void tgl_disable_dc3co(struct intel_display *display)
{
- drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n");
- intel_de_rmw(dev_priv, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0);
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ drm_dbg_kms(display->drm, "Disabling DC3CO\n");
+ intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0);
+ gen9_set_dc_state(display, DC_STATE_DISABLE);
/*
* Delay of 200us DC3CO Exit time B.Spec 49196
*/
usleep_range(200, 210);
}
-static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
+static void assert_can_enable_dc5(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum i915_power_well_id high_pg;
/* Power wells at this level and above must be disabled for DC5 entry */
- if (DISPLAY_VER(dev_priv) == 12)
+ if (DISPLAY_VER(display) == 12)
high_pg = ICL_DISP_PW_3;
else
high_pg = SKL_DISP_PW_2;
- drm_WARN_ONCE(&dev_priv->drm,
+ drm_WARN_ONCE(display->drm,
intel_display_power_well_is_enabled(dev_priv, high_pg),
"Power wells above platform's DC5 limit still enabled.\n");
- drm_WARN_ONCE(&dev_priv->drm,
- (intel_de_read(dev_priv, DC_STATE_EN) &
+ drm_WARN_ONCE(display->drm,
+ (intel_de_read(display, DC_STATE_EN) &
DC_STATE_EN_UPTO_DC5),
"DC5 already programmed to be enabled.\n");
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
@@ -812,60 +818,66 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
assert_dmc_loaded(dev_priv);
}
-void gen9_enable_dc5(struct drm_i915_private *dev_priv)
+void gen9_enable_dc5(struct intel_display *display)
{
- assert_can_enable_dc5(dev_priv);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
- drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n");
+ assert_can_enable_dc5(display);
+
+ drm_dbg_kms(display->drm, "Enabling DC5\n");
/* Wa Display #1183: skl,kbl,cfl */
- if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
- intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
+ if (DISPLAY_VER(display) == 9 && !IS_BROXTON(dev_priv))
+ intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,
0, SKL_SELECT_ALTERNATE_DC_EXIT);
- intel_dmc_wl_enable(&dev_priv->display);
+ intel_dmc_wl_enable(display);
- gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
+ gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5);
}
-static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
+static void assert_can_enable_dc6(struct intel_display *display)
{
- drm_WARN_ONCE(&dev_priv->drm,
- (intel_de_read(dev_priv, UTIL_PIN_CTL) &
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
+ drm_WARN_ONCE(display->drm,
+ (intel_de_read(display, UTIL_PIN_CTL) &
(UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) ==
(UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),
"Utility pin enabled in PWM mode\n");
- drm_WARN_ONCE(&dev_priv->drm,
- (intel_de_read(dev_priv, DC_STATE_EN) &
+ drm_WARN_ONCE(display->drm,
+ (intel_de_read(display, DC_STATE_EN) &
DC_STATE_EN_UPTO_DC6),
"DC6 already programmed to be enabled.\n");
assert_dmc_loaded(dev_priv);
}
-void skl_enable_dc6(struct drm_i915_private *dev_priv)
+void skl_enable_dc6(struct intel_display *display)
{
- assert_can_enable_dc6(dev_priv);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
- drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n");
+ assert_can_enable_dc6(display);
+
+ drm_dbg_kms(display->drm, "Enabling DC6\n");
/* Wa Display #1183: skl,kbl,cfl */
- if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
- intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
+ if (DISPLAY_VER(display) == 9 && !IS_BROXTON(dev_priv))
+ intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,
0, SKL_SELECT_ALTERNATE_DC_EXIT);
- intel_dmc_wl_enable(&dev_priv->display);
+ intel_dmc_wl_enable(display);
- gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
+ gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
}
-void bxt_enable_dc9(struct drm_i915_private *dev_priv)
+void bxt_enable_dc9(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
- assert_can_enable_dc9(dev_priv);
+ assert_can_enable_dc9(display);
- drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n");
+ drm_dbg_kms(display->drm, "Enabling DC9\n");
/*
* Power sequencer reset is not needed on
* platforms with South Display Engine on PCH,
@@ -873,18 +885,16 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv)
*/
if (!HAS_PCH_SPLIT(dev_priv))
intel_pps_reset_all(display);
- gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
+ gen9_set_dc_state(display, DC_STATE_EN_DC9);
}
-void bxt_disable_dc9(struct drm_i915_private *dev_priv)
+void bxt_disable_dc9(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ assert_can_disable_dc9(display);
- assert_can_disable_dc9(dev_priv);
+ drm_dbg_kms(display->drm, "Disabling DC9\n");
- drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n");
-
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ gen9_set_dc_state(display, DC_STATE_DISABLE);
intel_pps_unlock_regs_wa(display);
}
@@ -949,8 +959,10 @@ static void bxt_verify_dpio_phy_power_wells(struct drm_i915_private *dev_priv)
static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- return ((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
- (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
+ struct intel_display *display = &dev_priv->display;
+
+ return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+ (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
}
static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
@@ -965,23 +977,23 @@ static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
enabled_dbuf_slices);
}
-void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
+void gen9_disable_dc_states(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct i915_power_domains *power_domains = &display->power.domains;
struct intel_cdclk_config cdclk_config = {};
if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) {
- tgl_disable_dc3co(dev_priv);
+ tgl_disable_dc3co(display);
return;
}
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ gen9_set_dc_state(display, DC_STATE_DISABLE);
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(display))
return;
- intel_dmc_wl_disable(&dev_priv->display);
+ intel_dmc_wl_disable(display);
intel_cdclk_get_cdclk(display, &cdclk_config);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
@@ -994,7 +1006,7 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
bxt_verify_dpio_phy_power_wells(dev_priv);
- if (DISPLAY_VER(dev_priv) >= 11)
+ if (DISPLAY_VER(display) >= 11)
/*
* DMC retains HW context only for port A, the other combo
* PHY's HW context for port B is lost after DC transitions,
@@ -1006,26 +1018,29 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- gen9_disable_dc_states(dev_priv);
+ struct intel_display *display = &dev_priv->display;
+
+ gen9_disable_dc_states(display);
}
static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct intel_display *display = &dev_priv->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
if (!intel_dmc_has_payload(dev_priv))
return;
switch (power_domains->target_dc_state) {
case DC_STATE_EN_DC3CO:
- tgl_enable_dc3co(dev_priv);
+ tgl_enable_dc3co(display);
break;
case DC_STATE_EN_UPTO_DC6:
- skl_enable_dc6(dev_priv);
+ skl_enable_dc6(display);
break;
case DC_STATE_EN_UPTO_DC5:
- gen9_enable_dc5(dev_priv);
+ gen9_enable_dc5(display);
break;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index 9357a9a73c06..93559f7c6100 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -12,6 +12,7 @@
struct drm_i915_private;
struct i915_power_well_ops;
+struct intel_display;
struct intel_encoder;
#define for_each_power_well(__dev_priv, __power_well) \
@@ -154,13 +155,13 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
enum dpio_channel ch, bool override);
-void gen9_enable_dc5(struct drm_i915_private *dev_priv);
-void skl_enable_dc6(struct drm_i915_private *dev_priv);
-void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
-void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state);
-void gen9_disable_dc_states(struct drm_i915_private *dev_priv);
-void bxt_enable_dc9(struct drm_i915_private *dev_priv);
-void bxt_disable_dc9(struct drm_i915_private *dev_priv);
+void gen9_enable_dc5(struct intel_display *display);
+void skl_enable_dc6(struct intel_display *display);
+void gen9_sanitize_dc_state(struct intel_display *display);
+void gen9_set_dc_state(struct intel_display *display, u32 state);
+void gen9_disable_dc_states(struct intel_display *display);
+void bxt_enable_dc9(struct intel_display *display);
+void bxt_disable_dc9(struct intel_display *display);
extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
extern const struct i915_power_well_ops chv_pipe_power_well_ops;
--
2.44.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 4/6] drm/i915/vga: Convert VGA code to intel_display
2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala
` (2 preceding siblings ...)
2024-09-06 14:33 ` [PATCH 3/6] drm/i915/power: Convert low level DC state " Ville Syrjala
@ 2024-09-06 14:33 ` Ville Syrjala
2024-09-06 15:12 ` Rodrigo Vivi
2024-09-06 14:33 ` [PATCH 5/6] drm/i915/power: Convert "i830 power well" " Ville Syrjala
` (6 subsequent siblings)
10 siblings, 1 reply; 23+ messages in thread
From: Ville Syrjala @ 2024-09-06 14:33 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert the VGA code to
use it (as much as possible at this stage).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_display_driver.c | 11 ++---
.../i915/display/intel_display_power_well.c | 6 ++-
drivers/gpu/drm/i915/display/intel_vga.c | 45 ++++++++++---------
drivers/gpu/drm/i915/display/intel_vga.h | 14 +++---
drivers/gpu/drm/i915/i915_suspend.c | 3 +-
5 files changed, 43 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 434e52f450ff..f8da72af2107 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -221,7 +221,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
intel_bios_init(display);
- ret = intel_vga_register(i915);
+ ret = intel_vga_register(display);
if (ret)
goto cleanup_bios;
@@ -275,7 +275,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
intel_dmc_fini(i915);
intel_power_domains_driver_remove(i915);
cleanup_vga:
- intel_vga_unregister(i915);
+ intel_vga_unregister(display);
cleanup_bios:
intel_bios_driver_remove(display);
@@ -458,7 +458,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
intel_hti_init(display);
/* Just disable it once at startup */
- intel_vga_disable(i915);
+ intel_vga_disable(display);
intel_setup_outputs(i915);
ret = intel_dp_tunnel_mgr_init(display);
@@ -625,7 +625,7 @@ void intel_display_driver_remove_nogem(struct drm_i915_private *i915)
intel_power_domains_driver_remove(i915);
- intel_vga_unregister(i915);
+ intel_vga_unregister(display);
intel_bios_driver_remove(display);
}
@@ -683,12 +683,13 @@ __intel_display_driver_resume(struct drm_i915_private *i915,
struct drm_atomic_state *state,
struct drm_modeset_acquire_ctx *ctx)
{
+ struct intel_display *display = &i915->display;
struct drm_crtc_state *crtc_state;
struct drm_crtc *crtc;
int ret, i;
intel_modeset_setup_hw_state(i915, ctx);
- intel_vga_redisable(i915);
+ intel_vga_redisable(display);
if (!state)
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 1f0084ca6248..a5d9b17e03a2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -187,8 +187,10 @@ int intel_power_well_refcount(struct i915_power_well *power_well)
static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
u8 irq_pipe_mask, bool has_vga)
{
+ struct intel_display *display = &dev_priv->display;
+
if (has_vga)
- intel_vga_reset_io_mem(dev_priv);
+ intel_vga_reset_io_mem(display);
if (irq_pipe_mask)
gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
@@ -1248,7 +1250,7 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
intel_crt_reset(&encoder->base);
}
- intel_vga_redisable_power_on(dev_priv);
+ intel_vga_redisable_power_on(display);
intel_pps_unlock_regs_wa(display);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
index 0b5916c15307..2c76a0176a35 100644
--- a/drivers/gpu/drm/i915/display/intel_vga.c
+++ b/drivers/gpu/drm/i915/display/intel_vga.c
@@ -14,24 +14,26 @@
#include "intel_de.h"
#include "intel_vga.h"
-static i915_reg_t intel_vga_cntrl_reg(struct drm_i915_private *i915)
+static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
return VLV_VGACNTRL;
- else if (DISPLAY_VER(i915) >= 5)
+ else if (DISPLAY_VER(display) >= 5)
return CPU_VGACNTRL;
else
return VGACNTRL;
}
/* Disable the VGA plane that we never use */
-void intel_vga_disable(struct drm_i915_private *dev_priv)
+void intel_vga_disable(struct intel_display *display)
{
- struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
- i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv);
+ struct pci_dev *pdev = to_pci_dev(display->drm->dev);
+ i915_reg_t vga_reg = intel_vga_cntrl_reg(display);
u8 sr1;
- if (intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE)
+ if (intel_de_read(display, vga_reg) & VGA_DISP_DISABLE)
return;
/* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
@@ -42,23 +44,24 @@ void intel_vga_disable(struct drm_i915_private *dev_priv)
vga_put(pdev, VGA_RSRC_LEGACY_IO);
udelay(300);
- intel_de_write(dev_priv, vga_reg, VGA_DISP_DISABLE);
- intel_de_posting_read(dev_priv, vga_reg);
+ intel_de_write(display, vga_reg, VGA_DISP_DISABLE);
+ intel_de_posting_read(display, vga_reg);
}
-void intel_vga_redisable_power_on(struct drm_i915_private *dev_priv)
+void intel_vga_redisable_power_on(struct intel_display *display)
{
- i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv);
+ i915_reg_t vga_reg = intel_vga_cntrl_reg(display);
- if (!(intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE)) {
- drm_dbg_kms(&dev_priv->drm,
+ if (!(intel_de_read(display, vga_reg) & VGA_DISP_DISABLE)) {
+ drm_dbg_kms(display->drm,
"Something enabled VGA plane, disabling it\n");
- intel_vga_disable(dev_priv);
+ intel_vga_disable(display);
}
}
-void intel_vga_redisable(struct drm_i915_private *i915)
+void intel_vga_redisable(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
intel_wakeref_t wakeref;
/*
@@ -74,14 +77,14 @@ void intel_vga_redisable(struct drm_i915_private *i915)
if (!wakeref)
return;
- intel_vga_redisable_power_on(i915);
+ intel_vga_redisable_power_on(display);
intel_display_power_put(i915, POWER_DOMAIN_VGA, wakeref);
}
-void intel_vga_reset_io_mem(struct drm_i915_private *i915)
+void intel_vga_reset_io_mem(struct intel_display *display)
{
- struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct pci_dev *pdev = to_pci_dev(display->drm->dev);
/*
* After we re-enable the power well, if we touch VGA register 0x3d5
@@ -98,10 +101,10 @@ void intel_vga_reset_io_mem(struct drm_i915_private *i915)
vga_put(pdev, VGA_RSRC_LEGACY_IO);
}
-int intel_vga_register(struct drm_i915_private *i915)
+int intel_vga_register(struct intel_display *display)
{
- struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct pci_dev *pdev = to_pci_dev(display->drm->dev);
int ret;
/*
@@ -119,9 +122,9 @@ int intel_vga_register(struct drm_i915_private *i915)
return 0;
}
-void intel_vga_unregister(struct drm_i915_private *i915)
+void intel_vga_unregister(struct intel_display *display)
{
- struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct pci_dev *pdev = to_pci_dev(display->drm->dev);
vga_client_unregister(pdev);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vga.h b/drivers/gpu/drm/i915/display/intel_vga.h
index ba5b55b917f0..824dfc32a199 100644
--- a/drivers/gpu/drm/i915/display/intel_vga.h
+++ b/drivers/gpu/drm/i915/display/intel_vga.h
@@ -6,13 +6,13 @@
#ifndef __INTEL_VGA_H__
#define __INTEL_VGA_H__
-struct drm_i915_private;
+struct intel_display;
-void intel_vga_reset_io_mem(struct drm_i915_private *i915);
-void intel_vga_disable(struct drm_i915_private *i915);
-void intel_vga_redisable(struct drm_i915_private *i915);
-void intel_vga_redisable_power_on(struct drm_i915_private *i915);
-int intel_vga_register(struct drm_i915_private *i915);
-void intel_vga_unregister(struct drm_i915_private *i915);
+void intel_vga_reset_io_mem(struct intel_display *display);
+void intel_vga_disable(struct intel_display *display);
+void intel_vga_redisable(struct intel_display *display);
+void intel_vga_redisable_power_on(struct intel_display *display);
+int intel_vga_register(struct intel_display *display);
+void intel_vga_unregister(struct intel_display *display);
#endif /* __INTEL_VGA_H__ */
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index f8373a461f17..9d3d9b983032 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -118,6 +118,7 @@ void i915_save_display(struct drm_i915_private *dev_priv)
void i915_restore_display(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
if (!HAS_DISPLAY(dev_priv))
@@ -134,7 +135,7 @@ void i915_restore_display(struct drm_i915_private *dev_priv)
intel_de_write(dev_priv, DSPARB(dev_priv),
dev_priv->regfile.saveDSPARB);
- intel_vga_redisable(dev_priv);
+ intel_vga_redisable(display);
intel_gmbus_reset(dev_priv);
}
--
2.44.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 5/6] drm/i915/power: Convert "i830 power well" code to intel_display
2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala
` (3 preceding siblings ...)
2024-09-06 14:33 ` [PATCH 4/6] drm/i915/vga: Convert VGA " Ville Syrjala
@ 2024-09-06 14:33 ` Ville Syrjala
2024-09-06 15:13 ` Rodrigo Vivi
2024-09-06 14:33 ` [PATCH 6/6] drm/i915/dmc: Convert DMC " Ville Syrjala
` (5 subsequent siblings)
10 siblings, 1 reply; 23+ messages in thread
From: Ville Syrjala @ 2024-09-06 14:33 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert the "i830 power well"
code to use it (as much as possible at this stage).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 79 +++++++++----------
drivers/gpu/drm/i915/display/intel_display.h | 5 +-
.../i915/display/intel_display_power_well.c | 22 ++++--
3 files changed, 56 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b4ec9bf12aa7..0ec78b06ca80 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2226,9 +2226,10 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
static void i9xx_crtc_disable(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
+ struct intel_display *display = to_intel_display(state);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
/*
@@ -2267,7 +2268,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
/* clock the pipe down to 640x480@60 to potentially save power */
if (IS_I830(dev_priv))
- i830_enable_pipe(dev_priv, pipe);
+ i830_enable_pipe(display, pipe);
}
void intel_encoder_destroy(struct drm_encoder *encoder)
@@ -8257,9 +8258,8 @@ int intel_initial_commit(struct drm_device *dev)
return ret;
}
-void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
+void i830_enable_pipe(struct intel_display *display, enum pipe pipe)
{
- struct intel_display *display = &dev_priv->display;
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
enum transcoder cpu_transcoder = (enum transcoder)pipe;
/* 640x480@60Hz, ~25175 kHz */
@@ -8273,10 +8273,10 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
u32 dpll, fp;
int i;
- drm_WARN_ON(&dev_priv->drm,
+ drm_WARN_ON(display->drm,
i9xx_calc_dpll_params(48000, &clock) != 25154);
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
pipe_name(pipe), clock.vco, clock.dot);
@@ -8288,35 +8288,35 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
PLL_REF_INPUT_DREFCLK |
DPLL_VCO_ENABLE;
- intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
HACTIVE(640 - 1) | HTOTAL(800 - 1));
- intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
- intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
- intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
VACTIVE(480 - 1) | VTOTAL(525 - 1));
- intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
- intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
- intel_de_write(dev_priv, PIPESRC(dev_priv, pipe),
+ intel_de_write(display, PIPESRC(display, pipe),
PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
- intel_de_write(dev_priv, FP0(pipe), fp);
- intel_de_write(dev_priv, FP1(pipe), fp);
+ intel_de_write(display, FP0(pipe), fp);
+ intel_de_write(display, FP1(pipe), fp);
/*
* Apparently we need to have VGA mode enabled prior to changing
* the P1/P2 dividers. Otherwise the DPLL will keep using the old
* dividers, even though the register value does change.
*/
- intel_de_write(dev_priv, DPLL(dev_priv, pipe),
+ intel_de_write(display, DPLL(display, pipe),
dpll & ~DPLL_VGA_MODE_DIS);
- intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
+ intel_de_write(display, DPLL(display, pipe), dpll);
/* Wait for the clocks to stabilize. */
- intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
+ intel_de_posting_read(display, DPLL(display, pipe));
udelay(150);
/* The pixel multiplier can only be updated once the
@@ -8324,47 +8324,46 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
*
* So write it again.
*/
- intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
+ intel_de_write(display, DPLL(display, pipe), dpll);
/* We do this three times for luck */
for (i = 0; i < 3 ; i++) {
- intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
- intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
+ intel_de_write(display, DPLL(display, pipe), dpll);
+ intel_de_posting_read(display, DPLL(display, pipe));
udelay(150); /* wait for warmup */
}
- intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), TRANSCONF_ENABLE);
- intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe));
+ intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE);
+ intel_de_posting_read(display, TRANSCONF(display, pipe));
intel_wait_for_pipe_scanline_moving(crtc);
}
-void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
+void i830_disable_pipe(struct intel_display *display, enum pipe pipe)
{
- struct intel_display *display = &dev_priv->display;
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
- drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
+ drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n",
pipe_name(pipe));
- drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_A)) & DISP_ENABLE);
- drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_B)) & DISP_ENABLE);
- drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_C)) & DISP_ENABLE);
- drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & MCURSOR_MODE_MASK);
- drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_B)) & MCURSOR_MODE_MASK);
+ drm_WARN_ON(display->drm,
+ intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE);
+ drm_WARN_ON(display->drm,
+ intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE);
+ drm_WARN_ON(display->drm,
+ intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE);
+ drm_WARN_ON(display->drm,
+ intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK);
+ drm_WARN_ON(display->drm,
+ intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK);
- intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), 0);
- intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe));
+ intel_de_write(display, TRANSCONF(display, pipe), 0);
+ intel_de_posting_read(display, TRANSCONF(display, pipe));
intel_wait_for_pipe_scanline_stopped(crtc);
- intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS);
- intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
+ intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);
+ intel_de_posting_read(display, DPLL(display, pipe));
}
void intel_hpd_poll_fini(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index b21d9578d5db..7ca26e5cb20e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -52,6 +52,7 @@ struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_digital_port;
+struct intel_display;
struct intel_dp;
struct intel_encoder;
struct intel_initial_plane_config;
@@ -437,8 +438,8 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
-void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
-void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
+void i830_enable_pipe(struct intel_display *display, enum pipe pipe);
+void i830_disable_pipe(struct intel_display *display, enum pipe pipe);
int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
const char *name, u32 reg, int ref_freq);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index a5d9b17e03a2..9f275a6674a1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1066,24 +1066,30 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0)
- i830_enable_pipe(dev_priv, PIPE_A);
- if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0)
- i830_enable_pipe(dev_priv, PIPE_B);
+ struct intel_display *display = &dev_priv->display;
+
+ if ((intel_de_read(display, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0)
+ i830_enable_pipe(display, PIPE_A);
+ if ((intel_de_read(display, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0)
+ i830_enable_pipe(display, PIPE_B);
}
static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- i830_disable_pipe(dev_priv, PIPE_B);
- i830_disable_pipe(dev_priv, PIPE_A);
+ struct intel_display *display = &dev_priv->display;
+
+ i830_disable_pipe(display, PIPE_B);
+ i830_disable_pipe(display, PIPE_A);
}
static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- return intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE &&
- intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE;
+ struct intel_display *display = &dev_priv->display;
+
+ return intel_de_read(display, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE &&
+ intel_de_read(display, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE;
}
static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
--
2.44.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 6/6] drm/i915/dmc: Convert DMC code to intel_display
2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala
` (4 preceding siblings ...)
2024-09-06 14:33 ` [PATCH 5/6] drm/i915/power: Convert "i830 power well" " Ville Syrjala
@ 2024-09-06 14:33 ` Ville Syrjala
2024-09-06 15:16 ` Rodrigo Vivi
2024-09-06 15:43 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Some intel_display conversions Patchwork
` (4 subsequent siblings)
10 siblings, 1 reply; 23+ messages in thread
From: Ville Syrjala @ 2024-09-06 14:33 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert the DMC code to
use it (as much as possible at this stage).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 7 +-
.../drm/i915/display/intel_display_debugfs.c | 2 +-
.../drm/i915/display/intel_display_driver.c | 6 +-
.../drm/i915/display/intel_display_power.c | 17 +-
.../i915/display/intel_display_power_well.c | 8 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 391 +++++++++---------
drivers/gpu/drm/i915/display/intel_dmc.h | 26 +-
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 4 +-
.../drm/i915/display/intel_modeset_setup.c | 3 +-
drivers/gpu/drm/i915/i915_driver.c | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/xe/display/xe_display.c | 4 +-
12 files changed, 243 insertions(+), 233 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0ec78b06ca80..fdf244a32b24 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1690,7 +1690,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
intel_crtc_joined_pipe_mask(new_crtc_state))
- intel_dmc_enable_pipe(dev_priv, pipe_crtc->pipe);
+ intel_dmc_enable_pipe(display, pipe_crtc->pipe);
intel_encoders_pre_pll_enable(state, crtc);
@@ -1843,9 +1843,10 @@ static void ilk_crtc_disable(struct intel_atomic_state *state,
static void hsw_crtc_disable(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
+ struct intel_display *display = to_intel_display(state);
+ struct drm_i915_private *i915 = to_i915(display->drm);
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_crtc *pipe_crtc;
/*
@@ -1867,7 +1868,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc,
intel_crtc_joined_pipe_mask(old_crtc_state))
- intel_dmc_disable_pipe(i915, pipe_crtc->pipe);
+ intel_dmc_disable_pipe(display, pipe_crtc->pipe);
}
static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index c1bef34d1ffd..b75361e95e97 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1069,7 +1069,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
intel_bios_debugfs_register(display);
intel_cdclk_debugfs_register(display);
- intel_dmc_debugfs_register(i915);
+ intel_dmc_debugfs_register(display);
intel_fbc_debugfs_register(display);
intel_hpd_debugfs_register(i915);
intel_opregion_debugfs_register(display);
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index f8da72af2107..c106fb2dd20b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -237,7 +237,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
if (!HAS_DISPLAY(i915))
return 0;
- intel_dmc_init(i915);
+ intel_dmc_init(display);
i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0);
i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI |
@@ -272,7 +272,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
return 0;
cleanup_vga_client_pw_domain_dmc:
- intel_dmc_fini(i915);
+ intel_dmc_fini(display);
intel_power_domains_driver_remove(i915);
cleanup_vga:
intel_vga_unregister(display);
@@ -621,7 +621,7 @@ void intel_display_driver_remove_nogem(struct drm_i915_private *i915)
{
struct intel_display *display = &i915->display;
- intel_dmc_fini(i915);
+ intel_dmc_fini(display);
intel_power_domains_driver_remove(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 86ac494ed33b..ecabb674644b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1445,7 +1445,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
gen9_dbuf_enable(dev_priv);
if (resume)
- intel_dmc_load_program(dev_priv);
+ intel_dmc_load_program(display);
}
static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
@@ -1515,7 +1515,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
gen9_dbuf_enable(dev_priv);
if (resume)
- intel_dmc_load_program(dev_priv);
+ intel_dmc_load_program(display);
}
static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
@@ -1687,7 +1687,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1);
if (resume)
- intel_dmc_load_program(dev_priv);
+ intel_dmc_load_program(display);
/* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */
if (IS_DISPLAY_VER_FULL(dev_priv, IP_VER(12, 0), IP_VER(13, 0)))
@@ -1718,7 +1718,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
return;
gen9_disable_dc_states(display);
- intel_dmc_disable_program(dev_priv);
+ intel_dmc_disable_program(display);
/* 1. Disable all display engine functions -> aready done */
@@ -2073,7 +2073,8 @@ void intel_power_domains_disable(struct drm_i915_private *i915)
*/
void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle)
{
- struct i915_power_domains *power_domains = &i915->display.power.domains;
+ struct intel_display *display = &i915->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
intel_wakeref_t wakeref __maybe_unused =
fetch_and_zero(&power_domains->init_wakeref);
@@ -2087,7 +2088,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle)
* that would be blocked if the firmware was inactive.
*/
if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle &&
- intel_dmc_has_payload(i915)) {
+ intel_dmc_has_payload(display)) {
intel_display_power_flush_work(i915);
intel_power_domains_verify_state(i915);
return;
@@ -2286,7 +2287,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
if (DISPLAY_VER(i915) >= 11) {
bxt_disable_dc9(display);
icl_display_core_init(i915, true);
- if (intel_dmc_has_payload(i915)) {
+ if (intel_dmc_has_payload(display)) {
if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(display);
else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
@@ -2295,7 +2296,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
bxt_disable_dc9(display);
bxt_display_core_init(i915, true);
- if (intel_dmc_has_payload(i915) &&
+ if (intel_dmc_has_payload(display) &&
(power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
gen9_enable_dc5(display);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 9f275a6674a1..1898aff50ac4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -817,7 +817,7 @@ static void assert_can_enable_dc5(struct intel_display *display)
"DC5 already programmed to be enabled.\n");
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
- assert_dmc_loaded(dev_priv);
+ assert_dmc_loaded(display);
}
void gen9_enable_dc5(struct intel_display *display)
@@ -840,8 +840,6 @@ void gen9_enable_dc5(struct intel_display *display)
static void assert_can_enable_dc6(struct intel_display *display)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
-
drm_WARN_ONCE(display->drm,
(intel_de_read(display, UTIL_PIN_CTL) &
(UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) ==
@@ -852,7 +850,7 @@ static void assert_can_enable_dc6(struct intel_display *display)
DC_STATE_EN_UPTO_DC6),
"DC6 already programmed to be enabled.\n");
- assert_dmc_loaded(dev_priv);
+ assert_dmc_loaded(display);
}
void skl_enable_dc6(struct intel_display *display)
@@ -1031,7 +1029,7 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
struct intel_display *display = &dev_priv->display;
struct i915_power_domains *power_domains = &display->power.domains;
- if (!intel_dmc_has_payload(dev_priv))
+ if (!intel_dmc_has_payload(display))
return;
switch (power_domains->target_dc_state) {
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 7c756d5ba2a2..bbac6bfd1752 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -52,7 +52,7 @@ enum intel_dmc_id {
};
struct intel_dmc {
- struct drm_i915_private *i915;
+ struct intel_display *display;
struct work_struct work;
const char *fw_path;
u32 max_fw_size; /* bytes */
@@ -70,21 +70,21 @@ struct intel_dmc {
};
/* Note: This may be NULL. */
-static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915)
+static struct intel_dmc *display_to_dmc(struct intel_display *display)
{
- return i915->display.dmc.dmc;
+ return display->dmc.dmc;
}
-static const char *dmc_firmware_param(struct drm_i915_private *i915)
+static const char *dmc_firmware_param(struct intel_display *display)
{
- const char *p = i915->display.params.dmc_firmware_path;
+ const char *p = display->params.dmc_firmware_path;
return p && *p ? p : NULL;
}
-static bool dmc_firmware_param_disabled(struct drm_i915_private *i915)
+static bool dmc_firmware_param_disabled(struct intel_display *display)
{
- const char *p = dmc_firmware_param(i915);
+ const char *p = dmc_firmware_param(display);
/* Magic path to indicate disabled */
return p && !strcmp(p, "/dev/null");
@@ -162,18 +162,19 @@ MODULE_FIRMWARE(SKL_DMC_PATH);
#define BXT_DMC_MAX_FW_SIZE 0x3000
MODULE_FIRMWARE(BXT_DMC_PATH);
-static const char *dmc_firmware_default(struct drm_i915_private *i915, u32 *size)
+static const char *dmc_firmware_default(struct intel_display *display, u32 *size)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
const char *fw_path = NULL;
u32 max_fw_size = 0;
- if (DISPLAY_VER_FULL(i915) == IP_VER(20, 0)) {
+ if (DISPLAY_VER_FULL(display) == IP_VER(20, 0)) {
fw_path = XE2LPD_DMC_PATH;
max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
- } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) {
+ } else if (DISPLAY_VER_FULL(display) == IP_VER(14, 1)) {
fw_path = BMG_DMC_PATH;
max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
- } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
+ } else if (DISPLAY_VER_FULL(display) == IP_VER(14, 0)) {
fw_path = MTL_DMC_PATH;
max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
} else if (IS_DG2(i915)) {
@@ -194,7 +195,7 @@ static const char *dmc_firmware_default(struct drm_i915_private *i915, u32 *size
} else if (IS_TIGERLAKE(i915)) {
fw_path = TGL_DMC_PATH;
max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
- } else if (DISPLAY_VER(i915) == 11) {
+ } else if (DISPLAY_VER(display) == 11) {
fw_path = ICL_DMC_PATH;
max_fw_size = ICL_DMC_MAX_FW_SIZE;
} else if (IS_GEMINILAKE(i915)) {
@@ -375,70 +376,70 @@ static bool is_valid_dmc_id(enum intel_dmc_id dmc_id)
return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX;
}
-static bool has_dmc_id_fw(struct drm_i915_private *i915, enum intel_dmc_id dmc_id)
+static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id)
{
- struct intel_dmc *dmc = i915_to_dmc(i915);
+ struct intel_dmc *dmc = display_to_dmc(display);
return dmc && dmc->dmc_info[dmc_id].payload;
}
-bool intel_dmc_has_payload(struct drm_i915_private *i915)
+bool intel_dmc_has_payload(struct intel_display *display)
{
- return has_dmc_id_fw(i915, DMC_FW_MAIN);
+ return has_dmc_id_fw(display, DMC_FW_MAIN);
}
static const struct stepping_info *
-intel_get_stepping_info(struct drm_i915_private *i915,
+intel_get_stepping_info(struct intel_display *display,
struct stepping_info *si)
{
- const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(i915));
+ const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display));
si->stepping = step_name[0];
si->substepping = step_name[1];
return si;
}
-static void gen9_set_dc_state_debugmask(struct drm_i915_private *i915)
+static void gen9_set_dc_state_debugmask(struct intel_display *display)
{
/* The below bit doesn't need to be cleared ever afterwards */
- intel_de_rmw(i915, DC_STATE_DEBUG, 0,
+ intel_de_rmw(display, DC_STATE_DEBUG, 0,
DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
- intel_de_posting_read(i915, DC_STATE_DEBUG);
+ intel_de_posting_read(display, DC_STATE_DEBUG);
}
-static void disable_event_handler(struct drm_i915_private *i915,
+static void disable_event_handler(struct intel_display *display,
i915_reg_t ctl_reg, i915_reg_t htp_reg)
{
- intel_de_write(i915, ctl_reg,
+ intel_de_write(display, ctl_reg,
REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
DMC_EVT_CTL_TYPE_EDGE_0_1) |
REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
DMC_EVT_CTL_EVENT_ID_FALSE));
- intel_de_write(i915, htp_reg, 0);
+ intel_de_write(display, htp_reg, 0);
}
-static void disable_all_event_handlers(struct drm_i915_private *i915)
+static void disable_all_event_handlers(struct intel_display *display)
{
enum intel_dmc_id dmc_id;
/* TODO: disable the event handlers on pre-GEN12 platforms as well */
- if (DISPLAY_VER(i915) < 12)
+ if (DISPLAY_VER(display) < 12)
return;
for_each_dmc_id(dmc_id) {
int handler;
- if (!has_dmc_id_fw(i915, dmc_id))
+ if (!has_dmc_id_fw(display, dmc_id))
continue;
for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++)
- disable_event_handler(i915,
- DMC_EVT_CTL(i915, dmc_id, handler),
- DMC_EVT_HTP(i915, dmc_id, handler));
+ disable_event_handler(display,
+ DMC_EVT_CTL(display, dmc_id, handler),
+ DMC_EVT_HTP(display, dmc_id, handler));
}
}
-static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
+static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable)
{
enum pipe pipe;
@@ -451,84 +452,86 @@ static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool ena
*/
if (enable)
for (pipe = PIPE_A; pipe <= PIPE_D; pipe++)
- intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe),
+ intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),
0, PIPEDMC_GATING_DIS);
else
for (pipe = PIPE_C; pipe <= PIPE_D; pipe++)
- intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe),
+ intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),
PIPEDMC_GATING_DIS, 0);
}
-static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915)
+static void mtl_pipedmc_clock_gating_wa(struct intel_display *display)
{
/*
* Wa_16015201720
* The WA requires clock gating to be disabled all the time
* for pipe A and B.
*/
- intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0,
+ intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0,
MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B);
}
-static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
+static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable)
{
- if (DISPLAY_VER(i915) >= 14 && enable)
- mtl_pipedmc_clock_gating_wa(i915);
- else if (DISPLAY_VER(i915) == 13)
- adlp_pipedmc_clock_gating_wa(i915, enable);
+ if (DISPLAY_VER(display) >= 14 && enable)
+ mtl_pipedmc_clock_gating_wa(display);
+ else if (DISPLAY_VER(display) == 13)
+ adlp_pipedmc_clock_gating_wa(display, enable);
}
-void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
+void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe)
{
enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
- if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id))
+ if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
return;
- if (DISPLAY_VER(i915) >= 14)
- intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));
+ if (DISPLAY_VER(display) >= 14)
+ intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));
else
- intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);
+ intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);
}
-void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe)
+void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe)
{
enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
- if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id))
+ if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
return;
- if (DISPLAY_VER(i915) >= 14)
- intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);
+ if (DISPLAY_VER(display) >= 14)
+ intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);
else
- intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
+ intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
}
-static bool is_dmc_evt_ctl_reg(struct drm_i915_private *i915,
+static bool is_dmc_evt_ctl_reg(struct intel_display *display,
enum intel_dmc_id dmc_id, i915_reg_t reg)
{
u32 offset = i915_mmio_reg_offset(reg);
- u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, 0));
- u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
+ u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0));
+ u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
return offset >= start && offset < end;
}
-static bool is_dmc_evt_htp_reg(struct drm_i915_private *i915,
+static bool is_dmc_evt_htp_reg(struct intel_display *display,
enum intel_dmc_id dmc_id, i915_reg_t reg)
{
u32 offset = i915_mmio_reg_offset(reg);
- u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, 0));
- u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
+ u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0));
+ u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
return offset >= start && offset < end;
}
-static bool disable_dmc_evt(struct drm_i915_private *i915,
+static bool disable_dmc_evt(struct intel_display *display,
enum intel_dmc_id dmc_id,
i915_reg_t reg, u32 data)
{
- if (!is_dmc_evt_ctl_reg(i915, dmc_id, reg))
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
+ if (!is_dmc_evt_ctl_reg(display, dmc_id, reg))
return false;
/* keep all pipe DMC events disabled by default */
@@ -548,11 +551,11 @@ static bool disable_dmc_evt(struct drm_i915_private *i915,
return false;
}
-static u32 dmc_mmiodata(struct drm_i915_private *i915,
+static u32 dmc_mmiodata(struct intel_display *display,
struct intel_dmc *dmc,
enum intel_dmc_id dmc_id, int i)
{
- if (disable_dmc_evt(i915, dmc_id,
+ if (disable_dmc_evt(display, dmc_id,
dmc->dmc_info[dmc_id].mmioaddr[i],
dmc->dmc_info[dmc_id].mmiodata[i]))
return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
@@ -565,25 +568,26 @@ static u32 dmc_mmiodata(struct drm_i915_private *i915,
/**
* intel_dmc_load_program() - write the firmware from memory to register.
- * @i915: i915 drm device.
+ * @display: display instance
*
* DMC firmware is read from a .bin file and kept in internal memory one time.
* Everytime display comes back from low power state this function is called to
* copy the firmware from internal memory to registers.
*/
-void intel_dmc_load_program(struct drm_i915_private *i915)
+void intel_dmc_load_program(struct intel_display *display)
{
- struct i915_power_domains *power_domains = &i915->display.power.domains;
- struct intel_dmc *dmc = i915_to_dmc(i915);
+ struct drm_i915_private *i915 __maybe_unused = to_i915(display->drm);
+ struct i915_power_domains *power_domains = &display->power.domains;
+ struct intel_dmc *dmc = display_to_dmc(display);
enum intel_dmc_id dmc_id;
u32 i;
- if (!intel_dmc_has_payload(i915))
+ if (!intel_dmc_has_payload(display))
return;
- pipedmc_clock_gating_wa(i915, true);
+ pipedmc_clock_gating_wa(display, true);
- disable_all_event_handlers(i915);
+ disable_all_event_handlers(display);
assert_rpm_wakelock_held(&i915->runtime_pm);
@@ -591,7 +595,7 @@ void intel_dmc_load_program(struct drm_i915_private *i915)
for_each_dmc_id(dmc_id) {
for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) {
- intel_de_write_fw(i915,
+ intel_de_write_fw(display,
DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i),
dmc->dmc_info[dmc_id].payload[i]);
}
@@ -601,48 +605,48 @@ void intel_dmc_load_program(struct drm_i915_private *i915)
for_each_dmc_id(dmc_id) {
for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
- intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i],
- dmc_mmiodata(i915, dmc, dmc_id, i));
+ intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i],
+ dmc_mmiodata(display, dmc, dmc_id, i));
}
}
power_domains->dc_state = 0;
- gen9_set_dc_state_debugmask(i915);
+ gen9_set_dc_state_debugmask(display);
- pipedmc_clock_gating_wa(i915, false);
+ pipedmc_clock_gating_wa(display, false);
}
/**
* intel_dmc_disable_program() - disable the firmware
- * @i915: i915 drm device
+ * @display: display instance
*
* Disable all event handlers in the firmware, making sure the firmware is
* inactive after the display is uninitialized.
*/
-void intel_dmc_disable_program(struct drm_i915_private *i915)
+void intel_dmc_disable_program(struct intel_display *display)
{
- if (!intel_dmc_has_payload(i915))
+ if (!intel_dmc_has_payload(display))
return;
- pipedmc_clock_gating_wa(i915, true);
- disable_all_event_handlers(i915);
- pipedmc_clock_gating_wa(i915, false);
+ pipedmc_clock_gating_wa(display, true);
+ disable_all_event_handlers(display);
+ pipedmc_clock_gating_wa(display, false);
- intel_dmc_wl_disable(&i915->display);
+ intel_dmc_wl_disable(display);
}
-void assert_dmc_loaded(struct drm_i915_private *i915)
+void assert_dmc_loaded(struct intel_display *display)
{
- struct intel_dmc *dmc = i915_to_dmc(i915);
+ struct intel_dmc *dmc = display_to_dmc(display);
- drm_WARN_ONCE(&i915->drm, !dmc, "DMC not initialized\n");
- drm_WARN_ONCE(&i915->drm, dmc &&
- !intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+ drm_WARN_ONCE(display->drm, !dmc, "DMC not initialized\n");
+ drm_WARN_ONCE(display->drm, dmc &&
+ !intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
"DMC program storage start is NULL\n");
- drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE),
+ drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_SSP_BASE),
"DMC SSP Base Not fine\n");
- drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL),
+ drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_HTP_SKL),
"DMC HTP Not fine\n");
}
@@ -673,7 +677,7 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc,
const struct stepping_info *si,
u8 package_ver)
{
- struct drm_i915_private *i915 = dmc->i915;
+ struct intel_display *display = dmc->display;
enum intel_dmc_id dmc_id;
unsigned int i;
@@ -681,7 +685,7 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc,
dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;
if (!is_valid_dmc_id(dmc_id)) {
- drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", dmc_id);
+ drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id);
continue;
}
@@ -703,7 +707,7 @@ static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,
const u32 *mmioaddr, u32 mmio_count,
int header_ver, enum intel_dmc_id dmc_id)
{
- struct drm_i915_private *i915 = dmc->i915;
+ struct intel_display *display = dmc->display;
u32 start_range, end_range;
int i;
@@ -713,14 +717,14 @@ static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,
} else if (dmc_id == DMC_FW_MAIN) {
start_range = TGL_MAIN_MMIO_START;
end_range = TGL_MAIN_MMIO_END;
- } else if (DISPLAY_VER(i915) >= 13) {
+ } else if (DISPLAY_VER(display) >= 13) {
start_range = ADLP_PIPE_MMIO_START;
end_range = ADLP_PIPE_MMIO_END;
- } else if (DISPLAY_VER(i915) >= 12) {
+ } else if (DISPLAY_VER(display) >= 12) {
start_range = TGL_PIPE_MMIO_START(dmc_id);
end_range = TGL_PIPE_MMIO_END(dmc_id);
} else {
- drm_warn(&i915->drm, "Unknown mmio range for sanity check");
+ drm_warn(display->drm, "Unknown mmio range for sanity check");
return false;
}
@@ -736,7 +740,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
const struct intel_dmc_header_base *dmc_header,
size_t rem_size, enum intel_dmc_id dmc_id)
{
- struct drm_i915_private *i915 = dmc->i915;
+ struct intel_display *display = dmc->display;
struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
@@ -784,39 +788,39 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
start_mmioaddr = DMC_V1_MMIO_START_RANGE;
dmc_header_size = sizeof(*v1);
} else {
- drm_err(&i915->drm, "Unknown DMC fw header version: %u\n",
+ drm_err(display->drm, "Unknown DMC fw header version: %u\n",
dmc_header->header_ver);
return 0;
}
if (header_len_bytes != dmc_header_size) {
- drm_err(&i915->drm, "DMC firmware has wrong dmc header length "
+ drm_err(display->drm, "DMC firmware has wrong dmc header length "
"(%u bytes)\n", header_len_bytes);
return 0;
}
/* Cache the dmc header info. */
if (mmio_count > mmio_count_max) {
- drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);
+ drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);
return 0;
}
if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count,
dmc_header->header_ver, dmc_id)) {
- drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n");
+ drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n");
return 0;
}
- drm_dbg_kms(&i915->drm, "DMC %d:\n", dmc_id);
+ drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id);
for (i = 0; i < mmio_count; i++) {
dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
dmc_info->mmiodata[i] = mmiodata[i];
- drm_dbg_kms(&i915->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n",
+ drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n",
i, mmioaddr[i], mmiodata[i],
- is_dmc_evt_ctl_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" :
- is_dmc_evt_htp_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "",
- disable_dmc_evt(i915, dmc_id, dmc_info->mmioaddr[i],
+ is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" :
+ is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "",
+ disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i],
dmc_info->mmiodata[i]) ? " (disabling)" : "");
}
dmc_info->mmio_count = mmio_count;
@@ -830,7 +834,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
goto error_truncated;
if (payload_size > dmc->max_fw_size) {
- drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size);
+ drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size);
return 0;
}
dmc_info->dmc_fw_size = dmc_header->fw_size;
@@ -845,7 +849,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
return header_len_bytes + payload_size;
error_truncated:
- drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
+ drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
return 0;
}
@@ -855,7 +859,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
const struct stepping_info *si,
size_t rem_size)
{
- struct drm_i915_private *i915 = dmc->i915;
+ struct intel_display *display = dmc->display;
u32 package_size = sizeof(struct intel_package_header);
u32 num_entries, max_entries;
const struct intel_fw_info *fw_info;
@@ -868,7 +872,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
} else if (package_header->header_ver == 2) {
max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
} else {
- drm_err(&i915->drm, "DMC firmware has unknown header version %u\n",
+ drm_err(display->drm, "DMC firmware has unknown header version %u\n",
package_header->header_ver);
return 0;
}
@@ -882,7 +886,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
goto error_truncated;
if (package_header->header_len * 4 != package_size) {
- drm_err(&i915->drm, "DMC firmware has wrong package header length "
+ drm_err(display->drm, "DMC firmware has wrong package header length "
"(%u bytes)\n", package_size);
return 0;
}
@@ -900,7 +904,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
return package_size;
error_truncated:
- drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
+ drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
return 0;
}
@@ -909,16 +913,16 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
struct intel_css_header *css_header,
size_t rem_size)
{
- struct drm_i915_private *i915 = dmc->i915;
+ struct intel_display *display = dmc->display;
if (rem_size < sizeof(struct intel_css_header)) {
- drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
+ drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
return 0;
}
if (sizeof(struct intel_css_header) !=
(css_header->header_len * 4)) {
- drm_err(&i915->drm, "DMC firmware has wrong CSS header length "
+ drm_err(display->drm, "DMC firmware has wrong CSS header length "
"(%u bytes)\n",
(css_header->header_len * 4));
return 0;
@@ -931,12 +935,12 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw)
{
- struct drm_i915_private *i915 = dmc->i915;
+ struct intel_display *display = dmc->display;
struct intel_css_header *css_header;
struct intel_package_header *package_header;
struct intel_dmc_header_base *dmc_header;
struct stepping_info display_info = { '*', '*'};
- const struct stepping_info *si = intel_get_stepping_info(i915, &display_info);
+ const struct stepping_info *si = intel_get_stepping_info(display, &display_info);
enum intel_dmc_id dmc_id;
u32 readcount = 0;
u32 r, offset;
@@ -966,7 +970,7 @@ static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw)
offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4;
if (offset > fw->size) {
- drm_err(&i915->drm, "Reading beyond the fw_size\n");
+ drm_err(display->drm, "Reading beyond the fw_size\n");
continue;
}
@@ -974,30 +978,35 @@ static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw)
parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id);
}
- if (!intel_dmc_has_payload(i915)) {
- drm_err(&i915->drm, "DMC firmware main program not found\n");
+ if (!intel_dmc_has_payload(display)) {
+ drm_err(display->drm, "DMC firmware main program not found\n");
return -ENOENT;
}
return 0;
}
-static void intel_dmc_runtime_pm_get(struct drm_i915_private *i915)
+static void intel_dmc_runtime_pm_get(struct intel_display *display)
{
- drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref);
- i915->display.dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT);
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
+ drm_WARN_ON(display->drm, display->dmc.wakeref);
+ display->dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT);
}
-static void intel_dmc_runtime_pm_put(struct drm_i915_private *i915)
+static void intel_dmc_runtime_pm_put(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
intel_wakeref_t wakeref __maybe_unused =
- fetch_and_zero(&i915->display.dmc.wakeref);
+ fetch_and_zero(&display->dmc.wakeref);
intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
}
-static const char *dmc_fallback_path(struct drm_i915_private *i915)
+static const char *dmc_fallback_path(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
if (IS_ALDERLAKE_P(i915))
return ADLP_DMC_FALLBACK_PATH;
@@ -1007,45 +1016,45 @@ static const char *dmc_fallback_path(struct drm_i915_private *i915)
static void dmc_load_work_fn(struct work_struct *work)
{
struct intel_dmc *dmc = container_of(work, typeof(*dmc), work);
- struct drm_i915_private *i915 = dmc->i915;
+ struct intel_display *display = dmc->display;
const struct firmware *fw = NULL;
const char *fallback_path;
int err;
- err = request_firmware(&fw, dmc->fw_path, i915->drm.dev);
+ err = request_firmware(&fw, dmc->fw_path, display->drm->dev);
- if (err == -ENOENT && !dmc_firmware_param(i915)) {
- fallback_path = dmc_fallback_path(i915);
+ if (err == -ENOENT && !dmc_firmware_param(display)) {
+ fallback_path = dmc_fallback_path(display);
if (fallback_path) {
- drm_dbg_kms(&i915->drm, "%s not found, falling back to %s\n",
+ drm_dbg_kms(display->drm, "%s not found, falling back to %s\n",
dmc->fw_path, fallback_path);
- err = request_firmware(&fw, fallback_path, i915->drm.dev);
+ err = request_firmware(&fw, fallback_path, display->drm->dev);
if (err == 0)
dmc->fw_path = fallback_path;
}
}
if (err) {
- drm_notice(&i915->drm,
+ drm_notice(display->drm,
"Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n",
dmc->fw_path, ERR_PTR(err));
- drm_notice(&i915->drm, "DMC firmware homepage: %s",
+ drm_notice(display->drm, "DMC firmware homepage: %s",
INTEL_DMC_FIRMWARE_URL);
return;
}
err = parse_dmc_fw(dmc, fw);
if (err) {
- drm_notice(&i915->drm,
+ drm_notice(display->drm,
"Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n",
dmc->fw_path, ERR_PTR(err));
goto out;
}
- intel_dmc_load_program(i915);
- intel_dmc_runtime_pm_put(i915);
+ intel_dmc_load_program(display);
+ intel_dmc_runtime_pm_put(display);
- drm_info(&i915->drm, "Finished loading DMC firmware %s (v%u.%u)\n",
+ drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n",
dmc->fw_path, DMC_VERSION_MAJOR(dmc->version),
DMC_VERSION_MINOR(dmc->version));
@@ -1055,16 +1064,17 @@ static void dmc_load_work_fn(struct work_struct *work)
/**
* intel_dmc_init() - initialize the firmware loading.
- * @i915: i915 drm device.
+ * @display: display instance
*
* This function is called at the time of loading the display driver to read
* firmware from a .bin file and copied into a internal memory.
*/
-void intel_dmc_init(struct drm_i915_private *i915)
+void intel_dmc_init(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_dmc *dmc;
- if (!HAS_DMC(i915))
+ if (!HAS_DMC(display))
return;
/*
@@ -1075,35 +1085,35 @@ void intel_dmc_init(struct drm_i915_private *i915)
* suspend as runtime suspend *requires* a working DMC for whatever
* reason.
*/
- intel_dmc_runtime_pm_get(i915);
+ intel_dmc_runtime_pm_get(display);
dmc = kzalloc(sizeof(*dmc), GFP_KERNEL);
if (!dmc)
return;
- dmc->i915 = i915;
+ dmc->display = display;
INIT_WORK(&dmc->work, dmc_load_work_fn);
- dmc->fw_path = dmc_firmware_default(i915, &dmc->max_fw_size);
+ dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size);
- if (dmc_firmware_param_disabled(i915)) {
- drm_info(&i915->drm, "Disabling DMC firmware and runtime PM\n");
+ if (dmc_firmware_param_disabled(display)) {
+ drm_info(display->drm, "Disabling DMC firmware and runtime PM\n");
goto out;
}
- if (dmc_firmware_param(i915))
- dmc->fw_path = dmc_firmware_param(i915);
+ if (dmc_firmware_param(display))
+ dmc->fw_path = dmc_firmware_param(display);
if (!dmc->fw_path) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"No known DMC firmware for platform, disabling runtime PM\n");
goto out;
}
- i915->display.dmc.dmc = dmc;
+ display->dmc.dmc = dmc;
- drm_dbg_kms(&i915->drm, "Loading %s\n", dmc->fw_path);
+ drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path);
queue_work(i915->unordered_wq, &dmc->work);
return;
@@ -1114,87 +1124,87 @@ void intel_dmc_init(struct drm_i915_private *i915)
/**
* intel_dmc_suspend() - prepare DMC firmware before system suspend
- * @i915: i915 drm device
+ * @display: display instance
*
* Prepare the DMC firmware before entering system suspend. This includes
* flushing pending work items and releasing any resources acquired during
* init.
*/
-void intel_dmc_suspend(struct drm_i915_private *i915)
+void intel_dmc_suspend(struct intel_display *display)
{
- struct intel_dmc *dmc = i915_to_dmc(i915);
+ struct intel_dmc *dmc = display_to_dmc(display);
- if (!HAS_DMC(i915))
+ if (!HAS_DMC(display))
return;
if (dmc)
flush_work(&dmc->work);
- intel_dmc_wl_disable(&i915->display);
+ intel_dmc_wl_disable(display);
/* Drop the reference held in case DMC isn't loaded. */
- if (!intel_dmc_has_payload(i915))
- intel_dmc_runtime_pm_put(i915);
+ if (!intel_dmc_has_payload(display))
+ intel_dmc_runtime_pm_put(display);
}
/**
* intel_dmc_resume() - init DMC firmware during system resume
- * @i915: i915 drm device
+ * @display: display instance
*
* Reinitialize the DMC firmware during system resume, reacquiring any
* resources released in intel_dmc_suspend().
*/
-void intel_dmc_resume(struct drm_i915_private *i915)
+void intel_dmc_resume(struct intel_display *display)
{
- if (!HAS_DMC(i915))
+ if (!HAS_DMC(display))
return;
/*
* Reacquire the reference to keep RPM disabled in case DMC isn't
* loaded.
*/
- if (!intel_dmc_has_payload(i915))
- intel_dmc_runtime_pm_get(i915);
+ if (!intel_dmc_has_payload(display))
+ intel_dmc_runtime_pm_get(display);
}
/**
* intel_dmc_fini() - unload the DMC firmware.
- * @i915: i915 drm device.
+ * @display: display instance
*
* Firmmware unloading includes freeing the internal memory and reset the
* firmware loading status.
*/
-void intel_dmc_fini(struct drm_i915_private *i915)
+void intel_dmc_fini(struct intel_display *display)
{
- struct intel_dmc *dmc = i915_to_dmc(i915);
+ struct intel_dmc *dmc = display_to_dmc(display);
enum intel_dmc_id dmc_id;
- if (!HAS_DMC(i915))
+ if (!HAS_DMC(display))
return;
- intel_dmc_suspend(i915);
- drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref);
+ intel_dmc_suspend(display);
+ drm_WARN_ON(display->drm, display->dmc.wakeref);
if (dmc) {
for_each_dmc_id(dmc_id)
kfree(dmc->dmc_info[dmc_id].payload);
kfree(dmc);
- i915->display.dmc.dmc = NULL;
+ display->dmc.dmc = NULL;
}
}
void intel_dmc_print_error_state(struct drm_printer *p,
- struct drm_i915_private *i915)
+ struct intel_display *display)
{
- struct intel_dmc *dmc = i915_to_dmc(i915);
+ struct intel_dmc *dmc = display_to_dmc(display);
- if (!HAS_DMC(i915))
+ if (!HAS_DMC(display))
return;
drm_printf(p, "DMC initialized: %s\n", str_yes_no(dmc));
drm_printf(p, "DMC loaded: %s\n",
- str_yes_no(intel_dmc_has_payload(i915)));
+ str_yes_no(intel_dmc_has_payload(display)));
if (dmc)
drm_printf(p, "DMC fw version: %d.%d\n",
DMC_VERSION_MAJOR(dmc->version),
@@ -1203,40 +1213,41 @@ void intel_dmc_print_error_state(struct drm_printer *p,
static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
{
- struct drm_i915_private *i915 = m->private;
- struct intel_dmc *dmc = i915_to_dmc(i915);
+ struct intel_display *display = m->private;
+ struct drm_i915_private *i915 = to_i915(display->drm);
+ struct intel_dmc *dmc = display_to_dmc(display);
intel_wakeref_t wakeref;
i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
- if (!HAS_DMC(i915))
+ if (!HAS_DMC(display))
return -ENODEV;
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc));
seq_printf(m, "fw loaded: %s\n",
- str_yes_no(intel_dmc_has_payload(i915)));
+ str_yes_no(intel_dmc_has_payload(display)));
seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A");
seq_printf(m, "Pipe A fw needed: %s\n",
- str_yes_no(DISPLAY_VER(i915) >= 12));
+ str_yes_no(DISPLAY_VER(display) >= 12));
seq_printf(m, "Pipe A fw loaded: %s\n",
- str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEA)));
+ str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA)));
seq_printf(m, "Pipe B fw needed: %s\n",
str_yes_no(IS_ALDERLAKE_P(i915) ||
- DISPLAY_VER(i915) >= 14));
+ DISPLAY_VER(display) >= 14));
seq_printf(m, "Pipe B fw loaded: %s\n",
- str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEB)));
+ str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB)));
- if (!intel_dmc_has_payload(i915))
+ if (!intel_dmc_has_payload(display))
goto out;
seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),
DMC_VERSION_MINOR(dmc->version));
- if (DISPLAY_VER(i915) >= 12) {
+ if (DISPLAY_VER(display) >= 12) {
i915_reg_t dc3co_reg;
- if (IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) {
+ if (IS_DGFX(i915) || DISPLAY_VER(display) >= 14) {
dc3co_reg = DG1_DMC_DEBUG3;
dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
} else {
@@ -1246,7 +1257,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
}
seq_printf(m, "DC3CO count: %d\n",
- intel_de_read(i915, dc3co_reg));
+ intel_de_read(display, dc3co_reg));
} else {
dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT :
SKL_DMC_DC3_DC5_COUNT;
@@ -1254,18 +1265,18 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
dc6_reg = SKL_DMC_DC5_DC6_COUNT;
}
- seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg));
+ seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
if (i915_mmio_reg_valid(dc6_reg))
seq_printf(m, "DC5 -> DC6 count: %d\n",
- intel_de_read(i915, dc6_reg));
+ intel_de_read(display, dc6_reg));
seq_printf(m, "program base: 0x%08x\n",
- intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
+ intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
out:
seq_printf(m, "ssp base: 0x%08x\n",
- intel_de_read(i915, DMC_SSP_BASE));
- seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL));
+ intel_de_read(display, DMC_SSP_BASE));
+ seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL));
intel_runtime_pm_put(&i915->runtime_pm, wakeref);
@@ -1274,10 +1285,10 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status);
-void intel_dmc_debugfs_register(struct drm_i915_private *i915)
+void intel_dmc_debugfs_register(struct intel_display *display)
{
- struct drm_minor *minor = i915->drm.primary;
+ struct drm_minor *minor = display->drm->primary;
debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root,
- i915, &intel_dmc_debugfs_status_fops);
+ display, &intel_dmc_debugfs_status_fops);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 54cff6002e31..2ead2ec1f820 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -9,22 +9,22 @@
#include <linux/types.h>
enum pipe;
-struct drm_i915_private;
struct drm_printer;
+struct intel_display;
-void intel_dmc_init(struct drm_i915_private *i915);
-void intel_dmc_load_program(struct drm_i915_private *i915);
-void intel_dmc_disable_program(struct drm_i915_private *i915);
-void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe);
-void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe);
-void intel_dmc_fini(struct drm_i915_private *i915);
-void intel_dmc_suspend(struct drm_i915_private *i915);
-void intel_dmc_resume(struct drm_i915_private *i915);
-bool intel_dmc_has_payload(struct drm_i915_private *i915);
-void intel_dmc_debugfs_register(struct drm_i915_private *i915);
+void intel_dmc_init(struct intel_display *display);
+void intel_dmc_load_program(struct intel_display *display);
+void intel_dmc_disable_program(struct intel_display *display);
+void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe);
+void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe);
+void intel_dmc_fini(struct intel_display *display);
+void intel_dmc_suspend(struct intel_display *display);
+void intel_dmc_resume(struct intel_display *display);
+bool intel_dmc_has_payload(struct intel_display *display);
+void intel_dmc_debugfs_register(struct intel_display *display);
void intel_dmc_print_error_state(struct drm_printer *p,
- struct drm_i915_private *i915);
+ struct intel_display *display);
-void assert_dmc_loaded(struct drm_i915_private *i915);
+void assert_dmc_loaded(struct intel_display *display);
#endif /* __INTEL_DMC_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index d9864b9cc429..5634ff07269d 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -109,10 +109,8 @@ static bool intel_dmc_wl_check_range(u32 address)
static bool __intel_dmc_wl_supported(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
-
if (DISPLAY_VER(display) < 20 ||
- !intel_dmc_has_payload(i915) ||
+ !intel_dmc_has_payload(display) ||
!display->params.enable_dmc_wl)
return false;
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 1f57549fce00..bcc5cf137a88 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -960,6 +960,7 @@ static void intel_early_display_was(struct drm_i915_private *i915)
void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
struct drm_modeset_acquire_ctx *ctx)
{
+ struct intel_display *display = &i915->display;
struct intel_encoder *encoder;
struct intel_crtc *crtc;
intel_wakeref_t wakeref;
@@ -987,7 +988,7 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
drm_crtc_vblank_reset(&crtc->base);
if (crtc_state->hw.active) {
- intel_dmc_enable_pipe(i915, crtc->pipe);
+ intel_dmc_enable_pipe(display, crtc->pipe);
intel_crtc_vblank_on(crtc_state);
}
}
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index fe905d65ddf7..943e938040c0 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -959,7 +959,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
intel_encoder_suspend_all(&i915->display);
intel_encoder_shutdown_all(&i915->display);
- intel_dmc_suspend(i915);
+ intel_dmc_suspend(&i915->display);
i915_gem_suspend(i915);
@@ -1054,7 +1054,7 @@ static int i915_drm_suspend(struct drm_device *dev)
dev_priv->suspend_count++;
- intel_dmc_suspend(dev_priv);
+ intel_dmc_suspend(display);
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
@@ -1164,7 +1164,7 @@ static int i915_drm_resume(struct drm_device *dev)
/* Must be called after GGTT is resumed. */
intel_dpt_resume(dev_priv);
- intel_dmc_resume(dev_priv);
+ intel_dmc_resume(display);
i915_restore_display(dev_priv);
intel_pps_unlock_regs_wa(display);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 6469b9bcf2ec..b455fa441609 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -875,7 +875,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
- intel_dmc_print_error_state(&p, m->i915);
+ intel_dmc_print_error_state(&p, &m->i915->display);
err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock));
err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended));
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index c0e9aa7a274f..10d707e05d6e 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -353,7 +353,7 @@ void xe_display_pm_suspend(struct xe_device *xe, bool runtime)
intel_opregion_suspend(display, s2idle ? PCI_D1 : PCI_D3cold);
- intel_dmc_suspend(xe);
+ intel_dmc_suspend(display);
}
void xe_display_pm_suspend_late(struct xe_device *xe)
@@ -395,7 +395,7 @@ void xe_display_pm_resume(struct xe_device *xe, bool runtime)
if (!xe->info.probe_display)
return;
- intel_dmc_resume(xe);
+ intel_dmc_resume(display);
if (has_display(xe))
drm_mode_config_reset(&xe->drm);
--
2.44.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display
2024-09-06 14:33 ` [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display Ville Syrjala
@ 2024-09-06 15:09 ` Rodrigo Vivi
2024-09-06 15:18 ` Jani Nikula
1 sibling, 0 replies; 23+ messages in thread
From: Rodrigo Vivi @ 2024-09-06 15:09 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx, intel-xe
On Fri, Sep 06, 2024 at 05:33:02PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> struct intel_display will replace struct drm_i915_private as
> the main thing for display code. Convert the CDCLK code to
> use it (as much as possible at this stage).
better to take this one in quickly before it starts to conflict
on rebases.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 1168 +++++++++--------
> drivers/gpu/drm/i915/display/intel_cdclk.h | 24 +-
> .../drm/i915/display/intel_display_debugfs.c | 2 +-
> .../drm/i915/display/intel_display_device.c | 2 +-
> .../drm/i915/display/intel_display_driver.c | 17 +-
> .../drm/i915/display/intel_display_power.c | 35 +-
> .../i915/display/intel_display_power_well.c | 9 +-
> drivers/gpu/drm/i915/display/skl_watermark.c | 3 +-
> 8 files changed, 657 insertions(+), 603 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 9d870d15d888..b4eda0a2a45d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -113,81 +113,81 @@
> */
>
> struct intel_cdclk_funcs {
> - void (*get_cdclk)(struct drm_i915_private *i915,
> + void (*get_cdclk)(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config);
> - void (*set_cdclk)(struct drm_i915_private *i915,
> + void (*set_cdclk)(struct intel_display *display,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe);
> int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
> u8 (*calc_voltage_level)(int cdclk);
> };
>
> -void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
> +void intel_cdclk_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> - dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config);
> + display->funcs.cdclk->get_cdclk(display, cdclk_config);
> }
>
> -static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
> +static void intel_cdclk_set_cdclk(struct intel_display *display,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> {
> - dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe);
> + display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe);
> }
>
> static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_display *display = to_intel_display(state);
>
> - return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(state);
> + return display->funcs.cdclk->modeset_calc_cdclk(state);
> }
>
> -static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
> +static u8 intel_cdclk_calc_voltage_level(struct intel_display *display,
> int cdclk)
> {
> - return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk);
> + return display->funcs.cdclk->calc_voltage_level(cdclk);
> }
>
> -static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
> +static void fixed_133mhz_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> cdclk_config->cdclk = 133333;
> }
>
> -static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
> +static void fixed_200mhz_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> cdclk_config->cdclk = 200000;
> }
>
> -static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
> +static void fixed_266mhz_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> cdclk_config->cdclk = 266667;
> }
>
> -static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
> +static void fixed_333mhz_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> cdclk_config->cdclk = 333333;
> }
>
> -static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
> +static void fixed_400mhz_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> cdclk_config->cdclk = 400000;
> }
>
> -static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
> +static void fixed_450mhz_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> cdclk_config->cdclk = 450000;
> }
>
> -static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
> +static void i85x_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> + struct pci_dev *pdev = to_pci_dev(display->drm->dev);
> u16 hpllcc = 0;
>
> /*
> @@ -226,10 +226,10 @@ static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
> }
> }
>
> -static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
> +static void i915gm_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> + struct pci_dev *pdev = to_pci_dev(display->drm->dev);
> u16 gcfgc = 0;
>
> pci_read_config_word(pdev, GCFGC, &gcfgc);
> @@ -250,10 +250,10 @@ static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
> }
> }
>
> -static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
> +static void i945gm_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> + struct pci_dev *pdev = to_pci_dev(display->drm->dev);
> u16 gcfgc = 0;
>
> pci_read_config_word(pdev, GCFGC, &gcfgc);
> @@ -274,7 +274,7 @@ static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
> }
> }
>
> -static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
> +static unsigned int intel_hpll_vco(struct intel_display *display)
> {
> static const unsigned int blb_vco[8] = {
> [0] = 3200000,
> @@ -313,6 +313,7 @@ static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
> [4] = 2666667,
> [5] = 4266667,
> };
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> const unsigned int *vco_table;
> unsigned int vco;
> u8 tmp = 0;
> @@ -331,23 +332,23 @@ static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
> else
> return 0;
>
> - tmp = intel_de_read(dev_priv,
> + tmp = intel_de_read(display,
> IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
>
> vco = vco_table[tmp & 0x7];
> if (vco == 0)
> - drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
> + drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
> tmp);
> else
> - drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco);
> + drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco);
>
> return vco;
> }
>
> -static void g33_get_cdclk(struct drm_i915_private *dev_priv,
> +static void g33_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> + struct pci_dev *pdev = to_pci_dev(display->drm->dev);
> static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
> static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
> static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
> @@ -356,7 +357,7 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv,
> unsigned int cdclk_sel;
> u16 tmp = 0;
>
> - cdclk_config->vco = intel_hpll_vco(dev_priv);
> + cdclk_config->vco = intel_hpll_vco(display);
>
> pci_read_config_word(pdev, GCFGC, &tmp);
>
> @@ -387,16 +388,16 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv,
> return;
>
> fail:
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
> cdclk_config->vco, tmp);
> cdclk_config->cdclk = 190476;
> }
>
> -static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
> +static void pnv_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> + struct pci_dev *pdev = to_pci_dev(display->drm->dev);
> u16 gcfgc = 0;
>
> pci_read_config_word(pdev, GCFGC, &gcfgc);
> @@ -415,7 +416,7 @@ static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
> cdclk_config->cdclk = 200000;
> break;
> default:
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "Unknown pnv display core clock 0x%04x\n", gcfgc);
> fallthrough;
> case GC_DISPLAY_CLOCK_133_MHZ_PNV:
> @@ -427,10 +428,10 @@ static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
> }
> }
>
> -static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
> +static void i965gm_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> + struct pci_dev *pdev = to_pci_dev(display->drm->dev);
> static const u8 div_3200[] = { 16, 10, 8 };
> static const u8 div_4000[] = { 20, 12, 10 };
> static const u8 div_5333[] = { 24, 16, 14 };
> @@ -438,7 +439,7 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
> unsigned int cdclk_sel;
> u16 tmp = 0;
>
> - cdclk_config->vco = intel_hpll_vco(dev_priv);
> + cdclk_config->vco = intel_hpll_vco(display);
>
> pci_read_config_word(pdev, GCFGC, &tmp);
>
> @@ -466,20 +467,20 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
> return;
>
> fail:
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
> cdclk_config->vco, tmp);
> cdclk_config->cdclk = 200000;
> }
>
> -static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
> +static void gm45_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> + struct pci_dev *pdev = to_pci_dev(display->drm->dev);
> unsigned int cdclk_sel;
> u16 tmp = 0;
>
> - cdclk_config->vco = intel_hpll_vco(dev_priv);
> + cdclk_config->vco = intel_hpll_vco(display);
>
> pci_read_config_word(pdev, GCFGC, &tmp);
>
> @@ -495,7 +496,7 @@ static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
> cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
> break;
> default:
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
> cdclk_config->vco, tmp);
> cdclk_config->cdclk = 222222;
> @@ -503,15 +504,16 @@ static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
> }
> }
>
> -static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
> +static void hsw_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> - u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> + u32 lcpll = intel_de_read(display, LCPLL_CTL);
> u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
>
> if (lcpll & LCPLL_CD_SOURCE_FCLK)
> cdclk_config->cdclk = 800000;
> - else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
> + else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
> cdclk_config->cdclk = 450000;
> else if (freq == LCPLL_CLK_FREQ_450)
> cdclk_config->cdclk = 450000;
> @@ -521,8 +523,9 @@ static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
> cdclk_config->cdclk = 540000;
> }
>
> -static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
> +static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
> 333333 : 320000;
>
> @@ -541,8 +544,10 @@ static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
> return 200000;
> }
>
> -static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
> +static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> if (IS_VALLEYVIEW(dev_priv)) {
> if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
> return 2;
> @@ -560,9 +565,10 @@ static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
> }
> }
>
> -static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
> +static void vlv_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 val;
>
> vlv_iosf_sb_get(dev_priv,
> @@ -586,8 +592,9 @@ static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
> DSPFREQGUAR_SHIFT_CHV;
> }
>
> -static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
> +static void vlv_program_pfi_credits(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> unsigned int credits, default_credits;
>
> if (IS_CHERRYVIEW(dev_priv))
> @@ -595,7 +602,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
> else
> default_credits = PFI_CREDIT(8);
>
> - if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) {
> + if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
> /* CHV suggested value is 31 or 63 */
> if (IS_CHERRYVIEW(dev_priv))
> credits = PFI_CREDIT_63;
> @@ -609,24 +616,25 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
> * WA - write default credits before re-programming
> * FIXME: should we also set the resend bit here?
> */
> - intel_de_write(dev_priv, GCI_CONTROL,
> + intel_de_write(display, GCI_CONTROL,
> VGA_FAST_MODE_DISABLE | default_credits);
>
> - intel_de_write(dev_priv, GCI_CONTROL,
> + intel_de_write(display, GCI_CONTROL,
> VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
>
> /*
> * FIXME is this guaranteed to clear
> * immediately or should we poll for it?
> */
> - drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);
> + drm_WARN_ON(display->drm,
> + intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND);
> }
>
> -static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
> +static void vlv_set_cdclk(struct intel_display *display,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> int cdclk = cdclk_config->cdclk;
> u32 val, cmd = cdclk_config->voltage_level;
> intel_wakeref_t wakeref;
> @@ -663,7 +671,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
> if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
> DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
> 50)) {
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "timed out waiting for CDclk change\n");
> }
>
> @@ -682,7 +690,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
> if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
> CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
> 50))
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "timed out waiting for CDclk change\n");
> }
>
> @@ -705,17 +713,18 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
> BIT(VLV_IOSF_SB_BUNIT) |
> BIT(VLV_IOSF_SB_PUNIT));
>
> - intel_update_cdclk(dev_priv);
> + intel_update_cdclk(display);
>
> - vlv_program_pfi_credits(dev_priv);
> + vlv_program_pfi_credits(display);
>
> intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
> }
>
> -static void chv_set_cdclk(struct drm_i915_private *dev_priv,
> +static void chv_set_cdclk(struct intel_display *display,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> int cdclk = cdclk_config->cdclk;
> u32 val, cmd = cdclk_config->voltage_level;
> intel_wakeref_t wakeref;
> @@ -747,15 +756,15 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
> if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
> DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
> 50)) {
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "timed out waiting for CDclk change\n");
> }
>
> vlv_punit_put(dev_priv);
>
> - intel_update_cdclk(dev_priv);
> + intel_update_cdclk(display);
>
> - vlv_program_pfi_credits(dev_priv);
> + vlv_program_pfi_credits(display);
>
> intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
> }
> @@ -787,15 +796,15 @@ static u8 bdw_calc_voltage_level(int cdclk)
> }
> }
>
> -static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
> +static void bdw_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> - u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
> + u32 lcpll = intel_de_read(display, LCPLL_CTL);
> u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
>
> if (lcpll & LCPLL_CD_SOURCE_FCLK)
> cdclk_config->cdclk = 800000;
> - else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
> + else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
> cdclk_config->cdclk = 450000;
> else if (freq == LCPLL_CLK_FREQ_450)
> cdclk_config->cdclk = 450000;
> @@ -831,15 +840,16 @@ static u32 bdw_cdclk_freq_sel(int cdclk)
> }
> }
>
> -static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
> +static void bdw_set_cdclk(struct intel_display *display,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> int cdclk = cdclk_config->cdclk;
> int ret;
>
> - if (drm_WARN(&dev_priv->drm,
> - (intel_de_read(dev_priv, LCPLL_CTL) &
> + if (drm_WARN(display->drm,
> + (intel_de_read(display, LCPLL_CTL) &
> (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
> LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
> LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
> @@ -849,39 +859,39 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
>
> ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
> if (ret) {
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "failed to inform pcode about cdclk change\n");
> return;
> }
>
> - intel_de_rmw(dev_priv, LCPLL_CTL,
> + intel_de_rmw(display, LCPLL_CTL,
> 0, LCPLL_CD_SOURCE_FCLK);
>
> /*
> * According to the spec, it should be enough to poll for this 1 us.
> * However, extensive testing shows that this can take longer.
> */
> - if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
> + if (wait_for_us(intel_de_read(display, LCPLL_CTL) &
> LCPLL_CD_SOURCE_FCLK_DONE, 100))
> - drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
> + drm_err(display->drm, "Switching to FCLK failed\n");
>
> - intel_de_rmw(dev_priv, LCPLL_CTL,
> + intel_de_rmw(display, LCPLL_CTL,
> LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk));
>
> - intel_de_rmw(dev_priv, LCPLL_CTL,
> + intel_de_rmw(display, LCPLL_CTL,
> LCPLL_CD_SOURCE_FCLK, 0);
>
> - if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
> + if (wait_for_us((intel_de_read(display, LCPLL_CTL) &
> LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
> - drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
> + drm_err(display->drm, "Switching back to LCPLL failed\n");
>
> snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ,
> cdclk_config->voltage_level);
>
> - intel_de_write(dev_priv, CDCLK_FREQ,
> + intel_de_write(display, CDCLK_FREQ,
> DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
>
> - intel_update_cdclk(dev_priv);
> + intel_update_cdclk(display);
> }
>
> static int skl_calc_cdclk(int min_cdclk, int vco)
> @@ -919,7 +929,7 @@ static u8 skl_calc_voltage_level(int cdclk)
> return 0;
> }
>
> -static void skl_dpll0_update(struct drm_i915_private *dev_priv,
> +static void skl_dpll0_update(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> u32 val;
> @@ -927,16 +937,16 @@ static void skl_dpll0_update(struct drm_i915_private *dev_priv,
> cdclk_config->ref = 24000;
> cdclk_config->vco = 0;
>
> - val = intel_de_read(dev_priv, LCPLL1_CTL);
> + val = intel_de_read(display, LCPLL1_CTL);
> if ((val & LCPLL_PLL_ENABLE) == 0)
> return;
>
> - if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0))
> + if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0))
> return;
>
> - val = intel_de_read(dev_priv, DPLL_CTRL1);
> + val = intel_de_read(display, DPLL_CTRL1);
>
> - if (drm_WARN_ON(&dev_priv->drm,
> + if (drm_WARN_ON(display->drm,
> (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
> DPLL_CTRL1_SSC(SKL_DPLL0) |
> DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
> @@ -960,19 +970,19 @@ static void skl_dpll0_update(struct drm_i915_private *dev_priv,
> }
> }
>
> -static void skl_get_cdclk(struct drm_i915_private *dev_priv,
> +static void skl_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> u32 cdctl;
>
> - skl_dpll0_update(dev_priv, cdclk_config);
> + skl_dpll0_update(display, cdclk_config);
>
> cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
>
> if (cdclk_config->vco == 0)
> goto out;
>
> - cdctl = intel_de_read(dev_priv, CDCLK_CTL);
> + cdctl = intel_de_read(display, CDCLK_CTL);
>
> if (cdclk_config->vco == 8640000) {
> switch (cdctl & CDCLK_FREQ_SEL_MASK) {
> @@ -1027,19 +1037,19 @@ static int skl_cdclk_decimal(int cdclk)
> return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
> }
>
> -static void skl_set_preferred_cdclk_vco(struct drm_i915_private *i915, int vco)
> +static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco)
> {
> - bool changed = i915->display.cdclk.skl_preferred_vco_freq != vco;
> + bool changed = display->cdclk.skl_preferred_vco_freq != vco;
>
> - i915->display.cdclk.skl_preferred_vco_freq = vco;
> + display->cdclk.skl_preferred_vco_freq = vco;
>
> if (changed)
> - intel_update_max_cdclk(i915);
> + intel_update_max_cdclk(display);
> }
>
> -static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco)
> +static u32 skl_dpll0_link_rate(struct intel_display *display, int vco)
> {
> - drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
> + drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
>
> /*
> * We always enable DPLL0 with the lowest link rate possible, but still
> @@ -1056,47 +1066,47 @@ static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco)
> return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0);
> }
>
> -static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
> +static void skl_dpll0_enable(struct intel_display *display, int vco)
> {
> - intel_de_rmw(dev_priv, DPLL_CTRL1,
> + intel_de_rmw(display, DPLL_CTRL1,
> DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
> DPLL_CTRL1_SSC(SKL_DPLL0) |
> DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0),
> DPLL_CTRL1_OVERRIDE(SKL_DPLL0) |
> - skl_dpll0_link_rate(dev_priv, vco));
> - intel_de_posting_read(dev_priv, DPLL_CTRL1);
> + skl_dpll0_link_rate(display, vco));
> + intel_de_posting_read(display, DPLL_CTRL1);
>
> - intel_de_rmw(dev_priv, LCPLL1_CTL,
> + intel_de_rmw(display, LCPLL1_CTL,
> 0, LCPLL_PLL_ENABLE);
>
> - if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
> - drm_err(&dev_priv->drm, "DPLL0 not locked\n");
> + if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
> + drm_err(display->drm, "DPLL0 not locked\n");
>
> - dev_priv->display.cdclk.hw.vco = vco;
> + display->cdclk.hw.vco = vco;
>
> /* We'll want to keep using the current vco from now on. */
> - skl_set_preferred_cdclk_vco(dev_priv, vco);
> + skl_set_preferred_cdclk_vco(display, vco);
> }
>
> -static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
> +static void skl_dpll0_disable(struct intel_display *display)
> {
> - intel_de_rmw(dev_priv, LCPLL1_CTL,
> + intel_de_rmw(display, LCPLL1_CTL,
> LCPLL_PLL_ENABLE, 0);
>
> - if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
> - drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
> + if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
> + drm_err(display->drm, "Couldn't disable DPLL0\n");
>
> - dev_priv->display.cdclk.hw.vco = 0;
> + display->cdclk.hw.vco = 0;
> }
>
> -static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
> +static u32 skl_cdclk_freq_sel(struct intel_display *display,
> int cdclk, int vco)
> {
> switch (cdclk) {
> default:
> - drm_WARN_ON(&dev_priv->drm,
> - cdclk != dev_priv->display.cdclk.hw.bypass);
> - drm_WARN_ON(&dev_priv->drm, vco != 0);
> + drm_WARN_ON(display->drm,
> + cdclk != display->cdclk.hw.bypass);
> + drm_WARN_ON(display->drm, vco != 0);
> fallthrough;
> case 308571:
> case 337500:
> @@ -1112,10 +1122,11 @@ static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
> }
> }
>
> -static void skl_set_cdclk(struct drm_i915_private *dev_priv,
> +static void skl_set_cdclk(struct intel_display *display,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> int cdclk = cdclk_config->cdclk;
> int vco = cdclk_config->vco;
> u32 freq_select, cdclk_ctl;
> @@ -1129,7 +1140,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
> * use the corresponding VCO freq as that always leads to using the
> * minimum 308MHz CDCLK.
> */
> - drm_WARN_ON_ONCE(&dev_priv->drm,
> + drm_WARN_ON_ONCE(display->drm,
> IS_SKYLAKE(dev_priv) && vco == 8640000);
>
> ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
> @@ -1137,54 +1148,54 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
> SKL_CDCLK_READY_FOR_CHANGE,
> SKL_CDCLK_READY_FOR_CHANGE, 3);
> if (ret) {
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "Failed to inform PCU about cdclk change (%d)\n", ret);
> return;
> }
>
> - freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco);
> + freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
>
> - if (dev_priv->display.cdclk.hw.vco != 0 &&
> - dev_priv->display.cdclk.hw.vco != vco)
> - skl_dpll0_disable(dev_priv);
> + if (display->cdclk.hw.vco != 0 &&
> + display->cdclk.hw.vco != vco)
> + skl_dpll0_disable(display);
>
> - cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);
> + cdclk_ctl = intel_de_read(display, CDCLK_CTL);
>
> - if (dev_priv->display.cdclk.hw.vco != vco) {
> + if (display->cdclk.hw.vco != vco) {
> /* Wa Display #1183: skl,kbl,cfl */
> cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
> cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
> - intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
> + intel_de_write(display, CDCLK_CTL, cdclk_ctl);
> }
>
> /* Wa Display #1183: skl,kbl,cfl */
> cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
> - intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
> - intel_de_posting_read(dev_priv, CDCLK_CTL);
> + intel_de_write(display, CDCLK_CTL, cdclk_ctl);
> + intel_de_posting_read(display, CDCLK_CTL);
>
> - if (dev_priv->display.cdclk.hw.vco != vco)
> - skl_dpll0_enable(dev_priv, vco);
> + if (display->cdclk.hw.vco != vco)
> + skl_dpll0_enable(display, vco);
>
> /* Wa Display #1183: skl,kbl,cfl */
> cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
> - intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
> + intel_de_write(display, CDCLK_CTL, cdclk_ctl);
>
> cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
> - intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
> + intel_de_write(display, CDCLK_CTL, cdclk_ctl);
>
> /* Wa Display #1183: skl,kbl,cfl */
> cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
> - intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
> - intel_de_posting_read(dev_priv, CDCLK_CTL);
> + intel_de_write(display, CDCLK_CTL, cdclk_ctl);
> + intel_de_posting_read(display, CDCLK_CTL);
>
> /* inform PCU of the change */
> snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
> cdclk_config->voltage_level);
>
> - intel_update_cdclk(dev_priv);
> + intel_update_cdclk(display);
> }
>
> -static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> +static void skl_sanitize_cdclk(struct intel_display *display)
> {
> u32 cdctl, expected;
>
> @@ -1193,15 +1204,15 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> * There is SWF18 scratchpad register defined which is set by the
> * pre-os which can be used by the OS drivers to check the status
> */
> - if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
> + if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
> goto sanitize;
>
> - intel_update_cdclk(dev_priv);
> - intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
> + intel_update_cdclk(display);
> + intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
>
> /* Is PLL enabled and locked ? */
> - if (dev_priv->display.cdclk.hw.vco == 0 ||
> - dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
> + if (display->cdclk.hw.vco == 0 ||
> + display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
> goto sanitize;
>
> /* DPLL okay; verify the cdclock
> @@ -1210,60 +1221,60 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> * decimal part is programmed wrong from BIOS where pre-os does not
> * enable display. Verify the same as well.
> */
> - cdctl = intel_de_read(dev_priv, CDCLK_CTL);
> + cdctl = intel_de_read(display, CDCLK_CTL);
> expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
> - skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk);
> + skl_cdclk_decimal(display->cdclk.hw.cdclk);
> if (cdctl == expected)
> /* All well; nothing to sanitize */
> return;
>
> sanitize:
> - drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
> + drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
>
> /* force cdclk programming */
> - dev_priv->display.cdclk.hw.cdclk = 0;
> + display->cdclk.hw.cdclk = 0;
> /* force full PLL disable + enable */
> - dev_priv->display.cdclk.hw.vco = ~0;
> + display->cdclk.hw.vco = ~0;
> }
>
> -static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
> +static void skl_cdclk_init_hw(struct intel_display *display)
> {
> struct intel_cdclk_config cdclk_config;
>
> - skl_sanitize_cdclk(dev_priv);
> + skl_sanitize_cdclk(display);
>
> - if (dev_priv->display.cdclk.hw.cdclk != 0 &&
> - dev_priv->display.cdclk.hw.vco != 0) {
> + if (display->cdclk.hw.cdclk != 0 &&
> + display->cdclk.hw.vco != 0) {
> /*
> * Use the current vco as our initial
> * guess as to what the preferred vco is.
> */
> - if (dev_priv->display.cdclk.skl_preferred_vco_freq == 0)
> - skl_set_preferred_cdclk_vco(dev_priv,
> - dev_priv->display.cdclk.hw.vco);
> + if (display->cdclk.skl_preferred_vco_freq == 0)
> + skl_set_preferred_cdclk_vco(display,
> + display->cdclk.hw.vco);
> return;
> }
>
> - cdclk_config = dev_priv->display.cdclk.hw;
> + cdclk_config = display->cdclk.hw;
>
> - cdclk_config.vco = dev_priv->display.cdclk.skl_preferred_vco_freq;
> + cdclk_config.vco = display->cdclk.skl_preferred_vco_freq;
> if (cdclk_config.vco == 0)
> cdclk_config.vco = 8100000;
> cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
> cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
>
> - skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
> + skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
> }
>
> -static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
> +static void skl_cdclk_uninit_hw(struct intel_display *display)
> {
> - struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
> + struct intel_cdclk_config cdclk_config = display->cdclk.hw;
>
> cdclk_config.cdclk = cdclk_config.bypass;
> cdclk_config.vco = 0;
> cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
>
> - skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
> + skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
> }
>
> struct intel_cdclk_vals {
> @@ -1471,37 +1482,37 @@ static int cdclk_divider(int cdclk, int vco, u16 waveform)
> cdclk * cdclk_squash_len);
> }
>
> -static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
> +static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk)
> {
> - const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
> + const struct intel_cdclk_vals *table = display->cdclk.table;
> int i;
>
> for (i = 0; table[i].refclk; i++)
> - if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
> + if (table[i].refclk == display->cdclk.hw.ref &&
> table[i].cdclk >= min_cdclk)
> return table[i].cdclk;
>
> - drm_WARN(&dev_priv->drm, 1,
> + drm_WARN(display->drm, 1,
> "Cannot satisfy minimum cdclk %d with refclk %u\n",
> - min_cdclk, dev_priv->display.cdclk.hw.ref);
> + min_cdclk, display->cdclk.hw.ref);
> return 0;
> }
>
> -static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> +static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk)
> {
> - const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
> + const struct intel_cdclk_vals *table = display->cdclk.table;
> int i;
>
> - if (cdclk == dev_priv->display.cdclk.hw.bypass)
> + if (cdclk == display->cdclk.hw.bypass)
> return 0;
>
> for (i = 0; table[i].refclk; i++)
> - if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
> + if (table[i].refclk == display->cdclk.hw.ref &&
> table[i].cdclk == cdclk)
> - return dev_priv->display.cdclk.hw.ref * table[i].ratio;
> + return display->cdclk.hw.ref * table[i].ratio;
>
> - drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
> - cdclk, dev_priv->display.cdclk.hw.ref);
> + drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
> + cdclk, display->cdclk.hw.ref);
> return 0;
> }
>
> @@ -1583,10 +1594,10 @@ static u8 rplu_calc_voltage_level(int cdclk)
> rplu_voltage_level_max_cdclk);
> }
>
> -static void icl_readout_refclk(struct drm_i915_private *dev_priv,
> +static void icl_readout_refclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> - u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
> + u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
>
> switch (dssm) {
> default:
> @@ -1604,19 +1615,20 @@ static void icl_readout_refclk(struct drm_i915_private *dev_priv,
> }
> }
>
> -static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
> +static void bxt_de_pll_readout(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 val, ratio;
>
> if (IS_DG2(dev_priv))
> cdclk_config->ref = 38400;
> - else if (DISPLAY_VER(dev_priv) >= 11)
> - icl_readout_refclk(dev_priv, cdclk_config);
> + else if (DISPLAY_VER(display) >= 11)
> + icl_readout_refclk(display, cdclk_config);
> else
> cdclk_config->ref = 19200;
>
> - val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);
> + val = intel_de_read(display, BXT_DE_PLL_ENABLE);
> if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
> (val & BXT_DE_PLL_LOCK) == 0) {
> /*
> @@ -1631,26 +1643,26 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
> * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
> * gen9lp had it in a separate PLL control register.
> */
> - if (DISPLAY_VER(dev_priv) >= 11)
> + if (DISPLAY_VER(display) >= 11)
> ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
> else
> - ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
> + ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
>
> cdclk_config->vco = ratio * cdclk_config->ref;
> }
>
> -static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> +static void bxt_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config)
> {
> u32 squash_ctl = 0;
> u32 divider;
> int div;
>
> - bxt_de_pll_readout(dev_priv, cdclk_config);
> + bxt_de_pll_readout(display, cdclk_config);
>
> - if (DISPLAY_VER(dev_priv) >= 12)
> + if (DISPLAY_VER(display) >= 12)
> cdclk_config->bypass = cdclk_config->ref / 2;
> - else if (DISPLAY_VER(dev_priv) >= 11)
> + else if (DISPLAY_VER(display) >= 11)
> cdclk_config->bypass = 50000;
> else
> cdclk_config->bypass = cdclk_config->ref;
> @@ -1660,7 +1672,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> goto out;
> }
>
> - divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
> + divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
>
> switch (divider) {
> case BXT_CDCLK_CD2X_DIV_SEL_1:
> @@ -1680,8 +1692,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> return;
> }
>
> - if (HAS_CDCLK_SQUASH(dev_priv))
> - squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
> + if (HAS_CDCLK_SQUASH(display))
> + squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL);
>
> if (squash_ctl & CDCLK_SQUASH_ENABLE) {
> u16 waveform;
> @@ -1697,107 +1709,107 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> }
>
> out:
> - if (DISPLAY_VER(dev_priv) >= 20)
> - cdclk_config->joined_mbus = intel_de_read(dev_priv, MBUS_CTL) & MBUS_JOIN;
> + if (DISPLAY_VER(display) >= 20)
> + cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;
> /*
> * Can't read this out :( Let's assume it's
> * at least what the CDCLK frequency requires.
> */
> cdclk_config->voltage_level =
> - intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk);
> + intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk);
> }
>
> -static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
> +static void bxt_de_pll_disable(struct intel_display *display)
> {
> - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0);
> + intel_de_write(display, BXT_DE_PLL_ENABLE, 0);
>
> /* Timeout 200us */
> - if (intel_de_wait_for_clear(dev_priv,
> + if (intel_de_wait_for_clear(display,
> BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
> - drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");
> + drm_err(display->drm, "timeout waiting for DE PLL unlock\n");
>
> - dev_priv->display.cdclk.hw.vco = 0;
> + display->cdclk.hw.vco = 0;
> }
>
> -static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
> +static void bxt_de_pll_enable(struct intel_display *display, int vco)
> {
> - int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
> + int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
>
> - intel_de_rmw(dev_priv, BXT_DE_PLL_CTL,
> + intel_de_rmw(display, BXT_DE_PLL_CTL,
> BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
>
> - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
> + intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
>
> /* Timeout 200us */
> - if (intel_de_wait_for_set(dev_priv,
> + if (intel_de_wait_for_set(display,
> BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
> - drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");
> + drm_err(display->drm, "timeout waiting for DE PLL lock\n");
>
> - dev_priv->display.cdclk.hw.vco = vco;
> + display->cdclk.hw.vco = vco;
> }
>
> -static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
> +static void icl_cdclk_pll_disable(struct intel_display *display)
> {
> - intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE,
> + intel_de_rmw(display, BXT_DE_PLL_ENABLE,
> BXT_DE_PLL_PLL_ENABLE, 0);
>
> /* Timeout 200us */
> - if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
> - drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n");
> + if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
> + drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n");
>
> - dev_priv->display.cdclk.hw.vco = 0;
> + display->cdclk.hw.vco = 0;
> }
>
> -static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
> +static void icl_cdclk_pll_enable(struct intel_display *display, int vco)
> {
> - int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
> + int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
> u32 val;
>
> val = ICL_CDCLK_PLL_RATIO(ratio);
> - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> + intel_de_write(display, BXT_DE_PLL_ENABLE, val);
>
> val |= BXT_DE_PLL_PLL_ENABLE;
> - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> + intel_de_write(display, BXT_DE_PLL_ENABLE, val);
>
> /* Timeout 200us */
> - if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
> - drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n");
> + if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
> + drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n");
>
> - dev_priv->display.cdclk.hw.vco = vco;
> + display->cdclk.hw.vco = vco;
> }
>
> -static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
> +static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco)
> {
> - int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
> + int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
> u32 val;
>
> /* Write PLL ratio without disabling */
> val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
> - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> + intel_de_write(display, BXT_DE_PLL_ENABLE, val);
>
> /* Submit freq change request */
> val |= BXT_DE_PLL_FREQ_REQ;
> - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> + intel_de_write(display, BXT_DE_PLL_ENABLE, val);
>
> /* Timeout 200us */
> - if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
> + if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE,
> BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
> - drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n");
> + drm_err(display->drm, "timeout waiting for FREQ change request ack\n");
>
> val &= ~BXT_DE_PLL_FREQ_REQ;
> - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> + intel_de_write(display, BXT_DE_PLL_ENABLE, val);
>
> - dev_priv->display.cdclk.hw.vco = vco;
> + display->cdclk.hw.vco = vco;
> }
>
> -static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> +static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe)
> {
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + if (DISPLAY_VER(display) >= 12) {
> if (pipe == INVALID_PIPE)
> return TGL_CDCLK_CD2X_PIPE_NONE;
> else
> return TGL_CDCLK_CD2X_PIPE(pipe);
> - } else if (DISPLAY_VER(dev_priv) >= 11) {
> + } else if (DISPLAY_VER(display) >= 11) {
> if (pipe == INVALID_PIPE)
> return ICL_CDCLK_CD2X_PIPE_NONE;
> else
> @@ -1810,15 +1822,15 @@ static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe
> }
> }
>
> -static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
> +static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display,
> int cdclk, int vco, u16 waveform)
> {
> /* cdclk = vco / 2 / div{1,1.5,2,4} */
> switch (cdclk_divider(cdclk, vco, waveform)) {
> default:
> - drm_WARN_ON(&dev_priv->drm,
> - cdclk != dev_priv->display.cdclk.hw.bypass);
> - drm_WARN_ON(&dev_priv->drm, vco != 0);
> + drm_WARN_ON(display->drm,
> + cdclk != display->cdclk.hw.bypass);
> + drm_WARN_ON(display->drm, vco != 0);
> fallthrough;
> case 2:
> return BXT_CDCLK_CD2X_DIV_SEL_1;
> @@ -1831,47 +1843,47 @@ static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
> }
> }
>
> -static u16 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
> +static u16 cdclk_squash_waveform(struct intel_display *display,
> int cdclk)
> {
> - const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
> + const struct intel_cdclk_vals *table = display->cdclk.table;
> int i;
>
> - if (cdclk == dev_priv->display.cdclk.hw.bypass)
> + if (cdclk == display->cdclk.hw.bypass)
> return 0;
>
> for (i = 0; table[i].refclk; i++)
> - if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
> + if (table[i].refclk == display->cdclk.hw.ref &&
> table[i].cdclk == cdclk)
> return table[i].waveform;
>
> - drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
> - cdclk, dev_priv->display.cdclk.hw.ref);
> + drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
> + cdclk, display->cdclk.hw.ref);
>
> return 0xffff;
> }
>
> -static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco)
> +static void icl_cdclk_pll_update(struct intel_display *display, int vco)
> {
> - if (i915->display.cdclk.hw.vco != 0 &&
> - i915->display.cdclk.hw.vco != vco)
> - icl_cdclk_pll_disable(i915);
> + if (display->cdclk.hw.vco != 0 &&
> + display->cdclk.hw.vco != vco)
> + icl_cdclk_pll_disable(display);
>
> - if (i915->display.cdclk.hw.vco != vco)
> - icl_cdclk_pll_enable(i915, vco);
> + if (display->cdclk.hw.vco != vco)
> + icl_cdclk_pll_enable(display, vco);
> }
>
> -static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
> +static void bxt_cdclk_pll_update(struct intel_display *display, int vco)
> {
> - if (i915->display.cdclk.hw.vco != 0 &&
> - i915->display.cdclk.hw.vco != vco)
> - bxt_de_pll_disable(i915);
> + if (display->cdclk.hw.vco != 0 &&
> + display->cdclk.hw.vco != vco)
> + bxt_de_pll_disable(display);
>
> - if (i915->display.cdclk.hw.vco != vco)
> - bxt_de_pll_enable(i915, vco);
> + if (display->cdclk.hw.vco != vco)
> + bxt_de_pll_enable(display, vco);
> }
>
> -static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
> +static void dg2_cdclk_squash_program(struct intel_display *display,
> u16 waveform)
> {
> u32 squash_ctl = 0;
> @@ -1880,7 +1892,7 @@ static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
> squash_ctl = CDCLK_SQUASH_ENABLE |
> CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
>
> - intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
> + intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl);
> }
>
> static bool cdclk_pll_is_unknown(unsigned int vco)
> @@ -1893,38 +1905,40 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
> return vco == ~0;
> }
>
> -static bool mdclk_source_is_cdclk_pll(struct drm_i915_private *i915)
> +static bool mdclk_source_is_cdclk_pll(struct intel_display *display)
> {
> - return DISPLAY_VER(i915) >= 20;
> + return DISPLAY_VER(display) >= 20;
> }
>
> -static u32 xe2lpd_mdclk_source_sel(struct drm_i915_private *i915)
> +static u32 xe2lpd_mdclk_source_sel(struct intel_display *display)
> {
> - if (mdclk_source_is_cdclk_pll(i915))
> + if (mdclk_source_is_cdclk_pll(display))
> return MDCLK_SOURCE_SEL_CDCLK_PLL;
>
> return MDCLK_SOURCE_SEL_CD2XCLK;
> }
>
> -int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> +int intel_mdclk_cdclk_ratio(struct intel_display *display,
> const struct intel_cdclk_config *cdclk_config)
> {
> - if (mdclk_source_is_cdclk_pll(i915))
> + if (mdclk_source_is_cdclk_pll(display))
> return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
>
> /* Otherwise, source for MDCLK is CD2XCLK. */
> return 2;
> }
>
> -static void xe2lpd_mdclk_cdclk_ratio_program(struct drm_i915_private *i915,
> +static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display,
> const struct intel_cdclk_config *cdclk_config)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> intel_dbuf_mdclk_cdclk_ratio_update(i915,
> - intel_mdclk_cdclk_ratio(i915, cdclk_config),
> + intel_mdclk_cdclk_ratio(display, cdclk_config),
> cdclk_config->joined_mbus);
> }
>
> -static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915,
> +static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display,
> const struct intel_cdclk_config *old_cdclk_config,
> const struct intel_cdclk_config *new_cdclk_config,
> struct intel_cdclk_config *mid_cdclk_config)
> @@ -1937,11 +1951,11 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
> return false;
>
> /* Return if both Squash and Crawl are not present */
> - if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
> + if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
> return false;
>
> - old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
> - new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
> + old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk);
> + new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk);
>
> /* Return if Squash only or Crawl only is the desired action */
> if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||
> @@ -1958,7 +1972,7 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
> * Should not happen currently. We might need more midpoint
> * transitions if we need to also change the cd2x divider.
> */
> - if (drm_WARN_ON(&i915->drm, old_div != new_div))
> + if (drm_WARN_ON(display->drm, old_div != new_div))
> return false;
>
> *mid_cdclk_config = *new_cdclk_config;
> @@ -1987,37 +2001,40 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
>
> /* make sure the mid clock came out sane */
>
> - drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk <
> + drm_WARN_ON(display->drm, mid_cdclk_config->cdclk <
> min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
> - drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk >
> - i915->display.cdclk.max_cdclk_freq);
> - drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) !=
> + drm_WARN_ON(display->drm, mid_cdclk_config->cdclk >
> + display->cdclk.max_cdclk_freq);
> + drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) !=
> mid_waveform);
>
> return true;
> }
>
> -static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
> +static bool pll_enable_wa_needed(struct intel_display *display)
> {
> - return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) ||
> - DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) ||
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> + return (DISPLAY_VER_FULL(display) == IP_VER(20, 0) ||
> + DISPLAY_VER_FULL(display) == IP_VER(14, 0) ||
> IS_DG2(dev_priv)) &&
> - dev_priv->display.cdclk.hw.vco > 0;
> + display->cdclk.hw.vco > 0;
> }
>
> -static u32 bxt_cdclk_ctl(struct drm_i915_private *i915,
> +static u32 bxt_cdclk_ctl(struct intel_display *display,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> int cdclk = cdclk_config->cdclk;
> int vco = cdclk_config->vco;
> u16 waveform;
> u32 val;
>
> - waveform = cdclk_squash_waveform(i915, cdclk);
> + waveform = cdclk_squash_waveform(display, cdclk);
>
> - val = bxt_cdclk_cd2x_div_sel(i915, cdclk, vco, waveform) |
> - bxt_cdclk_cd2x_pipe(i915, pipe);
> + val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) |
> + bxt_cdclk_cd2x_pipe(display, pipe);
>
> /*
> * Disable SSA Precharge when CD clock frequency < 500 MHz,
> @@ -2027,52 +2044,52 @@ static u32 bxt_cdclk_ctl(struct drm_i915_private *i915,
> cdclk >= 500000)
> val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
>
> - if (DISPLAY_VER(i915) >= 20)
> - val |= xe2lpd_mdclk_source_sel(i915);
> + if (DISPLAY_VER(display) >= 20)
> + val |= xe2lpd_mdclk_source_sel(display);
> else
> val |= skl_cdclk_decimal(cdclk);
>
> return val;
> }
>
> -static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> +static void _bxt_set_cdclk(struct intel_display *display,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> {
> - struct intel_display *display = &dev_priv->display;
> int cdclk = cdclk_config->cdclk;
> int vco = cdclk_config->vco;
>
> - if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 &&
> - !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
> - if (dev_priv->display.cdclk.hw.vco != vco)
> - adlp_cdclk_pll_crawl(dev_priv, vco);
> - } else if (DISPLAY_VER(dev_priv) >= 11) {
> + if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 &&
> + !cdclk_pll_is_unknown(display->cdclk.hw.vco)) {
> + if (display->cdclk.hw.vco != vco)
> + adlp_cdclk_pll_crawl(display, vco);
> + } else if (DISPLAY_VER(display) >= 11) {
> /* wa_15010685871: dg2, mtl */
> - if (pll_enable_wa_needed(dev_priv))
> - dg2_cdclk_squash_program(dev_priv, 0);
> + if (pll_enable_wa_needed(display))
> + dg2_cdclk_squash_program(display, 0);
>
> - icl_cdclk_pll_update(dev_priv, vco);
> + icl_cdclk_pll_update(display, vco);
> } else {
> - bxt_cdclk_pll_update(dev_priv, vco);
> + bxt_cdclk_pll_update(display, vco);
> }
>
> - if (HAS_CDCLK_SQUASH(dev_priv)) {
> - u16 waveform = cdclk_squash_waveform(dev_priv, cdclk);
> + if (HAS_CDCLK_SQUASH(display)) {
> + u16 waveform = cdclk_squash_waveform(display, cdclk);
>
> - dg2_cdclk_squash_program(dev_priv, waveform);
> + dg2_cdclk_squash_program(display, waveform);
> }
>
> - intel_de_write(dev_priv, CDCLK_CTL, bxt_cdclk_ctl(dev_priv, cdclk_config, pipe));
> + intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe));
>
> if (pipe != INVALID_PIPE)
> intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
> }
>
> -static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> +static void bxt_set_cdclk(struct intel_display *display,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct intel_cdclk_config mid_cdclk_config;
> int cdclk = cdclk_config->cdclk;
> int ret = 0;
> @@ -2083,9 +2100,9 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> * mailbox communication, skip
> * this step.
> */
> - if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv))
> + if (DISPLAY_VER(display) >= 14 || IS_DG2(dev_priv))
> /* NOOP */;
> - else if (DISPLAY_VER(dev_priv) >= 11)
> + else if (DISPLAY_VER(display) >= 11)
> ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
> SKL_CDCLK_PREPARE_FOR_CHANGE,
> SKL_CDCLK_READY_FOR_CHANGE,
> @@ -2100,35 +2117,35 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> 0x80000000, 150, 2);
>
> if (ret) {
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
> ret, cdclk);
> return;
> }
>
> - if (DISPLAY_VER(dev_priv) >= 20 && cdclk < dev_priv->display.cdclk.hw.cdclk)
> - xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config);
> + if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)
> + xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
>
> - if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw,
> + if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw,
> cdclk_config, &mid_cdclk_config)) {
> - _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe);
> - _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
> + _bxt_set_cdclk(display, &mid_cdclk_config, pipe);
> + _bxt_set_cdclk(display, cdclk_config, pipe);
> } else {
> - _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
> + _bxt_set_cdclk(display, cdclk_config, pipe);
> }
>
> - if (DISPLAY_VER(dev_priv) >= 20 && cdclk > dev_priv->display.cdclk.hw.cdclk)
> - xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config);
> + if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
> + xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
>
> - if (DISPLAY_VER(dev_priv) >= 14)
> + if (DISPLAY_VER(display) >= 14)
> /*
> * NOOP - No Pcode communication needed for
> * Display versions 14 and beyond
> */;
> - else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv))
> + else if (DISPLAY_VER(display) >= 11 && !IS_DG2(dev_priv))
> ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
> cdclk_config->voltage_level);
> - if (DISPLAY_VER(dev_priv) < 11) {
> + if (DISPLAY_VER(display) < 11) {
> /*
> * The timeout isn't specified, the 2ms used here is based on
> * experiment.
> @@ -2141,42 +2158,42 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> 150, 2);
> }
> if (ret) {
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "PCode CDCLK freq set failed, (err %d, freq %d)\n",
> ret, cdclk);
> return;
> }
>
> - intel_update_cdclk(dev_priv);
> + intel_update_cdclk(display);
>
> - if (DISPLAY_VER(dev_priv) >= 11)
> + if (DISPLAY_VER(display) >= 11)
> /*
> * Can't read out the voltage level :(
> * Let's just assume everything is as expected.
> */
> - dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level;
> + display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
> }
>
> -static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
> +static void bxt_sanitize_cdclk(struct intel_display *display)
> {
> u32 cdctl, expected;
> int cdclk, vco;
>
> - intel_update_cdclk(dev_priv);
> - intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
> + intel_update_cdclk(display);
> + intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
>
> - if (dev_priv->display.cdclk.hw.vco == 0 ||
> - dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
> + if (display->cdclk.hw.vco == 0 ||
> + display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
> goto sanitize;
>
> /* Make sure this is a legal cdclk value for the platform */
> - cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk);
> - if (cdclk != dev_priv->display.cdclk.hw.cdclk)
> + cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk);
> + if (cdclk != display->cdclk.hw.cdclk)
> goto sanitize;
>
> /* Make sure the VCO is correct for the cdclk */
> - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
> - if (vco != dev_priv->display.cdclk.hw.vco)
> + vco = bxt_calc_cdclk_pll_vco(display, cdclk);
> + if (vco != display->cdclk.hw.vco)
> goto sanitize;
>
> /*
> @@ -2184,129 +2201,133 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
> * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
> * so sanitize this register.
> */
> - cdctl = intel_de_read(dev_priv, CDCLK_CTL);
> - expected = bxt_cdclk_ctl(dev_priv, &dev_priv->display.cdclk.hw, INVALID_PIPE);
> + cdctl = intel_de_read(display, CDCLK_CTL);
> + expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE);
>
> /*
> * Let's ignore the pipe field, since BIOS could have configured the
> * dividers both synching to an active pipe, or asynchronously
> * (PIPE_NONE).
> */
> - cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
> - expected &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
> + cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
> + expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
>
> if (cdctl == expected)
> /* All well; nothing to sanitize */
> return;
>
> sanitize:
> - drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
> + drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
>
> /* force cdclk programming */
> - dev_priv->display.cdclk.hw.cdclk = 0;
> + display->cdclk.hw.cdclk = 0;
>
> /* force full PLL disable + enable */
> - dev_priv->display.cdclk.hw.vco = ~0;
> + display->cdclk.hw.vco = ~0;
> }
>
> -static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
> +static void bxt_cdclk_init_hw(struct intel_display *display)
> {
> struct intel_cdclk_config cdclk_config;
>
> - bxt_sanitize_cdclk(dev_priv);
> + bxt_sanitize_cdclk(display);
>
> - if (dev_priv->display.cdclk.hw.cdclk != 0 &&
> - dev_priv->display.cdclk.hw.vco != 0)
> + if (display->cdclk.hw.cdclk != 0 &&
> + display->cdclk.hw.vco != 0)
> return;
>
> - cdclk_config = dev_priv->display.cdclk.hw;
> + cdclk_config = display->cdclk.hw;
>
> /*
> * FIXME:
> * - The initial CDCLK needs to be read from VBT.
> * Need to make this change after VBT has changes for BXT.
> */
> - cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
> - cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
> + cdclk_config.cdclk = bxt_calc_cdclk(display, 0);
> + cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk);
> cdclk_config.voltage_level =
> - intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
> + intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
>
> - bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
> + bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
> }
>
> -static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
> +static void bxt_cdclk_uninit_hw(struct intel_display *display)
> {
> - struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
> + struct intel_cdclk_config cdclk_config = display->cdclk.hw;
>
> cdclk_config.cdclk = cdclk_config.bypass;
> cdclk_config.vco = 0;
> cdclk_config.voltage_level =
> - intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
> + intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
>
> - bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
> + bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
> }
>
> /**
> * intel_cdclk_init_hw - Initialize CDCLK hardware
> - * @i915: i915 device
> + * @display: display instance
> *
> - * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
> + * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and
> * sanitizing the state of the hardware if needed. This is generally done only
> * during the display core initialization sequence, after which the DMC will
> * take care of turning CDCLK off/on as needed.
> */
> -void intel_cdclk_init_hw(struct drm_i915_private *i915)
> +void intel_cdclk_init_hw(struct intel_display *display)
> {
> - if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
> - bxt_cdclk_init_hw(i915);
> - else if (DISPLAY_VER(i915) == 9)
> - skl_cdclk_init_hw(i915);
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> + if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915))
> + bxt_cdclk_init_hw(display);
> + else if (DISPLAY_VER(display) == 9)
> + skl_cdclk_init_hw(display);
> }
>
> /**
> * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
> - * @i915: i915 device
> + * @display: display instance
> *
> * Uninitialize CDCLK. This is done only during the display core
> * uninitialization sequence.
> */
> -void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
> +void intel_cdclk_uninit_hw(struct intel_display *display)
> {
> - if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
> - bxt_cdclk_uninit_hw(i915);
> - else if (DISPLAY_VER(i915) == 9)
> - skl_cdclk_uninit_hw(i915);
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> + if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915))
> + bxt_cdclk_uninit_hw(display);
> + else if (DISPLAY_VER(display) == 9)
> + skl_cdclk_uninit_hw(display);
> }
>
> -static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915,
> +static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display,
> const struct intel_cdclk_config *a,
> const struct intel_cdclk_config *b)
> {
> u16 old_waveform;
> u16 new_waveform;
>
> - drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco));
> + drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco));
>
> if (a->vco == 0 || b->vco == 0)
> return false;
>
> - if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
> + if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
> return false;
>
> - old_waveform = cdclk_squash_waveform(i915, a->cdclk);
> - new_waveform = cdclk_squash_waveform(i915, b->cdclk);
> + old_waveform = cdclk_squash_waveform(display, a->cdclk);
> + new_waveform = cdclk_squash_waveform(display, b->cdclk);
>
> return a->vco != b->vco &&
> old_waveform != new_waveform;
> }
>
> -static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
> +static bool intel_cdclk_can_crawl(struct intel_display *display,
> const struct intel_cdclk_config *a,
> const struct intel_cdclk_config *b)
> {
> int a_div, b_div;
>
> - if (!HAS_CDCLK_CRAWL(dev_priv))
> + if (!HAS_CDCLK_CRAWL(display))
> return false;
>
> /*
> @@ -2322,7 +2343,7 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
> a->ref == b->ref;
> }
>
> -static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
> +static bool intel_cdclk_can_squash(struct intel_display *display,
> const struct intel_cdclk_config *a,
> const struct intel_cdclk_config *b)
> {
> @@ -2332,7 +2353,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
> * the moment all platforms with squasher use a fixed cd2x
> * divider.
> */
> - if (!HAS_CDCLK_SQUASH(dev_priv))
> + if (!HAS_CDCLK_SQUASH(display))
> return false;
>
> return a->cdclk != b->cdclk &&
> @@ -2361,7 +2382,7 @@ bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
> /**
> * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
> * configurations requires only a cd2x divider update
> - * @dev_priv: i915 device
> + * @display: display instance
> * @a: first CDCLK configuration
> * @b: second CDCLK configuration
> *
> @@ -2369,12 +2390,14 @@ bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
> * True if changing between the two CDCLK configurations
> * can be done with just a cd2x divider update, false if not.
> */
> -static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
> +static bool intel_cdclk_can_cd2x_update(struct intel_display *display,
> const struct intel_cdclk_config *a,
> const struct intel_cdclk_config *b)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> /* Older hw doesn't have the capability */
> - if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv))
> + if (DISPLAY_VER(display) < 10 && !IS_BROXTON(dev_priv))
> return false;
>
> /*
> @@ -2383,7 +2406,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
> * the moment all platforms with squasher use a fixed cd2x
> * divider.
> */
> - if (HAS_CDCLK_SQUASH(dev_priv))
> + if (HAS_CDCLK_SQUASH(display))
> return false;
>
> return a->cdclk != b->cdclk &&
> @@ -2407,23 +2430,24 @@ static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
> a->voltage_level != b->voltage_level;
> }
>
> -void intel_cdclk_dump_config(struct drm_i915_private *i915,
> +void intel_cdclk_dump_config(struct intel_display *display,
> const struct intel_cdclk_config *cdclk_config,
> const char *context)
> {
> - drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
> + drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
> context, cdclk_config->cdclk, cdclk_config->vco,
> cdclk_config->ref, cdclk_config->bypass,
> cdclk_config->voltage_level);
> }
>
> -static void intel_pcode_notify(struct drm_i915_private *i915,
> +static void intel_pcode_notify(struct intel_display *display,
> u8 voltage_level,
> u8 active_pipe_count,
> u16 cdclk,
> bool cdclk_update_valid,
> bool pipe_count_update_valid)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> int ret;
> u32 update_mask = 0;
>
> @@ -2444,26 +2468,27 @@ static void intel_pcode_notify(struct drm_i915_private *i915,
> SKL_CDCLK_READY_FOR_CHANGE,
> SKL_CDCLK_READY_FOR_CHANGE, 3);
> if (ret)
> - drm_err(&i915->drm,
> + drm_err(display->drm,
> "Failed to inform PCU about display config (err %d)\n",
> ret);
> }
>
> -static void intel_set_cdclk(struct drm_i915_private *dev_priv,
> +static void intel_set_cdclk(struct intel_display *display,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe, const char *context)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct intel_encoder *encoder;
>
> - if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config))
> + if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config))
> return;
>
> - if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk))
> + if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk))
> return;
>
> - intel_cdclk_dump_config(dev_priv, cdclk_config, context);
> + intel_cdclk_dump_config(display, cdclk_config, context);
>
> - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> + for_each_intel_encoder_with_psr(display->drm, encoder) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> intel_psr_pause(intel_dp);
> @@ -2476,24 +2501,24 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
> * functions use cdclk. Not all platforms/ports do,
> * but we'll lock them all for simplicity.
> */
> - mutex_lock(&dev_priv->display.gmbus.mutex);
> - for_each_intel_dp(&dev_priv->drm, encoder) {
> + mutex_lock(&display->gmbus.mutex);
> + for_each_intel_dp(display->drm, encoder) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
> - &dev_priv->display.gmbus.mutex);
> + &display->gmbus.mutex);
> }
>
> - intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
> + intel_cdclk_set_cdclk(display, cdclk_config, pipe);
>
> - for_each_intel_dp(&dev_priv->drm, encoder) {
> + for_each_intel_dp(display->drm, encoder) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> mutex_unlock(&intel_dp->aux.hw_mutex);
> }
> - mutex_unlock(&dev_priv->display.gmbus.mutex);
> + mutex_unlock(&display->gmbus.mutex);
>
> - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> + for_each_intel_encoder_with_psr(display->drm, encoder) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> intel_psr_resume(intel_dp);
> @@ -2501,17 +2526,17 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
>
> intel_audio_cdclk_change_post(dev_priv);
>
> - if (drm_WARN(&dev_priv->drm,
> - intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config),
> + if (drm_WARN(display->drm,
> + intel_cdclk_changed(&display->cdclk.hw, cdclk_config),
> "cdclk state doesn't match!\n")) {
> - intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]");
> - intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]");
> + intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]");
> + intel_cdclk_dump_config(display, cdclk_config, "[sw state]");
> }
> }
>
> static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
> {
> - struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_display *display = to_intel_display(state);
> const struct intel_cdclk_state *old_cdclk_state =
> intel_atomic_get_old_cdclk_state(state);
> const struct intel_cdclk_state *new_cdclk_state =
> @@ -2550,13 +2575,13 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
> if (update_pipe_count)
> num_active_pipes = hweight8(new_cdclk_state->active_pipes);
>
> - intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk,
> + intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> change_cdclk, update_pipe_count);
> }
>
> static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
> {
> - struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_display *display = to_intel_display(state);
> const struct intel_cdclk_state *new_cdclk_state =
> intel_atomic_get_new_cdclk_state(state);
> const struct intel_cdclk_state *old_cdclk_state =
> @@ -2587,7 +2612,7 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
> if (update_pipe_count)
> num_active_pipes = hweight8(new_cdclk_state->active_pipes);
>
> - intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk,
> + intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> update_cdclk, update_pipe_count);
> }
>
> @@ -2612,7 +2637,8 @@ bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
> void
> intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
> {
> - struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_display *display = to_intel_display(state);
> + struct drm_i915_private *i915 = to_i915(display->drm);
> const struct intel_cdclk_state *old_cdclk_state =
> intel_atomic_get_old_cdclk_state(state);
> const struct intel_cdclk_state *new_cdclk_state =
> @@ -2649,9 +2675,9 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
> */
> cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus;
>
> - drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> + drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
>
> - intel_set_cdclk(i915, &cdclk_config, pipe,
> + intel_set_cdclk(display, &cdclk_config, pipe,
> "Pre changing CDCLK to");
> }
>
> @@ -2665,7 +2691,8 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
> void
> intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
> {
> - struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_display *display = to_intel_display(state);
> + struct drm_i915_private *i915 = to_i915(display->drm);
> const struct intel_cdclk_state *old_cdclk_state =
> intel_atomic_get_old_cdclk_state(state);
> const struct intel_cdclk_state *new_cdclk_state =
> @@ -2685,20 +2712,21 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
> else
> pipe = INVALID_PIPE;
>
> - drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> + drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
>
> - intel_set_cdclk(i915, &new_cdclk_state->actual, pipe,
> + intel_set_cdclk(display, &new_cdclk_state->actual, pipe,
> "Post changing CDCLK to");
> }
>
> static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_display *display = to_intel_display(crtc_state->uapi.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> int pixel_rate = crtc_state->pixel_rate;
>
> - if (DISPLAY_VER(dev_priv) >= 10)
> + if (DISPLAY_VER(display) >= 10)
> return DIV_ROUND_UP(pixel_rate, 2);
> - else if (DISPLAY_VER(dev_priv) == 9 ||
> + else if (DISPLAY_VER(display) == 9 ||
> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> return pixel_rate;
> else if (IS_CHERRYVIEW(dev_priv))
> @@ -2712,11 +2740,11 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
> static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc);
> struct intel_plane *plane;
> int min_cdclk = 0;
>
> - for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
> + for_each_intel_plane_on_crtc(display->drm, crtc, plane)
> min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk);
>
> return min_cdclk;
> @@ -2725,7 +2753,7 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
> static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc);
> int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
> int min_cdclk = 0;
>
> @@ -2754,7 +2782,7 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
> * Since PPC = 2 with bigjoiner
> * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
> */
> - int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
> + int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24;
> int min_cdclk_bj =
> (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
> pixel_clock) / (2 * bigjoiner_interface_bits);
> @@ -2767,8 +2795,9 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
>
> int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv =
> - to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_display *display =
> + to_intel_display(crtc_state->uapi.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> int min_cdclk;
>
> if (!crtc_state->hw.enable)
> @@ -2789,10 +2818,10 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> crtc_state->has_audio &&
> crtc_state->port_clock >= 540000 &&
> crtc_state->lane_count == 4) {
> - if (DISPLAY_VER(dev_priv) == 10) {
> + if (DISPLAY_VER(display) == 10) {
> /* Display WA #1145: glk */
> min_cdclk = max(316800, min_cdclk);
> - } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
> + } else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) {
> /* Display WA #1144: skl,bxt */
> min_cdclk = max(432000, min_cdclk);
> }
> @@ -2802,7 +2831,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> * According to BSpec, "The CD clock frequency must be at least twice
> * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> */
> - if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9)
> + if (crtc_state->has_audio && DISPLAY_VER(display) >= 9)
> min_cdclk = max(2 * 96000, min_cdclk);
>
> /*
> @@ -2844,7 +2873,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>
> static int intel_compute_min_cdclk(struct intel_atomic_state *state)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_display *display = to_intel_display(state);
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct intel_cdclk_state *cdclk_state =
> intel_atomic_get_new_cdclk_state(state);
> const struct intel_bw_state *bw_state;
> @@ -2887,7 +2917,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
>
> min_cdclk = max(cdclk_state->force_min_cdclk,
> cdclk_state->bw_min_cdclk);
> - for_each_pipe(dev_priv, pipe)
> + for_each_pipe(display, pipe)
> min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
>
> /*
> @@ -2902,10 +2932,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
> !is_power_of_2(cdclk_state->active_pipes))
> min_cdclk = max(2 * 96000, min_cdclk);
>
> - if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) {
> - drm_dbg_kms(&dev_priv->drm,
> + if (min_cdclk > display->cdclk.max_cdclk_freq) {
> + drm_dbg_kms(display->drm,
> "required cdclk (%d kHz) exceeds max (%d kHz)\n",
> - min_cdclk, dev_priv->display.cdclk.max_cdclk_freq);
> + min_cdclk, display->cdclk.max_cdclk_freq);
> return -EINVAL;
> }
>
> @@ -2927,7 +2957,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
> */
> static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_display *display = to_intel_display(state);
> struct intel_cdclk_state *cdclk_state =
> intel_atomic_get_new_cdclk_state(state);
> struct intel_crtc *crtc;
> @@ -2955,7 +2985,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> }
>
> min_voltage_level = 0;
> - for_each_pipe(dev_priv, pipe)
> + for_each_pipe(display, pipe)
> min_voltage_level = max(cdclk_state->min_voltage_level[pipe],
> min_voltage_level);
>
> @@ -2964,7 +2994,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
>
> static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_display *display = to_intel_display(state);
> struct intel_cdclk_state *cdclk_state =
> intel_atomic_get_new_cdclk_state(state);
> int min_cdclk, cdclk;
> @@ -2973,18 +3003,18 @@ static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
> if (min_cdclk < 0)
> return min_cdclk;
>
> - cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
> + cdclk = vlv_calc_cdclk(display, min_cdclk);
>
> cdclk_state->logical.cdclk = cdclk;
> cdclk_state->logical.voltage_level =
> - vlv_calc_voltage_level(dev_priv, cdclk);
> + vlv_calc_voltage_level(display, cdclk);
>
> if (!cdclk_state->active_pipes) {
> - cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
> + cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk);
>
> cdclk_state->actual.cdclk = cdclk;
> cdclk_state->actual.voltage_level =
> - vlv_calc_voltage_level(dev_priv, cdclk);
> + vlv_calc_voltage_level(display, cdclk);
> } else {
> cdclk_state->actual = cdclk_state->logical;
> }
> @@ -3023,7 +3053,7 @@ static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
>
> static int skl_dpll0_vco(struct intel_atomic_state *state)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_display *display = to_intel_display(state);
> struct intel_cdclk_state *cdclk_state =
> intel_atomic_get_new_cdclk_state(state);
> struct intel_crtc *crtc;
> @@ -3032,7 +3062,7 @@ static int skl_dpll0_vco(struct intel_atomic_state *state)
>
> vco = cdclk_state->logical.vco;
> if (!vco)
> - vco = dev_priv->display.cdclk.skl_preferred_vco_freq;
> + vco = display->cdclk.skl_preferred_vco_freq;
>
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> if (!crtc_state->hw.enable)
> @@ -3094,7 +3124,7 @@ static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
>
> static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_display *display = to_intel_display(state);
> struct intel_cdclk_state *cdclk_state =
> intel_atomic_get_new_cdclk_state(state);
> int min_cdclk, min_voltage_level, cdclk, vco;
> @@ -3107,23 +3137,23 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
> if (min_voltage_level < 0)
> return min_voltage_level;
>
> - cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
> - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
> + cdclk = bxt_calc_cdclk(display, min_cdclk);
> + vco = bxt_calc_cdclk_pll_vco(display, cdclk);
>
> cdclk_state->logical.vco = vco;
> cdclk_state->logical.cdclk = cdclk;
> cdclk_state->logical.voltage_level =
> max_t(int, min_voltage_level,
> - intel_cdclk_calc_voltage_level(dev_priv, cdclk));
> + intel_cdclk_calc_voltage_level(display, cdclk));
>
> if (!cdclk_state->active_pipes) {
> - cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
> - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
> + cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk);
> + vco = bxt_calc_cdclk_pll_vco(display, cdclk);
>
> cdclk_state->actual.vco = vco;
> cdclk_state->actual.cdclk = cdclk;
> cdclk_state->actual.voltage_level =
> - intel_cdclk_calc_voltage_level(dev_priv, cdclk);
> + intel_cdclk_calc_voltage_level(display, cdclk);
> } else {
> cdclk_state->actual = cdclk_state->logical;
> }
> @@ -3175,10 +3205,10 @@ static const struct intel_global_state_funcs intel_cdclk_funcs = {
> struct intel_cdclk_state *
> intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_display *display = to_intel_display(state);
> struct intel_global_state *cdclk_state;
>
> - cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj);
> + cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj);
> if (IS_ERR(cdclk_state))
> return ERR_CAST(cdclk_state);
>
> @@ -3234,24 +3264,26 @@ int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joi
> return intel_atomic_lock_global_state(&cdclk_state->base);
> }
>
> -int intel_cdclk_init(struct drm_i915_private *dev_priv)
> +int intel_cdclk_init(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct intel_cdclk_state *cdclk_state;
>
> cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
> if (!cdclk_state)
> return -ENOMEM;
>
> - intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
> + intel_atomic_global_obj_init(dev_priv, &display->cdclk.obj,
> &cdclk_state->base, &intel_cdclk_funcs);
>
> return 0;
> }
>
> -static bool intel_cdclk_need_serialize(struct drm_i915_private *i915,
> +static bool intel_cdclk_need_serialize(struct intel_display *display,
> const struct intel_cdclk_state *old_cdclk_state,
> const struct intel_cdclk_state *new_cdclk_state)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) !=
> hweight8(new_cdclk_state->active_pipes);
> bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual,
> @@ -3266,7 +3298,6 @@ static bool intel_cdclk_need_serialize(struct drm_i915_private *i915,
> int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> {
> struct intel_display *display = to_intel_display(state);
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> const struct intel_cdclk_state *old_cdclk_state;
> struct intel_cdclk_state *new_cdclk_state;
> enum pipe pipe = INVALID_PIPE;
> @@ -3285,7 +3316,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> if (ret)
> return ret;
>
> - if (intel_cdclk_need_serialize(dev_priv, old_cdclk_state, new_cdclk_state)) {
> + if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) {
> /*
> * Also serialize commits across all crtcs
> * if the actual hw needs to be poked.
> @@ -3305,7 +3336,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> }
>
> if (is_power_of_2(new_cdclk_state->active_pipes) &&
> - intel_cdclk_can_cd2x_update(dev_priv,
> + intel_cdclk_can_cd2x_update(display,
> &old_cdclk_state->actual,
> &new_cdclk_state->actual)) {
> struct intel_crtc *crtc;
> @@ -3322,25 +3353,25 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> pipe = INVALID_PIPE;
> }
>
> - if (intel_cdclk_can_crawl_and_squash(dev_priv,
> + if (intel_cdclk_can_crawl_and_squash(display,
> &old_cdclk_state->actual,
> &new_cdclk_state->actual)) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Can change cdclk via crawling and squashing\n");
> - } else if (intel_cdclk_can_squash(dev_priv,
> + } else if (intel_cdclk_can_squash(display,
> &old_cdclk_state->actual,
> &new_cdclk_state->actual)) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Can change cdclk via squashing\n");
> - } else if (intel_cdclk_can_crawl(dev_priv,
> + } else if (intel_cdclk_can_crawl(display,
> &old_cdclk_state->actual,
> &new_cdclk_state->actual)) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Can change cdclk via crawling\n");
> } else if (pipe != INVALID_PIPE) {
> new_cdclk_state->pipe = pipe;
>
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Can change cdclk cd2x divider with pipe %c active\n",
> pipe_name(pipe));
> } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual,
> @@ -3352,24 +3383,24 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
>
> new_cdclk_state->disable_pipes = true;
>
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Modeset required for cdclk change\n");
> }
>
> - if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) !=
> - intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) {
> - int ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual);
> + if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) !=
> + intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) {
> + int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual);
>
> ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
> if (ret)
> return ret;
> }
>
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
> new_cdclk_state->logical.cdclk,
> new_cdclk_state->actual.cdclk);
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "New voltage level calculated to be logical %u, actual %u\n",
> new_cdclk_state->logical.voltage_level,
> new_cdclk_state->actual.voltage_level);
> @@ -3377,18 +3408,19 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> return 0;
> }
>
> -static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> +static int intel_compute_max_dotclk(struct intel_display *display)
> {
> - int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> + int max_cdclk_freq = display->cdclk.max_cdclk_freq;
>
> - if (DISPLAY_VER(dev_priv) >= 10)
> + if (DISPLAY_VER(display) >= 10)
> return 2 * max_cdclk_freq;
> - else if (DISPLAY_VER(dev_priv) == 9 ||
> + else if (DISPLAY_VER(display) == 9 ||
> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> return max_cdclk_freq;
> else if (IS_CHERRYVIEW(dev_priv))
> return max_cdclk_freq*95/100;
> - else if (DISPLAY_VER(dev_priv) < 4)
> + else if (DISPLAY_VER(display) < 4)
> return 2*max_cdclk_freq*90/100;
> else
> return max_cdclk_freq*90/100;
> @@ -3396,34 +3428,36 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>
> /**
> * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
> - * @dev_priv: i915 device
> + * @display: display instance
> *
> * Determine the maximum CDCLK frequency the platform supports, and also
> * derive the maximum dot clock frequency the maximum CDCLK frequency
> * allows.
> */
> -void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> +void intel_update_max_cdclk(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
> - if (dev_priv->display.cdclk.hw.ref == 24000)
> - dev_priv->display.cdclk.max_cdclk_freq = 552000;
> + if (display->cdclk.hw.ref == 24000)
> + display->cdclk.max_cdclk_freq = 552000;
> else
> - dev_priv->display.cdclk.max_cdclk_freq = 556800;
> - } else if (DISPLAY_VER(dev_priv) >= 11) {
> - if (dev_priv->display.cdclk.hw.ref == 24000)
> - dev_priv->display.cdclk.max_cdclk_freq = 648000;
> + display->cdclk.max_cdclk_freq = 556800;
> + } else if (DISPLAY_VER(display) >= 11) {
> + if (display->cdclk.hw.ref == 24000)
> + display->cdclk.max_cdclk_freq = 648000;
> else
> - dev_priv->display.cdclk.max_cdclk_freq = 652800;
> + display->cdclk.max_cdclk_freq = 652800;
> } else if (IS_GEMINILAKE(dev_priv)) {
> - dev_priv->display.cdclk.max_cdclk_freq = 316800;
> + display->cdclk.max_cdclk_freq = 316800;
> } else if (IS_BROXTON(dev_priv)) {
> - dev_priv->display.cdclk.max_cdclk_freq = 624000;
> - } else if (DISPLAY_VER(dev_priv) == 9) {
> - u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> + display->cdclk.max_cdclk_freq = 624000;
> + } else if (DISPLAY_VER(display) == 9) {
> + u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> int max_cdclk, vco;
>
> - vco = dev_priv->display.cdclk.skl_preferred_vco_freq;
> - drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
> + vco = display->cdclk.skl_preferred_vco_freq;
> + drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
>
> /*
> * Use the lower (vco 8640) cdclk values as a
> @@ -3439,7 +3473,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> else
> max_cdclk = 308571;
>
> - dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
> + display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
> } else if (IS_BROADWELL(dev_priv)) {
> /*
> * FIXME with extra cooling we can allow
> @@ -3447,41 +3481,43 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> * How can we know if extra cooling is
> * available? PCI ID, VTB, something else?
> */
> - if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
> - dev_priv->display.cdclk.max_cdclk_freq = 450000;
> + if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
> + display->cdclk.max_cdclk_freq = 450000;
> else if (IS_BROADWELL_ULX(dev_priv))
> - dev_priv->display.cdclk.max_cdclk_freq = 450000;
> + display->cdclk.max_cdclk_freq = 450000;
> else if (IS_BROADWELL_ULT(dev_priv))
> - dev_priv->display.cdclk.max_cdclk_freq = 540000;
> + display->cdclk.max_cdclk_freq = 540000;
> else
> - dev_priv->display.cdclk.max_cdclk_freq = 675000;
> + display->cdclk.max_cdclk_freq = 675000;
> } else if (IS_CHERRYVIEW(dev_priv)) {
> - dev_priv->display.cdclk.max_cdclk_freq = 320000;
> + display->cdclk.max_cdclk_freq = 320000;
> } else if (IS_VALLEYVIEW(dev_priv)) {
> - dev_priv->display.cdclk.max_cdclk_freq = 400000;
> + display->cdclk.max_cdclk_freq = 400000;
> } else {
> /* otherwise assume cdclk is fixed */
> - dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk;
> + display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk;
> }
>
> - dev_priv->display.cdclk.max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
> + display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display);
>
> - drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
> - dev_priv->display.cdclk.max_cdclk_freq);
> + drm_dbg(display->drm, "Max CD clock rate: %d kHz\n",
> + display->cdclk.max_cdclk_freq);
>
> - drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
> - dev_priv->display.cdclk.max_dotclk_freq);
> + drm_dbg(display->drm, "Max dotclock rate: %d kHz\n",
> + display->cdclk.max_dotclk_freq);
> }
>
> /**
> * intel_update_cdclk - Determine the current CDCLK frequency
> - * @dev_priv: i915 device
> + * @display: display instance
> *
> * Determine the current CDCLK frequency.
> */
> -void intel_update_cdclk(struct drm_i915_private *dev_priv)
> +void intel_update_cdclk(struct intel_display *display)
> {
> - intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw);
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> + intel_cdclk_get_cdclk(display, &display->cdclk.hw);
>
> /*
> * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
> @@ -3490,28 +3526,29 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
> * generate GMBus clock. This will vary with the cdclk freq.
> */
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - intel_de_write(dev_priv, GMBUSFREQ_VLV,
> - DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000));
> + intel_de_write(display, GMBUSFREQ_VLV,
> + DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000));
> }
>
> -static int dg1_rawclk(struct drm_i915_private *dev_priv)
> +static int dg1_rawclk(struct intel_display *display)
> {
> /*
> * DG1 always uses a 38.4 MHz rawclk. The bspec tells us
> * "Program Numerator=2, Denominator=4, Divider=37 decimal."
> */
> - intel_de_write(dev_priv, PCH_RAWCLK_FREQ,
> + intel_de_write(display, PCH_RAWCLK_FREQ,
> CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
>
> return 38400;
> }
>
> -static int cnp_rawclk(struct drm_i915_private *dev_priv)
> +static int cnp_rawclk(struct intel_display *display)
> {
> - u32 rawclk;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> int divider, fraction;
> + u32 rawclk;
>
> - if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
> + if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
> /* 24 MHz */
> divider = 24000;
> fraction = 0;
> @@ -3531,37 +3568,42 @@ static int cnp_rawclk(struct drm_i915_private *dev_priv)
> rawclk |= ICP_RAWCLK_NUM(numerator);
> }
>
> - intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk);
> + intel_de_write(display, PCH_RAWCLK_FREQ, rawclk);
> return divider + fraction;
> }
>
> -static int pch_rawclk(struct drm_i915_private *dev_priv)
> +static int pch_rawclk(struct intel_display *display)
> {
> - return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
> + return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
> }
>
> -static int vlv_hrawclk(struct drm_i915_private *dev_priv)
> +static int vlv_hrawclk(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> /* RAWCLK_FREQ_VLV register updated from power well code */
> return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
> CCK_DISPLAY_REF_CLOCK_CONTROL);
> }
>
> -static int i9xx_hrawclk(struct drm_i915_private *i915)
> +static int i9xx_hrawclk(struct intel_display *display)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> /* hrawclock is 1/4 the FSB frequency */
> return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
> }
>
> /**
> * intel_read_rawclk - Determine the current RAWCLK frequency
> - * @dev_priv: i915 device
> + * @display: display instance
> *
> * Determine the current RAWCLK frequency. RAWCLK is a fixed
> * frequency clock so this needs to done only once.
> */
> -u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
> +u32 intel_read_rawclk(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 freq;
>
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
> @@ -3572,15 +3614,15 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
> */
> freq = 38400;
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> - freq = dg1_rawclk(dev_priv);
> + freq = dg1_rawclk(display);
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
> - freq = cnp_rawclk(dev_priv);
> + freq = cnp_rawclk(display);
> else if (HAS_PCH_SPLIT(dev_priv))
> - freq = pch_rawclk(dev_priv);
> + freq = pch_rawclk(display);
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - freq = vlv_hrawclk(dev_priv);
> - else if (DISPLAY_VER(dev_priv) >= 3)
> - freq = i9xx_hrawclk(dev_priv);
> + freq = vlv_hrawclk(display);
> + else if (DISPLAY_VER(display) >= 3)
> + freq = i9xx_hrawclk(display);
> else
> /* no rawclk on other platforms, or no need to know it */
> return 0;
> @@ -3590,23 +3632,23 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
>
> static int i915_cdclk_info_show(struct seq_file *m, void *unused)
> {
> - struct drm_i915_private *i915 = m->private;
> + struct intel_display *display = m->private;
>
> - seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk);
> - seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq);
> - seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->display.cdclk.max_dotclk_freq);
> + seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk);
> + seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq);
> + seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq);
>
> return 0;
> }
>
> DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info);
>
> -void intel_cdclk_debugfs_register(struct drm_i915_private *i915)
> +void intel_cdclk_debugfs_register(struct intel_display *display)
> {
> - struct drm_minor *minor = i915->drm.primary;
> + struct drm_minor *minor = display->drm->primary;
>
> debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root,
> - i915, &i915_cdclk_info_fops);
> + display, &i915_cdclk_info_fops);
> }
>
> static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
> @@ -3747,97 +3789,99 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
>
> /**
> * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
> - * @dev_priv: i915 device
> + * @display: display instance
> */
> -void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> +void intel_init_cdclk_hooks(struct intel_display *display)
> {
> - if (DISPLAY_VER(dev_priv) >= 20) {
> - dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
> - dev_priv->display.cdclk.table = xe2lpd_cdclk_table;
> - } else if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1)) {
> - dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
> - dev_priv->display.cdclk.table = xe2hpd_cdclk_table;
> - } else if (DISPLAY_VER(dev_priv) >= 14) {
> - dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
> - dev_priv->display.cdclk.table = mtl_cdclk_table;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> + if (DISPLAY_VER(display) >= 20) {
> + display->funcs.cdclk = &rplu_cdclk_funcs;
> + display->cdclk.table = xe2lpd_cdclk_table;
> + } else if (DISPLAY_VER_FULL(display) >= IP_VER(14, 1)) {
> + display->funcs.cdclk = &rplu_cdclk_funcs;
> + display->cdclk.table = xe2hpd_cdclk_table;
> + } else if (DISPLAY_VER(display) >= 14) {
> + display->funcs.cdclk = &rplu_cdclk_funcs;
> + display->cdclk.table = mtl_cdclk_table;
> } else if (IS_DG2(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> - dev_priv->display.cdclk.table = dg2_cdclk_table;
> + display->funcs.cdclk = &tgl_cdclk_funcs;
> + display->cdclk.table = dg2_cdclk_table;
> } else if (IS_ALDERLAKE_P(dev_priv)) {
> /* Wa_22011320316:adl-p[a0] */
> if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> - dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
> - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> + display->cdclk.table = adlp_a_step_cdclk_table;
> + display->funcs.cdclk = &tgl_cdclk_funcs;
> } else if (IS_RAPTORLAKE_U(dev_priv)) {
> - dev_priv->display.cdclk.table = rplu_cdclk_table;
> - dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
> + display->cdclk.table = rplu_cdclk_table;
> + display->funcs.cdclk = &rplu_cdclk_funcs;
> } else {
> - dev_priv->display.cdclk.table = adlp_cdclk_table;
> - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> + display->cdclk.table = adlp_cdclk_table;
> + display->funcs.cdclk = &tgl_cdclk_funcs;
> }
> } else if (IS_ROCKETLAKE(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> - dev_priv->display.cdclk.table = rkl_cdclk_table;
> - } else if (DISPLAY_VER(dev_priv) >= 12) {
> - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> - dev_priv->display.cdclk.table = icl_cdclk_table;
> + display->funcs.cdclk = &tgl_cdclk_funcs;
> + display->cdclk.table = rkl_cdclk_table;
> + } else if (DISPLAY_VER(display) >= 12) {
> + display->funcs.cdclk = &tgl_cdclk_funcs;
> + display->cdclk.table = icl_cdclk_table;
> } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
> - dev_priv->display.cdclk.table = icl_cdclk_table;
> - } else if (DISPLAY_VER(dev_priv) >= 11) {
> - dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
> - dev_priv->display.cdclk.table = icl_cdclk_table;
> + display->funcs.cdclk = &ehl_cdclk_funcs;
> + display->cdclk.table = icl_cdclk_table;
> + } else if (DISPLAY_VER(display) >= 11) {
> + display->funcs.cdclk = &icl_cdclk_funcs;
> + display->cdclk.table = icl_cdclk_table;
> } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
> + display->funcs.cdclk = &bxt_cdclk_funcs;
> if (IS_GEMINILAKE(dev_priv))
> - dev_priv->display.cdclk.table = glk_cdclk_table;
> + display->cdclk.table = glk_cdclk_table;
> else
> - dev_priv->display.cdclk.table = bxt_cdclk_table;
> - } else if (DISPLAY_VER(dev_priv) == 9) {
> - dev_priv->display.funcs.cdclk = &skl_cdclk_funcs;
> + display->cdclk.table = bxt_cdclk_table;
> + } else if (DISPLAY_VER(display) == 9) {
> + display->funcs.cdclk = &skl_cdclk_funcs;
> } else if (IS_BROADWELL(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs;
> + display->funcs.cdclk = &bdw_cdclk_funcs;
> } else if (IS_HASWELL(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs;
> + display->funcs.cdclk = &hsw_cdclk_funcs;
> } else if (IS_CHERRYVIEW(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &chv_cdclk_funcs;
> + display->funcs.cdclk = &chv_cdclk_funcs;
> } else if (IS_VALLEYVIEW(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs;
> + display->funcs.cdclk = &vlv_cdclk_funcs;
> } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
> + display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
> } else if (IS_IRONLAKE(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs;
> + display->funcs.cdclk = &ilk_cdclk_funcs;
> } else if (IS_GM45(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs;
> + display->funcs.cdclk = &gm45_cdclk_funcs;
> } else if (IS_G45(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
> + display->funcs.cdclk = &g33_cdclk_funcs;
> } else if (IS_I965GM(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs;
> + display->funcs.cdclk = &i965gm_cdclk_funcs;
> } else if (IS_I965G(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
> + display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
> } else if (IS_PINEVIEW(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs;
> + display->funcs.cdclk = &pnv_cdclk_funcs;
> } else if (IS_G33(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
> + display->funcs.cdclk = &g33_cdclk_funcs;
> } else if (IS_I945GM(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs;
> + display->funcs.cdclk = &i945gm_cdclk_funcs;
> } else if (IS_I945G(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
> + display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
> } else if (IS_I915GM(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs;
> + display->funcs.cdclk = &i915gm_cdclk_funcs;
> } else if (IS_I915G(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs;
> + display->funcs.cdclk = &i915g_cdclk_funcs;
> } else if (IS_I865G(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs;
> + display->funcs.cdclk = &i865g_cdclk_funcs;
> } else if (IS_I85X(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs;
> + display->funcs.cdclk = &i85x_cdclk_funcs;
> } else if (IS_I845G(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs;
> + display->funcs.cdclk = &i845g_cdclk_funcs;
> } else if (IS_I830(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
> + display->funcs.cdclk = &i830_cdclk_funcs;
> }
>
> - if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
> + if (drm_WARN(display->drm, !display->funcs.cdclk,
> "Unknown platform. Assuming i830\n"))
> - dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
> + display->funcs.cdclk = &i830_cdclk_funcs;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 1fe445a3a30b..6b0e7a41eba3 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -11,9 +11,9 @@
> #include "intel_display_limits.h"
> #include "intel_global_state.h"
>
> -struct drm_i915_private;
> struct intel_atomic_state;
> struct intel_crtc_state;
> +struct intel_display;
>
> struct intel_cdclk_config {
> unsigned int cdclk, vco, ref, bypass;
> @@ -59,24 +59,24 @@ struct intel_cdclk_state {
> };
>
> int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
> -void intel_cdclk_init_hw(struct drm_i915_private *i915);
> -void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
> -void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> -void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> -void intel_update_cdclk(struct drm_i915_private *dev_priv);
> -u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
> +void intel_cdclk_init_hw(struct intel_display *display);
> +void intel_cdclk_uninit_hw(struct intel_display *display);
> +void intel_init_cdclk_hooks(struct intel_display *display);
> +void intel_update_max_cdclk(struct intel_display *display);
> +void intel_update_cdclk(struct intel_display *display);
> +u32 intel_read_rawclk(struct intel_display *display);
> bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
> const struct intel_cdclk_config *b);
> -int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> +int intel_mdclk_cdclk_ratio(struct intel_display *display,
> const struct intel_cdclk_config *cdclk_config);
> bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state);
> void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
> void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
> -void intel_cdclk_dump_config(struct drm_i915_private *i915,
> +void intel_cdclk_dump_config(struct intel_display *display,
> const struct intel_cdclk_config *cdclk_config,
> const char *context);
> int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
> -void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
> +void intel_cdclk_get_cdclk(struct intel_display *display,
> struct intel_cdclk_config *cdclk_config);
> int intel_cdclk_atomic_check(struct intel_atomic_state *state,
> bool *need_cdclk_calc);
> @@ -92,7 +92,7 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
> #define intel_atomic_get_new_cdclk_state(state) \
> to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->cdclk.obj))
>
> -int intel_cdclk_init(struct drm_i915_private *dev_priv);
> -void intel_cdclk_debugfs_register(struct drm_i915_private *i915);
> +int intel_cdclk_init(struct intel_display *display);
> +void intel_cdclk_debugfs_register(struct intel_display *display);
>
> #endif /* __INTEL_CDCLK_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 830b9eb60976..c1bef34d1ffd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1068,7 +1068,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
> minor->debugfs_root, minor);
>
> intel_bios_debugfs_register(display);
> - intel_cdclk_debugfs_register(i915);
> + intel_cdclk_debugfs_register(display);
> intel_dmc_debugfs_register(i915);
> intel_fbc_debugfs_register(display);
> intel_hpd_debugfs_register(i915);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 408c76852495..9ff08dbefc76 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -1678,7 +1678,7 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9
> }
> }
>
> - display_runtime->rawclk_freq = intel_read_rawclk(i915);
> + display_runtime->rawclk_freq = intel_read_rawclk(&i915->display);
> drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq);
>
> return;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index e7670774ecd0..434e52f450ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -82,16 +82,17 @@ bool intel_display_driver_probe_defer(struct pci_dev *pdev)
>
> void intel_display_driver_init_hw(struct drm_i915_private *i915)
> {
> + struct intel_display *display = &i915->display;
> struct intel_cdclk_state *cdclk_state;
>
> if (!HAS_DISPLAY(i915))
> return;
>
> - cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state);
> + cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state);
>
> - intel_update_cdclk(i915);
> - intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK");
> - cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
> + intel_update_cdclk(display);
> + intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
> + cdclk_state->logical = cdclk_state->actual = display->cdclk.hw;
>
> intel_display_wa_apply(i915);
> }
> @@ -194,7 +195,7 @@ void intel_display_driver_early_probe(struct drm_i915_private *i915)
> intel_display_irq_init(i915);
> intel_dkl_phy_init(i915);
> intel_color_init_hooks(i915);
> - intel_init_cdclk_hooks(i915);
> + intel_init_cdclk_hooks(&i915->display);
> intel_audio_hooks_init(i915);
> intel_dpll_init_clock_hook(i915);
> intel_init_display_hooks(i915);
> @@ -244,7 +245,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
>
> intel_mode_config_init(i915);
>
> - ret = intel_cdclk_init(i915);
> + ret = intel_cdclk_init(display);
> if (ret)
> goto cleanup_vga_client_pw_domain_dmc;
>
> @@ -451,8 +452,8 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
> intel_display_driver_init_hw(i915);
> intel_dpll_update_ref_clks(i915);
>
> - if (i915->display.cdclk.max_cdclk_freq == 0)
> - intel_update_max_cdclk(i915);
> + if (display->cdclk.max_cdclk_freq == 0)
> + intel_update_max_cdclk(display);
>
> intel_hti_init(display);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index ef2fdbf97346..eb3e2a56af1d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1300,6 +1300,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
> */
> static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> u32 val;
>
> val = intel_de_read(dev_priv, LCPLL_CTL);
> @@ -1343,8 +1344,8 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
>
> intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>
> - intel_update_cdclk(dev_priv);
> - intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
> + intel_update_cdclk(display);
> + intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
> }
>
> /*
> @@ -1416,7 +1417,8 @@ static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
> static void skl_display_core_init(struct drm_i915_private *dev_priv,
> bool resume)
> {
> - struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
> + struct intel_display *display = &dev_priv->display;
> + struct i915_power_domains *power_domains = &display->power.domains;
> struct i915_power_well *well;
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> @@ -1438,7 +1440,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
>
> mutex_unlock(&power_domains->lock);
>
> - intel_cdclk_init_hw(dev_priv);
> + intel_cdclk_init_hw(display);
>
> gen9_dbuf_enable(dev_priv);
>
> @@ -1448,7 +1450,8 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
>
> static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
> {
> - struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
> + struct intel_display *display = &dev_priv->display;
> + struct i915_power_domains *power_domains = &display->power.domains;
> struct i915_power_well *well;
>
> if (!HAS_DISPLAY(dev_priv))
> @@ -1459,7 +1462,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
>
> gen9_dbuf_disable(dev_priv);
>
> - intel_cdclk_uninit_hw(dev_priv);
> + intel_cdclk_uninit_hw(display);
>
> /* The spec doesn't call for removing the reset handshake flag */
> /* disable PG1 and Misc I/O */
> @@ -1482,7 +1485,8 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
>
> static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume)
> {
> - struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
> + struct intel_display *display = &dev_priv->display;
> + struct i915_power_domains *power_domains = &display->power.domains;
> struct i915_power_well *well;
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> @@ -1506,7 +1510,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
>
> mutex_unlock(&power_domains->lock);
>
> - intel_cdclk_init_hw(dev_priv);
> + intel_cdclk_init_hw(display);
>
> gen9_dbuf_enable(dev_priv);
>
> @@ -1516,7 +1520,8 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
>
> static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
> {
> - struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
> + struct intel_display *display = &dev_priv->display;
> + struct i915_power_domains *power_domains = &display->power.domains;
> struct i915_power_well *well;
>
> if (!HAS_DISPLAY(dev_priv))
> @@ -1527,7 +1532,7 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
>
> gen9_dbuf_disable(dev_priv);
>
> - intel_cdclk_uninit_hw(dev_priv);
> + intel_cdclk_uninit_hw(display);
>
> /* The spec doesn't call for removing the reset handshake flag */
>
> @@ -1623,7 +1628,8 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> static void icl_display_core_init(struct drm_i915_private *dev_priv,
> bool resume)
> {
> - struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
> + struct intel_display *display = &dev_priv->display;
> + struct i915_power_domains *power_domains = &display->power.domains;
> struct i915_power_well *well;
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> @@ -1657,7 +1663,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0);
>
> /* 4. Enable CDCLK. */
> - intel_cdclk_init_hw(dev_priv);
> + intel_cdclk_init_hw(display);
>
> if (DISPLAY_VER(dev_priv) >= 12)
> gen12_dbuf_slices_config(dev_priv);
> @@ -1704,7 +1710,8 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
>
> static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
> {
> - struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
> + struct intel_display *display = &dev_priv->display;
> + struct i915_power_domains *power_domains = &display->power.domains;
> struct i915_power_well *well;
>
> if (!HAS_DISPLAY(dev_priv))
> @@ -1719,7 +1726,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
> gen9_dbuf_disable(dev_priv);
>
> /* 3. Disable CD clock */
> - intel_cdclk_uninit_hw(dev_priv);
> + intel_cdclk_uninit_hw(display);
>
> if (DISPLAY_VER(dev_priv) == 14)
> intel_de_rmw(dev_priv, DC_STATE_EN, 0,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 46e9eff12c23..7b40a5b88214 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -967,7 +967,8 @@ static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
>
> void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
> {
> - struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
> + struct intel_display *display = &dev_priv->display;
> + struct i915_power_domains *power_domains = &display->power.domains;
> struct intel_cdclk_config cdclk_config = {};
>
> if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) {
> @@ -982,10 +983,10 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
>
> intel_dmc_wl_disable(&dev_priv->display);
>
> - intel_cdclk_get_cdclk(dev_priv, &cdclk_config);
> + intel_cdclk_get_cdclk(display, &cdclk_config);
> /* Can't read out voltage_level so can't use intel_cdclk_changed() */
> - drm_WARN_ON(&dev_priv->drm,
> - intel_cdclk_clock_changed(&dev_priv->display.cdclk.hw,
> + drm_WARN_ON(display->drm,
> + intel_cdclk_clock_changed(&display->cdclk.hw,
> &cdclk_config));
>
> gen9_assert_dbuf_enabled(dev_priv);
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 29835b638495..6e1f04d5ef47 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2973,6 +2973,7 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>
> static void skl_wm_get_hw_state(struct drm_i915_private *i915)
> {
> + struct intel_display *display = &i915->display;
> struct intel_dbuf_state *dbuf_state =
> to_intel_dbuf_state(i915->display.dbuf.obj.state);
> struct intel_crtc *crtc;
> @@ -2980,7 +2981,7 @@ static void skl_wm_get_hw_state(struct drm_i915_private *i915)
> if (HAS_MBUS_JOINING(i915))
> dbuf_state->joined_mbus = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN;
>
> - dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(i915, &i915->display.cdclk.hw);
> + dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw);
>
> for_each_intel_crtc(&i915->drm, crtc) {
> struct intel_crtc_state *crtc_state =
> --
> 2.44.2
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/6] drm/i915/cdclk: Add missing braces
2024-09-06 14:33 ` [PATCH 1/6] drm/i915/cdclk: Add missing braces Ville Syrjala
@ 2024-09-06 15:10 ` Rodrigo Vivi
2024-09-06 15:19 ` Jani Nikula
1 sibling, 0 replies; 23+ messages in thread
From: Rodrigo Vivi @ 2024-09-06 15:10 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx, intel-xe
On Fri, Sep 06, 2024 at 05:33:01PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> CodingStyle says when one branch of an if ladder is braced
> then all of them should be. Make it so.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 66964c7d2a2c..9d870d15d888 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2053,8 +2053,9 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> dg2_cdclk_squash_program(dev_priv, 0);
>
> icl_cdclk_pll_update(dev_priv, vco);
> - } else
> + } else {
> bxt_cdclk_pll_update(dev_priv, vco);
> + }
>
> if (HAS_CDCLK_SQUASH(dev_priv)) {
> u16 waveform = cdclk_squash_waveform(dev_priv, cdclk);
> --
> 2.44.2
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/6] drm/i915/power: Convert low level DC state code to intel_display
2024-09-06 14:33 ` [PATCH 3/6] drm/i915/power: Convert low level DC state " Ville Syrjala
@ 2024-09-06 15:10 ` Rodrigo Vivi
0 siblings, 0 replies; 23+ messages in thread
From: Rodrigo Vivi @ 2024-09-06 15:10 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx, intel-xe
On Fri, Sep 06, 2024 at 05:33:03PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> struct intel_display will replace struct drm_i915_private as
> the main thing for display code. Convert the lower level
> DC state code to use it (as much as possible at this stage).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 41 ++--
> .../i915/display/intel_display_power_well.c | 199 ++++++++++--------
> .../i915/display/intel_display_power_well.h | 15 +-
> 3 files changed, 139 insertions(+), 116 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index eb3e2a56af1d..86ac494ed33b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1421,7 +1421,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
> struct i915_power_domains *power_domains = &display->power.domains;
> struct i915_power_well *well;
>
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> + gen9_set_dc_state(display, DC_STATE_DISABLE);
>
> /* enable PCH reset handshake */
> intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
> @@ -1457,7 +1457,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - gen9_disable_dc_states(dev_priv);
> + gen9_disable_dc_states(display);
> /* TODO: disable DMC program */
>
> gen9_dbuf_disable(dev_priv);
> @@ -1489,7 +1489,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
> struct i915_power_domains *power_domains = &display->power.domains;
> struct i915_power_well *well;
>
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> + gen9_set_dc_state(display, DC_STATE_DISABLE);
>
> /*
> * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
> @@ -1527,7 +1527,7 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - gen9_disable_dc_states(dev_priv);
> + gen9_disable_dc_states(display);
> /* TODO: disable DMC program */
>
> gen9_dbuf_disable(dev_priv);
> @@ -1632,7 +1632,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> struct i915_power_domains *power_domains = &display->power.domains;
> struct i915_power_well *well;
>
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> + gen9_set_dc_state(display, DC_STATE_DISABLE);
>
> /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> @@ -1717,7 +1717,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - gen9_disable_dc_states(dev_priv);
> + gen9_disable_dc_states(display);
> intel_dmc_disable_program(dev_priv);
>
> /* 1. Disable all display engine functions -> aready done */
> @@ -2232,9 +2232,11 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
>
> void intel_display_power_suspend_late(struct drm_i915_private *i915)
> {
> + struct intel_display *display = &i915->display;
> +
> if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
> IS_BROXTON(i915)) {
> - bxt_enable_dc9(i915);
> + bxt_enable_dc9(display);
> } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> hsw_enable_pc8(i915);
> }
> @@ -2246,10 +2248,12 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915)
>
> void intel_display_power_resume_early(struct drm_i915_private *i915)
> {
> + struct intel_display *display = &i915->display;
> +
> if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
> IS_BROXTON(i915)) {
> - gen9_sanitize_dc_state(i915);
> - bxt_disable_dc9(i915);
> + gen9_sanitize_dc_state(display);
> + bxt_disable_dc9(display);
> } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> hsw_disable_pc8(i915);
> }
> @@ -2261,12 +2265,14 @@ void intel_display_power_resume_early(struct drm_i915_private *i915)
>
> void intel_display_power_suspend(struct drm_i915_private *i915)
> {
> + struct intel_display *display = &i915->display;
> +
> if (DISPLAY_VER(i915) >= 11) {
> icl_display_core_uninit(i915);
> - bxt_enable_dc9(i915);
> + bxt_enable_dc9(display);
> } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
> bxt_display_core_uninit(i915);
> - bxt_enable_dc9(i915);
> + bxt_enable_dc9(display);
> } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> hsw_enable_pc8(i915);
> }
> @@ -2274,23 +2280,24 @@ void intel_display_power_suspend(struct drm_i915_private *i915)
>
> void intel_display_power_resume(struct drm_i915_private *i915)
> {
> - struct i915_power_domains *power_domains = &i915->display.power.domains;
> + struct intel_display *display = &i915->display;
> + struct i915_power_domains *power_domains = &display->power.domains;
>
> if (DISPLAY_VER(i915) >= 11) {
> - bxt_disable_dc9(i915);
> + bxt_disable_dc9(display);
> icl_display_core_init(i915, true);
> if (intel_dmc_has_payload(i915)) {
> if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
> - skl_enable_dc6(i915);
> + skl_enable_dc6(display);
> else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
> - gen9_enable_dc5(i915);
> + gen9_enable_dc5(display);
> }
> } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
> - bxt_disable_dc9(i915);
> + bxt_disable_dc9(display);
> bxt_display_core_init(i915, true);
> if (intel_dmc_has_payload(i915) &&
> (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
> - gen9_enable_dc5(i915);
> + gen9_enable_dc5(display);
> } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> hsw_disable_pc8(i915);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 7b40a5b88214..1f0084ca6248 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -601,20 +601,22 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
> return (val & mask) == mask;
> }
>
> -static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
> +static void assert_can_enable_dc9(struct intel_display *display)
> {
> - drm_WARN_ONCE(&dev_priv->drm,
> - (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9),
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> + drm_WARN_ONCE(display->drm,
> + (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9),
> "DC9 already programmed to be enabled.\n");
> - drm_WARN_ONCE(&dev_priv->drm,
> - intel_de_read(dev_priv, DC_STATE_EN) &
> + drm_WARN_ONCE(display->drm,
> + intel_de_read(display, DC_STATE_EN) &
> DC_STATE_EN_UPTO_DC5,
> "DC5 still not disabled to enable DC9.\n");
> - drm_WARN_ONCE(&dev_priv->drm,
> - intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) &
> + drm_WARN_ONCE(display->drm,
> + intel_de_read(display, HSW_PWR_WELL_CTL2) &
> HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),
> "Power well 2 on.\n");
> - drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
> + drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv),
> "Interrupts not disabled yet.\n");
>
> /*
> @@ -626,12 +628,14 @@ static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
> */
> }
>
> -static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
> +static void assert_can_disable_dc9(struct intel_display *display)
> {
> - drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> + drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv),
> "Interrupts not disabled yet.\n");
> - drm_WARN_ONCE(&dev_priv->drm,
> - intel_de_read(dev_priv, DC_STATE_EN) &
> + drm_WARN_ONCE(display->drm,
> + intel_de_read(display, DC_STATE_EN) &
> DC_STATE_EN_UPTO_DC5,
> "DC5 still not disabled.\n");
>
> @@ -644,14 +648,14 @@ static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
> */
> }
>
> -static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
> +static void gen9_write_dc_state(struct intel_display *display,
> u32 state)
> {
> int rewrites = 0;
> int rereads = 0;
> u32 v;
>
> - intel_de_write(dev_priv, DC_STATE_EN, state);
> + intel_de_write(display, DC_STATE_EN, state);
>
> /* It has been observed that disabling the dc6 state sometimes
> * doesn't stick and dmc keeps returning old value. Make sure
> @@ -659,10 +663,10 @@ static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
> * we are confident that state is exactly what we want.
> */
> do {
> - v = intel_de_read(dev_priv, DC_STATE_EN);
> + v = intel_de_read(display, DC_STATE_EN);
>
> if (v != state) {
> - intel_de_write(dev_priv, DC_STATE_EN, state);
> + intel_de_write(display, DC_STATE_EN, state);
> rewrites++;
> rereads = 0;
> } else if (rereads++ > 5) {
> @@ -672,27 +676,28 @@ static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
> } while (rewrites < 100);
>
> if (v != state)
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "Writing dc state to 0x%x failed, now 0x%x\n",
> state, v);
>
> /* Most of the times we need one retry, avoid spam */
> if (rewrites > 1)
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Rewrote dc state to 0x%x %d times\n",
> state, rewrites);
> }
>
> -static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
> +static u32 gen9_dc_mask(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 mask;
>
> mask = DC_STATE_EN_UPTO_DC5;
>
> - if (DISPLAY_VER(dev_priv) >= 12)
> + if (DISPLAY_VER(display) >= 12)
> mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
> | DC_STATE_EN_DC9;
> - else if (DISPLAY_VER(dev_priv) == 11)
> + else if (DISPLAY_VER(display) == 11)
> mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
> else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> mask |= DC_STATE_EN_DC9;
> @@ -702,17 +707,17 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
> return mask;
> }
>
> -void gen9_sanitize_dc_state(struct drm_i915_private *i915)
> +void gen9_sanitize_dc_state(struct intel_display *display)
> {
> - struct i915_power_domains *power_domains = &i915->display.power.domains;
> + struct i915_power_domains *power_domains = &display->power.domains;
> u32 val;
>
> - if (!HAS_DISPLAY(i915))
> + if (!HAS_DISPLAY(display))
> return;
>
> - val = intel_de_read(i915, DC_STATE_EN) & gen9_dc_mask(i915);
> + val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display);
>
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "Resetting DC state tracking from %02x to %02x\n",
> power_domains->dc_state, val);
> power_domains->dc_state = val;
> @@ -720,7 +725,7 @@ void gen9_sanitize_dc_state(struct drm_i915_private *i915)
>
> /**
> * gen9_set_dc_state - set target display C power state
> - * @dev_priv: i915 device instance
> + * @display: display instance
> * @state: target DC power state
> * - DC_STATE_DISABLE
> * - DC_STATE_EN_UPTO_DC5
> @@ -741,70 +746,71 @@ void gen9_sanitize_dc_state(struct drm_i915_private *i915)
> * back on and register state is restored. This is guaranteed by the MMIO write
> * to DC_STATE_EN blocking until the state is restored.
> */
> -void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
> +void gen9_set_dc_state(struct intel_display *display, u32 state)
> {
> - struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
> + struct i915_power_domains *power_domains = &display->power.domains;
> u32 val;
> u32 mask;
>
> - if (!HAS_DISPLAY(dev_priv))
> + if (!HAS_DISPLAY(display))
> return;
>
> - if (drm_WARN_ON_ONCE(&dev_priv->drm,
> + if (drm_WARN_ON_ONCE(display->drm,
> state & ~power_domains->allowed_dc_mask))
> state &= power_domains->allowed_dc_mask;
>
> - val = intel_de_read(dev_priv, DC_STATE_EN);
> - mask = gen9_dc_mask(dev_priv);
> - drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to %02x\n",
> + val = intel_de_read(display, DC_STATE_EN);
> + mask = gen9_dc_mask(display);
> + drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n",
> val & mask, state);
>
> /* Check if DMC is ignoring our DC state requests */
> if ((val & mask) != power_domains->dc_state)
> - drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
> + drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
> power_domains->dc_state, val & mask);
>
> val &= ~mask;
> val |= state;
>
> - gen9_write_dc_state(dev_priv, val);
> + gen9_write_dc_state(display, val);
>
> power_domains->dc_state = val & mask;
> }
>
> -static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
> +static void tgl_enable_dc3co(struct intel_display *display)
> {
> - drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n");
> - gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
> + drm_dbg_kms(display->drm, "Enabling DC3CO\n");
> + gen9_set_dc_state(display, DC_STATE_EN_DC3CO);
> }
>
> -static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)
> +static void tgl_disable_dc3co(struct intel_display *display)
> {
> - drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n");
> - intel_de_rmw(dev_priv, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0);
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> + drm_dbg_kms(display->drm, "Disabling DC3CO\n");
> + intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0);
> + gen9_set_dc_state(display, DC_STATE_DISABLE);
> /*
> * Delay of 200us DC3CO Exit time B.Spec 49196
> */
> usleep_range(200, 210);
> }
>
> -static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
> +static void assert_can_enable_dc5(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> enum i915_power_well_id high_pg;
>
> /* Power wells at this level and above must be disabled for DC5 entry */
> - if (DISPLAY_VER(dev_priv) == 12)
> + if (DISPLAY_VER(display) == 12)
> high_pg = ICL_DISP_PW_3;
> else
> high_pg = SKL_DISP_PW_2;
>
> - drm_WARN_ONCE(&dev_priv->drm,
> + drm_WARN_ONCE(display->drm,
> intel_display_power_well_is_enabled(dev_priv, high_pg),
> "Power wells above platform's DC5 limit still enabled.\n");
>
> - drm_WARN_ONCE(&dev_priv->drm,
> - (intel_de_read(dev_priv, DC_STATE_EN) &
> + drm_WARN_ONCE(display->drm,
> + (intel_de_read(display, DC_STATE_EN) &
> DC_STATE_EN_UPTO_DC5),
> "DC5 already programmed to be enabled.\n");
> assert_rpm_wakelock_held(&dev_priv->runtime_pm);
> @@ -812,60 +818,66 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
> assert_dmc_loaded(dev_priv);
> }
>
> -void gen9_enable_dc5(struct drm_i915_private *dev_priv)
> +void gen9_enable_dc5(struct intel_display *display)
> {
> - assert_can_enable_dc5(dev_priv);
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
>
> - drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n");
> + assert_can_enable_dc5(display);
> +
> + drm_dbg_kms(display->drm, "Enabling DC5\n");
>
> /* Wa Display #1183: skl,kbl,cfl */
> - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
> - intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> + if (DISPLAY_VER(display) == 9 && !IS_BROXTON(dev_priv))
> + intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,
> 0, SKL_SELECT_ALTERNATE_DC_EXIT);
>
> - intel_dmc_wl_enable(&dev_priv->display);
> + intel_dmc_wl_enable(display);
>
> - gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> + gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5);
> }
>
> -static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
> +static void assert_can_enable_dc6(struct intel_display *display)
> {
> - drm_WARN_ONCE(&dev_priv->drm,
> - (intel_de_read(dev_priv, UTIL_PIN_CTL) &
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> + drm_WARN_ONCE(display->drm,
> + (intel_de_read(display, UTIL_PIN_CTL) &
> (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) ==
> (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),
> "Utility pin enabled in PWM mode\n");
> - drm_WARN_ONCE(&dev_priv->drm,
> - (intel_de_read(dev_priv, DC_STATE_EN) &
> + drm_WARN_ONCE(display->drm,
> + (intel_de_read(display, DC_STATE_EN) &
> DC_STATE_EN_UPTO_DC6),
> "DC6 already programmed to be enabled.\n");
>
> assert_dmc_loaded(dev_priv);
> }
>
> -void skl_enable_dc6(struct drm_i915_private *dev_priv)
> +void skl_enable_dc6(struct intel_display *display)
> {
> - assert_can_enable_dc6(dev_priv);
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
>
> - drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n");
> + assert_can_enable_dc6(display);
> +
> + drm_dbg_kms(display->drm, "Enabling DC6\n");
>
> /* Wa Display #1183: skl,kbl,cfl */
> - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
> - intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> + if (DISPLAY_VER(display) == 9 && !IS_BROXTON(dev_priv))
> + intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,
> 0, SKL_SELECT_ALTERNATE_DC_EXIT);
>
> - intel_dmc_wl_enable(&dev_priv->display);
> + intel_dmc_wl_enable(display);
>
> - gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
> + gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
> }
>
> -void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> +void bxt_enable_dc9(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
>
> - assert_can_enable_dc9(dev_priv);
> + assert_can_enable_dc9(display);
>
> - drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n");
> + drm_dbg_kms(display->drm, "Enabling DC9\n");
> /*
> * Power sequencer reset is not needed on
> * platforms with South Display Engine on PCH,
> @@ -873,18 +885,16 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> */
> if (!HAS_PCH_SPLIT(dev_priv))
> intel_pps_reset_all(display);
> - gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
> + gen9_set_dc_state(display, DC_STATE_EN_DC9);
> }
>
> -void bxt_disable_dc9(struct drm_i915_private *dev_priv)
> +void bxt_disable_dc9(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> + assert_can_disable_dc9(display);
>
> - assert_can_disable_dc9(dev_priv);
> + drm_dbg_kms(display->drm, "Disabling DC9\n");
>
> - drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n");
> -
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> + gen9_set_dc_state(display, DC_STATE_DISABLE);
>
> intel_pps_unlock_regs_wa(display);
> }
> @@ -949,8 +959,10 @@ static void bxt_verify_dpio_phy_power_wells(struct drm_i915_private *dev_priv)
> static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - return ((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
> - (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
> + struct intel_display *display = &dev_priv->display;
> +
> + return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
> + (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
> }
>
> static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
> @@ -965,23 +977,23 @@ static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
> enabled_dbuf_slices);
> }
>
> -void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
> +void gen9_disable_dc_states(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct i915_power_domains *power_domains = &display->power.domains;
> struct intel_cdclk_config cdclk_config = {};
>
> if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) {
> - tgl_disable_dc3co(dev_priv);
> + tgl_disable_dc3co(display);
> return;
> }
>
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> + gen9_set_dc_state(display, DC_STATE_DISABLE);
>
> - if (!HAS_DISPLAY(dev_priv))
> + if (!HAS_DISPLAY(display))
> return;
>
> - intel_dmc_wl_disable(&dev_priv->display);
> + intel_dmc_wl_disable(display);
>
> intel_cdclk_get_cdclk(display, &cdclk_config);
> /* Can't read out voltage_level so can't use intel_cdclk_changed() */
> @@ -994,7 +1006,7 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> bxt_verify_dpio_phy_power_wells(dev_priv);
>
> - if (DISPLAY_VER(dev_priv) >= 11)
> + if (DISPLAY_VER(display) >= 11)
> /*
> * DMC retains HW context only for port A, the other combo
> * PHY's HW context for port B is lost after DC transitions,
> @@ -1006,26 +1018,29 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
> static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - gen9_disable_dc_states(dev_priv);
> + struct intel_display *display = &dev_priv->display;
> +
> + gen9_disable_dc_states(display);
> }
>
> static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
> + struct intel_display *display = &dev_priv->display;
> + struct i915_power_domains *power_domains = &display->power.domains;
>
> if (!intel_dmc_has_payload(dev_priv))
> return;
>
> switch (power_domains->target_dc_state) {
> case DC_STATE_EN_DC3CO:
> - tgl_enable_dc3co(dev_priv);
> + tgl_enable_dc3co(display);
> break;
> case DC_STATE_EN_UPTO_DC6:
> - skl_enable_dc6(dev_priv);
> + skl_enable_dc6(display);
> break;
> case DC_STATE_EN_UPTO_DC5:
> - gen9_enable_dc5(dev_priv);
> + gen9_enable_dc5(display);
> break;
> }
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> index 9357a9a73c06..93559f7c6100 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> @@ -12,6 +12,7 @@
>
> struct drm_i915_private;
> struct i915_power_well_ops;
> +struct intel_display;
> struct intel_encoder;
>
> #define for_each_power_well(__dev_priv, __power_well) \
> @@ -154,13 +155,13 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
> bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> enum dpio_channel ch, bool override);
>
> -void gen9_enable_dc5(struct drm_i915_private *dev_priv);
> -void skl_enable_dc6(struct drm_i915_private *dev_priv);
> -void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
> -void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state);
> -void gen9_disable_dc_states(struct drm_i915_private *dev_priv);
> -void bxt_enable_dc9(struct drm_i915_private *dev_priv);
> -void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> +void gen9_enable_dc5(struct intel_display *display);
> +void skl_enable_dc6(struct intel_display *display);
> +void gen9_sanitize_dc_state(struct intel_display *display);
> +void gen9_set_dc_state(struct intel_display *display, u32 state);
> +void gen9_disable_dc_states(struct intel_display *display);
> +void bxt_enable_dc9(struct intel_display *display);
> +void bxt_disable_dc9(struct intel_display *display);
>
> extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
> extern const struct i915_power_well_ops chv_pipe_power_well_ops;
> --
> 2.44.2
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 4/6] drm/i915/vga: Convert VGA code to intel_display
2024-09-06 14:33 ` [PATCH 4/6] drm/i915/vga: Convert VGA " Ville Syrjala
@ 2024-09-06 15:12 ` Rodrigo Vivi
0 siblings, 0 replies; 23+ messages in thread
From: Rodrigo Vivi @ 2024-09-06 15:12 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx, intel-xe
On Fri, Sep 06, 2024 at 05:33:04PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> struct intel_display will replace struct drm_i915_private as
> the main thing for display code. Convert the VGA code to
> use it (as much as possible at this stage).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> .../drm/i915/display/intel_display_driver.c | 11 ++---
> .../i915/display/intel_display_power_well.c | 6 ++-
> drivers/gpu/drm/i915/display/intel_vga.c | 45 ++++++++++---------
> drivers/gpu/drm/i915/display/intel_vga.h | 14 +++---
> drivers/gpu/drm/i915/i915_suspend.c | 3 +-
> 5 files changed, 43 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 434e52f450ff..f8da72af2107 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -221,7 +221,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
>
> intel_bios_init(display);
>
> - ret = intel_vga_register(i915);
> + ret = intel_vga_register(display);
> if (ret)
> goto cleanup_bios;
>
> @@ -275,7 +275,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
> intel_dmc_fini(i915);
> intel_power_domains_driver_remove(i915);
> cleanup_vga:
> - intel_vga_unregister(i915);
> + intel_vga_unregister(display);
> cleanup_bios:
> intel_bios_driver_remove(display);
>
> @@ -458,7 +458,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
> intel_hti_init(display);
>
> /* Just disable it once at startup */
> - intel_vga_disable(i915);
> + intel_vga_disable(display);
> intel_setup_outputs(i915);
>
> ret = intel_dp_tunnel_mgr_init(display);
> @@ -625,7 +625,7 @@ void intel_display_driver_remove_nogem(struct drm_i915_private *i915)
>
> intel_power_domains_driver_remove(i915);
>
> - intel_vga_unregister(i915);
> + intel_vga_unregister(display);
>
> intel_bios_driver_remove(display);
> }
> @@ -683,12 +683,13 @@ __intel_display_driver_resume(struct drm_i915_private *i915,
> struct drm_atomic_state *state,
> struct drm_modeset_acquire_ctx *ctx)
> {
> + struct intel_display *display = &i915->display;
> struct drm_crtc_state *crtc_state;
> struct drm_crtc *crtc;
> int ret, i;
>
> intel_modeset_setup_hw_state(i915, ctx);
> - intel_vga_redisable(i915);
> + intel_vga_redisable(display);
>
> if (!state)
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 1f0084ca6248..a5d9b17e03a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -187,8 +187,10 @@ int intel_power_well_refcount(struct i915_power_well *power_well)
> static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
> u8 irq_pipe_mask, bool has_vga)
> {
> + struct intel_display *display = &dev_priv->display;
I was going to say that it would be probably good to replace the function argument..
> +
> if (has_vga)
> - intel_vga_reset_io_mem(dev_priv);
> + intel_vga_reset_io_mem(display);
>
> if (irq_pipe_mask)
> gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
but then I noticed it is still used internally...
but anyway, I believe it is already a step towards the right direction and we replace
the inner cases as we go...
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> @@ -1248,7 +1250,7 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
> intel_crt_reset(&encoder->base);
> }
>
> - intel_vga_redisable_power_on(dev_priv);
> + intel_vga_redisable_power_on(display);
>
> intel_pps_unlock_regs_wa(display);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
> index 0b5916c15307..2c76a0176a35 100644
> --- a/drivers/gpu/drm/i915/display/intel_vga.c
> +++ b/drivers/gpu/drm/i915/display/intel_vga.c
> @@ -14,24 +14,26 @@
> #include "intel_de.h"
> #include "intel_vga.h"
>
> -static i915_reg_t intel_vga_cntrl_reg(struct drm_i915_private *i915)
> +static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> return VLV_VGACNTRL;
> - else if (DISPLAY_VER(i915) >= 5)
> + else if (DISPLAY_VER(display) >= 5)
> return CPU_VGACNTRL;
> else
> return VGACNTRL;
> }
>
> /* Disable the VGA plane that we never use */
> -void intel_vga_disable(struct drm_i915_private *dev_priv)
> +void intel_vga_disable(struct intel_display *display)
> {
> - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> - i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv);
> + struct pci_dev *pdev = to_pci_dev(display->drm->dev);
> + i915_reg_t vga_reg = intel_vga_cntrl_reg(display);
> u8 sr1;
>
> - if (intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE)
> + if (intel_de_read(display, vga_reg) & VGA_DISP_DISABLE)
> return;
>
> /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
> @@ -42,23 +44,24 @@ void intel_vga_disable(struct drm_i915_private *dev_priv)
> vga_put(pdev, VGA_RSRC_LEGACY_IO);
> udelay(300);
>
> - intel_de_write(dev_priv, vga_reg, VGA_DISP_DISABLE);
> - intel_de_posting_read(dev_priv, vga_reg);
> + intel_de_write(display, vga_reg, VGA_DISP_DISABLE);
> + intel_de_posting_read(display, vga_reg);
> }
>
> -void intel_vga_redisable_power_on(struct drm_i915_private *dev_priv)
> +void intel_vga_redisable_power_on(struct intel_display *display)
> {
> - i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv);
> + i915_reg_t vga_reg = intel_vga_cntrl_reg(display);
>
> - if (!(intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE)) {
> - drm_dbg_kms(&dev_priv->drm,
> + if (!(intel_de_read(display, vga_reg) & VGA_DISP_DISABLE)) {
> + drm_dbg_kms(display->drm,
> "Something enabled VGA plane, disabling it\n");
> - intel_vga_disable(dev_priv);
> + intel_vga_disable(display);
> }
> }
>
> -void intel_vga_redisable(struct drm_i915_private *i915)
> +void intel_vga_redisable(struct intel_display *display)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> intel_wakeref_t wakeref;
>
> /*
> @@ -74,14 +77,14 @@ void intel_vga_redisable(struct drm_i915_private *i915)
> if (!wakeref)
> return;
>
> - intel_vga_redisable_power_on(i915);
> + intel_vga_redisable_power_on(display);
>
> intel_display_power_put(i915, POWER_DOMAIN_VGA, wakeref);
> }
>
> -void intel_vga_reset_io_mem(struct drm_i915_private *i915)
> +void intel_vga_reset_io_mem(struct intel_display *display)
> {
> - struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + struct pci_dev *pdev = to_pci_dev(display->drm->dev);
>
> /*
> * After we re-enable the power well, if we touch VGA register 0x3d5
> @@ -98,10 +101,10 @@ void intel_vga_reset_io_mem(struct drm_i915_private *i915)
> vga_put(pdev, VGA_RSRC_LEGACY_IO);
> }
>
> -int intel_vga_register(struct drm_i915_private *i915)
> +int intel_vga_register(struct intel_display *display)
> {
>
> - struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + struct pci_dev *pdev = to_pci_dev(display->drm->dev);
> int ret;
>
> /*
> @@ -119,9 +122,9 @@ int intel_vga_register(struct drm_i915_private *i915)
> return 0;
> }
>
> -void intel_vga_unregister(struct drm_i915_private *i915)
> +void intel_vga_unregister(struct intel_display *display)
> {
> - struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + struct pci_dev *pdev = to_pci_dev(display->drm->dev);
>
> vga_client_unregister(pdev);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_vga.h b/drivers/gpu/drm/i915/display/intel_vga.h
> index ba5b55b917f0..824dfc32a199 100644
> --- a/drivers/gpu/drm/i915/display/intel_vga.h
> +++ b/drivers/gpu/drm/i915/display/intel_vga.h
> @@ -6,13 +6,13 @@
> #ifndef __INTEL_VGA_H__
> #define __INTEL_VGA_H__
>
> -struct drm_i915_private;
> +struct intel_display;
>
> -void intel_vga_reset_io_mem(struct drm_i915_private *i915);
> -void intel_vga_disable(struct drm_i915_private *i915);
> -void intel_vga_redisable(struct drm_i915_private *i915);
> -void intel_vga_redisable_power_on(struct drm_i915_private *i915);
> -int intel_vga_register(struct drm_i915_private *i915);
> -void intel_vga_unregister(struct drm_i915_private *i915);
> +void intel_vga_reset_io_mem(struct intel_display *display);
> +void intel_vga_disable(struct intel_display *display);
> +void intel_vga_redisable(struct intel_display *display);
> +void intel_vga_redisable_power_on(struct intel_display *display);
> +int intel_vga_register(struct intel_display *display);
> +void intel_vga_unregister(struct intel_display *display);
>
> #endif /* __INTEL_VGA_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index f8373a461f17..9d3d9b983032 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -118,6 +118,7 @@ void i915_save_display(struct drm_i915_private *dev_priv)
>
> void i915_restore_display(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
>
> if (!HAS_DISPLAY(dev_priv))
> @@ -134,7 +135,7 @@ void i915_restore_display(struct drm_i915_private *dev_priv)
> intel_de_write(dev_priv, DSPARB(dev_priv),
> dev_priv->regfile.saveDSPARB);
>
> - intel_vga_redisable(dev_priv);
> + intel_vga_redisable(display);
>
> intel_gmbus_reset(dev_priv);
> }
> --
> 2.44.2
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 5/6] drm/i915/power: Convert "i830 power well" code to intel_display
2024-09-06 14:33 ` [PATCH 5/6] drm/i915/power: Convert "i830 power well" " Ville Syrjala
@ 2024-09-06 15:13 ` Rodrigo Vivi
0 siblings, 0 replies; 23+ messages in thread
From: Rodrigo Vivi @ 2024-09-06 15:13 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx, intel-xe
On Fri, Sep 06, 2024 at 05:33:05PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> struct intel_display will replace struct drm_i915_private as
> the main thing for display code. Convert the "i830 power well"
> code to use it (as much as possible at this stage).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 79 +++++++++----------
> drivers/gpu/drm/i915/display/intel_display.h | 5 +-
> .../i915/display/intel_display_power_well.c | 22 ++++--
> 3 files changed, 56 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b4ec9bf12aa7..0ec78b06ca80 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2226,9 +2226,10 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> static void i9xx_crtc_disable(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> + struct intel_display *display = to_intel_display(state);
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct intel_crtc_state *old_crtc_state =
> intel_atomic_get_old_crtc_state(state, crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> /*
> @@ -2267,7 +2268,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
>
> /* clock the pipe down to 640x480@60 to potentially save power */
> if (IS_I830(dev_priv))
> - i830_enable_pipe(dev_priv, pipe);
> + i830_enable_pipe(display, pipe);
> }
>
> void intel_encoder_destroy(struct drm_encoder *encoder)
> @@ -8257,9 +8258,8 @@ int intel_initial_commit(struct drm_device *dev)
> return ret;
> }
>
> -void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> +void i830_enable_pipe(struct intel_display *display, enum pipe pipe)
> {
> - struct intel_display *display = &dev_priv->display;
> struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
> enum transcoder cpu_transcoder = (enum transcoder)pipe;
> /* 640x480@60Hz, ~25175 kHz */
> @@ -8273,10 +8273,10 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> u32 dpll, fp;
> int i;
>
> - drm_WARN_ON(&dev_priv->drm,
> + drm_WARN_ON(display->drm,
> i9xx_calc_dpll_params(48000, &clock) != 25154);
>
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
> pipe_name(pipe), clock.vco, clock.dot);
>
> @@ -8288,35 +8288,35 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> PLL_REF_INPUT_DREFCLK |
> DPLL_VCO_ENABLE;
>
> - intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
> HACTIVE(640 - 1) | HTOTAL(800 - 1));
> - intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
> HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
> - intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
> HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
> - intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> VACTIVE(480 - 1) | VTOTAL(525 - 1));
> - intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
> VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
> - intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
> VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
> - intel_de_write(dev_priv, PIPESRC(dev_priv, pipe),
> + intel_de_write(display, PIPESRC(display, pipe),
> PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
>
> - intel_de_write(dev_priv, FP0(pipe), fp);
> - intel_de_write(dev_priv, FP1(pipe), fp);
> + intel_de_write(display, FP0(pipe), fp);
> + intel_de_write(display, FP1(pipe), fp);
>
> /*
> * Apparently we need to have VGA mode enabled prior to changing
> * the P1/P2 dividers. Otherwise the DPLL will keep using the old
> * dividers, even though the register value does change.
> */
> - intel_de_write(dev_priv, DPLL(dev_priv, pipe),
> + intel_de_write(display, DPLL(display, pipe),
> dpll & ~DPLL_VGA_MODE_DIS);
> - intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
> + intel_de_write(display, DPLL(display, pipe), dpll);
>
> /* Wait for the clocks to stabilize. */
> - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
> + intel_de_posting_read(display, DPLL(display, pipe));
> udelay(150);
>
> /* The pixel multiplier can only be updated once the
> @@ -8324,47 +8324,46 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> *
> * So write it again.
> */
> - intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
> + intel_de_write(display, DPLL(display, pipe), dpll);
>
> /* We do this three times for luck */
> for (i = 0; i < 3 ; i++) {
> - intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
> - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
> + intel_de_write(display, DPLL(display, pipe), dpll);
> + intel_de_posting_read(display, DPLL(display, pipe));
> udelay(150); /* wait for warmup */
> }
>
> - intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), TRANSCONF_ENABLE);
> - intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe));
> + intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE);
> + intel_de_posting_read(display, TRANSCONF(display, pipe));
>
> intel_wait_for_pipe_scanline_moving(crtc);
> }
>
> -void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> +void i830_disable_pipe(struct intel_display *display, enum pipe pipe)
> {
> - struct intel_display *display = &dev_priv->display;
> struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
>
> - drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
> + drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n",
> pipe_name(pipe));
>
> - drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_A)) & DISP_ENABLE);
> - drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_B)) & DISP_ENABLE);
> - drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_C)) & DISP_ENABLE);
> - drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & MCURSOR_MODE_MASK);
> - drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_B)) & MCURSOR_MODE_MASK);
> + drm_WARN_ON(display->drm,
> + intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE);
> + drm_WARN_ON(display->drm,
> + intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE);
> + drm_WARN_ON(display->drm,
> + intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE);
> + drm_WARN_ON(display->drm,
> + intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK);
> + drm_WARN_ON(display->drm,
> + intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK);
>
> - intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), 0);
> - intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe));
> + intel_de_write(display, TRANSCONF(display, pipe), 0);
> + intel_de_posting_read(display, TRANSCONF(display, pipe));
>
> intel_wait_for_pipe_scanline_stopped(crtc);
>
> - intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS);
> - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
> + intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);
> + intel_de_posting_read(display, DPLL(display, pipe));
> }
>
> void intel_hpd_poll_fini(struct drm_i915_private *i915)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index b21d9578d5db..7ca26e5cb20e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -52,6 +52,7 @@ struct intel_atomic_state;
> struct intel_crtc;
> struct intel_crtc_state;
> struct intel_digital_port;
> +struct intel_display;
> struct intel_dp;
> struct intel_encoder;
> struct intel_initial_plane_config;
> @@ -437,8 +438,8 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
> void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
> void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
> void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
> -void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
> -void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
> +void i830_enable_pipe(struct intel_display *display, enum pipe pipe);
> +void i830_disable_pipe(struct intel_display *display, enum pipe pipe);
> int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
> int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
> const char *name, u32 reg, int ref_freq);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index a5d9b17e03a2..9f275a6674a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1066,24 +1066,30 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
> static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0)
> - i830_enable_pipe(dev_priv, PIPE_A);
> - if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0)
> - i830_enable_pipe(dev_priv, PIPE_B);
> + struct intel_display *display = &dev_priv->display;
> +
> + if ((intel_de_read(display, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0)
> + i830_enable_pipe(display, PIPE_A);
> + if ((intel_de_read(display, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0)
> + i830_enable_pipe(display, PIPE_B);
> }
>
> static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - i830_disable_pipe(dev_priv, PIPE_B);
> - i830_disable_pipe(dev_priv, PIPE_A);
> + struct intel_display *display = &dev_priv->display;
> +
> + i830_disable_pipe(display, PIPE_B);
> + i830_disable_pipe(display, PIPE_A);
> }
>
> static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - return intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE &&
> - intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE;
> + struct intel_display *display = &dev_priv->display;
> +
> + return intel_de_read(display, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE &&
> + intel_de_read(display, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE;
> }
>
> static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
> --
> 2.44.2
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 6/6] drm/i915/dmc: Convert DMC code to intel_display
2024-09-06 14:33 ` [PATCH 6/6] drm/i915/dmc: Convert DMC " Ville Syrjala
@ 2024-09-06 15:16 ` Rodrigo Vivi
0 siblings, 0 replies; 23+ messages in thread
From: Rodrigo Vivi @ 2024-09-06 15:16 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx, intel-xe
On Fri, Sep 06, 2024 at 05:33:06PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> struct intel_display will replace struct drm_i915_private as
> the main thing for display code. Convert the DMC code to
> use it (as much as possible at this stage).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 7 +-
> .../drm/i915/display/intel_display_debugfs.c | 2 +-
> .../drm/i915/display/intel_display_driver.c | 6 +-
> .../drm/i915/display/intel_display_power.c | 17 +-
> .../i915/display/intel_display_power_well.c | 8 +-
> drivers/gpu/drm/i915/display/intel_dmc.c | 391 +++++++++---------
> drivers/gpu/drm/i915/display/intel_dmc.h | 26 +-
> drivers/gpu/drm/i915/display/intel_dmc_wl.c | 4 +-
> .../drm/i915/display/intel_modeset_setup.c | 3 +-
> drivers/gpu/drm/i915/i915_driver.c | 6 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> drivers/gpu/drm/xe/display/xe_display.c | 4 +-
> 12 files changed, 243 insertions(+), 233 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0ec78b06ca80..fdf244a32b24 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1690,7 +1690,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
>
> for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
> intel_crtc_joined_pipe_mask(new_crtc_state))
> - intel_dmc_enable_pipe(dev_priv, pipe_crtc->pipe);
> + intel_dmc_enable_pipe(display, pipe_crtc->pipe);
>
> intel_encoders_pre_pll_enable(state, crtc);
>
> @@ -1843,9 +1843,10 @@ static void ilk_crtc_disable(struct intel_atomic_state *state,
> static void hsw_crtc_disable(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> + struct intel_display *display = to_intel_display(state);
> + struct drm_i915_private *i915 = to_i915(display->drm);
> const struct intel_crtc_state *old_crtc_state =
> intel_atomic_get_old_crtc_state(state, crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> struct intel_crtc *pipe_crtc;
>
> /*
> @@ -1867,7 +1868,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
>
> for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc,
> intel_crtc_joined_pipe_mask(old_crtc_state))
> - intel_dmc_disable_pipe(i915, pipe_crtc->pipe);
> + intel_dmc_disable_pipe(display, pipe_crtc->pipe);
> }
>
> static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index c1bef34d1ffd..b75361e95e97 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1069,7 +1069,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
>
> intel_bios_debugfs_register(display);
> intel_cdclk_debugfs_register(display);
> - intel_dmc_debugfs_register(i915);
> + intel_dmc_debugfs_register(display);
> intel_fbc_debugfs_register(display);
> intel_hpd_debugfs_register(i915);
> intel_opregion_debugfs_register(display);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index f8da72af2107..c106fb2dd20b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -237,7 +237,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
> if (!HAS_DISPLAY(i915))
> return 0;
>
> - intel_dmc_init(i915);
> + intel_dmc_init(display);
>
> i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0);
> i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI |
> @@ -272,7 +272,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
> return 0;
>
> cleanup_vga_client_pw_domain_dmc:
> - intel_dmc_fini(i915);
> + intel_dmc_fini(display);
> intel_power_domains_driver_remove(i915);
> cleanup_vga:
> intel_vga_unregister(display);
> @@ -621,7 +621,7 @@ void intel_display_driver_remove_nogem(struct drm_i915_private *i915)
> {
> struct intel_display *display = &i915->display;
>
> - intel_dmc_fini(i915);
> + intel_dmc_fini(display);
>
> intel_power_domains_driver_remove(i915);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 86ac494ed33b..ecabb674644b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1445,7 +1445,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
> gen9_dbuf_enable(dev_priv);
>
> if (resume)
> - intel_dmc_load_program(dev_priv);
> + intel_dmc_load_program(display);
> }
>
> static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
> @@ -1515,7 +1515,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
> gen9_dbuf_enable(dev_priv);
>
> if (resume)
> - intel_dmc_load_program(dev_priv);
> + intel_dmc_load_program(display);
> }
>
> static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
> @@ -1687,7 +1687,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1);
>
> if (resume)
> - intel_dmc_load_program(dev_priv);
> + intel_dmc_load_program(display);
>
> /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */
> if (IS_DISPLAY_VER_FULL(dev_priv, IP_VER(12, 0), IP_VER(13, 0)))
> @@ -1718,7 +1718,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
> return;
>
> gen9_disable_dc_states(display);
> - intel_dmc_disable_program(dev_priv);
> + intel_dmc_disable_program(display);
>
> /* 1. Disable all display engine functions -> aready done */
>
> @@ -2073,7 +2073,8 @@ void intel_power_domains_disable(struct drm_i915_private *i915)
> */
> void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle)
> {
> - struct i915_power_domains *power_domains = &i915->display.power.domains;
> + struct intel_display *display = &i915->display;
> + struct i915_power_domains *power_domains = &display->power.domains;
> intel_wakeref_t wakeref __maybe_unused =
> fetch_and_zero(&power_domains->init_wakeref);
>
> @@ -2087,7 +2088,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle)
> * that would be blocked if the firmware was inactive.
> */
> if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle &&
> - intel_dmc_has_payload(i915)) {
> + intel_dmc_has_payload(display)) {
> intel_display_power_flush_work(i915);
> intel_power_domains_verify_state(i915);
> return;
> @@ -2286,7 +2287,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
> if (DISPLAY_VER(i915) >= 11) {
> bxt_disable_dc9(display);
> icl_display_core_init(i915, true);
> - if (intel_dmc_has_payload(i915)) {
> + if (intel_dmc_has_payload(display)) {
> if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
> skl_enable_dc6(display);
> else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
> @@ -2295,7 +2296,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
> } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
> bxt_disable_dc9(display);
> bxt_display_core_init(i915, true);
> - if (intel_dmc_has_payload(i915) &&
> + if (intel_dmc_has_payload(display) &&
> (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
> gen9_enable_dc5(display);
> } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 9f275a6674a1..1898aff50ac4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -817,7 +817,7 @@ static void assert_can_enable_dc5(struct intel_display *display)
> "DC5 already programmed to be enabled.\n");
> assert_rpm_wakelock_held(&dev_priv->runtime_pm);
>
> - assert_dmc_loaded(dev_priv);
> + assert_dmc_loaded(display);
> }
>
> void gen9_enable_dc5(struct intel_display *display)
> @@ -840,8 +840,6 @@ void gen9_enable_dc5(struct intel_display *display)
>
> static void assert_can_enable_dc6(struct intel_display *display)
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> -
> drm_WARN_ONCE(display->drm,
> (intel_de_read(display, UTIL_PIN_CTL) &
> (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) ==
> @@ -852,7 +850,7 @@ static void assert_can_enable_dc6(struct intel_display *display)
> DC_STATE_EN_UPTO_DC6),
> "DC6 already programmed to be enabled.\n");
>
> - assert_dmc_loaded(dev_priv);
> + assert_dmc_loaded(display);
> }
>
> void skl_enable_dc6(struct intel_display *display)
> @@ -1031,7 +1029,7 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> struct intel_display *display = &dev_priv->display;
> struct i915_power_domains *power_domains = &display->power.domains;
>
> - if (!intel_dmc_has_payload(dev_priv))
> + if (!intel_dmc_has_payload(display))
> return;
>
> switch (power_domains->target_dc_state) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 7c756d5ba2a2..bbac6bfd1752 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -52,7 +52,7 @@ enum intel_dmc_id {
> };
>
> struct intel_dmc {
> - struct drm_i915_private *i915;
> + struct intel_display *display;
> struct work_struct work;
> const char *fw_path;
> u32 max_fw_size; /* bytes */
> @@ -70,21 +70,21 @@ struct intel_dmc {
> };
>
> /* Note: This may be NULL. */
> -static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915)
> +static struct intel_dmc *display_to_dmc(struct intel_display *display)
> {
> - return i915->display.dmc.dmc;
> + return display->dmc.dmc;
> }
>
> -static const char *dmc_firmware_param(struct drm_i915_private *i915)
> +static const char *dmc_firmware_param(struct intel_display *display)
> {
> - const char *p = i915->display.params.dmc_firmware_path;
> + const char *p = display->params.dmc_firmware_path;
>
> return p && *p ? p : NULL;
> }
>
> -static bool dmc_firmware_param_disabled(struct drm_i915_private *i915)
> +static bool dmc_firmware_param_disabled(struct intel_display *display)
> {
> - const char *p = dmc_firmware_param(i915);
> + const char *p = dmc_firmware_param(display);
>
> /* Magic path to indicate disabled */
> return p && !strcmp(p, "/dev/null");
> @@ -162,18 +162,19 @@ MODULE_FIRMWARE(SKL_DMC_PATH);
> #define BXT_DMC_MAX_FW_SIZE 0x3000
> MODULE_FIRMWARE(BXT_DMC_PATH);
>
> -static const char *dmc_firmware_default(struct drm_i915_private *i915, u32 *size)
> +static const char *dmc_firmware_default(struct intel_display *display, u32 *size)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> const char *fw_path = NULL;
> u32 max_fw_size = 0;
>
> - if (DISPLAY_VER_FULL(i915) == IP_VER(20, 0)) {
> + if (DISPLAY_VER_FULL(display) == IP_VER(20, 0)) {
> fw_path = XE2LPD_DMC_PATH;
> max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
> - } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) {
> + } else if (DISPLAY_VER_FULL(display) == IP_VER(14, 1)) {
> fw_path = BMG_DMC_PATH;
> max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
> - } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
> + } else if (DISPLAY_VER_FULL(display) == IP_VER(14, 0)) {
> fw_path = MTL_DMC_PATH;
> max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
> } else if (IS_DG2(i915)) {
> @@ -194,7 +195,7 @@ static const char *dmc_firmware_default(struct drm_i915_private *i915, u32 *size
> } else if (IS_TIGERLAKE(i915)) {
> fw_path = TGL_DMC_PATH;
> max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
> - } else if (DISPLAY_VER(i915) == 11) {
> + } else if (DISPLAY_VER(display) == 11) {
> fw_path = ICL_DMC_PATH;
> max_fw_size = ICL_DMC_MAX_FW_SIZE;
> } else if (IS_GEMINILAKE(i915)) {
> @@ -375,70 +376,70 @@ static bool is_valid_dmc_id(enum intel_dmc_id dmc_id)
> return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX;
> }
>
> -static bool has_dmc_id_fw(struct drm_i915_private *i915, enum intel_dmc_id dmc_id)
> +static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id)
> {
> - struct intel_dmc *dmc = i915_to_dmc(i915);
> + struct intel_dmc *dmc = display_to_dmc(display);
>
> return dmc && dmc->dmc_info[dmc_id].payload;
> }
>
> -bool intel_dmc_has_payload(struct drm_i915_private *i915)
> +bool intel_dmc_has_payload(struct intel_display *display)
> {
> - return has_dmc_id_fw(i915, DMC_FW_MAIN);
> + return has_dmc_id_fw(display, DMC_FW_MAIN);
> }
>
> static const struct stepping_info *
> -intel_get_stepping_info(struct drm_i915_private *i915,
> +intel_get_stepping_info(struct intel_display *display,
> struct stepping_info *si)
> {
> - const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(i915));
> + const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display));
>
> si->stepping = step_name[0];
> si->substepping = step_name[1];
> return si;
> }
>
> -static void gen9_set_dc_state_debugmask(struct drm_i915_private *i915)
> +static void gen9_set_dc_state_debugmask(struct intel_display *display)
> {
> /* The below bit doesn't need to be cleared ever afterwards */
> - intel_de_rmw(i915, DC_STATE_DEBUG, 0,
> + intel_de_rmw(display, DC_STATE_DEBUG, 0,
> DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
> - intel_de_posting_read(i915, DC_STATE_DEBUG);
> + intel_de_posting_read(display, DC_STATE_DEBUG);
> }
>
> -static void disable_event_handler(struct drm_i915_private *i915,
> +static void disable_event_handler(struct intel_display *display,
> i915_reg_t ctl_reg, i915_reg_t htp_reg)
> {
> - intel_de_write(i915, ctl_reg,
> + intel_de_write(display, ctl_reg,
> REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
> DMC_EVT_CTL_TYPE_EDGE_0_1) |
> REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
> DMC_EVT_CTL_EVENT_ID_FALSE));
> - intel_de_write(i915, htp_reg, 0);
> + intel_de_write(display, htp_reg, 0);
> }
>
> -static void disable_all_event_handlers(struct drm_i915_private *i915)
> +static void disable_all_event_handlers(struct intel_display *display)
> {
> enum intel_dmc_id dmc_id;
>
> /* TODO: disable the event handlers on pre-GEN12 platforms as well */
> - if (DISPLAY_VER(i915) < 12)
> + if (DISPLAY_VER(display) < 12)
> return;
>
> for_each_dmc_id(dmc_id) {
> int handler;
>
> - if (!has_dmc_id_fw(i915, dmc_id))
> + if (!has_dmc_id_fw(display, dmc_id))
> continue;
>
> for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++)
> - disable_event_handler(i915,
> - DMC_EVT_CTL(i915, dmc_id, handler),
> - DMC_EVT_HTP(i915, dmc_id, handler));
> + disable_event_handler(display,
> + DMC_EVT_CTL(display, dmc_id, handler),
> + DMC_EVT_HTP(display, dmc_id, handler));
> }
> }
>
> -static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> +static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable)
> {
> enum pipe pipe;
>
> @@ -451,84 +452,86 @@ static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool ena
> */
> if (enable)
> for (pipe = PIPE_A; pipe <= PIPE_D; pipe++)
> - intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe),
> + intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),
> 0, PIPEDMC_GATING_DIS);
> else
> for (pipe = PIPE_C; pipe <= PIPE_D; pipe++)
> - intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe),
> + intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),
> PIPEDMC_GATING_DIS, 0);
> }
>
> -static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915)
> +static void mtl_pipedmc_clock_gating_wa(struct intel_display *display)
> {
> /*
> * Wa_16015201720
> * The WA requires clock gating to be disabled all the time
> * for pipe A and B.
> */
> - intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0,
> + intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0,
> MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B);
> }
>
> -static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> +static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable)
> {
> - if (DISPLAY_VER(i915) >= 14 && enable)
> - mtl_pipedmc_clock_gating_wa(i915);
> - else if (DISPLAY_VER(i915) == 13)
> - adlp_pipedmc_clock_gating_wa(i915, enable);
> + if (DISPLAY_VER(display) >= 14 && enable)
> + mtl_pipedmc_clock_gating_wa(display);
> + else if (DISPLAY_VER(display) == 13)
> + adlp_pipedmc_clock_gating_wa(display, enable);
> }
>
> -void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
> +void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe)
> {
> enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
>
> - if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id))
> + if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
> return;
>
> - if (DISPLAY_VER(i915) >= 14)
> - intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));
> + if (DISPLAY_VER(display) >= 14)
> + intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));
> else
> - intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);
> + intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);
> }
>
> -void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe)
> +void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe)
> {
> enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
>
> - if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id))
> + if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
> return;
>
> - if (DISPLAY_VER(i915) >= 14)
> - intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);
> + if (DISPLAY_VER(display) >= 14)
> + intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);
> else
> - intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
> + intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
> }
>
> -static bool is_dmc_evt_ctl_reg(struct drm_i915_private *i915,
> +static bool is_dmc_evt_ctl_reg(struct intel_display *display,
> enum intel_dmc_id dmc_id, i915_reg_t reg)
> {
> u32 offset = i915_mmio_reg_offset(reg);
> - u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, 0));
> - u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
> + u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0));
> + u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
>
> return offset >= start && offset < end;
> }
>
> -static bool is_dmc_evt_htp_reg(struct drm_i915_private *i915,
> +static bool is_dmc_evt_htp_reg(struct intel_display *display,
> enum intel_dmc_id dmc_id, i915_reg_t reg)
> {
> u32 offset = i915_mmio_reg_offset(reg);
> - u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, 0));
> - u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
> + u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0));
> + u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
>
> return offset >= start && offset < end;
> }
>
> -static bool disable_dmc_evt(struct drm_i915_private *i915,
> +static bool disable_dmc_evt(struct intel_display *display,
> enum intel_dmc_id dmc_id,
> i915_reg_t reg, u32 data)
> {
> - if (!is_dmc_evt_ctl_reg(i915, dmc_id, reg))
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> + if (!is_dmc_evt_ctl_reg(display, dmc_id, reg))
> return false;
>
> /* keep all pipe DMC events disabled by default */
> @@ -548,11 +551,11 @@ static bool disable_dmc_evt(struct drm_i915_private *i915,
> return false;
> }
>
> -static u32 dmc_mmiodata(struct drm_i915_private *i915,
> +static u32 dmc_mmiodata(struct intel_display *display,
> struct intel_dmc *dmc,
> enum intel_dmc_id dmc_id, int i)
> {
> - if (disable_dmc_evt(i915, dmc_id,
> + if (disable_dmc_evt(display, dmc_id,
> dmc->dmc_info[dmc_id].mmioaddr[i],
> dmc->dmc_info[dmc_id].mmiodata[i]))
> return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
> @@ -565,25 +568,26 @@ static u32 dmc_mmiodata(struct drm_i915_private *i915,
>
> /**
> * intel_dmc_load_program() - write the firmware from memory to register.
> - * @i915: i915 drm device.
> + * @display: display instance
> *
> * DMC firmware is read from a .bin file and kept in internal memory one time.
> * Everytime display comes back from low power state this function is called to
> * copy the firmware from internal memory to registers.
> */
> -void intel_dmc_load_program(struct drm_i915_private *i915)
> +void intel_dmc_load_program(struct intel_display *display)
> {
> - struct i915_power_domains *power_domains = &i915->display.power.domains;
> - struct intel_dmc *dmc = i915_to_dmc(i915);
> + struct drm_i915_private *i915 __maybe_unused = to_i915(display->drm);
> + struct i915_power_domains *power_domains = &display->power.domains;
> + struct intel_dmc *dmc = display_to_dmc(display);
> enum intel_dmc_id dmc_id;
> u32 i;
>
> - if (!intel_dmc_has_payload(i915))
> + if (!intel_dmc_has_payload(display))
> return;
>
> - pipedmc_clock_gating_wa(i915, true);
> + pipedmc_clock_gating_wa(display, true);
>
> - disable_all_event_handlers(i915);
> + disable_all_event_handlers(display);
>
> assert_rpm_wakelock_held(&i915->runtime_pm);
>
> @@ -591,7 +595,7 @@ void intel_dmc_load_program(struct drm_i915_private *i915)
>
> for_each_dmc_id(dmc_id) {
> for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) {
> - intel_de_write_fw(i915,
> + intel_de_write_fw(display,
> DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i),
> dmc->dmc_info[dmc_id].payload[i]);
> }
> @@ -601,48 +605,48 @@ void intel_dmc_load_program(struct drm_i915_private *i915)
>
> for_each_dmc_id(dmc_id) {
> for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
> - intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i],
> - dmc_mmiodata(i915, dmc, dmc_id, i));
> + intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i],
> + dmc_mmiodata(display, dmc, dmc_id, i));
> }
> }
>
> power_domains->dc_state = 0;
>
> - gen9_set_dc_state_debugmask(i915);
> + gen9_set_dc_state_debugmask(display);
>
> - pipedmc_clock_gating_wa(i915, false);
> + pipedmc_clock_gating_wa(display, false);
> }
>
> /**
> * intel_dmc_disable_program() - disable the firmware
> - * @i915: i915 drm device
> + * @display: display instance
> *
> * Disable all event handlers in the firmware, making sure the firmware is
> * inactive after the display is uninitialized.
> */
> -void intel_dmc_disable_program(struct drm_i915_private *i915)
> +void intel_dmc_disable_program(struct intel_display *display)
> {
> - if (!intel_dmc_has_payload(i915))
> + if (!intel_dmc_has_payload(display))
> return;
>
> - pipedmc_clock_gating_wa(i915, true);
> - disable_all_event_handlers(i915);
> - pipedmc_clock_gating_wa(i915, false);
> + pipedmc_clock_gating_wa(display, true);
> + disable_all_event_handlers(display);
> + pipedmc_clock_gating_wa(display, false);
>
> - intel_dmc_wl_disable(&i915->display);
> + intel_dmc_wl_disable(display);
> }
>
> -void assert_dmc_loaded(struct drm_i915_private *i915)
> +void assert_dmc_loaded(struct intel_display *display)
> {
> - struct intel_dmc *dmc = i915_to_dmc(i915);
> + struct intel_dmc *dmc = display_to_dmc(display);
>
> - drm_WARN_ONCE(&i915->drm, !dmc, "DMC not initialized\n");
> - drm_WARN_ONCE(&i915->drm, dmc &&
> - !intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
> + drm_WARN_ONCE(display->drm, !dmc, "DMC not initialized\n");
> + drm_WARN_ONCE(display->drm, dmc &&
> + !intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
> "DMC program storage start is NULL\n");
> - drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE),
> + drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_SSP_BASE),
> "DMC SSP Base Not fine\n");
> - drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL),
> + drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_HTP_SKL),
> "DMC HTP Not fine\n");
> }
>
> @@ -673,7 +677,7 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc,
> const struct stepping_info *si,
> u8 package_ver)
> {
> - struct drm_i915_private *i915 = dmc->i915;
> + struct intel_display *display = dmc->display;
> enum intel_dmc_id dmc_id;
> unsigned int i;
>
> @@ -681,7 +685,7 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc,
> dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;
>
> if (!is_valid_dmc_id(dmc_id)) {
> - drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", dmc_id);
> + drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id);
> continue;
> }
>
> @@ -703,7 +707,7 @@ static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,
> const u32 *mmioaddr, u32 mmio_count,
> int header_ver, enum intel_dmc_id dmc_id)
> {
> - struct drm_i915_private *i915 = dmc->i915;
> + struct intel_display *display = dmc->display;
> u32 start_range, end_range;
> int i;
>
> @@ -713,14 +717,14 @@ static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,
> } else if (dmc_id == DMC_FW_MAIN) {
> start_range = TGL_MAIN_MMIO_START;
> end_range = TGL_MAIN_MMIO_END;
> - } else if (DISPLAY_VER(i915) >= 13) {
> + } else if (DISPLAY_VER(display) >= 13) {
> start_range = ADLP_PIPE_MMIO_START;
> end_range = ADLP_PIPE_MMIO_END;
> - } else if (DISPLAY_VER(i915) >= 12) {
> + } else if (DISPLAY_VER(display) >= 12) {
> start_range = TGL_PIPE_MMIO_START(dmc_id);
> end_range = TGL_PIPE_MMIO_END(dmc_id);
> } else {
> - drm_warn(&i915->drm, "Unknown mmio range for sanity check");
> + drm_warn(display->drm, "Unknown mmio range for sanity check");
> return false;
> }
>
> @@ -736,7 +740,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> const struct intel_dmc_header_base *dmc_header,
> size_t rem_size, enum intel_dmc_id dmc_id)
> {
> - struct drm_i915_private *i915 = dmc->i915;
> + struct intel_display *display = dmc->display;
> struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
> unsigned int header_len_bytes, dmc_header_size, payload_size, i;
> const u32 *mmioaddr, *mmiodata;
> @@ -784,39 +788,39 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> start_mmioaddr = DMC_V1_MMIO_START_RANGE;
> dmc_header_size = sizeof(*v1);
> } else {
> - drm_err(&i915->drm, "Unknown DMC fw header version: %u\n",
> + drm_err(display->drm, "Unknown DMC fw header version: %u\n",
> dmc_header->header_ver);
> return 0;
> }
>
> if (header_len_bytes != dmc_header_size) {
> - drm_err(&i915->drm, "DMC firmware has wrong dmc header length "
> + drm_err(display->drm, "DMC firmware has wrong dmc header length "
> "(%u bytes)\n", header_len_bytes);
> return 0;
> }
>
> /* Cache the dmc header info. */
> if (mmio_count > mmio_count_max) {
> - drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);
> + drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);
> return 0;
> }
>
> if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count,
> dmc_header->header_ver, dmc_id)) {
> - drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n");
> + drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n");
> return 0;
> }
>
> - drm_dbg_kms(&i915->drm, "DMC %d:\n", dmc_id);
> + drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id);
> for (i = 0; i < mmio_count; i++) {
> dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
> dmc_info->mmiodata[i] = mmiodata[i];
>
> - drm_dbg_kms(&i915->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n",
> + drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n",
> i, mmioaddr[i], mmiodata[i],
> - is_dmc_evt_ctl_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" :
> - is_dmc_evt_htp_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "",
> - disable_dmc_evt(i915, dmc_id, dmc_info->mmioaddr[i],
> + is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" :
> + is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "",
> + disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i],
> dmc_info->mmiodata[i]) ? " (disabling)" : "");
> }
> dmc_info->mmio_count = mmio_count;
> @@ -830,7 +834,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> goto error_truncated;
>
> if (payload_size > dmc->max_fw_size) {
> - drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size);
> + drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size);
> return 0;
> }
> dmc_info->dmc_fw_size = dmc_header->fw_size;
> @@ -845,7 +849,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> return header_len_bytes + payload_size;
>
> error_truncated:
> - drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
> + drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
> return 0;
> }
>
> @@ -855,7 +859,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
> const struct stepping_info *si,
> size_t rem_size)
> {
> - struct drm_i915_private *i915 = dmc->i915;
> + struct intel_display *display = dmc->display;
> u32 package_size = sizeof(struct intel_package_header);
> u32 num_entries, max_entries;
> const struct intel_fw_info *fw_info;
> @@ -868,7 +872,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
> } else if (package_header->header_ver == 2) {
> max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
> } else {
> - drm_err(&i915->drm, "DMC firmware has unknown header version %u\n",
> + drm_err(display->drm, "DMC firmware has unknown header version %u\n",
> package_header->header_ver);
> return 0;
> }
> @@ -882,7 +886,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
> goto error_truncated;
>
> if (package_header->header_len * 4 != package_size) {
> - drm_err(&i915->drm, "DMC firmware has wrong package header length "
> + drm_err(display->drm, "DMC firmware has wrong package header length "
> "(%u bytes)\n", package_size);
> return 0;
> }
> @@ -900,7 +904,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
> return package_size;
>
> error_truncated:
> - drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
> + drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
> return 0;
> }
>
> @@ -909,16 +913,16 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
> struct intel_css_header *css_header,
> size_t rem_size)
> {
> - struct drm_i915_private *i915 = dmc->i915;
> + struct intel_display *display = dmc->display;
>
> if (rem_size < sizeof(struct intel_css_header)) {
> - drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
> + drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
> return 0;
> }
>
> if (sizeof(struct intel_css_header) !=
> (css_header->header_len * 4)) {
> - drm_err(&i915->drm, "DMC firmware has wrong CSS header length "
> + drm_err(display->drm, "DMC firmware has wrong CSS header length "
> "(%u bytes)\n",
> (css_header->header_len * 4));
> return 0;
> @@ -931,12 +935,12 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
>
> static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw)
> {
> - struct drm_i915_private *i915 = dmc->i915;
> + struct intel_display *display = dmc->display;
> struct intel_css_header *css_header;
> struct intel_package_header *package_header;
> struct intel_dmc_header_base *dmc_header;
> struct stepping_info display_info = { '*', '*'};
> - const struct stepping_info *si = intel_get_stepping_info(i915, &display_info);
> + const struct stepping_info *si = intel_get_stepping_info(display, &display_info);
> enum intel_dmc_id dmc_id;
> u32 readcount = 0;
> u32 r, offset;
> @@ -966,7 +970,7 @@ static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw)
>
> offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4;
> if (offset > fw->size) {
> - drm_err(&i915->drm, "Reading beyond the fw_size\n");
> + drm_err(display->drm, "Reading beyond the fw_size\n");
> continue;
> }
>
> @@ -974,30 +978,35 @@ static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw)
> parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id);
> }
>
> - if (!intel_dmc_has_payload(i915)) {
> - drm_err(&i915->drm, "DMC firmware main program not found\n");
> + if (!intel_dmc_has_payload(display)) {
> + drm_err(display->drm, "DMC firmware main program not found\n");
> return -ENOENT;
> }
>
> return 0;
> }
>
> -static void intel_dmc_runtime_pm_get(struct drm_i915_private *i915)
> +static void intel_dmc_runtime_pm_get(struct intel_display *display)
> {
> - drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref);
> - i915->display.dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT);
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> + drm_WARN_ON(display->drm, display->dmc.wakeref);
> + display->dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT);
> }
>
> -static void intel_dmc_runtime_pm_put(struct drm_i915_private *i915)
> +static void intel_dmc_runtime_pm_put(struct intel_display *display)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> intel_wakeref_t wakeref __maybe_unused =
> - fetch_and_zero(&i915->display.dmc.wakeref);
> + fetch_and_zero(&display->dmc.wakeref);
>
> intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
> }
>
> -static const char *dmc_fallback_path(struct drm_i915_private *i915)
> +static const char *dmc_fallback_path(struct intel_display *display)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> +
> if (IS_ALDERLAKE_P(i915))
> return ADLP_DMC_FALLBACK_PATH;
>
> @@ -1007,45 +1016,45 @@ static const char *dmc_fallback_path(struct drm_i915_private *i915)
> static void dmc_load_work_fn(struct work_struct *work)
> {
> struct intel_dmc *dmc = container_of(work, typeof(*dmc), work);
> - struct drm_i915_private *i915 = dmc->i915;
> + struct intel_display *display = dmc->display;
> const struct firmware *fw = NULL;
> const char *fallback_path;
> int err;
>
> - err = request_firmware(&fw, dmc->fw_path, i915->drm.dev);
> + err = request_firmware(&fw, dmc->fw_path, display->drm->dev);
>
> - if (err == -ENOENT && !dmc_firmware_param(i915)) {
> - fallback_path = dmc_fallback_path(i915);
> + if (err == -ENOENT && !dmc_firmware_param(display)) {
> + fallback_path = dmc_fallback_path(display);
> if (fallback_path) {
> - drm_dbg_kms(&i915->drm, "%s not found, falling back to %s\n",
> + drm_dbg_kms(display->drm, "%s not found, falling back to %s\n",
> dmc->fw_path, fallback_path);
> - err = request_firmware(&fw, fallback_path, i915->drm.dev);
> + err = request_firmware(&fw, fallback_path, display->drm->dev);
> if (err == 0)
> dmc->fw_path = fallback_path;
> }
> }
>
> if (err) {
> - drm_notice(&i915->drm,
> + drm_notice(display->drm,
> "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n",
> dmc->fw_path, ERR_PTR(err));
> - drm_notice(&i915->drm, "DMC firmware homepage: %s",
> + drm_notice(display->drm, "DMC firmware homepage: %s",
> INTEL_DMC_FIRMWARE_URL);
> return;
> }
>
> err = parse_dmc_fw(dmc, fw);
> if (err) {
> - drm_notice(&i915->drm,
> + drm_notice(display->drm,
> "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n",
> dmc->fw_path, ERR_PTR(err));
> goto out;
> }
>
> - intel_dmc_load_program(i915);
> - intel_dmc_runtime_pm_put(i915);
> + intel_dmc_load_program(display);
> + intel_dmc_runtime_pm_put(display);
>
> - drm_info(&i915->drm, "Finished loading DMC firmware %s (v%u.%u)\n",
> + drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n",
> dmc->fw_path, DMC_VERSION_MAJOR(dmc->version),
> DMC_VERSION_MINOR(dmc->version));
>
> @@ -1055,16 +1064,17 @@ static void dmc_load_work_fn(struct work_struct *work)
>
> /**
> * intel_dmc_init() - initialize the firmware loading.
> - * @i915: i915 drm device.
> + * @display: display instance
> *
> * This function is called at the time of loading the display driver to read
> * firmware from a .bin file and copied into a internal memory.
> */
> -void intel_dmc_init(struct drm_i915_private *i915)
> +void intel_dmc_init(struct intel_display *display)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> struct intel_dmc *dmc;
>
> - if (!HAS_DMC(i915))
> + if (!HAS_DMC(display))
> return;
>
> /*
> @@ -1075,35 +1085,35 @@ void intel_dmc_init(struct drm_i915_private *i915)
> * suspend as runtime suspend *requires* a working DMC for whatever
> * reason.
> */
> - intel_dmc_runtime_pm_get(i915);
> + intel_dmc_runtime_pm_get(display);
>
> dmc = kzalloc(sizeof(*dmc), GFP_KERNEL);
> if (!dmc)
> return;
>
> - dmc->i915 = i915;
> + dmc->display = display;
>
> INIT_WORK(&dmc->work, dmc_load_work_fn);
>
> - dmc->fw_path = dmc_firmware_default(i915, &dmc->max_fw_size);
> + dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size);
>
> - if (dmc_firmware_param_disabled(i915)) {
> - drm_info(&i915->drm, "Disabling DMC firmware and runtime PM\n");
> + if (dmc_firmware_param_disabled(display)) {
> + drm_info(display->drm, "Disabling DMC firmware and runtime PM\n");
> goto out;
> }
>
> - if (dmc_firmware_param(i915))
> - dmc->fw_path = dmc_firmware_param(i915);
> + if (dmc_firmware_param(display))
> + dmc->fw_path = dmc_firmware_param(display);
>
> if (!dmc->fw_path) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "No known DMC firmware for platform, disabling runtime PM\n");
> goto out;
> }
>
> - i915->display.dmc.dmc = dmc;
> + display->dmc.dmc = dmc;
>
> - drm_dbg_kms(&i915->drm, "Loading %s\n", dmc->fw_path);
> + drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path);
> queue_work(i915->unordered_wq, &dmc->work);
>
> return;
> @@ -1114,87 +1124,87 @@ void intel_dmc_init(struct drm_i915_private *i915)
>
> /**
> * intel_dmc_suspend() - prepare DMC firmware before system suspend
> - * @i915: i915 drm device
> + * @display: display instance
> *
> * Prepare the DMC firmware before entering system suspend. This includes
> * flushing pending work items and releasing any resources acquired during
> * init.
> */
> -void intel_dmc_suspend(struct drm_i915_private *i915)
> +void intel_dmc_suspend(struct intel_display *display)
> {
> - struct intel_dmc *dmc = i915_to_dmc(i915);
> + struct intel_dmc *dmc = display_to_dmc(display);
>
> - if (!HAS_DMC(i915))
> + if (!HAS_DMC(display))
> return;
>
> if (dmc)
> flush_work(&dmc->work);
>
> - intel_dmc_wl_disable(&i915->display);
> + intel_dmc_wl_disable(display);
>
> /* Drop the reference held in case DMC isn't loaded. */
> - if (!intel_dmc_has_payload(i915))
> - intel_dmc_runtime_pm_put(i915);
> + if (!intel_dmc_has_payload(display))
> + intel_dmc_runtime_pm_put(display);
> }
>
> /**
> * intel_dmc_resume() - init DMC firmware during system resume
> - * @i915: i915 drm device
> + * @display: display instance
> *
> * Reinitialize the DMC firmware during system resume, reacquiring any
> * resources released in intel_dmc_suspend().
> */
> -void intel_dmc_resume(struct drm_i915_private *i915)
> +void intel_dmc_resume(struct intel_display *display)
> {
> - if (!HAS_DMC(i915))
> + if (!HAS_DMC(display))
> return;
>
> /*
> * Reacquire the reference to keep RPM disabled in case DMC isn't
> * loaded.
> */
> - if (!intel_dmc_has_payload(i915))
> - intel_dmc_runtime_pm_get(i915);
> + if (!intel_dmc_has_payload(display))
> + intel_dmc_runtime_pm_get(display);
> }
>
> /**
> * intel_dmc_fini() - unload the DMC firmware.
> - * @i915: i915 drm device.
> + * @display: display instance
> *
> * Firmmware unloading includes freeing the internal memory and reset the
> * firmware loading status.
> */
> -void intel_dmc_fini(struct drm_i915_private *i915)
> +void intel_dmc_fini(struct intel_display *display)
> {
> - struct intel_dmc *dmc = i915_to_dmc(i915);
> + struct intel_dmc *dmc = display_to_dmc(display);
> enum intel_dmc_id dmc_id;
>
> - if (!HAS_DMC(i915))
> + if (!HAS_DMC(display))
> return;
>
> - intel_dmc_suspend(i915);
> - drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref);
> + intel_dmc_suspend(display);
> + drm_WARN_ON(display->drm, display->dmc.wakeref);
>
> if (dmc) {
> for_each_dmc_id(dmc_id)
> kfree(dmc->dmc_info[dmc_id].payload);
>
> kfree(dmc);
> - i915->display.dmc.dmc = NULL;
> + display->dmc.dmc = NULL;
> }
> }
>
> void intel_dmc_print_error_state(struct drm_printer *p,
> - struct drm_i915_private *i915)
> + struct intel_display *display)
> {
> - struct intel_dmc *dmc = i915_to_dmc(i915);
> + struct intel_dmc *dmc = display_to_dmc(display);
>
> - if (!HAS_DMC(i915))
> + if (!HAS_DMC(display))
> return;
>
> drm_printf(p, "DMC initialized: %s\n", str_yes_no(dmc));
> drm_printf(p, "DMC loaded: %s\n",
> - str_yes_no(intel_dmc_has_payload(i915)));
> + str_yes_no(intel_dmc_has_payload(display)));
> if (dmc)
> drm_printf(p, "DMC fw version: %d.%d\n",
> DMC_VERSION_MAJOR(dmc->version),
> @@ -1203,40 +1213,41 @@ void intel_dmc_print_error_state(struct drm_printer *p,
>
> static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> {
> - struct drm_i915_private *i915 = m->private;
> - struct intel_dmc *dmc = i915_to_dmc(i915);
> + struct intel_display *display = m->private;
> + struct drm_i915_private *i915 = to_i915(display->drm);
> + struct intel_dmc *dmc = display_to_dmc(display);
> intel_wakeref_t wakeref;
> i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
>
> - if (!HAS_DMC(i915))
> + if (!HAS_DMC(display))
> return -ENODEV;
>
> wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>
> seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc));
> seq_printf(m, "fw loaded: %s\n",
> - str_yes_no(intel_dmc_has_payload(i915)));
> + str_yes_no(intel_dmc_has_payload(display)));
> seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A");
> seq_printf(m, "Pipe A fw needed: %s\n",
> - str_yes_no(DISPLAY_VER(i915) >= 12));
> + str_yes_no(DISPLAY_VER(display) >= 12));
> seq_printf(m, "Pipe A fw loaded: %s\n",
> - str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEA)));
> + str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA)));
> seq_printf(m, "Pipe B fw needed: %s\n",
> str_yes_no(IS_ALDERLAKE_P(i915) ||
> - DISPLAY_VER(i915) >= 14));
> + DISPLAY_VER(display) >= 14));
> seq_printf(m, "Pipe B fw loaded: %s\n",
> - str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEB)));
> + str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB)));
>
> - if (!intel_dmc_has_payload(i915))
> + if (!intel_dmc_has_payload(display))
> goto out;
>
> seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),
> DMC_VERSION_MINOR(dmc->version));
>
> - if (DISPLAY_VER(i915) >= 12) {
> + if (DISPLAY_VER(display) >= 12) {
> i915_reg_t dc3co_reg;
>
> - if (IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) {
> + if (IS_DGFX(i915) || DISPLAY_VER(display) >= 14) {
> dc3co_reg = DG1_DMC_DEBUG3;
> dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> } else {
> @@ -1246,7 +1257,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> }
>
> seq_printf(m, "DC3CO count: %d\n",
> - intel_de_read(i915, dc3co_reg));
> + intel_de_read(display, dc3co_reg));
> } else {
> dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT :
> SKL_DMC_DC3_DC5_COUNT;
> @@ -1254,18 +1265,18 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> dc6_reg = SKL_DMC_DC5_DC6_COUNT;
> }
>
> - seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg));
> + seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
> if (i915_mmio_reg_valid(dc6_reg))
> seq_printf(m, "DC5 -> DC6 count: %d\n",
> - intel_de_read(i915, dc6_reg));
> + intel_de_read(display, dc6_reg));
>
> seq_printf(m, "program base: 0x%08x\n",
> - intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> + intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
>
> out:
> seq_printf(m, "ssp base: 0x%08x\n",
> - intel_de_read(i915, DMC_SSP_BASE));
> - seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL));
> + intel_de_read(display, DMC_SSP_BASE));
> + seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL));
>
> intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>
> @@ -1274,10 +1285,10 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>
> DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status);
>
> -void intel_dmc_debugfs_register(struct drm_i915_private *i915)
> +void intel_dmc_debugfs_register(struct intel_display *display)
> {
> - struct drm_minor *minor = i915->drm.primary;
> + struct drm_minor *minor = display->drm->primary;
>
> debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root,
> - i915, &intel_dmc_debugfs_status_fops);
> + display, &intel_dmc_debugfs_status_fops);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index 54cff6002e31..2ead2ec1f820 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -9,22 +9,22 @@
> #include <linux/types.h>
>
> enum pipe;
> -struct drm_i915_private;
> struct drm_printer;
> +struct intel_display;
>
> -void intel_dmc_init(struct drm_i915_private *i915);
> -void intel_dmc_load_program(struct drm_i915_private *i915);
> -void intel_dmc_disable_program(struct drm_i915_private *i915);
> -void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe);
> -void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe);
> -void intel_dmc_fini(struct drm_i915_private *i915);
> -void intel_dmc_suspend(struct drm_i915_private *i915);
> -void intel_dmc_resume(struct drm_i915_private *i915);
> -bool intel_dmc_has_payload(struct drm_i915_private *i915);
> -void intel_dmc_debugfs_register(struct drm_i915_private *i915);
> +void intel_dmc_init(struct intel_display *display);
> +void intel_dmc_load_program(struct intel_display *display);
> +void intel_dmc_disable_program(struct intel_display *display);
> +void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe);
> +void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe);
> +void intel_dmc_fini(struct intel_display *display);
> +void intel_dmc_suspend(struct intel_display *display);
> +void intel_dmc_resume(struct intel_display *display);
> +bool intel_dmc_has_payload(struct intel_display *display);
> +void intel_dmc_debugfs_register(struct intel_display *display);
> void intel_dmc_print_error_state(struct drm_printer *p,
> - struct drm_i915_private *i915);
> + struct intel_display *display);
>
> -void assert_dmc_loaded(struct drm_i915_private *i915);
> +void assert_dmc_loaded(struct intel_display *display);
>
> #endif /* __INTEL_DMC_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> index d9864b9cc429..5634ff07269d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> @@ -109,10 +109,8 @@ static bool intel_dmc_wl_check_range(u32 address)
>
> static bool __intel_dmc_wl_supported(struct intel_display *display)
> {
> - struct drm_i915_private *i915 = to_i915(display->drm);
> -
> if (DISPLAY_VER(display) < 20 ||
> - !intel_dmc_has_payload(i915) ||
> + !intel_dmc_has_payload(display) ||
> !display->params.enable_dmc_wl)
> return false;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index 1f57549fce00..bcc5cf137a88 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -960,6 +960,7 @@ static void intel_early_display_was(struct drm_i915_private *i915)
> void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
> struct drm_modeset_acquire_ctx *ctx)
> {
> + struct intel_display *display = &i915->display;
> struct intel_encoder *encoder;
> struct intel_crtc *crtc;
> intel_wakeref_t wakeref;
> @@ -987,7 +988,7 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
> drm_crtc_vblank_reset(&crtc->base);
>
> if (crtc_state->hw.active) {
> - intel_dmc_enable_pipe(i915, crtc->pipe);
> + intel_dmc_enable_pipe(display, crtc->pipe);
> intel_crtc_vblank_on(crtc_state);
> }
> }
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index fe905d65ddf7..943e938040c0 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -959,7 +959,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
> intel_encoder_suspend_all(&i915->display);
> intel_encoder_shutdown_all(&i915->display);
>
> - intel_dmc_suspend(i915);
> + intel_dmc_suspend(&i915->display);
>
> i915_gem_suspend(i915);
>
> @@ -1054,7 +1054,7 @@ static int i915_drm_suspend(struct drm_device *dev)
>
> dev_priv->suspend_count++;
>
> - intel_dmc_suspend(dev_priv);
> + intel_dmc_suspend(display);
>
> enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>
> @@ -1164,7 +1164,7 @@ static int i915_drm_resume(struct drm_device *dev)
> /* Must be called after GGTT is resumed. */
> intel_dpt_resume(dev_priv);
>
> - intel_dmc_resume(dev_priv);
> + intel_dmc_resume(display);
>
> i915_restore_display(dev_priv);
> intel_pps_unlock_regs_wa(display);
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 6469b9bcf2ec..b455fa441609 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -875,7 +875,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
>
> err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
>
> - intel_dmc_print_error_state(&p, m->i915);
> + intel_dmc_print_error_state(&p, &m->i915->display);
>
> err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock));
> err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended));
> diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
> index c0e9aa7a274f..10d707e05d6e 100644
> --- a/drivers/gpu/drm/xe/display/xe_display.c
> +++ b/drivers/gpu/drm/xe/display/xe_display.c
> @@ -353,7 +353,7 @@ void xe_display_pm_suspend(struct xe_device *xe, bool runtime)
>
> intel_opregion_suspend(display, s2idle ? PCI_D1 : PCI_D3cold);
>
> - intel_dmc_suspend(xe);
> + intel_dmc_suspend(display);
> }
>
> void xe_display_pm_suspend_late(struct xe_device *xe)
> @@ -395,7 +395,7 @@ void xe_display_pm_resume(struct xe_device *xe, bool runtime)
> if (!xe->info.probe_display)
> return;
>
> - intel_dmc_resume(xe);
> + intel_dmc_resume(display);
>
> if (has_display(xe))
> drm_mode_config_reset(&xe->drm);
> --
> 2.44.2
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display
2024-09-06 14:33 ` [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display Ville Syrjala
2024-09-06 15:09 ` Rodrigo Vivi
@ 2024-09-06 15:18 ` Jani Nikula
2024-09-06 16:17 ` Ville Syrjälä
1 sibling, 1 reply; 23+ messages in thread
From: Jani Nikula @ 2024-09-06 15:18 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On Fri, 06 Sep 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> struct intel_display will replace struct drm_i915_private as
> the main thing for display code. Convert the CDCLK code to
> use it (as much as possible at this stage).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Some nitpicks inline, but overall
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
[snip]
> @@ -2685,20 +2712,21 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
> else
> pipe = INVALID_PIPE;
>
> - drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> + drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
>
> - intel_set_cdclk(i915, &new_cdclk_state->actual, pipe,
> + intel_set_cdclk(display, &new_cdclk_state->actual, pipe,
> "Post changing CDCLK to");
> }
>
> static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_display *display = to_intel_display(crtc_state->uapi.crtc->dev);
This works, but to_intel_display(crtc_state) is enough.
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
I usually don't bother with changing the dev_priv initialization if it
keeps working. I just put the display stuff first. But this works.
> int pixel_rate = crtc_state->pixel_rate;
>
> - if (DISPLAY_VER(dev_priv) >= 10)
> + if (DISPLAY_VER(display) >= 10)
> return DIV_ROUND_UP(pixel_rate, 2);
> - else if (DISPLAY_VER(dev_priv) == 9 ||
> + else if (DISPLAY_VER(display) == 9 ||
> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> return pixel_rate;
> else if (IS_CHERRYVIEW(dev_priv))
> @@ -2712,11 +2740,11 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
[snip]
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 408c76852495..9ff08dbefc76 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -1678,7 +1678,7 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9
> }
> }
>
> - display_runtime->rawclk_freq = intel_read_rawclk(i915);
> + display_runtime->rawclk_freq = intel_read_rawclk(&i915->display);
I generally prefer adding that struct intel_display local variable when
I need it the first time, so the subsequent changes are less churn.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/6] drm/i915/cdclk: Add missing braces
2024-09-06 14:33 ` [PATCH 1/6] drm/i915/cdclk: Add missing braces Ville Syrjala
2024-09-06 15:10 ` Rodrigo Vivi
@ 2024-09-06 15:19 ` Jani Nikula
1 sibling, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2024-09-06 15:19 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On Fri, 06 Sep 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> CodingStyle says when one branch of an if ladder is braced
> then all of them should be. Make it so.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 66964c7d2a2c..9d870d15d888 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2053,8 +2053,9 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> dg2_cdclk_squash_program(dev_priv, 0);
>
> icl_cdclk_pll_update(dev_priv, vco);
> - } else
> + } else {
> bxt_cdclk_pll_update(dev_priv, vco);
> + }
>
> if (HAS_CDCLK_SQUASH(dev_priv)) {
> u16 waveform = cdclk_squash_waveform(dev_priv, cdclk);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Some intel_display conversions
2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala
` (5 preceding siblings ...)
2024-09-06 14:33 ` [PATCH 6/6] drm/i915/dmc: Convert DMC " Ville Syrjala
@ 2024-09-06 15:43 ` Patchwork
2024-09-06 15:43 ` ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2024-09-06 15:43 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Some intel_display conversions
URL : https://patchwork.freedesktop.org/series/138331/
State : warning
== Summary ==
Error: dim checkpatch failed
0f1a2e1d9ca9 drm/i915/cdclk: Add missing braces
f31c381fad0a drm/i915/cdclk: Convert CDCLK code to intel_display
-:1467: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 26)
#1467: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:2103:
+ if (DISPLAY_VER(display) >= 14 || IS_DG2(dev_priv))
/* NOOP */;
-:1508: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 19)
#1508: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:2140:
+ if (DISPLAY_VER(display) >= 14)
[...]
*/;
-:2895: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#2895: FILE: drivers/gpu/drm/i915/display/intel_display_driver.c:95:
+ cdclk_state->logical = cdclk_state->actual = display->cdclk.hw;
total: 0 errors, 2 warnings, 1 checks, 2934 lines checked
e8bcf398a0cc drm/i915/power: Convert low level DC state code to intel_display
55bd47b4af6b drm/i915/vga: Convert VGA code to intel_display
1f4c4c02e55e drm/i915/power: Convert "i830 power well" code to intel_display
6fbc2c329423 drm/i915/dmc: Convert DMC code to intel_display
-:603: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#603: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:645:
+ !intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
-:710: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#710: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:821:
+ is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" :
-:711: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#711: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:822:
+ is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "",
-:1169: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#1169: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:1274:
+ intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
total: 0 errors, 4 warnings, 0 checks, 1210 lines checked
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: Some intel_display conversions
2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala
` (6 preceding siblings ...)
2024-09-06 15:43 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Some intel_display conversions Patchwork
@ 2024-09-06 15:43 ` Patchwork
2024-09-06 16:08 ` ✗ Fi.CI.BAT: failure " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2024-09-06 15:43 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Some intel_display conversions
URL : https://patchwork.freedesktop.org/series/138331/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Some intel_display conversions
2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala
` (7 preceding siblings ...)
2024-09-06 15:43 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2024-09-06 16:08 ` Patchwork
2024-09-09 14:15 ` Ville Syrjälä
2024-09-10 5:34 ` ✓ Fi.CI.BAT: success " Patchwork
2024-09-11 0:54 ` ✗ Fi.CI.IGT: failure " Patchwork
10 siblings, 1 reply; 23+ messages in thread
From: Patchwork @ 2024-09-06 16:08 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5151 bytes --]
== Series Details ==
Series: drm/i915: Some intel_display conversions
URL : https://patchwork.freedesktop.org/series/138331/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15373 -> Patchwork_138331v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_138331v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_138331v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/index.html
Participating hosts (42 -> 39)
------------------------------
Additional (1): fi-elk-e7500
Missing (4): fi-glk-j4005 fi-kbl-8809g fi-snb-2520m fi-bsw-n3050
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_138331v1:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live:
- bat-adlp-9: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-adlp-9/igt@i915_selftest@live.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-adlp-9/igt@i915_selftest@live.html
Known issues
------------
Here are the changes found in Patchwork_138331v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@nullptr:
- bat-arls-1: [PASS][3] -> [DMESG-WARN][4] ([i915#12102])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-arls-1/igt@fbdev@nullptr.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-arls-1/igt@fbdev@nullptr.html
* igt@i915_selftest@live@gt_lrc:
- bat-adlp-9: [PASS][5] -> [INCOMPLETE][6] ([i915#9413])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-adlp-9/igt@i915_selftest@live@gt_lrc.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-adlp-9/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@workarounds:
- bat-mtlp-6: [PASS][7] -> [ABORT][8] ([i915#12061]) +1 other test abort
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-hdmi-a-1:
- fi-elk-e7500: NOTRUN -> [SKIP][9] +25 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/fi-elk-e7500/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-hdmi-a-1.html
* igt@kms_pipe_crc_basic@nonblocking-crc:
- bat-arls-5: [PASS][10] -> [INCOMPLETE][11] ([i915#11320])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-arls-5/igt@kms_pipe_crc_basic@nonblocking-crc.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-arls-5/igt@kms_pipe_crc_basic@nonblocking-crc.html
#### Possible fixes ####
* igt@fbdev@read:
- bat-arls-1: [DMESG-WARN][12] ([i915#12102]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-arls-1/igt@fbdev@read.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-arls-1/igt@fbdev@read.html
* igt@i915_selftest@live:
- bat-arls-1: [DMESG-WARN][14] ([i915#10341]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-arls-1/igt@i915_selftest@live.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-arls-1/igt@i915_selftest@live.html
* igt@i915_selftest@live@hangcheck:
- bat-arls-1: [DMESG-WARN][16] ([i915#11349]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-arls-1/igt@i915_selftest@live@hangcheck.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-arls-1/igt@i915_selftest@live@hangcheck.html
[i915#10341]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10341
[i915#11320]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11320
[i915#11349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11349
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12102
[i915#9413]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9413
Build changes
-------------
* Linux: CI_DRM_15373 -> Patchwork_138331v1
CI-20190529: 20190529
CI_DRM_15373: 6094a8d70f8599700297da58bcf80d5b1915adff @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8007: 8f9900c288f4cf1244d66baa71bc6d9355747cbd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_138331v1: 6094a8d70f8599700297da58bcf80d5b1915adff @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/index.html
[-- Attachment #2: Type: text/html, Size: 6060 bytes --]
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display
2024-09-06 15:18 ` Jani Nikula
@ 2024-09-06 16:17 ` Ville Syrjälä
0 siblings, 0 replies; 23+ messages in thread
From: Ville Syrjälä @ 2024-09-06 16:17 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Fri, Sep 06, 2024 at 06:18:58PM +0300, Jani Nikula wrote:
> On Fri, 06 Sep 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > struct intel_display will replace struct drm_i915_private as
> > the main thing for display code. Convert the CDCLK code to
> > use it (as much as possible at this stage).
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Some nitpicks inline, but overall
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> [snip]
>
> > @@ -2685,20 +2712,21 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
> > else
> > pipe = INVALID_PIPE;
> >
> > - drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
> > + drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
> >
> > - intel_set_cdclk(i915, &new_cdclk_state->actual, pipe,
> > + intel_set_cdclk(display, &new_cdclk_state->actual, pipe,
> > "Post changing CDCLK to");
> > }
> >
> > static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > + struct intel_display *display = to_intel_display(crtc_state->uapi.crtc->dev);
>
> This works, but to_intel_display(crtc_state) is enough.
Not entirely sure I like the magic going quite that deep.
Though I suppose we do have a lot of that, so maybe it's
best to make it simple as possible.
> > + struct drm_i915_private *dev_priv = to_i915(display->drm);
>
> I usually don't bother with changing the dev_priv initialization if it
> keeps working. I just put the display stuff first. But this works.
>
> > int pixel_rate = crtc_state->pixel_rate;
> >
> > - if (DISPLAY_VER(dev_priv) >= 10)
> > + if (DISPLAY_VER(display) >= 10)
> > return DIV_ROUND_UP(pixel_rate, 2);
> > - else if (DISPLAY_VER(dev_priv) == 9 ||
> > + else if (DISPLAY_VER(display) == 9 ||
> > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> > return pixel_rate;
> > else if (IS_CHERRYVIEW(dev_priv))
> > @@ -2712,11 +2740,11 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
>
> [snip]
>
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> > index 408c76852495..9ff08dbefc76 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> > @@ -1678,7 +1678,7 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9
> > }
> > }
> >
> > - display_runtime->rawclk_freq = intel_read_rawclk(i915);
> > + display_runtime->rawclk_freq = intel_read_rawclk(&i915->display);
>
> I generally prefer adding that struct intel_display local variable when
> I need it the first time, so the subsequent changes are less churn.
Yeah, I tried to follow that, unless the surrounding code already has
tons of &i915->display stuff in it. But here that isn't the case, so
apparently I just failed to follow the procedure fully.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915: Some intel_display conversions
2024-09-06 16:08 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2024-09-09 14:15 ` Ville Syrjälä
2024-09-10 8:14 ` Illipilli, TejasreeX
0 siblings, 1 reply; 23+ messages in thread
From: Ville Syrjälä @ 2024-09-09 14:15 UTC (permalink / raw)
To: intel-gfx; +Cc: I915-ci-infra
On Fri, Sep 06, 2024 at 04:08:52PM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Some intel_display conversions
> URL : https://patchwork.freedesktop.org/series/138331/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_15373 -> Patchwork_138331v1
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_138331v1 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_138331v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/index.html
>
> Participating hosts (42 -> 39)
> ------------------------------
>
> Additional (1): fi-elk-e7500
> Missing (4): fi-glk-j4005 fi-kbl-8809g fi-snb-2520m fi-bsw-n3050
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_138331v1:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@i915_selftest@live:
> - bat-adlp-9: [PASS][1] -> [INCOMPLETE][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-adlp-9/igt@i915_selftest@live.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-adlp-9/igt@i915_selftest@live.html
Some unrelated thing. Please proceed to shard testing.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Some intel_display conversions
2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala
` (8 preceding siblings ...)
2024-09-06 16:08 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2024-09-10 5:34 ` Patchwork
2024-09-11 0:54 ` ✗ Fi.CI.IGT: failure " Patchwork
10 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2024-09-10 5:34 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4332 bytes --]
== Series Details ==
Series: drm/i915: Some intel_display conversions
URL : https://patchwork.freedesktop.org/series/138331/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15373 -> Patchwork_138331v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/index.html
Participating hosts (42 -> 39)
------------------------------
Additional (1): fi-elk-e7500
Missing (4): fi-glk-j4005 fi-kbl-8809g fi-snb-2520m fi-bsw-n3050
Known issues
------------
Here are the changes found in Patchwork_138331v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@nullptr:
- bat-arls-1: [PASS][1] -> [DMESG-WARN][2] ([i915#12102])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-arls-1/igt@fbdev@nullptr.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-arls-1/igt@fbdev@nullptr.html
* igt@i915_selftest@live:
- bat-adlp-9: [PASS][3] -> [INCOMPLETE][4] ([i915#9413]) +1 other test incomplete
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-adlp-9/igt@i915_selftest@live.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-adlp-9/igt@i915_selftest@live.html
* igt@i915_selftest@live@workarounds:
- bat-mtlp-6: [PASS][5] -> [ABORT][6] ([i915#12061]) +1 other test abort
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-hdmi-a-1:
- fi-elk-e7500: NOTRUN -> [SKIP][7] +25 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/fi-elk-e7500/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-hdmi-a-1.html
* igt@kms_pipe_crc_basic@nonblocking-crc:
- bat-arls-5: [PASS][8] -> [INCOMPLETE][9] ([i915#11320])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-arls-5/igt@kms_pipe_crc_basic@nonblocking-crc.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-arls-5/igt@kms_pipe_crc_basic@nonblocking-crc.html
#### Possible fixes ####
* igt@fbdev@read:
- bat-arls-1: [DMESG-WARN][10] ([i915#12102]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-arls-1/igt@fbdev@read.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-arls-1/igt@fbdev@read.html
* igt@i915_selftest@live:
- bat-arls-1: [DMESG-WARN][12] ([i915#10341]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-arls-1/igt@i915_selftest@live.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-arls-1/igt@i915_selftest@live.html
* igt@i915_selftest@live@hangcheck:
- bat-arls-1: [DMESG-WARN][14] ([i915#11349]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-arls-1/igt@i915_selftest@live@hangcheck.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-arls-1/igt@i915_selftest@live@hangcheck.html
[i915#10341]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10341
[i915#11320]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11320
[i915#11349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11349
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12102
[i915#9413]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9413
Build changes
-------------
* Linux: CI_DRM_15373 -> Patchwork_138331v1
CI-20190529: 20190529
CI_DRM_15373: 6094a8d70f8599700297da58bcf80d5b1915adff @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8007: 8f9900c288f4cf1244d66baa71bc6d9355747cbd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_138331v1: 6094a8d70f8599700297da58bcf80d5b1915adff @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/index.html
[-- Attachment #2: Type: text/html, Size: 5204 bytes --]
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: ✗ Fi.CI.BAT: failure for drm/i915: Some intel_display conversions
2024-09-09 14:15 ` Ville Syrjälä
@ 2024-09-10 8:14 ` Illipilli, TejasreeX
0 siblings, 0 replies; 23+ messages in thread
From: Illipilli, TejasreeX @ 2024-09-10 8:14 UTC (permalink / raw)
To: Ville Syrjälä, intel-gfx@lists.freedesktop.org
Cc: I915-ci-infra@lists.freedesktop.org
Hi ,
https://patchwork.freedesktop.org/series/138331/ -Re-reported.
Thanks,
Tejasree
-----Original Message-----
From: I915-ci-infra <i915-ci-infra-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjälä
Sent: Monday, September 9, 2024 7:46 PM
To: intel-gfx@lists.freedesktop.org
Cc: I915-ci-infra@lists.freedesktop.org
Subject: Re: ✗ Fi.CI.BAT: failure for drm/i915: Some intel_display conversions
On Fri, Sep 06, 2024 at 04:08:52PM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Some intel_display conversions
> URL : https://patchwork.freedesktop.org/series/138331/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_15373 -> Patchwork_138331v1
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_138331v1 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_138331v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/index.html
>
> Participating hosts (42 -> 39)
> ------------------------------
>
> Additional (1): fi-elk-e7500
> Missing (4): fi-glk-j4005 fi-kbl-8809g fi-snb-2520m fi-bsw-n3050
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_138331v1:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@i915_selftest@live:
> - bat-adlp-9: [PASS][1] -> [INCOMPLETE][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/bat-adlp-9/igt@i915_selftest@live.html
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/bat-adlp-9
> /igt@i915_selftest@live.html
Some unrelated thing. Please proceed to shard testing.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: Some intel_display conversions
2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala
` (9 preceding siblings ...)
2024-09-10 5:34 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2024-09-11 0:54 ` Patchwork
10 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2024-09-11 0:54 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 75426 bytes --]
== Series Details ==
Series: drm/i915: Some intel_display conversions
URL : https://patchwork.freedesktop.org/series/138331/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15373_full -> Patchwork_138331v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_138331v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_138331v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 10)
------------------------------
Additional (1): shard-snb-0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_138331v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_atomic_transition@modeset-transition:
- shard-glk: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-glk6/igt@kms_atomic_transition@modeset-transition.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-glk8/igt@kms_atomic_transition@modeset-transition.html
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-dg1: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg1-17/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-13/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html
* igt@perf@polling:
- shard-dg2: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-3/igt@perf@polling.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-2/igt@perf@polling.html
Known issues
------------
Here are the changes found in Patchwork_138331v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-keep-cache:
- shard-dg1: NOTRUN -> [SKIP][7] ([i915#8411]) +1 other test skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@api_intel_bb@blit-reloc-keep-cache.html
* igt@api_intel_bb@crc32:
- shard-rkl: NOTRUN -> [SKIP][8] ([i915#6230])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@api_intel_bb@crc32.html
* igt@debugfs_test@basic-hwmon:
- shard-tglu: NOTRUN -> [SKIP][9] ([i915#9318])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-5/igt@debugfs_test@basic-hwmon.html
* igt@drm_fdinfo@most-busy-check-all:
- shard-rkl: [PASS][10] -> [FAIL][11] ([i915#12179])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-rkl-1/igt@drm_fdinfo@most-busy-check-all.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all.html
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [PASS][12] -> [FAIL][13] ([i915#7742])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-rkl-1/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@drm_fdinfo@virtual-busy:
- shard-dg2: NOTRUN -> [SKIP][14] ([i915#8414])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@drm_fdinfo@virtual-busy.html
* igt@drm_fdinfo@virtual-busy-all:
- shard-dg1: NOTRUN -> [SKIP][15] ([i915#8414])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@drm_fdinfo@virtual-busy-all.html
* igt@gem_bad_reloc@negative-reloc-lut:
- shard-rkl: NOTRUN -> [SKIP][16] ([i915#3281]) +1 other test skip
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@gem_bad_reloc@negative-reloc-lut.html
* igt@gem_ccs@block-multicopy-compressed:
- shard-tglu: NOTRUN -> [SKIP][17] ([i915#9323])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@gem_ccs@block-multicopy-compressed.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-tglu: NOTRUN -> [SKIP][18] ([i915#3555] / [i915#9323])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-5/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-dg1: NOTRUN -> [SKIP][19] ([i915#9323])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-dg2: NOTRUN -> [SKIP][20] ([i915#7697])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-rkl: NOTRUN -> [SKIP][21] ([i915#6335])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-4/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_create@create-ext-set-pat:
- shard-dg1: NOTRUN -> [SKIP][22] ([i915#8562])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_engines@invalid-engines:
- shard-tglu: [PASS][23] -> [FAIL][24] ([i915#12027])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-tglu-3/igt@gem_ctx_engines@invalid-engines.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-3/igt@gem_ctx_engines@invalid-engines.html
* igt@gem_ctx_persistence@heartbeat-stop:
- shard-dg1: NOTRUN -> [SKIP][25] ([i915#8555])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@gem_ctx_persistence@heartbeat-stop.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt:
- shard-dg2: NOTRUN -> [SKIP][26] ([i915#5882]) +7 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@gem_ctx_persistence@saturated-hostile-nopreempt.html
* igt@gem_exec_endless@dispatch:
- shard-dg2: [PASS][27] -> [TIMEOUT][28] ([i915#7016])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-5/igt@gem_exec_endless@dispatch.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-10/igt@gem_exec_endless@dispatch.html
* igt@gem_exec_endless@dispatch@bcs0:
- shard-dg2: [PASS][29] -> [TIMEOUT][30] ([i915#3778] / [i915#7016])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-5/igt@gem_exec_endless@dispatch@bcs0.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-10/igt@gem_exec_endless@dispatch@bcs0.html
* igt@gem_exec_fair@basic-none-solo:
- shard-tglu: NOTRUN -> [FAIL][31] ([i915#2842]) +1 other test fail
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-5/igt@gem_exec_fair@basic-none-solo.html
* igt@gem_exec_fair@basic-sync:
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#3539]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@gem_exec_fair@basic-sync.html
* igt@gem_exec_flush@basic-uc-rw-default:
- shard-dg1: NOTRUN -> [SKIP][33] ([i915#3539] / [i915#4852]) +2 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-17/igt@gem_exec_flush@basic-uc-rw-default.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-dg2: NOTRUN -> [SKIP][34] ([i915#5107])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_exec_reloc@basic-gtt-read:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#3281]) +7 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@gem_exec_reloc@basic-gtt-read.html
* igt@gem_exec_reloc@basic-wc-read-active:
- shard-dg1: NOTRUN -> [SKIP][36] ([i915#3281]) +4 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@gem_exec_reloc@basic-wc-read-active.html
* igt@gem_exec_schedule@reorder-wide:
- shard-dg2: NOTRUN -> [SKIP][37] ([i915#4537] / [i915#4812]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@gem_exec_schedule@reorder-wide.html
* igt@gem_fence_thrash@bo-write-verify-x:
- shard-dg2: NOTRUN -> [SKIP][38] ([i915#4860]) +3 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@gem_fence_thrash@bo-write-verify-x.html
* igt@gem_fence_thrash@bo-write-verify-y:
- shard-dg1: NOTRUN -> [SKIP][39] ([i915#4860])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@gem_fence_thrash@bo-write-verify-y.html
* igt@gem_lmem_evict@dontneed-evict-race:
- shard-tglu: NOTRUN -> [SKIP][40] ([i915#4613] / [i915#7582])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@gem_lmem_evict@dontneed-evict-race.html
* igt@gem_lmem_swapping@heavy-random:
- shard-glk: NOTRUN -> [SKIP][41] ([i915#4613]) +2 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-glk8/igt@gem_lmem_swapping@heavy-random.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: NOTRUN -> [TIMEOUT][42] ([i915#5493]) +1 other test timeout
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-dg1: NOTRUN -> [SKIP][43] ([i915#12193])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_lmem_swapping@verify-random-ccs@lmem0:
- shard-dg1: NOTRUN -> [SKIP][44] ([i915#4565])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@gem_lmem_swapping@verify-random-ccs@lmem0.html
* igt@gem_mmap@bad-object:
- shard-dg1: NOTRUN -> [SKIP][45] ([i915#4083]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@gem_mmap@bad-object.html
* igt@gem_mmap_gtt@cpuset-big-copy:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#4077]) +5 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@gem_mmap_gtt@cpuset-big-copy.html
* igt@gem_mmap_gtt@fault-concurrent:
- shard-dg1: NOTRUN -> [SKIP][47] ([i915#4077]) +4 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-17/igt@gem_mmap_gtt@fault-concurrent.html
* igt@gem_mmap_wc@fault-concurrent:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#4083])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@gem_mmap_wc@fault-concurrent.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-dg1: NOTRUN -> [SKIP][49] ([i915#3282]) +2 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_pread@display:
- shard-rkl: NOTRUN -> [SKIP][50] ([i915#3282])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@gem_pread@display.html
* igt@gem_pread@exhaustion:
- shard-tglu: NOTRUN -> [WARN][51] ([i915#2658])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-self:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#3282]) +2 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@gem_pwrite@basic-self.html
* igt@gem_pxp@display-protected-crc:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#4270]) +2 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-dg1: NOTRUN -> [SKIP][54] ([i915#4270]) +2 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-17/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_pxp@reject-modify-context-protection-off-1:
- shard-tglu: NOTRUN -> [SKIP][55] ([i915#4270])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@gem_pxp@reject-modify-context-protection-off-1.html
* igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
- shard-rkl: NOTRUN -> [SKIP][56] ([i915#4270])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-dg2: NOTRUN -> [SKIP][57] ([i915#5190] / [i915#8428]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-rkl: NOTRUN -> [SKIP][58] ([i915#8411])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_set_tiling_vs_pwrite:
- shard-dg1: NOTRUN -> [SKIP][59] ([i915#4079])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-17/igt@gem_set_tiling_vs_pwrite.html
* igt@gem_userptr_blits@access-control:
- shard-rkl: NOTRUN -> [SKIP][60] ([i915#3297])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@gem_userptr_blits@access-control.html
* igt@gem_userptr_blits@coherency-sync:
- shard-tglu: NOTRUN -> [SKIP][61] ([i915#3297])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-dg2: NOTRUN -> [SKIP][62] ([i915#3297] / [i915#4880])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gen3_render_linear_blits:
- shard-dg2: NOTRUN -> [SKIP][63] +7 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@gen3_render_linear_blits.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-tglu: NOTRUN -> [SKIP][64] ([i915#2527] / [i915#2856])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-5/igt@gen9_exec_parse@batch-invalid-length.html
* igt@gen9_exec_parse@batch-without-end:
- shard-dg2: NOTRUN -> [SKIP][65] ([i915#2856]) +1 other test skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@gen9_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@bb-chained:
- shard-rkl: NOTRUN -> [SKIP][66] ([i915#2527])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@gen9_exec_parse@bb-chained.html
* igt@gen9_exec_parse@bb-start-param:
- shard-dg1: NOTRUN -> [SKIP][67] ([i915#2527]) +2 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-17/igt@gen9_exec_parse@bb-start-param.html
* igt@i915_module_load@load:
- shard-dg2: NOTRUN -> [SKIP][68] ([i915#6227])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@i915_module_load@load.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-snb: [PASS][69] -> [ABORT][70] ([i915#9820])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-snb2/igt@i915_module_load@reload-with-fault-injection.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-snb5/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-tglu: NOTRUN -> [SKIP][71] ([i915#6590]) +1 other test skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0:
- shard-dg1: [PASS][72] -> [FAIL][73] ([i915#3591])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][74] -> [INCOMPLETE][75] ([i915#7790])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-snb6/igt@i915_pm_rps@reset.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-snb5/igt@i915_pm_rps@reset.html
* igt@i915_pm_rps@thresholds:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#11681]) +1 other test skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@i915_pm_rps@thresholds.html
* igt@i915_query@query-topology-coherent-slice-mask:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#6188])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@i915_query@query-topology-coherent-slice-mask.html
* igt@i915_selftest@live@workarounds:
- shard-mtlp: [PASS][78] -> [ABORT][79] ([i915#12061]) +1 other test abort
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-mtlp-2/igt@i915_selftest@live@workarounds.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-mtlp-5/igt@i915_selftest@live@workarounds.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- shard-dg1: NOTRUN -> [SKIP][80] ([i915#4212]) +2 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@clobberred-modifier:
- shard-dg2: NOTRUN -> [SKIP][81] ([i915#4212])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@kms_addfb_basic@clobberred-modifier.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-dg1: NOTRUN -> [SKIP][82] ([i915#9531])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@modeset-transition@2x-outputs:
- shard-glk: [PASS][83] -> [FAIL][84] ([i915#11859])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-glk6/igt@kms_atomic_transition@modeset-transition@2x-outputs.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-glk8/igt@kms_atomic_transition@modeset-transition@2x-outputs.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][85] ([i915#5956]) +1 other test fail
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-4.html
* igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1:
- shard-snb: [PASS][86] -> [FAIL][87] ([i915#5956]) +1 other test fail
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-snb5/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-snb4/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-tglu: NOTRUN -> [SKIP][88] ([i915#5286]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-5/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-rkl: NOTRUN -> [SKIP][89] ([i915#5286])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-dg1: NOTRUN -> [SKIP][90] ([i915#4538] / [i915#5286]) +4 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-dg2: NOTRUN -> [SKIP][91] ([i915#4538] / [i915#5190]) +4 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][92] ([i915#3638]) +4 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- shard-rkl: NOTRUN -> [SKIP][93] +4 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][94] ([i915#4538]) +2 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html
* igt@kms_big_joiner@invalid-modeset-force-joiner:
- shard-dg1: NOTRUN -> [SKIP][95] ([i915#10656])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@kms_big_joiner@invalid-modeset-force-joiner.html
* igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][96] ([i915#10307] / [i915#6095]) +141 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][97] ([i915#6095]) +79 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-17/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs:
- shard-tglu: NOTRUN -> [SKIP][98] ([i915#6095]) +24 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][99] ([i915#10307] / [i915#10434] / [i915#6095]) +11 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-10/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][100] ([i915#6095]) +64 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-2/igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-b-hdmi-a-1.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-tglu: NOTRUN -> [SKIP][101] ([i915#3742])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-5/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][102] ([i915#4087]) +4 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3.html
* igt@kms_chamelium_edid@dp-mode-timings:
- shard-dg2: NOTRUN -> [SKIP][103] ([i915#7828]) +4 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@kms_chamelium_edid@dp-mode-timings.html
* igt@kms_chamelium_edid@hdmi-edid-read:
- shard-rkl: NOTRUN -> [SKIP][104] ([i915#7828]) +1 other test skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@kms_chamelium_edid@hdmi-edid-read.html
* igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
- shard-dg1: NOTRUN -> [SKIP][105] ([i915#7828]) +6 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-17/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html
* igt@kms_chamelium_hpd@vga-hpd-without-ddc:
- shard-tglu: NOTRUN -> [SKIP][106] ([i915#7828]) +3 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html
* igt@kms_content_protection@content-type-change:
- shard-dg1: NOTRUN -> [SKIP][107] ([i915#9424])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-17/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-dg1: NOTRUN -> [SKIP][108] ([i915#3299])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-dg2: NOTRUN -> [SKIP][109] ([i915#3299])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-tglu: NOTRUN -> [SKIP][110] ([i915#3116] / [i915#3299])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@srm@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [TIMEOUT][111] ([i915#7173])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-11/igt@kms_content_protection@srm@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-dg1: NOTRUN -> [SKIP][112] ([i915#3555]) +6 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-tglu: NOTRUN -> [SKIP][113] ([i915#11453]) +1 other test skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-dg1: NOTRUN -> [SKIP][114] ([i915#4103] / [i915#4213]) +2 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-17/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-tglu: NOTRUN -> [SKIP][115] ([i915#4103])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-rkl: NOTRUN -> [SKIP][116] ([i915#9723])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-tglu: NOTRUN -> [SKIP][117] ([i915#1769] / [i915#3555] / [i915#3804])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][118] ([i915#3804])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dsc@dsc-basic:
- shard-dg1: NOTRUN -> [SKIP][119] ([i915#3555] / [i915#3840]) +1 other test skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-17/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-rkl: NOTRUN -> [SKIP][120] ([i915#3840])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-dg1: NOTRUN -> [SKIP][121] ([i915#3840])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#3555] / [i915#3840])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-dg1: NOTRUN -> [SKIP][123] ([i915#3469]) +1 other test skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@display-3x:
- shard-dg2: NOTRUN -> [SKIP][124] ([i915#1839])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@kms_feature_discovery@display-3x.html
* igt@kms_feature_discovery@psr2:
- shard-dg2: NOTRUN -> [SKIP][125] ([i915#658])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-dg1: NOTRUN -> [SKIP][126] ([i915#9934])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-fences-interruptible:
- shard-dg1: NOTRUN -> [SKIP][127] ([i915#8381])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@kms_flip@2x-flip-vs-fences-interruptible.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-tglu: NOTRUN -> [SKIP][128] ([i915#3637])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@flip-vs-absolute-wf_vblank:
- shard-dg1: NOTRUN -> [FAIL][129] ([i915#2122]) +1 other test fail
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-17/igt@kms_flip@flip-vs-absolute-wf_vblank.html
* igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
- shard-snb: [PASS][130] -> [INCOMPLETE][131] ([i915#4839]) +1 other test incomplete
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-snb2/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-snb6/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@a-vga1:
- shard-snb: [PASS][132] -> [FAIL][133] ([i915#2122]) +1 other test fail
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-snb2/igt@kms_flip@wf_vblank-ts-check-interruptible@a-vga1.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-snb7/igt@kms_flip@wf_vblank-ts-check-interruptible@a-vga1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling:
- shard-rkl: NOTRUN -> [SKIP][134] ([i915#2672] / [i915#3555])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][135] ([i915#2672])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling:
- shard-dg2: NOTRUN -> [SKIP][136] ([i915#2672] / [i915#3555] / [i915#5190])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling:
- shard-dg1: NOTRUN -> [SKIP][137] ([i915#2672] / [i915#3555]) +3 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][138] ([i915#2587] / [i915#2672]) +3 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-tglu: NOTRUN -> [SKIP][139] ([i915#2672] / [i915#3555]) +1 other test skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][140] ([i915#2587] / [i915#2672]) +1 other test skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][141] ([i915#2672] / [i915#3555])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][142] ([i915#2672]) +1 other test skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff:
- shard-tglu: NOTRUN -> [SKIP][143] +33 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][144] ([i915#8708]) +13 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][145] ([i915#5439])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][146] ([i915#1825]) +6 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
- shard-dg1: NOTRUN -> [SKIP][147] +27 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt:
- shard-dg2: NOTRUN -> [SKIP][148] ([i915#5354]) +17 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
- shard-dg1: NOTRUN -> [SKIP][149] ([i915#3458]) +15 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][150] ([i915#3023]) +7 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-dg1: NOTRUN -> [SKIP][151] ([i915#5439])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-dg1: NOTRUN -> [SKIP][152] ([i915#9766])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][153] ([i915#3458]) +6 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-glk: NOTRUN -> [SKIP][154] +141 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-glk8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][155] ([i915#8708]) +7 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch:
- shard-tglu: NOTRUN -> [SKIP][156] ([i915#3555] / [i915#8228])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@static-toggle:
- shard-dg1: NOTRUN -> [SKIP][157] ([i915#3555] / [i915#8228])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@kms_hdr@static-toggle.html
* igt@kms_hdr@static-toggle-suspend:
- shard-dg2: [PASS][158] -> [SKIP][159] ([i915#3555] / [i915#8228])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-11/igt@kms_hdr@static-toggle-suspend.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-10/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_panel_fitting@atomic-fastset:
- shard-dg2: NOTRUN -> [SKIP][160] ([i915#6301])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@kms_panel_fitting@atomic-fastset.html
* igt@kms_panel_fitting@legacy:
- shard-tglu: NOTRUN -> [SKIP][161] ([i915#6301])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_lowres@tiling-y:
- shard-dg2: NOTRUN -> [SKIP][162] ([i915#8821])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@kms_plane_lowres@tiling-y.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [FAIL][163] ([i915#8292])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-13/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][164] ([i915#9423]) +3 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-13/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-c-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][165] ([i915#9423]) +4 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-5/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][166] ([i915#9423]) +10 other tests skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
- shard-tglu: NOTRUN -> [SKIP][167] ([i915#6953])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][168] ([i915#5235]) +2 other tests skip
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][169] ([i915#9728])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-hdmi-a-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-dp-4:
- shard-dg2: NOTRUN -> [SKIP][170] ([i915#9423]) +15 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-11/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-dp-4.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][171] ([i915#9728]) +5 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-4/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
- shard-dg1: NOTRUN -> [SKIP][172] ([i915#6953])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][173] ([i915#9728]) +11 other tests skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4.html
* igt@kms_pm_dc@dc6-dpms:
- shard-dg1: NOTRUN -> [SKIP][174] ([i915#3361])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@kms_pm_dc@dc6-dpms.html
- shard-tglu: [PASS][175] -> [FAIL][176] ([i915#9295])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-tglu-3/igt@kms_pm_dc@dc6-dpms.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-9/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc9-dpms:
- shard-tglu: [PASS][177] -> [SKIP][178] ([i915#4281])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-tglu-3/igt@kms_pm_dc@dc9-dpms.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-9/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg2: [PASS][179] -> [SKIP][180] ([i915#9519]) +1 other test skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-10/igt@kms_pm_rpm@dpms-lpsp.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-5/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-rkl: [PASS][181] -> [SKIP][182] ([i915#9519]) +1 other test skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp-stress.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp-stress.html
- shard-dg1: NOTRUN -> [SKIP][183] ([i915#9519])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-17/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-exceed-sf:
- shard-tglu: NOTRUN -> [SKIP][184] ([i915#11520]) +2 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-primary-plane-update-sf-dmg-area:
- shard-rkl: NOTRUN -> [SKIP][185] ([i915#11520])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@kms_psr2_sf@fbc-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-dg2: NOTRUN -> [SKIP][186] ([i915#11520]) +1 other test skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-dg1: NOTRUN -> [SKIP][187] ([i915#11520]) +3 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-14/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-dg2: NOTRUN -> [SKIP][188] ([i915#9683])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@fbc-pr-sprite-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][189] ([i915#1072] / [i915#9732]) +10 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@kms_psr@fbc-pr-sprite-mmap-gtt.html
* igt@kms_psr@fbc-psr-basic:
- shard-rkl: NOTRUN -> [SKIP][190] ([i915#1072] / [i915#9732]) +6 other tests skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-4/igt@kms_psr@fbc-psr-basic.html
* igt@kms_psr@fbc-psr2-primary-mmap-gtt:
- shard-tglu: NOTRUN -> [SKIP][191] ([i915#9732]) +8 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-5/igt@kms_psr@fbc-psr2-primary-mmap-gtt.html
* igt@kms_psr@psr2-sprite-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][192] ([i915#1072] / [i915#9732]) +15 other tests skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-16/igt@kms_psr@psr2-sprite-mmap-gtt.html
* igt@kms_rotation_crc@exhaust-fences:
- shard-dg1: NOTRUN -> [SKIP][193] ([i915#4884])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-16/igt@kms_rotation_crc@exhaust-fences.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-tglu: NOTRUN -> [SKIP][194] ([i915#5289])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-rkl: NOTRUN -> [SKIP][195] ([i915#3555]) +1 other test skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-tglu: NOTRUN -> [SKIP][196] ([i915#8623])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_universal_plane@cursor-fb-leak:
- shard-dg2: [PASS][197] -> [FAIL][198] ([i915#9196])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-11/igt@kms_universal_plane@cursor-fb-leak.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-5/igt@kms_universal_plane@cursor-fb-leak.html
- shard-dg1: [PASS][199] -> [FAIL][200] ([i915#9196])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg1-17/igt@kms_universal_plane@cursor-fb-leak.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-13/igt@kms_universal_plane@cursor-fb-leak.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-tglu: [PASS][201] -> [FAIL][202] ([i915#9196])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-tglu-10/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [FAIL][203] ([i915#9196])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-5/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-3.html
- shard-dg1: NOTRUN -> [FAIL][204] ([i915#9196])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-13/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-3.html
* igt@kms_vrr@flip-basic:
- shard-dg2: NOTRUN -> [SKIP][205] ([i915#3555]) +1 other test skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-8/igt@kms_vrr@flip-basic.html
* igt@kms_vrr@flip-basic-fastset:
- shard-rkl: NOTRUN -> [SKIP][206] ([i915#9906])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-dg1: NOTRUN -> [SKIP][207] ([i915#9906])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-17/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@kms_writeback@writeback-check-output:
- shard-dg2: NOTRUN -> [SKIP][208] ([i915#2437])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-dg1: NOTRUN -> [SKIP][209] ([i915#2437] / [i915#9412])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-tglu: NOTRUN -> [SKIP][210] ([i915#2437])
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@polling@0-rcs0:
- shard-dg2: [PASS][211] -> [FAIL][212] ([i915#10538])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-3/igt@perf@polling@0-rcs0.html
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-2/igt@perf@polling@0-rcs0.html
* igt@perf_pmu@all-busy-idle-check-all:
- shard-dg2: NOTRUN -> [FAIL][213] ([i915#11943])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@perf_pmu@all-busy-idle-check-all.html
* igt@perf_pmu@busy-double-start@vecs1:
- shard-dg2: [PASS][214] -> [FAIL][215] ([i915#4349]) +4 other tests fail
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-11/igt@perf_pmu@busy-double-start@vecs1.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-5/igt@perf_pmu@busy-double-start@vecs1.html
* igt@prime_vgem@basic-fence-read:
- shard-dg2: NOTRUN -> [SKIP][216] ([i915#3291] / [i915#3708]) +1 other test skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@fence-write-hang:
- shard-rkl: NOTRUN -> [SKIP][217] ([i915#3708])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@prime_vgem@fence-write-hang.html
* igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
- shard-dg1: NOTRUN -> [SKIP][218] ([i915#9917])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
* igt@syncobj_wait@invalid-wait-zero-handles:
- shard-dg2: NOTRUN -> [FAIL][219] ([i915#9781])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-7/igt@syncobj_wait@invalid-wait-zero-handles.html
#### Possible fixes ####
* igt@gem_eio@unwedge-stress:
- shard-dg1: [FAIL][220] ([i915#5784]) -> [PASS][221]
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg1-18/igt@gem_eio@unwedge-stress.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-13/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][222] ([i915#2842]) -> [PASS][223] +1 other test pass
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-tglu: [FAIL][224] ([i915#2842]) -> [PASS][225] +1 other test pass
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-tglu-9/igt@gem_exec_fair@basic-pace-share@rcs0.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-9/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-rkl: [FAIL][226] ([i915#2842]) -> [PASS][227] +2 other tests pass
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-rkl-2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_flush@basic-wb-ro-before-default:
- shard-tglu: [INCOMPLETE][228] -> [PASS][229] +1 other test pass
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-tglu-8/igt@gem_exec_flush@basic-wb-ro-before-default.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-6/igt@gem_exec_flush@basic-wb-ro-before-default.html
* igt@gem_exec_whisper@basic-contexts-all:
- shard-dg2: [INCOMPLETE][230] -> [PASS][231]
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-5/igt@gem_exec_whisper@basic-contexts-all.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-4/igt@gem_exec_whisper@basic-contexts-all.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
- shard-dg1: [FAIL][232] ([i915#3591]) -> [PASS][233]
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-rkl: [INCOMPLETE][234] ([i915#4817]) -> [PASS][235]
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-rkl-6/igt@i915_suspend@basic-s3-without-i915.html
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-4/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_flip@flip-vs-absolute-wf_vblank:
- shard-dg2: [FAIL][236] ([i915#2122]) -> [PASS][237] +2 other tests pass
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-6/igt@kms_flip@flip-vs-absolute-wf_vblank.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-6/igt@kms_flip@flip-vs-absolute-wf_vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-dg2: [FAIL][238] ([i915#6880]) -> [PASS][239]
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_hdr@static-swap:
- shard-dg2: [SKIP][240] ([i915#3555] / [i915#8228]) -> [PASS][241]
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-6/igt@kms_hdr@static-swap.html
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-11/igt@kms_hdr@static-swap.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-dg2: [SKIP][242] ([i915#9340]) -> [PASS][243]
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-3/igt@kms_pm_lpsp@kms-lpsp.html
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-2/igt@kms_pm_lpsp@kms-lpsp.html
- shard-rkl: [SKIP][244] ([i915#9340]) -> [PASS][245]
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-rkl-5/igt@kms_pm_lpsp@kms-lpsp.html
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-2/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-rkl: [SKIP][246] ([i915#9519]) -> [PASS][247]
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-rkl-2/igt@kms_pm_rpm@dpms-non-lpsp.html
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-6/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-dg2: [SKIP][248] ([i915#9519]) -> [PASS][249] +1 other test pass
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-3/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-10/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-snb: [FAIL][250] ([i915#9196]) -> [PASS][251] +1 other test pass
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-snb1/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-snb2/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1:
- shard-tglu: [FAIL][252] ([i915#9196]) -> [PASS][253]
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-tglu-10/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-tglu-8/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html
* igt@kms_vblank@query-forked-busy-hang:
- shard-dg1: [INCOMPLETE][254] -> [PASS][255]
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg1-13/igt@kms_vblank@query-forked-busy-hang.html
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg1-16/igt@kms_vblank@query-forked-busy-hang.html
#### Warnings ####
* igt@i915_selftest@mock:
- shard-glk: [DMESG-WARN][256] ([i915#1982] / [i915#9311]) -> [DMESG-WARN][257] ([i915#9311])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-glk6/igt@i915_selftest@mock.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-glk8/igt@i915_selftest@mock.html
- shard-rkl: [DMESG-WARN][258] ([i915#9311]) -> [DMESG-WARN][259] ([i915#1982] / [i915#9311])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-rkl-1/igt@i915_selftest@mock.html
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-rkl-5/igt@i915_selftest@mock.html
* igt@kms_content_protection@lic-type-0:
- shard-dg2: [TIMEOUT][260] ([i915#7173]) -> [SKIP][261] ([i915#9424])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-11/igt@kms_content_protection@lic-type-0.html
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-10/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@srm:
- shard-dg2: [SKIP][262] ([i915#7118]) -> [TIMEOUT][263] ([i915#7173])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-8/igt@kms_content_protection@srm.html
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-11/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent:
- shard-dg2: [FAIL][264] ([i915#1339] / [i915#7173]) -> [SKIP][265] ([i915#7118] / [i915#9424])
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-11/igt@kms_content_protection@uevent.html
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-5/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-dg2: [SKIP][266] ([i915#11453]) -> [SKIP][267] ([i915#11453] / [i915#3359])
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-6/igt@kms_cursor_crc@cursor-sliding-512x170.html
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-11/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- shard-dg2: [SKIP][268] ([i915#3458]) -> [SKIP][269] ([i915#10433] / [i915#3458]) +2 other tests skip
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
* igt@kms_psr@fbc-psr-primary-page-flip:
- shard-dg2: [SKIP][270] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][271] ([i915#1072] / [i915#9732]) +9 other tests skip
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-11/igt@kms_psr@fbc-psr-primary-page-flip.html
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-10/igt@kms_psr@fbc-psr-primary-page-flip.html
* igt@kms_psr@pr-cursor-render:
- shard-dg2: [SKIP][272] ([i915#1072] / [i915#9732]) -> [SKIP][273] ([i915#1072] / [i915#9673] / [i915#9732]) +5 other tests skip
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-8/igt@kms_psr@pr-cursor-render.html
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-11/igt@kms_psr@pr-cursor-render.html
* igt@kms_rotation_crc@bad-tiling:
- shard-dg2: [SKIP][274] ([i915#11131]) -> [SKIP][275] ([i915#11131] / [i915#4235])
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-dg2-6/igt@kms_rotation_crc@bad-tiling.html
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-dg2-11/igt@kms_rotation_crc@bad-tiling.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-glk: [FAIL][276] ([i915#10959]) -> [SKIP][277]
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15373/shard-glk6/igt@kms_tiled_display@basic-test-pattern.html
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/shard-glk8/igt@kms_tiled_display@basic-test-pattern.html
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10538
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10959]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10959
[i915#11131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11131
[i915#11453]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11453
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11859]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11859
[i915#11943]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11943
[i915#12027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12027
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12179
[i915#12193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12193
[i915#1339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1339
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3778
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
[i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
[i915#4884]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4884
[i915#5107]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5107
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#5882]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5882
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6188]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6188
[i915#6227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6227
[i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
[i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
[i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7016]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7016
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
[i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
[i915#7790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7790
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8821
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
[i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9728]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9728
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
[i915#9781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9781
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_15373 -> Patchwork_138331v1
* Piglit: None -> piglit_4509
CI-20190529: 20190529
CI_DRM_15373: 6094a8d70f8599700297da58bcf80d5b1915adff @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8007: 8f9900c288f4cf1244d66baa71bc6d9355747cbd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_138331v1: 6094a8d70f8599700297da58bcf80d5b1915adff @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138331v1/index.html
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^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2024-09-11 0:54 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala
2024-09-06 14:33 ` [PATCH 1/6] drm/i915/cdclk: Add missing braces Ville Syrjala
2024-09-06 15:10 ` Rodrigo Vivi
2024-09-06 15:19 ` Jani Nikula
2024-09-06 14:33 ` [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display Ville Syrjala
2024-09-06 15:09 ` Rodrigo Vivi
2024-09-06 15:18 ` Jani Nikula
2024-09-06 16:17 ` Ville Syrjälä
2024-09-06 14:33 ` [PATCH 3/6] drm/i915/power: Convert low level DC state " Ville Syrjala
2024-09-06 15:10 ` Rodrigo Vivi
2024-09-06 14:33 ` [PATCH 4/6] drm/i915/vga: Convert VGA " Ville Syrjala
2024-09-06 15:12 ` Rodrigo Vivi
2024-09-06 14:33 ` [PATCH 5/6] drm/i915/power: Convert "i830 power well" " Ville Syrjala
2024-09-06 15:13 ` Rodrigo Vivi
2024-09-06 14:33 ` [PATCH 6/6] drm/i915/dmc: Convert DMC " Ville Syrjala
2024-09-06 15:16 ` Rodrigo Vivi
2024-09-06 15:43 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Some intel_display conversions Patchwork
2024-09-06 15:43 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-09-06 16:08 ` ✗ Fi.CI.BAT: failure " Patchwork
2024-09-09 14:15 ` Ville Syrjälä
2024-09-10 8:14 ` Illipilli, TejasreeX
2024-09-10 5:34 ` ✓ Fi.CI.BAT: success " Patchwork
2024-09-11 0:54 ` ✗ Fi.CI.IGT: failure " Patchwork
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