* [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U
@ 2023-01-17 7:42 Chaitanya Kumar Borah
2023-01-17 7:42 ` [Intel-gfx] [RFC 1/2] drm/i915: Add RPL-U sub platform Chaitanya Kumar Borah
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-17 7:42 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
A new step of 480MHz has been added on SKUs that have an RPL-U
device id. This particular step is to support 120Hz panels
more efficiently.
This patchset adds a new table to include this new CDCLK
step. Details can be found in BSpec entry 55409.
Create a new sub-platform to identify RPL-U which will enable
us to make the differentiation during CDCLK initialization.
Furthermore, we need to make a distinction between ES (Engineering
Sample) and QS (Quality Sample) parts as this change comes only
to QS parts. This version of the patch does not include this change
as we are yet to make a decision if this particular part needs
to be upstreamed.(see comments on revision 2)
Chaitanya Kumar Borah (2):
drm/i915: Add RPL-U sub platform
drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
drivers/gpu/drm/i915/display/intel_cdclk.c | 27 ++++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 8 +++++++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
include/drm/i915_pciids.h | 11 +++++----
6 files changed, 47 insertions(+), 4 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [RFC 1/2] drm/i915: Add RPL-U sub platform
2023-01-17 7:42 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
@ 2023-01-17 7:42 ` Chaitanya Kumar Borah
2023-01-24 14:32 ` Jani Nikula
2023-01-17 7:42 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-17 7:42 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
Separate out RPLU device ids and add them to both RPL and
newly created RPL-U subplatforms.
v2: (Matt)
- Sort PCI-IDs numerically
- Name the sub-platform to accurately depict what it is for
- Make RPL-U part of RPL subplatform
v3: revert to RPL-U subplatform (Jani)
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 8 ++++++++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
include/drm/i915_pciids.h | 11 +++++++----
5 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 48fd82722f12..c88e514728a0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -619,6 +619,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
#define IS_ADLP_RPLP(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
+#define IS_ADLP_RPLU(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 6cc65079b18d..e9f3b99b3e00 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1234,6 +1234,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_DG1_IDS(&dg1_info),
INTEL_RPLS_IDS(&adl_s_info),
INTEL_RPLP_IDS(&adl_p_info),
+ INTEL_RPLU_IDS(&adl_p_info),
INTEL_DG2_IDS(&dg2_info),
INTEL_ATS_M_IDS(&ats_m_info),
INTEL_MTL_IDS(&mtl_info),
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 849baf6c3b3c..fec8bd116436 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -199,6 +199,11 @@ static const u16 subplatform_n_ids[] = {
static const u16 subplatform_rpl_ids[] = {
INTEL_RPLS_IDS(0),
INTEL_RPLP_IDS(0),
+ INTEL_RPLU_IDS(0)
+};
+
+static const u16 subplatform_rplu_ids[] = {
+ INTEL_RPLU_IDS(0),
};
static const u16 subplatform_g10_ids[] = {
@@ -268,6 +273,9 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
} else if (find_devid(devid, subplatform_rpl_ids,
ARRAY_SIZE(subplatform_rpl_ids))) {
mask = BIT(INTEL_SUBPLATFORM_RPL);
+ if (find_devid(devid, subplatform_rplu_ids,
+ ARRAY_SIZE(subplatform_rplu_ids)))
+ mask |= BIT(INTEL_SUBPLATFORM_RPLU);
} else if (find_devid(devid, subplatform_g10_ids,
ARRAY_SIZE(subplatform_g10_ids))) {
mask = BIT(INTEL_SUBPLATFORM_G10);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d588e5fd2eea..4a5cd337e4b5 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -127,6 +127,8 @@ enum intel_platform {
* bit set
*/
#define INTEL_SUBPLATFORM_N 1
+/* Sub Platform for RPL-U */
+#define INTEL_SUBPLATFORM_RPLU 2
/* MTL */
#define INTEL_SUBPLATFORM_M 0
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 4a4c190f7698..758be5fb09a2 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -684,14 +684,17 @@
INTEL_VGA_DEVICE(0xA78A, info), \
INTEL_VGA_DEVICE(0xA78B, info)
+/* RPL-U */
+#define INTEL_RPLU_IDS(info) \
+ INTEL_VGA_DEVICE(0xA721, info), \
+ INTEL_VGA_DEVICE(0xA7A1, info), \
+ INTEL_VGA_DEVICE(0xA7A9, info)
+
/* RPL-P */
#define INTEL_RPLP_IDS(info) \
INTEL_VGA_DEVICE(0xA720, info), \
- INTEL_VGA_DEVICE(0xA721, info), \
INTEL_VGA_DEVICE(0xA7A0, info), \
- INTEL_VGA_DEVICE(0xA7A1, info), \
- INTEL_VGA_DEVICE(0xA7A8, info), \
- INTEL_VGA_DEVICE(0xA7A9, info)
+ INTEL_VGA_DEVICE(0xA7A8, info)
/* DG2 */
#define INTEL_DG2_G10_IDS(info) \
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
2023-01-17 7:42 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-17 7:42 ` [Intel-gfx] [RFC 1/2] drm/i915: Add RPL-U sub platform Chaitanya Kumar Borah
@ 2023-01-17 7:42 ` Chaitanya Kumar Borah
2023-01-24 14:33 ` Jani Nikula
2023-01-17 8:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add new CDCLK step for RPL-U (rev5) Patchwork
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-17 7:42 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
A new step of 480MHz has been added on SKUs that have a RPL-U
device id to support 120Hz displays more efficiently. Use a
new quirk to identify the machine for which this change needs
to be applied.
BSpec: 55409
v2: (Matt)
- Add missing clock steps
- Correct reference clock typo
v3: - Revert to RPL-U subplatform
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 27 ++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0c107a38f9d0..a5e3497534f3 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1329,6 +1329,30 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals rplu_cdclk_table[] = {
+ { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
+ { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
+ { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
+ { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
+ { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
+ { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+
+ { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
+ { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
+ { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
+ { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
+ { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
+ { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
+
+ { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ {}
+};
+
static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{ .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
{ .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
@@ -3353,6 +3377,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
+ /* Bspec: 55409 */
+ else if (IS_ADLP_RPLU(dev_priv))
+ dev_priv->display.cdclk.table = rplu_cdclk_table;
else
dev_priv->display.cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add new CDCLK step for RPL-U (rev5)
2023-01-17 7:42 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-17 7:42 ` [Intel-gfx] [RFC 1/2] drm/i915: Add RPL-U sub platform Chaitanya Kumar Borah
2023-01-17 7:42 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
@ 2023-01-17 8:18 ` Patchwork
2023-01-17 13:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-01-17 15:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2023-01-17 8:18 UTC (permalink / raw)
To: Chaitanya Kumar Borah; +Cc: intel-gfx
== Series Details ==
Series: Add new CDCLK step for RPL-U (rev5)
URL : https://patchwork.freedesktop.org/series/111472/
State : warning
== Summary ==
Error: dim checkpatch failed
1160acd42953 drm/i915: Add RPL-U sub platform
-:91: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#91: FILE: include/drm/i915_pciids.h:688:
+#define INTEL_RPLU_IDS(info) \
+ INTEL_VGA_DEVICE(0xA721, info), \
+ INTEL_VGA_DEVICE(0xA7A1, info), \
+ INTEL_VGA_DEVICE(0xA7A9, info)
-:91: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#91: FILE: include/drm/i915_pciids.h:688:
+#define INTEL_RPLU_IDS(info) \
+ INTEL_VGA_DEVICE(0xA721, info), \
+ INTEL_VGA_DEVICE(0xA7A1, info), \
+ INTEL_VGA_DEVICE(0xA7A9, info)
total: 1 errors, 0 warnings, 1 checks, 64 lines checked
b2a1a12d2ce3 drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Add new CDCLK step for RPL-U (rev5)
2023-01-17 7:42 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
` (2 preceding siblings ...)
2023-01-17 8:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add new CDCLK step for RPL-U (rev5) Patchwork
@ 2023-01-17 13:51 ` Patchwork
2023-01-17 15:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2023-01-17 13:51 UTC (permalink / raw)
To: Chaitanya Kumar Borah; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4613 bytes --]
== Series Details ==
Series: Add new CDCLK step for RPL-U (rev5)
URL : https://patchwork.freedesktop.org/series/111472/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12589 -> Patchwork_111472v5
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/index.html
Participating hosts (44 -> 42)
------------------------------
Additional (1): fi-bsw-kefka
Missing (3): fi-kbl-soraka fi-rkl-11600 fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_111472v5 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@workarounds:
- bat-dg1-5: [PASS][1] -> [DMESG-FAIL][2] ([i915#4983])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/bat-dg1-5/igt@i915_selftest@live@workarounds.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/bat-dg1-5/igt@i915_selftest@live@workarounds.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: NOTRUN -> [FAIL][3] ([i915#6298])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
* igt@prime_vgem@basic-fence-flip:
- fi-bsw-kefka: NOTRUN -> [SKIP][4] ([fdo#109271]) +26 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/fi-bsw-kefka/igt@prime_vgem@basic-fence-flip.html
* igt@runner@aborted:
- bat-dg1-5: NOTRUN -> [FAIL][5] ([i915#4312])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/bat-dg1-5/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510: [FAIL][6] ([i915#7229]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
* igt@i915_selftest@live@gt_lrc:
- {bat-dg2-11}: [INCOMPLETE][8] ([i915#7609]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_mocs:
- {bat-adln-1}: [INCOMPLETE][10] ([i915#7884]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/bat-adln-1/igt@i915_selftest@live@gt_mocs.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/bat-adln-1/igt@i915_selftest@live@gt_mocs.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7852]: https://gitlab.freedesktop.org/drm/intel/issues/7852
[i915#7884]: https://gitlab.freedesktop.org/drm/intel/issues/7884
Build changes
-------------
* Linux: CI_DRM_12589 -> Patchwork_111472v5
CI-20190529: 20190529
CI_DRM_12589: a29e440e749278f57cf6cb90d4e915016df200fd @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7121: aa16e81259f59734230d441905b9d0f605e4a4b5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111472v5: a29e440e749278f57cf6cb90d4e915016df200fd @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
af0bcd906bfc drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
f325ff4f9951 drm/i915: Add RPL-U sub platform
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/index.html
[-- Attachment #2: Type: text/html, Size: 4867 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Add new CDCLK step for RPL-U (rev5)
2023-01-17 7:42 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
` (3 preceding siblings ...)
2023-01-17 13:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-01-17 15:36 ` Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2023-01-17 15:36 UTC (permalink / raw)
To: Chaitanya Kumar Borah; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 32420 bytes --]
== Series Details ==
Series: Add new CDCLK step for RPL-U (rev5)
URL : https://patchwork.freedesktop.org/series/111472/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12589_full -> Patchwork_111472v5_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/index.html
Participating hosts (12 -> 10)
------------------------------
Additional (1): shard-tglu-9
Missing (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005
New tests
---------
New tests have been introduced between CI_DRM_12589_full and Patchwork_111472v5_full:
### New IGT tests (128) ###
* igt@gem_ctx_engines@independent@bcs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_engines@independent@rcs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_engines@independent@vcs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_engines@independent@vcs1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@gem_ctx_engines@independent@vecs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_async@forked-writes:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_async@forked-writes@bcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_async@forked-writes@rcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_async@forked-writes@vcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_async@forked-writes@vcs1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_async@forked-writes@vecs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_balancer@fairslice:
- Statuses : 2 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_balancer@nohangcheck:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_balancer@noheartbeat:
- Statuses : 1 fail(s) 2 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_balancer@persistence:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_balancer@sequential:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_capture@capture@bcs0-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_capture@capture@rcs0-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_capture@capture@vcs0-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_capture@capture@vcs1-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_capture@capture@vecs0-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_create@legacy:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_fair@basic-deadline:
- Statuses : 2 fail(s) 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-flow:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-flow@rcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-none:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-none-rrul:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- Statuses : 3 fail(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-none-share:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-none-share@rcs0:
- Statuses : 3 fail(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-none-solo:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-none-solo@rcs0:
- Statuses : 3 fail(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-none-vip:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_fair@basic-none-vip@rcs0:
- Statuses : 3 fail(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-none@bcs0:
- Statuses : 2 fail(s) 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-none@rcs0:
- Statuses : 3 fail(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-none@vcs0:
- Statuses : 2 fail(s) 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-none@vcs1:
- Statuses : 1 fail(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-none@vecs0:
- Statuses : 2 fail(s) 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-pace:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-pace-share:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-pace-share@rcs0:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-pace-solo:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- Statuses : 2 fail(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-pace@bcs0:
- Statuses : 2 fail(s) 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-pace@rcs0:
- Statuses : 3 fail(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-pace@vcs0:
- Statuses : 3 fail(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-pace@vcs1:
- Statuses : 1 fail(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-pace@vecs0:
- Statuses : 3 fail(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-sync:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-sync@rcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-throttle:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_fair@basic-throttle@rcs0:
- Statuses : 1 fail(s) 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fairslice:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_schedule@fairslice-all:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fairslice@bcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fairslice@rcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fairslice@vcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fairslice@vcs1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fairslice@vecs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@preempt-user:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_schedule@preempt-user@bcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@preempt-user@rcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@preempt-user@vcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@preempt-user@vcs1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@preempt-user@vecs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-fairslice:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_schedule@u-fairslice-all:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-fairslice@bcs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-fairslice@rcs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-fairslice@vcs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-fairslice@vcs1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-fairslice@vecs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-independent:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_schedule@u-independent@bcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-independent@rcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-independent@vcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-independent@vcs1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-independent@vecs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-lateslice:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_schedule@u-lateslice@bcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-lateslice@rcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-lateslice@vcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-lateslice@vcs1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-lateslice@vecs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-semaphore-codependency:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-semaphore-noskip:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-semaphore-resolve:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-semaphore-user:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-submit-early-slice:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_schedule@u-submit-early-slice@bcs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-submit-early-slice@rcs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-submit-early-slice@vcs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-submit-early-slice@vcs1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-submit-early-slice@vecs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-submit-golden-slice:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_schedule@u-submit-golden-slice@bcs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-submit-golden-slice@rcs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-submit-golden-slice@vcs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-submit-golden-slice@vcs1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-submit-golden-slice@vecs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-submit-late-slice:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_schedule@u-submit-late-slice@bcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-submit-late-slice@rcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-submit-late-slice@vcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-submit-late-slice@vcs1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-submit-late-slice@vecs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_render_copy@linear-to-vebox-yf-tiled@lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_softpin@32b-excludes-last-page:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_softpin@full:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_softpin@zero:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gen9_exec_parse@shadow-peek:
- Statuses : 1 pass(s) 3 skip(s)
- Exec time: [0.0] s
* igt@kms_atomic_transition@modeset-transition:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_atomic_transition@modeset-transition-fencing:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_atomic_transition@modeset-transition-fencing@1x-outputs:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@kms_atomic_transition@modeset-transition-fencing@2x-outputs:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_atomic_transition@modeset-transition-nonblocking:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@1x-outputs:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_atomic_transition@modeset-transition-nonblocking@1x-outputs:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_atomic_transition@modeset-transition@1x-outputs:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_atomic_transition@modeset-transition@2x-outputs:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@perf@non-zero-reason:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@perf_pmu@gt-awake:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@perf_pmu@invalid-open:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@perf_pmu@rc6-suspend:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_111472v5_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-deadline (NEW):
- {shard-rkl}: [PASS][1] -> [FAIL][2] ([i915#2846])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-1/igt@gem_exec_fair@basic-deadline.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-rrul@rcs0 (NEW):
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-glk1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none@rcs0 (NEW):
- {shard-tglu}: NOTRUN -> [FAIL][5] ([i915#2842]) +11 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-tglu-7/igt@gem_exec_fair@basic-none@rcs0.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
- shard-glk: [PASS][6] -> [FAIL][7] ([i915#79])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-glk2/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-glk8/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271]) +20 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-glk5/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-glk: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#658])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-glk5/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
#### Possible fixes ####
* igt@drm_fdinfo@virtual-idle:
- {shard-rkl}: [FAIL][10] ([i915#7742]) -> [PASS][11] +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-3/igt@drm_fdinfo@virtual-idle.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-6/igt@drm_fdinfo@virtual-idle.html
* igt@gem_ctx_persistence@hang:
- {shard-rkl}: [SKIP][12] ([i915#6252]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-5/igt@gem_ctx_persistence@hang.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-3/igt@gem_ctx_persistence@hang.html
* igt@gem_eio@in-flight-suspend:
- {shard-rkl}: [FAIL][14] ([fdo#103375]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-4/igt@gem_eio@in-flight-suspend.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-1/igt@gem_eio@in-flight-suspend.html
* igt@gem_eio@reset-stress:
- {shard-dg1}: [FAIL][16] ([i915#5784]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-dg1-18/igt@gem_eio@reset-stress.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-dg1-17/igt@gem_eio@reset-stress.html
* igt@gem_exec_fair@basic-pace-share@rcs0 (NEW):
- {shard-rkl}: [FAIL][18] ([i915#2842]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_reloc@basic-write-read-active:
- {shard-rkl}: [SKIP][20] ([i915#3281]) -> [PASS][21] +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-1/igt@gem_exec_reloc@basic-write-read-active.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-5/igt@gem_exec_reloc@basic-write-read-active.html
* igt@gem_readwrite@beyond-eob:
- {shard-rkl}: [SKIP][22] ([i915#3282]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-1/igt@gem_readwrite@beyond-eob.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-5/igt@gem_readwrite@beyond-eob.html
* igt@gen9_exec_parse@bb-large:
- {shard-rkl}: [SKIP][24] ([i915#2527]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-1/igt@gen9_exec_parse@bb-large.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-5/igt@gen9_exec_parse@bb-large.html
* igt@i915_pipe_stress@stress-xrgb8888-ytiled:
- {shard-rkl}: [SKIP][26] ([i915#4098]) -> [PASS][27] +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-2/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-6/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
* igt@i915_pm_dc@dc6-dpms:
- {shard-rkl}: [SKIP][28] ([i915#3361]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-5/igt@i915_pm_dc@dc6-dpms.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-1/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_dc@dc6-psr:
- {shard-rkl}: [SKIP][30] ([i915#658]) -> [PASS][31] +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-3/igt@i915_pm_dc@dc6-psr.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-6/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@fences:
- {shard-rkl}: [SKIP][32] ([i915#1849]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-4/igt@i915_pm_rpm@fences.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-6/igt@i915_pm_rpm@fences.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-dg1}: [SKIP][34] ([i915#1397]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-dg1-19/igt@i915_pm_rpm@modeset-lpsp-stress.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-dg1-14/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_pm_rpm@system-suspend-modeset:
- {shard-rkl}: [SKIP][36] ([fdo#109308]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-2/igt@i915_pm_rpm@system-suspend-modeset.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-6/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- {shard-rkl}: [SKIP][38] ([i915#1845] / [i915#4098]) -> [PASS][39] +24 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_cursor_edge_walk@top-edge@pipe-a-hdmi-a-1-256x256:
- shard-glk: [DMESG-FAIL][40] ([i915#118]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-glk8/igt@kms_cursor_edge_walk@top-edge@pipe-a-hdmi-a-1-256x256.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-glk6/igt@kms_cursor_edge_walk@top-edge@pipe-a-hdmi-a-1-256x256.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- {shard-rkl}: [SKIP][42] ([i915#1849] / [i915#4098]) -> [PASS][43] +17 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_psr@cursor_blt:
- {shard-rkl}: [SKIP][44] ([i915#1072]) -> [PASS][45] +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-4/igt@kms_psr@cursor_blt.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-6/igt@kms_psr@cursor_blt.html
* igt@perf@gen12-oa-tlb-invalidate:
- {shard-rkl}: [SKIP][46] ([fdo#109289]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-5/igt@perf@gen12-oa-tlb-invalidate.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-3/igt@perf@gen12-oa-tlb-invalidate.html
* igt@prime_vgem@basic-fence-flip:
- {shard-rkl}: [SKIP][48] ([fdo#109295] / [i915#3708] / [i915#4098]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-3/igt@prime_vgem@basic-fence-flip.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-6/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-write:
- {shard-rkl}: [SKIP][50] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-rkl-1/igt@prime_vgem@basic-write.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-rkl-5/igt@prime_vgem@basic-write.html
* igt@sysfs_timeslice_duration@timeout@bcs0:
- {shard-dg1}: [FAIL][52] ([i915#1755]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12589/shard-dg1-17/igt@sysfs_timeslice_duration@timeout@bcs0.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/shard-dg1-17/igt@sysfs_timeslice_duration@timeout@bcs0.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12589 -> Patchwork_111472v5
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_12589: a29e440e749278f57cf6cb90d4e915016df200fd @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7121: aa16e81259f59734230d441905b9d0f605e4a4b5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111472v5: a29e440e749278f57cf6cb90d4e915016df200fd @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v5/index.html
[-- Attachment #2: Type: text/html, Size: 31523 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [RFC 1/2] drm/i915: Add RPL-U sub platform
2023-01-17 7:42 ` [Intel-gfx] [RFC 1/2] drm/i915: Add RPL-U sub platform Chaitanya Kumar Borah
@ 2023-01-24 14:32 ` Jani Nikula
2023-01-27 9:34 ` Borah, Chaitanya Kumar
0 siblings, 1 reply; 11+ messages in thread
From: Jani Nikula @ 2023-01-24 14:32 UTC (permalink / raw)
To: Chaitanya Kumar Borah, intel-gfx; +Cc: ville.syrjala
On Tue, 17 Jan 2023, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote:
> Separate out RPLU device ids and add them to both RPL and
> newly created RPL-U subplatforms.
>
> v2: (Matt)
> - Sort PCI-IDs numerically
> - Name the sub-platform to accurately depict what it is for
> - Make RPL-U part of RPL subplatform
>
> v3: revert to RPL-U subplatform (Jani)
>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.c | 8 ++++++++
> drivers/gpu/drm/i915/intel_device_info.h | 2 ++
> include/drm/i915_pciids.h | 11 +++++++----
> 5 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 48fd82722f12..c88e514728a0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -619,6 +619,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
> #define IS_ADLP_RPLP(dev_priv) \
> IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
> +#define IS_ADLP_RPLU(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 6cc65079b18d..e9f3b99b3e00 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1234,6 +1234,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_DG1_IDS(&dg1_info),
> INTEL_RPLS_IDS(&adl_s_info),
> INTEL_RPLP_IDS(&adl_p_info),
> + INTEL_RPLU_IDS(&adl_p_info),
You may want to drop this change, see later comment on how and why.
> INTEL_DG2_IDS(&dg2_info),
> INTEL_ATS_M_IDS(&ats_m_info),
> INTEL_MTL_IDS(&mtl_info),
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 849baf6c3b3c..fec8bd116436 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -199,6 +199,11 @@ static const u16 subplatform_n_ids[] = {
> static const u16 subplatform_rpl_ids[] = {
> INTEL_RPLS_IDS(0),
> INTEL_RPLP_IDS(0),
> + INTEL_RPLU_IDS(0)
Please always include the trailing , at the end to make future changes
easier. (However, you may want to drop this change altogether, see later
comment.)
> +};
> +
> +static const u16 subplatform_rplu_ids[] = {
> + INTEL_RPLU_IDS(0),
> };
>
> static const u16 subplatform_g10_ids[] = {
> @@ -268,6 +273,9 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> } else if (find_devid(devid, subplatform_rpl_ids,
> ARRAY_SIZE(subplatform_rpl_ids))) {
> mask = BIT(INTEL_SUBPLATFORM_RPL);
> + if (find_devid(devid, subplatform_rplu_ids,
> + ARRAY_SIZE(subplatform_rplu_ids)))
> + mask |= BIT(INTEL_SUBPLATFORM_RPLU);
> } else if (find_devid(devid, subplatform_g10_ids,
> ARRAY_SIZE(subplatform_g10_ids))) {
> mask = BIT(INTEL_SUBPLATFORM_G10);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index d588e5fd2eea..4a5cd337e4b5 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -127,6 +127,8 @@ enum intel_platform {
> * bit set
> */
> #define INTEL_SUBPLATFORM_N 1
> +/* Sub Platform for RPL-U */
This comment really adds nothing, it's exactly the same as the macro
name.
> +#define INTEL_SUBPLATFORM_RPLU 2
>
> /* MTL */
> #define INTEL_SUBPLATFORM_M 0
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 4a4c190f7698..758be5fb09a2 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -684,14 +684,17 @@
> INTEL_VGA_DEVICE(0xA78A, info), \
> INTEL_VGA_DEVICE(0xA78B, info)
>
> +/* RPL-U */
> +#define INTEL_RPLU_IDS(info) \
> + INTEL_VGA_DEVICE(0xA721, info), \
> + INTEL_VGA_DEVICE(0xA7A1, info), \
> + INTEL_VGA_DEVICE(0xA7A9, info)
> +
> /* RPL-P */
> #define INTEL_RPLP_IDS(info) \
> INTEL_VGA_DEVICE(0xA720, info), \
> - INTEL_VGA_DEVICE(0xA721, info), \
> INTEL_VGA_DEVICE(0xA7A0, info), \
> - INTEL_VGA_DEVICE(0xA7A1, info), \
> - INTEL_VGA_DEVICE(0xA7A8, info), \
> - INTEL_VGA_DEVICE(0xA7A9, info)
> + INTEL_VGA_DEVICE(0xA7A8, info)
Changing the INTEL_RPLP_IDS impacts arch/x86/kernel/early-quirks.c
too. As is, this drops the early quirks from RPL-U.
Your options are 1) modify early-quirks.c too, or 2) include RPL-U ids
in RPL-P:
#define INTEL_RPLP_IDS(info) \
+ INTEL_RPLU_IDS(info), \
- INTEL_VGA_DEVICE(0xA721, info), \
INTEL_VGA_DEVICE(0xA7A0, info), \
- INTEL_VGA_DEVICE(0xA7A1, info), \
- INTEL_VGA_DEVICE(0xA7A8, info), \
- INTEL_VGA_DEVICE(0xA7A9, info)
+ INTEL_VGA_DEVICE(0xA7A8, info)
With option 2, you also don't need to add INTEL_RPLU_IDS separately to
subplatform_rpl_ids[] or pciidlist[].
I might lean towards option 2, but no strong opinions.
BR,
Jani.
>
> /* DG2 */
> #define INTEL_DG2_G10_IDS(info) \
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
2023-01-17 7:42 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
@ 2023-01-24 14:33 ` Jani Nikula
0 siblings, 0 replies; 11+ messages in thread
From: Jani Nikula @ 2023-01-24 14:33 UTC (permalink / raw)
To: Chaitanya Kumar Borah, intel-gfx; +Cc: ville.syrjala
On Tue, 17 Jan 2023, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote:
> A new step of 480MHz has been added on SKUs that have a RPL-U
> device id to support 120Hz displays more efficiently. Use a
> new quirk to identify the machine for which this change needs
> to be applied.
>
> BSpec: 55409
>
> v2: (Matt)
> - Add missing clock steps
> - Correct reference clock typo
>
> v3: - Revert to RPL-U subplatform
>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 27 ++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 0c107a38f9d0..a5e3497534f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1329,6 +1329,30 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
> {}
> };
>
> +static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> + { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> + { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> + { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> + { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> + { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> + { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> +
> + { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> + { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> + { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> + { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> + { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> + { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> +
> + { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> + { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> + {}
> +};
> +
> static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
> { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
> @@ -3353,6 +3377,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> /* Wa_22011320316:adl-p[a0] */
> if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
> + /* Bspec: 55409 */
Please let's not add bspec references in comments.
BR,
Jani.
> + else if (IS_ADLP_RPLU(dev_priv))
> + dev_priv->display.cdclk.table = rplu_cdclk_table;
> else
> dev_priv->display.cdclk.table = adlp_cdclk_table;
> } else if (IS_ROCKETLAKE(dev_priv)) {
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [RFC 1/2] drm/i915: Add RPL-U sub platform
2023-01-24 14:32 ` Jani Nikula
@ 2023-01-27 9:34 ` Borah, Chaitanya Kumar
2023-01-27 18:04 ` Matt Roper
0 siblings, 1 reply; 11+ messages in thread
From: Borah, Chaitanya Kumar @ 2023-01-27 9:34 UTC (permalink / raw)
To: Roper, Matthew D, Jani Nikula
Cc: intel-gfx@lists.freedesktop.org, Syrjala, Ville
Hello Jani and Matt,
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Tuesday, January 24, 2023 8:02 PM
> To: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Syrjala, Ville
> <ville.syrjala@intel.com>; Srivatsa, Anusha <anusha.srivatsa@intel.com>;
> Roper, Matthew D <matthew.d.roper@intel.com>; Atwood, Matthew S
> <matthew.s.atwood@intel.com>; Borah, Chaitanya Kumar
> <chaitanya.kumar.borah@intel.com>
> Subject: Re: [RFC 1/2] drm/i915: Add RPL-U sub platform
>
> On Tue, 17 Jan 2023, Chaitanya Kumar Borah
> <chaitanya.kumar.borah@intel.com> wrote:
> > Separate out RPLU device ids and add them to both RPL and newly
> > created RPL-U subplatforms.
> >
> > v2: (Matt)
> > - Sort PCI-IDs numerically
> > - Name the sub-platform to accurately depict what it is for
> > - Make RPL-U part of RPL subplatform
> >
> > v3: revert to RPL-U subplatform (Jani)
> >
> > Signed-off-by: Chaitanya Kumar Borah
> <chaitanya.kumar.borah@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > drivers/gpu/drm/i915/intel_device_info.c | 8 ++++++++
> > drivers/gpu/drm/i915/intel_device_info.h | 2 ++
> > include/drm/i915_pciids.h | 11 +++++++----
> > 5 files changed, 20 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 48fd82722f12..c88e514728a0
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -619,6 +619,8 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
> > IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P,
> INTEL_SUBPLATFORM_N)
> > #define IS_ADLP_RPLP(dev_priv) \
> > IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P,
> INTEL_SUBPLATFORM_RPL)
> > +#define IS_ADLP_RPLU(dev_priv) \
> > + IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P,
> INTEL_SUBPLATFORM_RPLU)
> > #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> > (INTEL_DEVID(dev_priv) & 0xFF00) ==
> 0x0C00) #define
> > IS_BDW_ULT(dev_priv) \ diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c index 6cc65079b18d..e9f3b99b3e00
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -1234,6 +1234,7 @@ static const struct pci_device_id pciidlist[] = {
> > INTEL_DG1_IDS(&dg1_info),
> > INTEL_RPLS_IDS(&adl_s_info),
> > INTEL_RPLP_IDS(&adl_p_info),
> > + INTEL_RPLU_IDS(&adl_p_info),
>
> You may want to drop this change, see later comment on how and why.
>
> > INTEL_DG2_IDS(&dg2_info),
> > INTEL_ATS_M_IDS(&ats_m_info),
> > INTEL_MTL_IDS(&mtl_info),
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index 849baf6c3b3c..fec8bd116436 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -199,6 +199,11 @@ static const u16 subplatform_n_ids[] = { static
> > const u16 subplatform_rpl_ids[] = {
> > INTEL_RPLS_IDS(0),
> > INTEL_RPLP_IDS(0),
> > + INTEL_RPLU_IDS(0)
>
> Please always include the trailing , at the end to make future changes easier.
> (However, you may want to drop this change altogether, see later
> comment.)
>
> > +};
> > +
> > +static const u16 subplatform_rplu_ids[] = {
> > + INTEL_RPLU_IDS(0),
> > };
> >
> > static const u16 subplatform_g10_ids[] = { @@ -268,6 +273,9 @@ static
> > void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> > } else if (find_devid(devid, subplatform_rpl_ids,
> > ARRAY_SIZE(subplatform_rpl_ids))) {
> > mask = BIT(INTEL_SUBPLATFORM_RPL);
> > + if (find_devid(devid, subplatform_rplu_ids,
> > + ARRAY_SIZE(subplatform_rplu_ids)))
> > + mask |= BIT(INTEL_SUBPLATFORM_RPLU);
> > } else if (find_devid(devid, subplatform_g10_ids,
> > ARRAY_SIZE(subplatform_g10_ids))) {
> > mask = BIT(INTEL_SUBPLATFORM_G10);
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index d588e5fd2eea..4a5cd337e4b5 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -127,6 +127,8 @@ enum intel_platform {
> > * bit set
> > */
> > #define INTEL_SUBPLATFORM_N 1
> > +/* Sub Platform for RPL-U */
>
> This comment really adds nothing, it's exactly the same as the macro name.
>
Ack.
> > +#define INTEL_SUBPLATFORM_RPLU 2
> >
> > /* MTL */
> > #define INTEL_SUBPLATFORM_M 0
> > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> > index 4a4c190f7698..758be5fb09a2 100644
> > --- a/include/drm/i915_pciids.h
> > +++ b/include/drm/i915_pciids.h
> > @@ -684,14 +684,17 @@
> > INTEL_VGA_DEVICE(0xA78A, info), \
> > INTEL_VGA_DEVICE(0xA78B, info)
> >
> > +/* RPL-U */
> > +#define INTEL_RPLU_IDS(info) \
> > + INTEL_VGA_DEVICE(0xA721, info), \
> > + INTEL_VGA_DEVICE(0xA7A1, info), \
> > + INTEL_VGA_DEVICE(0xA7A9, info)
> > +
> > /* RPL-P */
> > #define INTEL_RPLP_IDS(info) \
> > INTEL_VGA_DEVICE(0xA720, info), \
> > - INTEL_VGA_DEVICE(0xA721, info), \
> > INTEL_VGA_DEVICE(0xA7A0, info), \
> > - INTEL_VGA_DEVICE(0xA7A1, info), \
> > - INTEL_VGA_DEVICE(0xA7A8, info), \
> > - INTEL_VGA_DEVICE(0xA7A9, info)
> > + INTEL_VGA_DEVICE(0xA7A8, info)
>
> Changing the INTEL_RPLP_IDS impacts arch/x86/kernel/early-quirks.c too. As
> is, this drops the early quirks from RPL-U.
>
Yes I missed the early quirks part in this revision. Thank you Jani for pointing out.
> Your options are 1) modify early-quirks.c too, or 2) include RPL-U ids in RPL-P:
>
> #define INTEL_RPLP_IDS(info) \
> + INTEL_RPLU_IDS(info), \
> - INTEL_VGA_DEVICE(0xA721, info), \
> INTEL_VGA_DEVICE(0xA7A0, info), \
> - INTEL_VGA_DEVICE(0xA7A1, info), \
> - INTEL_VGA_DEVICE(0xA7A8, info), \
> - INTEL_VGA_DEVICE(0xA7A9, info)
> + INTEL_VGA_DEVICE(0xA7A8, info)
>
> With option 2, you also don't need to add INTEL_RPLU_IDS separately to
> subplatform_rpl_ids[] or pciidlist[].
>
> I might lean towards option 2, but no strong opinions.
>
Thank you Jani for your suggestion. I am also inclined to the solution of adding RPLU IDs to RPLP platform.
To summarize, we would add the INTEL_RPLU_IDS(info) into INTEL_RPLP_IDS(info). As Jani pointed out, with this, there is no need to add INTEL_RPLU_IDS separately to
subplatform_rpl_ids[] or pciidlist[]. This also aligns with Bspec(55376) as RPL-U ids are listed under "RPL-P SKUs and Device IDs Info"
@Matt: I remember, we had discussed a similar option in our communications. Do you have any strong opinion against it?
If not I would go ahead with this implementation.
Regards
Chaitanya
>
> BR,
> Jani.
>
>
> >
> > /* DG2 */
> > #define INTEL_DG2_G10_IDS(info) \
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [RFC 1/2] drm/i915: Add RPL-U sub platform
2023-01-27 9:34 ` Borah, Chaitanya Kumar
@ 2023-01-27 18:04 ` Matt Roper
2023-01-30 10:19 ` Borah, Chaitanya Kumar
0 siblings, 1 reply; 11+ messages in thread
From: Matt Roper @ 2023-01-27 18:04 UTC (permalink / raw)
To: Borah, Chaitanya Kumar; +Cc: Syrjala, Ville, intel-gfx@lists.freedesktop.org
On Fri, Jan 27, 2023 at 01:34:31AM -0800, Borah, Chaitanya Kumar wrote:
> Hello Jani and Matt,
>
> > -----Original Message-----
> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > Sent: Tuesday, January 24, 2023 8:02 PM
> > To: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Cc: Shankar, Uma <uma.shankar@intel.com>; Syrjala, Ville
> > <ville.syrjala@intel.com>; Srivatsa, Anusha <anusha.srivatsa@intel.com>;
> > Roper, Matthew D <matthew.d.roper@intel.com>; Atwood, Matthew S
> > <matthew.s.atwood@intel.com>; Borah, Chaitanya Kumar
> > <chaitanya.kumar.borah@intel.com>
> > Subject: Re: [RFC 1/2] drm/i915: Add RPL-U sub platform
> >
> > On Tue, 17 Jan 2023, Chaitanya Kumar Borah
> > <chaitanya.kumar.borah@intel.com> wrote:
> > > Separate out RPLU device ids and add them to both RPL and newly
> > > created RPL-U subplatforms.
> > >
> > > v2: (Matt)
> > > - Sort PCI-IDs numerically
> > > - Name the sub-platform to accurately depict what it is for
> > > - Make RPL-U part of RPL subplatform
> > >
> > > v3: revert to RPL-U subplatform (Jani)
> > >
> > > Signed-off-by: Chaitanya Kumar Borah
> > <chaitanya.kumar.borah@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > > drivers/gpu/drm/i915/intel_device_info.c | 8 ++++++++
> > > drivers/gpu/drm/i915/intel_device_info.h | 2 ++
> > > include/drm/i915_pciids.h | 11 +++++++----
> > > 5 files changed, 20 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h index 48fd82722f12..c88e514728a0
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -619,6 +619,8 @@ IS_SUBPLATFORM(const struct drm_i915_private
> > *i915,
> > > IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P,
> > INTEL_SUBPLATFORM_N)
> > > #define IS_ADLP_RPLP(dev_priv) \
> > > IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P,
> > INTEL_SUBPLATFORM_RPL)
> > > +#define IS_ADLP_RPLU(dev_priv) \
> > > + IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P,
> > INTEL_SUBPLATFORM_RPLU)
> > > #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> > > (INTEL_DEVID(dev_priv) & 0xFF00) ==
> > 0x0C00) #define
> > > IS_BDW_ULT(dev_priv) \ diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > > b/drivers/gpu/drm/i915/i915_pci.c index 6cc65079b18d..e9f3b99b3e00
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -1234,6 +1234,7 @@ static const struct pci_device_id pciidlist[] = {
> > > INTEL_DG1_IDS(&dg1_info),
> > > INTEL_RPLS_IDS(&adl_s_info),
> > > INTEL_RPLP_IDS(&adl_p_info),
> > > + INTEL_RPLU_IDS(&adl_p_info),
> >
> > You may want to drop this change, see later comment on how and why.
> >
> > > INTEL_DG2_IDS(&dg2_info),
> > > INTEL_ATS_M_IDS(&ats_m_info),
> > > INTEL_MTL_IDS(&mtl_info),
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > > b/drivers/gpu/drm/i915/intel_device_info.c
> > > index 849baf6c3b3c..fec8bd116436 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > @@ -199,6 +199,11 @@ static const u16 subplatform_n_ids[] = { static
> > > const u16 subplatform_rpl_ids[] = {
> > > INTEL_RPLS_IDS(0),
> > > INTEL_RPLP_IDS(0),
> > > + INTEL_RPLU_IDS(0)
> >
> > Please always include the trailing , at the end to make future changes easier.
> > (However, you may want to drop this change altogether, see later
> > comment.)
> >
> > > +};
> > > +
> > > +static const u16 subplatform_rplu_ids[] = {
> > > + INTEL_RPLU_IDS(0),
> > > };
> > >
> > > static const u16 subplatform_g10_ids[] = { @@ -268,6 +273,9 @@ static
> > > void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> > > } else if (find_devid(devid, subplatform_rpl_ids,
> > > ARRAY_SIZE(subplatform_rpl_ids))) {
> > > mask = BIT(INTEL_SUBPLATFORM_RPL);
> > > + if (find_devid(devid, subplatform_rplu_ids,
> > > + ARRAY_SIZE(subplatform_rplu_ids)))
> > > + mask |= BIT(INTEL_SUBPLATFORM_RPLU);
> > > } else if (find_devid(devid, subplatform_g10_ids,
> > > ARRAY_SIZE(subplatform_g10_ids))) {
> > > mask = BIT(INTEL_SUBPLATFORM_G10);
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > > b/drivers/gpu/drm/i915/intel_device_info.h
> > > index d588e5fd2eea..4a5cd337e4b5 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > @@ -127,6 +127,8 @@ enum intel_platform {
> > > * bit set
> > > */
> > > #define INTEL_SUBPLATFORM_N 1
> > > +/* Sub Platform for RPL-U */
> >
> > This comment really adds nothing, it's exactly the same as the macro name.
> >
>
> Ack.
>
> > > +#define INTEL_SUBPLATFORM_RPLU 2
> > >
> > > /* MTL */
> > > #define INTEL_SUBPLATFORM_M 0
> > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> > > index 4a4c190f7698..758be5fb09a2 100644
> > > --- a/include/drm/i915_pciids.h
> > > +++ b/include/drm/i915_pciids.h
> > > @@ -684,14 +684,17 @@
> > > INTEL_VGA_DEVICE(0xA78A, info), \
> > > INTEL_VGA_DEVICE(0xA78B, info)
> > >
> > > +/* RPL-U */
> > > +#define INTEL_RPLU_IDS(info) \
> > > + INTEL_VGA_DEVICE(0xA721, info), \
> > > + INTEL_VGA_DEVICE(0xA7A1, info), \
> > > + INTEL_VGA_DEVICE(0xA7A9, info)
> > > +
> > > /* RPL-P */
> > > #define INTEL_RPLP_IDS(info) \
> > > INTEL_VGA_DEVICE(0xA720, info), \
> > > - INTEL_VGA_DEVICE(0xA721, info), \
> > > INTEL_VGA_DEVICE(0xA7A0, info), \
> > > - INTEL_VGA_DEVICE(0xA7A1, info), \
> > > - INTEL_VGA_DEVICE(0xA7A8, info), \
> > > - INTEL_VGA_DEVICE(0xA7A9, info)
> > > + INTEL_VGA_DEVICE(0xA7A8, info)
> >
> > Changing the INTEL_RPLP_IDS impacts arch/x86/kernel/early-quirks.c too. As
> > is, this drops the early quirks from RPL-U.
> >
>
> Yes I missed the early quirks part in this revision. Thank you Jani for pointing out.
>
> > Your options are 1) modify early-quirks.c too, or 2) include RPL-U ids in RPL-P:
> >
> > #define INTEL_RPLP_IDS(info) \
> > + INTEL_RPLU_IDS(info), \
> > - INTEL_VGA_DEVICE(0xA721, info), \
> > INTEL_VGA_DEVICE(0xA7A0, info), \
> > - INTEL_VGA_DEVICE(0xA7A1, info), \
> > - INTEL_VGA_DEVICE(0xA7A8, info), \
> > - INTEL_VGA_DEVICE(0xA7A9, info)
> > + INTEL_VGA_DEVICE(0xA7A8, info)
> >
> > With option 2, you also don't need to add INTEL_RPLU_IDS separately to
> > subplatform_rpl_ids[] or pciidlist[].
> >
> > I might lean towards option 2, but no strong opinions.
> >
>
> Thank you Jani for your suggestion. I am also inclined to the solution of adding RPLU IDs to RPLP platform.
>
> To summarize, we would add the INTEL_RPLU_IDS(info) into INTEL_RPLP_IDS(info). As Jani pointed out, with this, there is no need to add INTEL_RPLU_IDS separately to
> subplatform_rpl_ids[] or pciidlist[]. This also aligns with Bspec(55376) as RPL-U ids are listed under "RPL-P SKUs and Device IDs Info"
>
> @Matt: I remember, we had discussed a similar option in our communications. Do you have any strong opinion against it?
That sounds fine to me.
Thanks.
Matt
>
> If not I would go ahead with this implementation.
>
> Regards
>
> Chaitanya
>
> >
> > BR,
> > Jani.
> >
> >
> > >
> > > /* DG2 */
> > > #define INTEL_DG2_G10_IDS(info) \
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [RFC 1/2] drm/i915: Add RPL-U sub platform
2023-01-27 18:04 ` Matt Roper
@ 2023-01-30 10:19 ` Borah, Chaitanya Kumar
0 siblings, 0 replies; 11+ messages in thread
From: Borah, Chaitanya Kumar @ 2023-01-30 10:19 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: Syrjala, Ville, intel-gfx@lists.freedesktop.org
Hello,
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Friday, January 27, 2023 11:35 PM
> To: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>; Srivatsa,
> Anusha <anusha.srivatsa@intel.com>; Atwood, Matthew S
> <matthew.s.atwood@intel.com>; intel-gfx@lists.freedesktop.org
> Subject: Re: [RFC 1/2] drm/i915: Add RPL-U sub platform
>
> On Fri, Jan 27, 2023 at 01:34:31AM -0800, Borah, Chaitanya Kumar wrote:
> > Hello Jani and Matt,
> >
> > > -----Original Message-----
> > > From: Jani Nikula <jani.nikula@linux.intel.com>
> > > Sent: Tuesday, January 24, 2023 8:02 PM
> > > To: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>; intel-
> > > gfx@lists.freedesktop.org
> > > Cc: Shankar, Uma <uma.shankar@intel.com>; Syrjala, Ville
> > > <ville.syrjala@intel.com>; Srivatsa, Anusha
> > > <anusha.srivatsa@intel.com>; Roper, Matthew D
> > > <matthew.d.roper@intel.com>; Atwood, Matthew S
> > > <matthew.s.atwood@intel.com>; Borah, Chaitanya Kumar
> > > <chaitanya.kumar.borah@intel.com>
> > > Subject: Re: [RFC 1/2] drm/i915: Add RPL-U sub platform
> > >
> > > On Tue, 17 Jan 2023, Chaitanya Kumar Borah
> > > <chaitanya.kumar.borah@intel.com> wrote:
> > > > Separate out RPLU device ids and add them to both RPL and newly
> > > > created RPL-U subplatforms.
> > > >
> > > > v2: (Matt)
> > > > - Sort PCI-IDs numerically
> > > > - Name the sub-platform to accurately depict what it is for
> > > > - Make RPL-U part of RPL subplatform
> > > >
> > > > v3: revert to RPL-U subplatform (Jani)
> > > >
> > > > Signed-off-by: Chaitanya Kumar Borah
> > > <chaitanya.kumar.borah@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > > > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > > > drivers/gpu/drm/i915/intel_device_info.c | 8 ++++++++
> > > > drivers/gpu/drm/i915/intel_device_info.h | 2 ++
> > > > include/drm/i915_pciids.h | 11 +++++++----
> > > > 5 files changed, 20 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > > b/drivers/gpu/drm/i915/i915_drv.h index 48fd82722f12..c88e514728a0
> > > > 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > @@ -619,6 +619,8 @@ IS_SUBPLATFORM(const struct
> drm_i915_private
> > > *i915,
> > > > IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P,
> > > INTEL_SUBPLATFORM_N)
> > > > #define IS_ADLP_RPLP(dev_priv) \
> > > > IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P,
> > > INTEL_SUBPLATFORM_RPL)
> > > > +#define IS_ADLP_RPLU(dev_priv) \
> > > > + IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P,
> > > INTEL_SUBPLATFORM_RPLU)
> > > > #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> > > > (INTEL_DEVID(dev_priv) & 0xFF00) ==
> > > 0x0C00) #define
> > > > IS_BDW_ULT(dev_priv) \ diff --git
> > > > a/drivers/gpu/drm/i915/i915_pci.c
> > > > b/drivers/gpu/drm/i915/i915_pci.c index 6cc65079b18d..e9f3b99b3e00
> > > > 100644
> > > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > > @@ -1234,6 +1234,7 @@ static const struct pci_device_id pciidlist[] = {
> > > > INTEL_DG1_IDS(&dg1_info),
> > > > INTEL_RPLS_IDS(&adl_s_info),
> > > > INTEL_RPLP_IDS(&adl_p_info),
> > > > + INTEL_RPLU_IDS(&adl_p_info),
> > >
> > > You may want to drop this change, see later comment on how and why.
> > >
> > > > INTEL_DG2_IDS(&dg2_info),
> > > > INTEL_ATS_M_IDS(&ats_m_info),
> > > > INTEL_MTL_IDS(&mtl_info),
> > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > > > b/drivers/gpu/drm/i915/intel_device_info.c
> > > > index 849baf6c3b3c..fec8bd116436 100644
> > > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > > @@ -199,6 +199,11 @@ static const u16 subplatform_n_ids[] = {
> > > > static const u16 subplatform_rpl_ids[] = {
> > > > INTEL_RPLS_IDS(0),
> > > > INTEL_RPLP_IDS(0),
> > > > + INTEL_RPLU_IDS(0)
> > >
> > > Please always include the trailing , at the end to make future changes
> easier.
> > > (However, you may want to drop this change altogether, see later
> > > comment.)
> > >
> > > > +};
> > > > +
> > > > +static const u16 subplatform_rplu_ids[] = {
> > > > + INTEL_RPLU_IDS(0),
> > > > };
> > > >
> > > > static const u16 subplatform_g10_ids[] = { @@ -268,6 +273,9 @@
> > > > static void intel_device_info_subplatform_init(struct drm_i915_private
> *i915)
> > > > } else if (find_devid(devid, subplatform_rpl_ids,
> > > > ARRAY_SIZE(subplatform_rpl_ids))) {
> > > > mask = BIT(INTEL_SUBPLATFORM_RPL);
> > > > + if (find_devid(devid, subplatform_rplu_ids,
> > > > + ARRAY_SIZE(subplatform_rplu_ids)))
> > > > + mask |= BIT(INTEL_SUBPLATFORM_RPLU);
> > > > } else if (find_devid(devid, subplatform_g10_ids,
> > > > ARRAY_SIZE(subplatform_g10_ids))) {
> > > > mask = BIT(INTEL_SUBPLATFORM_G10); diff --git
> > > > a/drivers/gpu/drm/i915/intel_device_info.h
> > > > b/drivers/gpu/drm/i915/intel_device_info.h
> > > > index d588e5fd2eea..4a5cd337e4b5 100644
> > > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > > @@ -127,6 +127,8 @@ enum intel_platform {
> > > > * bit set
> > > > */
> > > > #define INTEL_SUBPLATFORM_N 1
> > > > +/* Sub Platform for RPL-U */
> > >
> > > This comment really adds nothing, it's exactly the same as the macro
> name.
> > >
> >
> > Ack.
> >
> > > > +#define INTEL_SUBPLATFORM_RPLU 2
> > > >
> > > > /* MTL */
> > > > #define INTEL_SUBPLATFORM_M 0
> > > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> > > > index 4a4c190f7698..758be5fb09a2 100644
> > > > --- a/include/drm/i915_pciids.h
> > > > +++ b/include/drm/i915_pciids.h
> > > > @@ -684,14 +684,17 @@
> > > > INTEL_VGA_DEVICE(0xA78A, info), \
> > > > INTEL_VGA_DEVICE(0xA78B, info)
> > > >
> > > > +/* RPL-U */
> > > > +#define INTEL_RPLU_IDS(info) \
> > > > + INTEL_VGA_DEVICE(0xA721, info), \
> > > > + INTEL_VGA_DEVICE(0xA7A1, info), \
> > > > + INTEL_VGA_DEVICE(0xA7A9, info)
> > > > +
> > > > /* RPL-P */
> > > > #define INTEL_RPLP_IDS(info) \
> > > > INTEL_VGA_DEVICE(0xA720, info), \
> > > > - INTEL_VGA_DEVICE(0xA721, info), \
> > > > INTEL_VGA_DEVICE(0xA7A0, info), \
> > > > - INTEL_VGA_DEVICE(0xA7A1, info), \
> > > > - INTEL_VGA_DEVICE(0xA7A8, info), \
> > > > - INTEL_VGA_DEVICE(0xA7A9, info)
> > > > + INTEL_VGA_DEVICE(0xA7A8, info)
> > >
> > > Changing the INTEL_RPLP_IDS impacts arch/x86/kernel/early-quirks.c
> > > too. As is, this drops the early quirks from RPL-U.
> > >
> >
> > Yes I missed the early quirks part in this revision. Thank you Jani for
> pointing out.
> >
> > > Your options are 1) modify early-quirks.c too, or 2) include RPL-U ids in
> RPL-P:
> > >
> > > #define INTEL_RPLP_IDS(info) \
> > > + INTEL_RPLU_IDS(info), \
> > > - INTEL_VGA_DEVICE(0xA721, info), \
> > > INTEL_VGA_DEVICE(0xA7A0, info), \
> > > - INTEL_VGA_DEVICE(0xA7A1, info), \
> > > - INTEL_VGA_DEVICE(0xA7A8, info), \
> > > - INTEL_VGA_DEVICE(0xA7A9, info)
> > > + INTEL_VGA_DEVICE(0xA7A8, info)
> > >
> > > With option 2, you also don't need to add INTEL_RPLU_IDS separately
> > > to subplatform_rpl_ids[] or pciidlist[].
> > >
> > > I might lean towards option 2, but no strong opinions.
> > >
> >
> > Thank you Jani for your suggestion. I am also inclined to the solution of
> adding RPLU IDs to RPLP platform.
> >
> > To summarize, we would add the INTEL_RPLU_IDS(info) into
> > INTEL_RPLP_IDS(info). As Jani pointed out, with this, there is no need to
> add INTEL_RPLU_IDS separately to subplatform_rpl_ids[] or pciidlist[]. This
> also aligns with Bspec(55376) as RPL-U ids are listed under "RPL-P SKUs and
> Device IDs Info"
> >
> > @Matt: I remember, we had discussed a similar option in our
> communications. Do you have any strong opinion against it?
>
> That sounds fine to me.
>
> Thanks.
>
Thank you Matt. I have floated a new series based on these comments.
Regards
Chaitanya
>
> Matt
>
> >
> > If not I would go ahead with this implementation.
> >
> > Regards
> >
> > Chaitanya
> >
> > >
> > > BR,
> > > Jani.
> > >
> > >
> > > >
> > > > /* DG2 */
> > > > #define INTEL_DG2_G10_IDS(info) \
> > >
> > > --
> > > Jani Nikula, Intel Open Source Graphics Center
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2023-01-30 10:19 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-01-17 7:42 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-17 7:42 ` [Intel-gfx] [RFC 1/2] drm/i915: Add RPL-U sub platform Chaitanya Kumar Borah
2023-01-24 14:32 ` Jani Nikula
2023-01-27 9:34 ` Borah, Chaitanya Kumar
2023-01-27 18:04 ` Matt Roper
2023-01-30 10:19 ` Borah, Chaitanya Kumar
2023-01-17 7:42 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
2023-01-24 14:33 ` Jani Nikula
2023-01-17 8:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add new CDCLK step for RPL-U (rev5) Patchwork
2023-01-17 13:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-01-17 15:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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