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* [PATCH] drm/i915/glk: Enable cold boot for GLK DSI
@ 2017-06-04  8:35 Madhav Chauhan
  2017-06-04  8:58 ` ✓ Fi.CI.BAT: success for " Patchwork
  2017-06-08 12:21 ` [PATCH] " Jani Nikula
  0 siblings, 2 replies; 3+ messages in thread
From: Madhav Chauhan @ 2017-06-04  8:35 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, ander.conselvan.de.oliveira, shashidhar.hiremath

As per BSEPC, if device ready bit is '0' in enable IO sequence
then its a cold boot/reset scenario eg: S3/S4 resume. In these
conditions we need to program certain registers and prepare port
from the middle of DSI enable sequence otherwise feature like S3/S4
doesn't work.

V2: Do not assume that on enable when power has not been lost,
all the registers contain the correct information already.
Program DSI registers for normal boot scenario from
glk_dsi_device_ready() (Jani N).

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 82 +++++++++++++++++++++++++---------------
 1 file changed, 51 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index fc0ef49..5582859 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -346,12 +346,17 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 	return true;
 }
 
-static void glk_dsi_device_ready(struct intel_encoder *encoder)
+static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
+			      struct intel_crtc_state *pipe_config);
+
+static void glk_dsi_device_ready(struct intel_encoder *encoder,
+				 struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port;
 	u32 tmp, val;
+	bool cold_boot = false;
 
 	/* Set the MIPI mode
 	 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
@@ -370,7 +375,10 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
 	/* Program LP Wake */
 	for_each_dsi_port(port, intel_dsi->ports) {
 		tmp = I915_READ(MIPI_CTRL(port));
-		tmp |= GLK_LP_WAKE;
+		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
+			tmp &= ~GLK_LP_WAKE;
+		else
+			tmp |= GLK_LP_WAKE;
 		I915_WRITE(MIPI_CTRL(port), tmp);
 	}
 
@@ -382,6 +390,15 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
 			DRM_ERROR("MIPIO port is powergated\n");
 	}
 
+	/* Check if cold boot scenario */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) &
+							DEVICE_READY);
+	}
+
+	if (cold_boot)
+		intel_dsi_prepare(encoder, pipe_config);
+
 	/* Wait for MIPI PHY status bit to set */
 	for_each_dsi_port(port, intel_dsi->ports) {
 		if (intel_wait_for_register(dev_priv,
@@ -402,34 +419,34 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
 			val |= DEVICE_READY;
 			I915_WRITE(MIPI_DEVICE_READY(port), val);
 			usleep_range(10, 15);
-		}
-
-		/* Enter ULPS */
-		val = I915_READ(MIPI_DEVICE_READY(port));
-		val &= ~ULPS_STATE_MASK;
-		val |= (ULPS_STATE_ENTER | DEVICE_READY);
-		I915_WRITE(MIPI_DEVICE_READY(port), val);
+		} else {
+			/* Enter ULPS */
+			val = I915_READ(MIPI_DEVICE_READY(port));
+			val &= ~ULPS_STATE_MASK;
+			val |= (ULPS_STATE_ENTER | DEVICE_READY);
+			I915_WRITE(MIPI_DEVICE_READY(port), val);
 
-		/* Wait for ULPS active */
-		if (intel_wait_for_register(dev_priv,
+			/* Wait for ULPS active */
+			if (intel_wait_for_register(dev_priv,
 				MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20))
-			DRM_ERROR("ULPS not active\n");
+				DRM_ERROR("ULPS not active\n");
 
-		/* Exit ULPS */
-		val = I915_READ(MIPI_DEVICE_READY(port));
-		val &= ~ULPS_STATE_MASK;
-		val |= (ULPS_STATE_EXIT | DEVICE_READY);
-		I915_WRITE(MIPI_DEVICE_READY(port), val);
+			/* Exit ULPS */
+			val = I915_READ(MIPI_DEVICE_READY(port));
+			val &= ~ULPS_STATE_MASK;
+			val |= (ULPS_STATE_EXIT | DEVICE_READY);
+			I915_WRITE(MIPI_DEVICE_READY(port), val);
 
-		/* Enter Normal Mode */
-		val = I915_READ(MIPI_DEVICE_READY(port));
-		val &= ~ULPS_STATE_MASK;
-		val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
-		I915_WRITE(MIPI_DEVICE_READY(port), val);
+			/* Enter Normal Mode */
+			val = I915_READ(MIPI_DEVICE_READY(port));
+			val &= ~ULPS_STATE_MASK;
+			val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
+			I915_WRITE(MIPI_DEVICE_READY(port), val);
 
-		tmp = I915_READ(MIPI_CTRL(port));
-		tmp &= ~GLK_LP_WAKE;
-		I915_WRITE(MIPI_CTRL(port), tmp);
+			tmp = I915_READ(MIPI_CTRL(port));
+			tmp &= ~GLK_LP_WAKE;
+			I915_WRITE(MIPI_CTRL(port), tmp);
+		}
 	}
 
 	/* Wait for Stop state */
@@ -447,6 +464,9 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
 				AFE_LATCHOUT, 20))
 			DRM_ERROR("D-PHY not entering LP-11 state\n");
 	}
+
+	if (!cold_boot)
+		intel_dsi_prepare(encoder, pipe_config);
 }
 
 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
@@ -515,7 +535,8 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 	}
 }
 
-static void intel_dsi_device_ready(struct intel_encoder *encoder)
+static void intel_dsi_device_ready(struct intel_encoder *encoder,
+				   struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
@@ -524,7 +545,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 	else if (IS_BROXTON(dev_priv))
 		bxt_dsi_device_ready(encoder);
 	else if (IS_GEMINILAKE(dev_priv))
-		glk_dsi_device_ready(encoder);
+		glk_dsi_device_ready(encoder, pipe_config);
 }
 
 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
@@ -710,8 +731,6 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
 	}
 }
 
-static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
-			      struct intel_crtc_state *pipe_config);
 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 
 static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
@@ -800,7 +819,8 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 		I915_WRITE(DSPCLK_GATE_D, val);
 	}
 
-	intel_dsi_prepare(encoder, pipe_config);
+	if (!IS_GEMINILAKE(dev_priv))
+		intel_dsi_prepare(encoder, pipe_config);
 
 	/* Power on, try both CRC pmic gpio and VBT */
 	if (intel_dsi->gpio_panel)
@@ -812,7 +832,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 
 	/* Put device in ready state (LP-11) */
-	intel_dsi_device_ready(encoder);
+	intel_dsi_device_ready(encoder, pipe_config);
 
 	/* Send initialization commands in LP mode */
 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
-- 
1.9.1

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 3+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/glk: Enable cold boot for GLK DSI
  2017-06-04  8:35 [PATCH] drm/i915/glk: Enable cold boot for GLK DSI Madhav Chauhan
@ 2017-06-04  8:58 ` Patchwork
  2017-06-08 12:21 ` [PATCH] " Jani Nikula
  1 sibling, 0 replies; 3+ messages in thread
From: Patchwork @ 2017-06-04  8:58 UTC (permalink / raw)
  To: Madhav Chauhan; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/glk: Enable cold boot for GLK DSI
URL   : https://patchwork.freedesktop.org/series/25253/
State : success

== Summary ==

Series 25253v1 drm/i915/glk: Enable cold boot for GLK DSI
https://patchwork.freedesktop.org/api/1.0/series/25253/revisions/1/mbox/

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time:449s
fi-bdw-gvtdvm    total:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  time:434s
fi-bsw-n3050     total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  time:582s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time:516s
fi-byt-j1900     total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  time:485s
fi-byt-n2820     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time:478s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time:433s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time:419s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time:416s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time:503s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time:461s
fi-kbl-7500u     total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  time:463s
fi-kbl-7560u     total:278  pass:263  dwarn:5   dfail:0   fail:0   skip:10  time:567s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time:459s
fi-skl-6700hq    total:278  pass:228  dwarn:1   dfail:0   fail:27  skip:22  time:399s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time:464s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time:504s
fi-skl-gvtdvm    total:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  time:438s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time:537s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time:404s

d919ad0d077110d2d48a4b7503ddc02c3864667d drm-tip: 2017y-06m-02d-21h-49m-57s UTC integration manifest
56e8ae7 drm/i915/glk: Enable cold boot for GLK DSI

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4871/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH] drm/i915/glk: Enable cold boot for GLK DSI
  2017-06-04  8:35 [PATCH] drm/i915/glk: Enable cold boot for GLK DSI Madhav Chauhan
  2017-06-04  8:58 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-06-08 12:21 ` Jani Nikula
  1 sibling, 0 replies; 3+ messages in thread
From: Jani Nikula @ 2017-06-08 12:21 UTC (permalink / raw)
  To: Madhav Chauhan, intel-gfx
  Cc: ander.conselvan.de.oliveira, shashidhar.hiremath

On Sun, 04 Jun 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> As per BSEPC, if device ready bit is '0' in enable IO sequence
> then its a cold boot/reset scenario eg: S3/S4 resume. In these
> conditions we need to program certain registers and prepare port
> from the middle of DSI enable sequence otherwise feature like S3/S4
> doesn't work.
>
> V2: Do not assume that on enable when power has not been lost,
> all the registers contain the correct information already.
> Program DSI registers for normal boot scenario from
> glk_dsi_device_ready() (Jani N).

Here's a few additional notes following our discussion.

First, please do this in two patches. Patch 1/2 to split
glk_dsi_device_ready into two parts, with no functional changes, and
calling the first part from intel_dsi_pre_enable. Patch 2/2 to make the
functional changes here.

> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 82 +++++++++++++++++++++++++---------------
>  1 file changed, 51 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index fc0ef49..5582859 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -346,12 +346,17 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
>  	return true;
>  }
>  
> -static void glk_dsi_device_ready(struct intel_encoder *encoder)
> +static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> +			      struct intel_crtc_state *pipe_config);
> +
> +static void glk_dsi_device_ready(struct intel_encoder *encoder,
> +				 struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	enum port port;
>  	u32 tmp, val;
> +	bool cold_boot = false;
>  
>  	/* Set the MIPI mode
>  	 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
> @@ -370,7 +375,10 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
>  	/* Program LP Wake */
>  	for_each_dsi_port(port, intel_dsi->ports) {
>  		tmp = I915_READ(MIPI_CTRL(port));
> -		tmp |= GLK_LP_WAKE;
> +		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
> +			tmp &= ~GLK_LP_WAKE;
> +		else
> +			tmp |= GLK_LP_WAKE;
>  		I915_WRITE(MIPI_CTRL(port), tmp);
>  	}
>  
> @@ -382,6 +390,15 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
>  			DRM_ERROR("MIPIO port is powergated\n");
>  	}
>  
> +	/* Check if cold boot scenario */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) &
> +							DEVICE_READY);
> +	}

Does device ready change mid-function here? Could you collect the cold
boot info in the previous loop above already?

BR,
Jani.

> +
> +	if (cold_boot)
> +		intel_dsi_prepare(encoder, pipe_config);
> +
>  	/* Wait for MIPI PHY status bit to set */
>  	for_each_dsi_port(port, intel_dsi->ports) {
>  		if (intel_wait_for_register(dev_priv,
> @@ -402,34 +419,34 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
>  			val |= DEVICE_READY;
>  			I915_WRITE(MIPI_DEVICE_READY(port), val);
>  			usleep_range(10, 15);
> -		}
> -
> -		/* Enter ULPS */
> -		val = I915_READ(MIPI_DEVICE_READY(port));
> -		val &= ~ULPS_STATE_MASK;
> -		val |= (ULPS_STATE_ENTER | DEVICE_READY);
> -		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +		} else {
> +			/* Enter ULPS */
> +			val = I915_READ(MIPI_DEVICE_READY(port));
> +			val &= ~ULPS_STATE_MASK;
> +			val |= (ULPS_STATE_ENTER | DEVICE_READY);
> +			I915_WRITE(MIPI_DEVICE_READY(port), val);
>  
> -		/* Wait for ULPS active */
> -		if (intel_wait_for_register(dev_priv,
> +			/* Wait for ULPS active */
> +			if (intel_wait_for_register(dev_priv,
>  				MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20))
> -			DRM_ERROR("ULPS not active\n");
> +				DRM_ERROR("ULPS not active\n");
>  
> -		/* Exit ULPS */
> -		val = I915_READ(MIPI_DEVICE_READY(port));
> -		val &= ~ULPS_STATE_MASK;
> -		val |= (ULPS_STATE_EXIT | DEVICE_READY);
> -		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +			/* Exit ULPS */
> +			val = I915_READ(MIPI_DEVICE_READY(port));
> +			val &= ~ULPS_STATE_MASK;
> +			val |= (ULPS_STATE_EXIT | DEVICE_READY);
> +			I915_WRITE(MIPI_DEVICE_READY(port), val);
>  
> -		/* Enter Normal Mode */
> -		val = I915_READ(MIPI_DEVICE_READY(port));
> -		val &= ~ULPS_STATE_MASK;
> -		val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
> -		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +			/* Enter Normal Mode */
> +			val = I915_READ(MIPI_DEVICE_READY(port));
> +			val &= ~ULPS_STATE_MASK;
> +			val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
> +			I915_WRITE(MIPI_DEVICE_READY(port), val);
>  
> -		tmp = I915_READ(MIPI_CTRL(port));
> -		tmp &= ~GLK_LP_WAKE;
> -		I915_WRITE(MIPI_CTRL(port), tmp);
> +			tmp = I915_READ(MIPI_CTRL(port));
> +			tmp &= ~GLK_LP_WAKE;
> +			I915_WRITE(MIPI_CTRL(port), tmp);
> +		}
>  	}
>  
>  	/* Wait for Stop state */
> @@ -447,6 +464,9 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
>  				AFE_LATCHOUT, 20))
>  			DRM_ERROR("D-PHY not entering LP-11 state\n");
>  	}
> +
> +	if (!cold_boot)
> +		intel_dsi_prepare(encoder, pipe_config);
>  }
>  
>  static void bxt_dsi_device_ready(struct intel_encoder *encoder)
> @@ -515,7 +535,8 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
>  	}
>  }
>  
> -static void intel_dsi_device_ready(struct intel_encoder *encoder)
> +static void intel_dsi_device_ready(struct intel_encoder *encoder,
> +				   struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  
> @@ -524,7 +545,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
>  	else if (IS_BROXTON(dev_priv))
>  		bxt_dsi_device_ready(encoder);
>  	else if (IS_GEMINILAKE(dev_priv))
> -		glk_dsi_device_ready(encoder);
> +		glk_dsi_device_ready(encoder, pipe_config);
>  }
>  
>  static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
> @@ -710,8 +731,6 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
>  	}
>  }
>  
> -static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> -			      struct intel_crtc_state *pipe_config);
>  static void intel_dsi_unprepare(struct intel_encoder *encoder);
>  
>  static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
> @@ -800,7 +819,8 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
>  		I915_WRITE(DSPCLK_GATE_D, val);
>  	}
>  
> -	intel_dsi_prepare(encoder, pipe_config);
> +	if (!IS_GEMINILAKE(dev_priv))
> +		intel_dsi_prepare(encoder, pipe_config);
>  
>  	/* Power on, try both CRC pmic gpio and VBT */
>  	if (intel_dsi->gpio_panel)
> @@ -812,7 +832,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
>  	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
>  
>  	/* Put device in ready state (LP-11) */
> -	intel_dsi_device_ready(encoder);
> +	intel_dsi_device_ready(encoder, pipe_config);
>  
>  	/* Send initialization commands in LP mode */
>  	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);

-- 
Jani Nikula, Intel Open Source Technology Center
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2017-06-08 12:17 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2017-06-04  8:35 [PATCH] drm/i915/glk: Enable cold boot for GLK DSI Madhav Chauhan
2017-06-04  8:58 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-06-08 12:21 ` [PATCH] " Jani Nikula

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