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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Implement UHBR bandwidth check
Date: Thu, 02 Feb 2023 12:05:56 +0200	[thread overview]
Message-ID: <87o7qc1iwr.fsf@intel.com> (raw)
In-Reply-To: <20230202094726.6435-3-stanislav.lisovskiy@intel.com>

On Thu, 02 Feb 2023, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote:
> According to spec, we should check if output_bpp * pixel_rate is less
> than DDI clock * 72, if UHBR is used.
>
> HSDES: 1406899791
> BSPEC: 49259
>
> v2: - Removed wrong comment(Rodrigo Vivi)
>     - Added HSDES to the commit msg(Rodrigo Vivi)
>     - Moved UHBR check to the MST specific code
>
> v3: - Changed commit subject(Rodrigo Vivi)
>     - Fixed the error message if check fails(Rodrigo Vivi)
>
> v4: - Move UHBR check to new helper function
>     - Now both for non-DSC/DSC we use that new check as
>       one of the constraints, when figuring out output bpp
>       to be used(Ville Syrjälä)
>
> v5: - Use symbol clock (32 bit per lane for DP2) instead of port
>       clock in the formula(Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 15 ++++++++++++++-
>  1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index e3e7c305fece..e63132557690 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -47,8 +47,21 @@
>  
>  static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp,
>  					  const struct drm_display_mode *adjusted_mode,
> -					  struct intel_crtc_state *crtc_state)
> +					  struct intel_crtc_state *pipe_config)

Stick to crtc_state naming.

>  {
> +	if (intel_dp_is_uhbr(pipe_config)) {
> +		int output_bpp = bpp;
> +		/* DisplayPort 2 128b/132b, bits per lane is always 32 */
> +		int symbol_clock = pipe_config->port_clock / 32;
> +
> +		if (output_bpp * adjusted_mode->crtc_clock >=
> +		    symbol_clock * 72) {
> +			drm_dbg_kms(&i915->drm, "UHBR check failed(required bw %d available %d)\n",
> +				    output_bpp * adjusted_mode->crtc_clock, symbol_clock * 72);
> +			return -EINVAL;
> +		}
> +	}
> +
>  	return 0;
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2023-02-02 10:06 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-02  9:47 [Intel-gfx] [PATCH 0/2] We need to have additional checks for DP MST UHBR Stanislav Lisovskiy
2023-02-02  9:47 ` [Intel-gfx] [PATCH 1/2] drm/i915: Add generic constraint checker when determining DP MST DSC bpp Stanislav Lisovskiy
2023-02-02 10:04   ` Jani Nikula
2023-02-02  9:47 ` [Intel-gfx] [PATCH 2/2] drm/i915: Implement UHBR bandwidth check Stanislav Lisovskiy
2023-02-02 10:05   ` Jani Nikula [this message]
2023-02-02 10:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for We need to have additional checks for DP MST UHBR (rev2) Patchwork
2023-02-02 16:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2023-01-16 11:19 [Intel-gfx] [PATCH 0/2] We need to have additional checks for DP MST UHBR Stanislav Lisovskiy
2023-01-16 11:19 ` [Intel-gfx] [PATCH 2/2] drm/i915: Implement UHBR bandwidth check Stanislav Lisovskiy
2023-01-24 18:43   ` Rodrigo Vivi
2023-01-31 15:00   ` Ville Syrjälä
2023-01-31 15:20     ` Lisovskiy, Stanislav
2023-01-31 15:41       ` Ville Syrjälä
2023-02-01 11:00         ` Lisovskiy, Stanislav
2023-02-01 12:47           ` Ville Syrjälä

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