From: Jani Nikula <jani.nikula@linux.intel.com>
To: Anusha Srivatsa <anusha.srivatsa@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Add missing checks for cdclk crawling
Date: Thu, 10 Nov 2022 13:28:19 +0200 [thread overview]
Message-ID: <87o7tf59rg.fsf@intel.com> (raw)
In-Reply-To: <20221110053724.14701-1-anusha.srivatsa@intel.com>
On Wed, 09 Nov 2022, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> cdclk_sanitize() function was written assuming vco was a signed integer.
> vco gets assigned to -1 (essentially ~0) for the case where PLL
> might be enabled and vco is not a frequency that will ever
> get used. In such a scenario the right thing to do is disable the
> PLL and re-enable it again with a valid frequency.
> However the vco is declared as a unsigned variable.
> With the above assumption, driver takes crawl path when not needed.
> Add explicit check to not crawl in the case of an invalid PLL.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 ++
> drivers/gpu/drm/i915/display/intel_cdclk.h | 1 +
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 8a9031012d74..91112d266763 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1962,6 +1962,8 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
> if (!HAS_CDCLK_CRAWL(dev_priv))
> return false;
>
> + if (intel_pll_is_unknown(a->vco))
> + return false;
> /*
> * The vco and cd2x divider will change independently
> * from each, so we disallow cd2x change when crawling.
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index c674879a84a5..6eb83d806f11 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -80,6 +80,7 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
> to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
> #define intel_atomic_get_new_cdclk_state(state) \
> to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
> +#define intel_pll_is_unknown(vco) ((vco) == ~0)
Why here? What does a pll function do in intel_cdclk.h?
BR,
Jani.
>
> int intel_cdclk_init(struct drm_i915_private *dev_priv);
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2022-11-10 11:28 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-10 5:37 [Intel-gfx] [PATCH] drm/i915/display: Add missing checks for cdclk crawling Anusha Srivatsa
2022-11-10 11:28 ` Jani Nikula [this message]
2022-11-10 17:43 ` Matt Roper
2022-11-10 21:20 ` Ville Syrjälä
2022-11-10 21:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
2022-11-10 21:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-11-11 6:13 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2022-11-11 19:26 [Intel-gfx] [PATCH] " Anusha Srivatsa
2022-11-11 19:39 ` Ville Syrjälä
2022-11-14 16:19 ` Srivatsa, Anusha
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