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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [Intel-gfx] [PATCH 04/10] drm/i915/gt: Couple tasklet scheduling for all CS interrupts
Date: Fri, 05 Jun 2020 18:33:19 +0300	[thread overview]
Message-ID: <87o8pxa5og.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20200605122334.2798-4-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> If any engine asks for the tasklet to be kicked from the CS interrupt,
> do so.

The why part is a bit thin. The plan is to use execlist tasklet
for move stuff from virtual rings to real ones?

-Mika

>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_irq.c | 17 ++++++++++++-----
>  drivers/gpu/drm/i915/gt/intel_gt_irq.h |  3 +++
>  drivers/gpu/drm/i915/gt/intel_rps.c    |  2 +-
>  drivers/gpu/drm/i915/i915_irq.c        |  8 ++++----
>  4 files changed, 20 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 0cc7dd54f4f9..28edf314a319 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -60,6 +60,13 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
>  		tasklet_hi_schedule(&engine->execlists.tasklet);
>  }
>  
> +void gen2_engine_cs_irq(struct intel_engine_cs *engine)
> +{
> +	intel_engine_signal_breadcrumbs(engine);
> +	if (intel_engine_needs_breadcrumb_tasklet(engine))
> +		tasklet_hi_schedule(&engine->execlists.tasklet);
> +}
> +
>  static u32
>  gen11_gt_engine_identity(struct intel_gt *gt,
>  			 const unsigned int bank, const unsigned int bit)
> @@ -273,9 +280,9 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>  void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
>  {
>  	if (gt_iir & GT_RENDER_USER_INTERRUPT)
> -		intel_engine_signal_breadcrumbs(gt->engine_class[RENDER_CLASS][0]);
> +		gen2_engine_cs_irq(gt->engine_class[RENDER_CLASS][0]);
>  	if (gt_iir & ILK_BSD_USER_INTERRUPT)
> -		intel_engine_signal_breadcrumbs(gt->engine_class[VIDEO_DECODE_CLASS][0]);
> +		gen2_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0]);
>  }
>  
>  static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir)
> @@ -299,11 +306,11 @@ static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir)
>  void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
>  {
>  	if (gt_iir & GT_RENDER_USER_INTERRUPT)
> -		intel_engine_signal_breadcrumbs(gt->engine_class[RENDER_CLASS][0]);
> +		gen2_engine_cs_irq(gt->engine_class[RENDER_CLASS][0]);
>  	if (gt_iir & GT_BSD_USER_INTERRUPT)
> -		intel_engine_signal_breadcrumbs(gt->engine_class[VIDEO_DECODE_CLASS][0]);
> +		gen2_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0]);
>  	if (gt_iir & GT_BLT_USER_INTERRUPT)
> -		intel_engine_signal_breadcrumbs(gt->engine_class[COPY_ENGINE_CLASS][0]);
> +		gen2_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0]);
>  
>  	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
>  		      GT_BSD_CS_ERROR_INTERRUPT |
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.h b/drivers/gpu/drm/i915/gt/intel_gt_irq.h
> index 886c5cf408a2..6c69cd563fe1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.h
> @@ -9,6 +9,7 @@
>  
>  #include <linux/types.h>
>  
> +struct intel_engine_cs;
>  struct intel_gt;
>  
>  #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
> @@ -19,6 +20,8 @@ struct intel_gt;
>  		      GEN8_GT_PM_IRQ | \
>  		      GEN8_GT_GUC_IRQ)
>  
> +void gen2_engine_cs_irq(struct intel_engine_cs *engine);
> +
>  void gen11_gt_irq_reset(struct intel_gt *gt);
>  void gen11_gt_irq_postinstall(struct intel_gt *gt);
>  void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl);
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 2f59fc6df3c2..2e4ddc9ca09d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -1741,7 +1741,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
>  		return;
>  
>  	if (pm_iir & PM_VEBOX_USER_INTERRUPT)
> -		intel_engine_signal_breadcrumbs(gt->engine[VECS0]);
> +		gen2_engine_cs_irq(gt->engine[VECS0]);
>  
>  	if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
>  		DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 8e823ba25f5f..b64f3b3bca70 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3686,7 +3686,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
>  		intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
>  
>  		if (iir & I915_USER_INTERRUPT)
> -			intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
> +			gen2_engine_cs_irq(dev_priv->gt.engine[RCS0]);
>  
>  		if (iir & I915_MASTER_ERROR_INTERRUPT)
>  			i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
> @@ -3791,7 +3791,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
>  		I915_WRITE(GEN2_IIR, iir);
>  
>  		if (iir & I915_USER_INTERRUPT)
> -			intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
> +			gen2_engine_cs_irq(dev_priv->gt.engine[RCS0]);
>  
>  		if (iir & I915_MASTER_ERROR_INTERRUPT)
>  			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
> @@ -3933,10 +3933,10 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
>  		I915_WRITE(GEN2_IIR, iir);
>  
>  		if (iir & I915_USER_INTERRUPT)
> -			intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
> +			gen2_engine_cs_irq(dev_priv->gt.engine[RCS0]);
>  
>  		if (iir & I915_BSD_USER_INTERRUPT)
> -			intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]);
> +			gen2_engine_cs_irq(dev_priv->gt.engine[VCS0]);
>  
>  		if (iir & I915_MASTER_ERROR_INTERRUPT)
>  			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
> -- 
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  reply	other threads:[~2020-06-05 15:35 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-05 12:23 [Intel-gfx] [PATCH 01/10] drm/i915/gt: Set timeslicing priority from queue Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 02/10] drm/i915/gt: Always check to enable timeslicing if not submitting Chris Wilson
2020-06-05 15:20   ` Mika Kuoppala
2020-06-05 15:32     ` Chris Wilson
2020-06-05 15:34       ` Mika Kuoppala
2020-06-05 12:23 ` [Intel-gfx] [PATCH 03/10] Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" Chris Wilson
2020-06-05 15:30   ` Mika Kuoppala
2020-06-05 12:23 ` [Intel-gfx] [PATCH 04/10] drm/i915/gt: Couple tasklet scheduling for all CS interrupts Chris Wilson
2020-06-05 15:33   ` Mika Kuoppala [this message]
2020-06-05 15:40     ` Chris Wilson
2020-06-05 15:43       ` Mika Kuoppala
2020-06-05 12:23 ` [Intel-gfx] [PATCH 05/10] drm/i915/gt: Support creation of 'internal' rings Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 06/10] drm/i915/gt: Use client timeline address for seqno writes Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 07/10] drm/i915/gt: Infrastructure for ring scheduling Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 08/10] drm/i915/gt: Enable busy-stats for ring-scheduler Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 09/10] drm/i915/gt: Implement ring scheduler for gen6/7 Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 10/10] drm/i915/gt: Enable ring scheduling " Chris Wilson
2020-06-05 12:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915/gt: Set timeslicing priority from queue Patchwork
2020-06-05 12:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-06-05 13:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-05 14:28 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-06-05 14:47 ` [Intel-gfx] [PATCH 01/10] " Mika Kuoppala

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