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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [Intel-gfx] [PATCH 02/10] drm/i915/gt: Always check to enable timeslicing if not submitting
Date: Fri, 05 Jun 2020 18:20:34 +0300	[thread overview]
Message-ID: <87wo4la69p.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20200605122334.2798-2-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> We may choose not to submit for a number of reasons, yet not fill both
> ELSP. In which case we must start timeslicing (there will be no ACK
> event on which to hook the start) if the queue would benefit from the
> currently active context being evicted.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 92c3368ffcbd..d55a5e0466e5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2362,10 +2362,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>  				if (last->context == rq->context)
>  					goto done;
>  
> -				if (i915_request_has_sentinel(last)) {
> -					start_timeslice(engine, rq_prio(rq));
> +				if (i915_request_has_sentinel(last))
>  					goto done;
> -				}
>  
>  				/*
>  				 * If GVT overrides us we only ever submit
> @@ -2446,6 +2444,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>  		set_preempt_timeout(engine, *active);
>  		execlists_submit_ports(engine);
>  	} else {
> +		start_timeslice(engine, execlists->queue_priority_hint);

If we ended up with same set of request, we want to skip submitting.
But why would we want to skip timeslicing?

-Mika

>  skip_submit:
>  		ring_set_paused(engine, 0);
>  	}
> -- 
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  reply	other threads:[~2020-06-05 15:23 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-05 12:23 [Intel-gfx] [PATCH 01/10] drm/i915/gt: Set timeslicing priority from queue Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 02/10] drm/i915/gt: Always check to enable timeslicing if not submitting Chris Wilson
2020-06-05 15:20   ` Mika Kuoppala [this message]
2020-06-05 15:32     ` Chris Wilson
2020-06-05 15:34       ` Mika Kuoppala
2020-06-05 12:23 ` [Intel-gfx] [PATCH 03/10] Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" Chris Wilson
2020-06-05 15:30   ` Mika Kuoppala
2020-06-05 12:23 ` [Intel-gfx] [PATCH 04/10] drm/i915/gt: Couple tasklet scheduling for all CS interrupts Chris Wilson
2020-06-05 15:33   ` Mika Kuoppala
2020-06-05 15:40     ` Chris Wilson
2020-06-05 15:43       ` Mika Kuoppala
2020-06-05 12:23 ` [Intel-gfx] [PATCH 05/10] drm/i915/gt: Support creation of 'internal' rings Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 06/10] drm/i915/gt: Use client timeline address for seqno writes Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 07/10] drm/i915/gt: Infrastructure for ring scheduling Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 08/10] drm/i915/gt: Enable busy-stats for ring-scheduler Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 09/10] drm/i915/gt: Implement ring scheduler for gen6/7 Chris Wilson
2020-06-05 12:23 ` [Intel-gfx] [PATCH 10/10] drm/i915/gt: Enable ring scheduling " Chris Wilson
2020-06-05 12:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915/gt: Set timeslicing priority from queue Patchwork
2020-06-05 12:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-06-05 13:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-05 14:28 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-06-05 14:47 ` [Intel-gfx] [PATCH 01/10] " Mika Kuoppala

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