[PATCH] drm/i915: implement WaMbcDriverBootEnable on Haswell

[PATCH] drm/i915: implement WaMbcDriverBootEnable on Haswell

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Also document the WA name for the previous gens that implement it.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 59068be..150aebd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3450,6 +3450,7 @@ static void gen6_init_clock_gating(struct drm_device *dev)
 		   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
 		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
 
+	/* WaMbcDriverBootEnable */
 	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
 		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
 
@@ -3520,6 +3521,10 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(CACHE_MODE_1,
 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
 
+	/* WaMbcDriverBootEnable */
+	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
+		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
+
 	/* XXX: This is a workaround for early silicon revisions and should be
 	 * removed later.
 	 */
@@ -3595,6 +3600,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 		intel_flush_display_plane(dev_priv, pipe);
 	}
 
+	/* WaMbcDriverBootEnable */
 	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
 		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
 
@@ -3647,6 +3653,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
 		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
 
+	/* WaMbcDriverBootEnable */
 	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
 		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
 
-- 
1.7.11.4

Re: [PATCH] drm/i915: implement WaMbcDriverBootEnable on Haswell

[Jani Nikula]

On Fri, 26 Oct 2012, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Also document the WA name for the previous gens that implement it.

Looks good based on the existing workarounds and specs; was unable to
find any further details on the WA.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 59068be..150aebd 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3450,6 +3450,7 @@ static void gen6_init_clock_gating(struct drm_device *dev)
>  		   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
>  		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
>  
> +	/* WaMbcDriverBootEnable */
>  	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
>  		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
>  
> @@ -3520,6 +3521,10 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(CACHE_MODE_1,
>  		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
>  
> +	/* WaMbcDriverBootEnable */
> +	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
> +		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
> +
>  	/* XXX: This is a workaround for early silicon revisions and should be
>  	 * removed later.
>  	 */
> @@ -3595,6 +3600,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>  		intel_flush_display_plane(dev_priv, pipe);
>  	}
>  
> +	/* WaMbcDriverBootEnable */
>  	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
>  		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
>  
> @@ -3647,6 +3653,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>  		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>  
> +	/* WaMbcDriverBootEnable */
>  	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
>  		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
>  
> -- 
> 1.7.11.4
>
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