[PATCH 1/6] drm/i915: Correct a comment about the use of the workqueue.

[PATCH 1/6] drm/i915: Correct a comment about the use of the workqueue.

[Eric Anholt]

It isn't used for the hangcheck, which does its work right from the
timer trigger, but hangcheck can lead to error state recording, which
is run off of the workqueue.

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_dma.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 4cd0491..cf4e06a 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1962,7 +1962,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	 * bo.
 	 *
 	 * It is also used for periodic low-priority events, such as
-	 * idle-timers and hangcheck.
+	 * idle-timers and recording error state.
 	 *
 	 * All tasks on the workqueue are expected to acquire the dev mutex
 	 * so there is no point in running more than one instance of the
-- 
1.7.2.3

[PATCH 5/6] drm/i915: Also reinit the BSD and BLT rings after a GPU reset.

[Eric Anholt]

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_drv.c |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 57e892d..af2de29 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -471,9 +471,12 @@ int i915_reset(struct drm_device *dev, u8 flags)
 	 */
 	if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 			!dev_priv->mm.suspended) {
-		struct intel_ring_buffer *ring = &dev_priv->render_ring;
 		dev_priv->mm.suspended = 0;
-		ring->init(ring);
+		dev_priv->render_ring.init(&dev_priv->render_ring);
+		if (HAS_BSD(dev))
+		    dev_priv->bsd_ring.init(&dev_priv->bsd_ring);
+		if (HAS_BLT(dev))
+		    dev_priv->blt_ring.init(&dev_priv->blt_ring);
 		mutex_unlock(&dev->struct_mutex);
 		drm_irq_uninstall(dev);
 		drm_irq_install(dev);
-- 
1.7.2.3

[PATCH 6/6] drm/i915: Add support for GPU reset on gen6.

[Eric Anholt]

This has proven sufficient to recover from a hang of the GPU using the
gem_bad_blit test while at the KMS console then starting X.  When
attempting the same during an X session, the timer doesn't appear to
trigger.

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_drv.c |   11 +++++++++++
 drivers/gpu/drm/i915/i915_reg.h |    6 ++++++
 2 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index af2de29..6fa0a5a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -404,6 +404,14 @@ static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 	return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 }
 
+static int gen6_do_reset(struct drm_device *dev, u8 flags)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
+	return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
+}
+
 /**
  * i965_reset - reset chip after a hang
  * @dev: drm device to reset
@@ -438,6 +446,9 @@ int i915_reset(struct drm_device *dev, u8 flags)
 	if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 		DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 	} else switch (INTEL_INFO(dev)->gen) {
+	case 6:
+		ret = gen6_do_reset(dev, flags);
+		break;
 	case 5:
 		ret = ironlake_do_reset(dev, flags);
 		break;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 00351a6..01b4998 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -78,6 +78,12 @@
 #define  GRDOM_RENDER	(1<<2)
 #define  GRDOM_MEDIA	(3<<2)
 
+#define GEN6_GDRST	0x941c
+#define  GEN6_GRDOM_FULL		(1 << 0)
+#define  GEN6_GRDOM_RENDER		(1 << 1)
+#define  GEN6_GRDOM_MEDIA		(1 << 2)
+#define  GEN6_GRDOM_BLT			(1 << 3)
+
 /* VGA stuff */
 
 #define VGA_ST01_MDA 0x3ba
-- 
1.7.2.3

Re: [PATCH 6/6] drm/i915: Add support for GPU reset on gen6.

[Chris Wilson]

Eric, only 3 patches (1, 5, 6) turned up in my inbox, can you either resend
these to me or push to your tree?

Thanks,
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 6/6] drm/i915: Add support for GPU reset on gen6.

[Eric Anholt]

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On Thu, 18 Nov 2010 14:53:24 +0000, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> Eric, only 3 patches (1, 5, 6) turned up in my inbox, can you either resend
> these to me or push to your tree?

Sorry the formatting of the mails produced was confusing.  The others
were the DP fixes and the comment fix sent in separate threads.

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Re: [PATCH 6/6] drm/i915: Add support for GPU reset on gen6.

[Chris Wilson]

On Fri, 19 Nov 2010 08:52:08 +0800, Eric Anholt <eric@anholt.net> wrote:
> On Thu, 18 Nov 2010 14:53:24 +0000, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > Eric, only 3 patches (1, 5, 6) turned up in my inbox, can you either resend
> > these to me or push to your tree?
> 
> Sorry the formatting of the mails produced was confusing.  The others
> were the DP fixes and the comment fix sent in separate threads.

Thanks, finally applied to -next.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre