[PATCH 00/14] drm/i915/display: conversions to struct intel

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* [PATCH 00/14] drm/i915/display: conversions to struct intel_display
@ 2025-02-12 16:36 Jani Nikula
  2025-02-12 16:36 ` [PATCH 01/14] drm/i915/dp: convert g4x_dp.[ch] to struct intel display Jani Nikula
                   ` (18 more replies)
  0 siblings, 19 replies; 35+ messages in thread
From: Jani Nikula @ 2025-02-12 16:36 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula

Convert a bunch of files and functions to struct intel display.

The approach is to mostly convert a file, then see what the stragglers
are, convert those too, and repeat.

The PCH checks are starting to become a big straggler for further
conversions.

BR,
Jani.

Jani Nikula (14):
  drm/i915/dp: convert g4x_dp.[ch] to struct intel display
  drm/i915/hdmi: convert g4x_hdmi.[ch] to struct intel_display
  drm/i915/ips: convert hsw_ips.c to struct intel_display
  drm/i915/display: convert assert_transcoder*() to struct intel_display
  drm/i915/display: convert assert_port_valid() to struct intel_display
  drm/i915/hpd: drop dev_priv parameter from intel_hpd_pin_default()
  drm/i915/display: convert
    intel_set_{cpu,pch}_fifo_underrun_reporting() to intel_display
  drm/i915/sdvo: convert intel_sdvo.[ch] to struct intel_display
  drm/i915/display: convert intel_cpu_transcoder_mode_valid() to
    intel_display
  drm/i915/display: convert intel_mode_valid_max_plane_size() to
    intel_display
  drm/i915/dsi: convert platform checks to display->platform.<platform>
    style
  drm/i915/combo-phy: convert intel_combo_phy.[ch] to struct
    intel_display
  drm/i915/display: convert intel_fifo_underrun.[ch] to struct
    intel_display
  drm/i915/display: convert i915_pipestat_enable_mask() to struct
    intel_display

 drivers/gpu/drm/i915/display/g4x_dp.c         |  99 +++---
 drivers/gpu/drm/i915/display/g4x_dp.h         |  14 +-
 drivers/gpu/drm/i915/display/g4x_hdmi.c       | 154 +++++----
 drivers/gpu/drm/i915/display/g4x_hdmi.h       |   6 +-
 drivers/gpu/drm/i915/display/hsw_ips.c        |  26 +-
 drivers/gpu/drm/i915/display/icl_dsi.c        |  21 +-
 .../gpu/drm/i915/display/intel_combo_phy.c    | 180 ++++++-----
 .../gpu/drm/i915/display/intel_combo_phy.h    |   8 +-
 drivers/gpu/drm/i915/display/intel_crt.c      |  21 +-
 drivers/gpu/drm/i915/display/intel_crtc.c     |   2 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  11 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 155 ++++-----
 drivers/gpu/drm/i915/display/intel_display.h  |  10 +-
 .../gpu/drm/i915/display/intel_display_irq.c  |  37 +--
 .../gpu/drm/i915/display/intel_display_irq.h  |   5 +-
 .../drm/i915/display/intel_display_power.c    |   5 +-
 .../i915/display/intel_display_power_well.c   |   3 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |   5 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   5 +-
 drivers/gpu/drm/i915/display/intel_dpll.c     |  30 +-
 drivers/gpu/drm/i915/display/intel_dsi.c      |   8 +-
 drivers/gpu/drm/i915/display/intel_dvo.c      |   8 +-
 drivers/gpu/drm/i915/display/intel_fdi.c      |   3 +-
 .../drm/i915/display/intel_fifo_underrun.c    | 181 ++++++-----
 .../drm/i915/display/intel_fifo_underrun.h    |  18 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |   5 +-
 drivers/gpu/drm/i915/display/intel_hotplug.c  |   4 +-
 drivers/gpu/drm/i915/display/intel_hotplug.h  |   3 +-
 drivers/gpu/drm/i915/display/intel_lvds.c     |   6 +-
 .../drm/i915/display/intel_modeset_setup.c    |   6 +-
 .../gpu/drm/i915/display/intel_pch_display.c  |   4 +-
 drivers/gpu/drm/i915/display/intel_pps.c      |  11 +-
 drivers/gpu/drm/i915/display/intel_sdvo.c     | 293 +++++++++---------
 drivers/gpu/drm/i915/display/intel_sdvo.h     |  10 +-
 drivers/gpu/drm/i915/display/intel_tv.c       |   6 +-
 drivers/gpu/drm/i915/display/vlv_dsi.c        |   8 +-
 36 files changed, 671 insertions(+), 700 deletions(-)

-- 
2.39.5


^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 01/14] drm/i915/dp: convert g4x_dp.[ch] to struct intel display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
@ 2025-02-12 16:36 ` Jani Nikula
  2025-02-13  8:48   ` Kandpal, Suraj
  2025-02-12 16:36 ` [PATCH 02/14] drm/i915/hdmi: convert g4x_hdmi.[ch] to struct intel_display Jani Nikula
                   ` (17 subsequent siblings)
  18 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2025-02-12 16:36 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula

Going forward, struct intel_display is the main display device data
pointer. Convert as much as possible of g4x_dp.[ch] to struct
intel_display.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c         | 80 +++++++++----------
 drivers/gpu/drm/i915/display/g4x_dp.h         | 14 ++--
 drivers/gpu/drm/i915/display/intel_display.c  | 20 ++---
 .../gpu/drm/i915/display/intel_pch_display.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_pps.c      | 11 ++-
 5 files changed, 61 insertions(+), 66 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index d3b5ead188ba..cfc796607a78 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -51,28 +51,29 @@ static const struct dpll chv_dpll[] = {
 	{ .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
 };
 
-const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
+const struct dpll *vlv_get_dpll(struct intel_display *display)
 {
-	return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0];
+	return display->platform.cherryview ? &chv_dpll[0] : &vlv_dpll[0];
 }
 
 static void g4x_dp_set_clock(struct intel_encoder *encoder,
 			     struct intel_crtc_state *pipe_config)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	const struct dpll *divisor = NULL;
 	int i, count = 0;
 
-	if (IS_G4X(dev_priv)) {
+	if (display->platform.g4x) {
 		divisor = g4x_dpll;
 		count = ARRAY_SIZE(g4x_dpll);
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		divisor = pch_dpll;
 		count = ARRAY_SIZE(pch_dpll);
-	} else if (IS_CHERRYVIEW(dev_priv)) {
+	} else if (display->platform.cherryview) {
 		divisor = chv_dpll;
 		count = ARRAY_SIZE(chv_dpll);
-	} else if (IS_VALLEYVIEW(dev_priv)) {
+	} else if (display->platform.valleyview) {
 		divisor = vlv_dpll;
 		count = ARRAY_SIZE(vlv_dpll);
 	}
@@ -129,7 +130,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
 
 	/* Split out the IBX/CPU vs CPT settings */
 
-	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
+	if (display->platform.ivybridge && port == PORT_A) {
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 			intel_dp->DP |= DP_SYNC_HS_HIGH;
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
@@ -148,7 +149,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
 			     pipe_config->enhanced_framing ?
 			     TRANS_DP_ENH_FRAMING : 0);
 	} else {
-		if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
+		if (display->platform.g4x && pipe_config->limited_color_range)
 			intel_dp->DP |= DP_COLOR_RANGE_16_235;
 
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
@@ -160,7 +161,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
 		if (pipe_config->enhanced_framing)
 			intel_dp->DP |= DP_ENHANCED_FRAMING;
 
-		if (IS_CHERRYVIEW(dev_priv))
+		if (display->platform.cherryview)
 			intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
 		else
 			intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
@@ -180,9 +181,8 @@ static void assert_dp_port(struct intel_dp *intel_dp, bool state)
 }
 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
 
-static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
+static void assert_edp_pll(struct intel_display *display, bool state)
 {
-	struct intel_display *display = &dev_priv->display;
 	bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE;
 
 	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
@@ -201,7 +201,7 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
 
 	assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
 	assert_dp_port_disabled(intel_dp);
-	assert_edp_pll_disabled(dev_priv);
+	assert_edp_pll_disabled(display);
 
 	drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",
 		    pipe_config->port_clock);
@@ -223,7 +223,7 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
 	 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
 	 * 2. Program DP PLL enable
 	 */
-	if (IS_IRONLAKE(dev_priv))
+	if (display->platform.ironlake)
 		intel_wait_for_vblank_if_active(display, !crtc->pipe);
 
 	intel_dp->DP |= DP_PLL_ENABLE;
@@ -242,7 +242,7 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp,
 
 	assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
 	assert_dp_port_disabled(intel_dp);
-	assert_edp_pll_enabled(dev_priv);
+	assert_edp_pll_enabled(display);
 
 	drm_dbg_kms(display->drm, "disabling eDP PLL\n");
 
@@ -253,10 +253,9 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp,
 	udelay(200);
 }
 
-static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
+static bool cpt_dp_port_selected(struct intel_display *display,
 				 enum port port, enum pipe *pipe)
 {
-	struct intel_display *display = &dev_priv->display;
 	enum pipe p;
 
 	for_each_pipe(display, p) {
@@ -277,11 +276,11 @@ static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
 	return false;
 }
 
-bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
+bool g4x_dp_port_enabled(struct intel_display *display,
 			 i915_reg_t dp_reg, enum port port,
 			 enum pipe *pipe)
 {
-	struct intel_display *display = &dev_priv->display;
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	bool ret;
 	u32 val;
 
@@ -290,11 +289,11 @@ bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
 	ret = val & DP_PORT_EN;
 
 	/* asserts want to know the pipe even if the port is disabled */
-	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
+	if (display->platform.ivybridge && port == PORT_A)
 		*pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
 	else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
-		ret &= cpt_dp_port_selected(dev_priv, port, pipe);
-	else if (IS_CHERRYVIEW(dev_priv))
+		ret &= cpt_dp_port_selected(display, port, pipe);
+	else if (display->platform.cherryview)
 		*pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
 	else
 		*pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
@@ -306,7 +305,6 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
 				  enum pipe *pipe)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	intel_wakeref_t wakeref;
 	bool ret;
@@ -316,7 +314,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
 	if (!wakeref)
 		return false;
 
-	ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
+	ret = g4x_dp_port_enabled(display, intel_dp->output_reg,
 				  encoder->port, pipe);
 
 	intel_display_power_put(display, encoder->power_domain, wakeref);
@@ -391,7 +389,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 
 	pipe_config->hw.adjusted_mode.flags |= flags;
 
-	if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
+	if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235)
 		pipe_config->limited_color_range = true;
 
 	pipe_config->lane_count =
@@ -433,7 +431,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
 
 	drm_dbg_kms(display->drm, "\n");
 
-	if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
+	if ((display->platform.ivybridge && port == PORT_A) ||
 	    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
 		intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
 		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
@@ -479,7 +477,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
 
 	msleep(intel_dp->pps.panel_power_down_delay);
 
-	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+	if (display->platform.valleyview || display->platform.cherryview)
 		vlv_pps_port_disable(encoder, old_crtc_state);
 }
 
@@ -682,7 +680,6 @@ static void intel_enable_dp(struct intel_atomic_state *state,
 			    const struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(state);
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	u32 dp_reg = intel_de_read(display, intel_dp->output_reg);
 	intel_wakeref_t wakeref;
@@ -691,7 +688,7 @@ static void intel_enable_dp(struct intel_atomic_state *state,
 		return;
 
 	with_intel_pps_lock(intel_dp, wakeref) {
-		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+		if (display->platform.valleyview || display->platform.cherryview)
 			vlv_pps_port_enable_unlocked(encoder, pipe_config);
 
 		intel_dp_enable_port(intel_dp, pipe_config);
@@ -701,10 +698,10 @@ static void intel_enable_dp(struct intel_atomic_state *state,
 		intel_pps_vdd_off_unlocked(intel_dp, true);
 	}
 
-	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+	if (display->platform.valleyview || display->platform.cherryview) {
 		unsigned int lane_mask = 0x0;
 
-		if (IS_CHERRYVIEW(dev_priv))
+		if (display->platform.cherryview)
 			lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
 
 		vlv_wait_port_ready(display, dp_to_dig_port(intel_dp), lane_mask);
@@ -1264,7 +1261,6 @@ static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder->dev);
-	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
 
 	intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
@@ -1272,7 +1268,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
 	intel_dp->reset_link_params = true;
 	intel_dp_invalidate_source_oui(intel_dp);
 
-	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+	if (display->platform.valleyview || display->platform.cherryview)
 		vlv_pps_pipe_reset(intel_dp);
 
 	intel_pps_encoder_reset(intel_dp);
@@ -1283,10 +1279,10 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = {
 	.destroy = intel_dp_encoder_destroy,
 };
 
-bool g4x_dp_init(struct drm_i915_private *dev_priv,
+bool g4x_dp_init(struct intel_display *display,
 		 i915_reg_t output_reg, enum port port)
 {
-	struct intel_display *display = &dev_priv->display;
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	const struct intel_bios_encoder_data *devdata;
 	struct intel_digital_port *dig_port;
 	struct intel_encoder *intel_encoder;
@@ -1337,14 +1333,14 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
 	intel_encoder->suspend = intel_dp_encoder_suspend;
 	intel_encoder->suspend_complete = g4x_dp_suspend_complete;
 	intel_encoder->shutdown = intel_dp_encoder_shutdown;
-	if (IS_CHERRYVIEW(dev_priv)) {
+	if (display->platform.cherryview) {
 		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
 		intel_encoder->pre_enable = chv_pre_enable_dp;
 		intel_encoder->enable = vlv_enable_dp;
 		intel_encoder->disable = vlv_disable_dp;
 		intel_encoder->post_disable = chv_post_disable_dp;
 		intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
-	} else if (IS_VALLEYVIEW(dev_priv)) {
+	} else if (display->platform.valleyview) {
 		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
 		intel_encoder->pre_enable = vlv_pre_enable_dp;
 		intel_encoder->enable = vlv_enable_dp;
@@ -1359,24 +1355,24 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
 	intel_encoder->audio_enable = g4x_dp_audio_enable;
 	intel_encoder->audio_disable = g4x_dp_audio_disable;
 
-	if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
+	if ((display->platform.ivybridge && port == PORT_A) ||
 	    (HAS_PCH_CPT(dev_priv) && port != PORT_A))
 		dig_port->dp.set_link_train = cpt_set_link_train;
 	else
 		dig_port->dp.set_link_train = g4x_set_link_train;
 
-	if (IS_CHERRYVIEW(dev_priv))
+	if (display->platform.cherryview)
 		intel_encoder->set_signal_levels = chv_set_signal_levels;
-	else if (IS_VALLEYVIEW(dev_priv))
+	else if (display->platform.valleyview)
 		intel_encoder->set_signal_levels = vlv_set_signal_levels;
-	else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
+	else if (display->platform.ivybridge && port == PORT_A)
 		intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels;
-	else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A)
+	else if (display->platform.sandybridge && port == PORT_A)
 		intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels;
 	else
 		intel_encoder->set_signal_levels = g4x_set_signal_levels;
 
-	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
+	if (display->platform.valleyview || display->platform.cherryview ||
 	    (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
 		dig_port->dp.preemph_max = intel_dp_preemph_max_3;
 		dig_port->dp.voltage_max = intel_dp_voltage_max_3;
@@ -1390,7 +1386,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
 
 	intel_encoder->type = INTEL_OUTPUT_DP;
 	intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);
-	if (IS_CHERRYVIEW(dev_priv)) {
+	if (display->platform.cherryview) {
 		if (port == PORT_D)
 			intel_encoder->pipe_mask = BIT(PIPE_C);
 		else
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.h b/drivers/gpu/drm/i915/display/g4x_dp.h
index 839a251dc069..0b28951b8365 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.h
+++ b/drivers/gpu/drm/i915/display/g4x_dp.h
@@ -12,30 +12,30 @@
 
 enum pipe;
 enum port;
-struct drm_i915_private;
 struct intel_crtc_state;
+struct intel_display;
 struct intel_dp;
 struct intel_encoder;
 
 #ifdef I915
-const struct dpll *vlv_get_dpll(struct drm_i915_private *i915);
-bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
+const struct dpll *vlv_get_dpll(struct intel_display *display);
+bool g4x_dp_port_enabled(struct intel_display *display,
 			 i915_reg_t dp_reg, enum port port,
 			 enum pipe *pipe);
-bool g4x_dp_init(struct drm_i915_private *dev_priv,
+bool g4x_dp_init(struct intel_display *display,
 		 i915_reg_t output_reg, enum port port);
 #else
-static inline const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
+static inline const struct dpll *vlv_get_dpll(struct intel_display *display)
 {
 	return NULL;
 }
-static inline bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
+static inline bool g4x_dp_port_enabled(struct intel_display *display,
 				       i915_reg_t dp_reg, int port,
 				       enum pipe *pipe)
 {
 	return false;
 }
-static inline bool g4x_dp_init(struct drm_i915_private *dev_priv,
+static inline bool g4x_dp_init(struct intel_display *display,
 			       i915_reg_t output_reg, int port)
 {
 	return false;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6c1e7441313e..e5ceedf56335 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8229,7 +8229,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		dpd_is_edp = intel_dp_is_port_edp(display, PORT_D);
 
 		if (ilk_has_edp_a(dev_priv))
-			g4x_dp_init(dev_priv, DP_A, PORT_A);
+			g4x_dp_init(display, DP_A, PORT_A);
 
 		if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
 			/* PCH SDVOB multiplex with HDMIB */
@@ -8237,7 +8237,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 			if (!found)
 				g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
 			if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
-				g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
+				g4x_dp_init(display, PCH_DP_B, PORT_B);
 		}
 
 		if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
@@ -8247,10 +8247,10 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 			g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
 
 		if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
-			g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
+			g4x_dp_init(display, PCH_DP_C, PORT_C);
 
 		if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
-			g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
+			g4x_dp_init(display, PCH_DP_D, PORT_D);
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		bool has_edp, has_port;
 
@@ -8275,14 +8275,14 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		has_edp = intel_dp_is_port_edp(display, PORT_B);
 		has_port = intel_bios_is_port_present(display, PORT_B);
 		if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
-			has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
+			has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B);
 		if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
 			g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
 
 		has_edp = intel_dp_is_port_edp(display, PORT_C);
 		has_port = intel_bios_is_port_present(display, PORT_C);
 		if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
-			has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
+			has_edp &= g4x_dp_init(display, VLV_DP_C, PORT_C);
 		if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
 			g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
 
@@ -8293,7 +8293,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 			 */
 			has_port = intel_bios_is_port_present(display, PORT_D);
 			if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
-				g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
+				g4x_dp_init(display, CHV_DP_D, PORT_D);
 			if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
 				g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
 		}
@@ -8320,7 +8320,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 			}
 
 			if (!found && IS_G4X(dev_priv))
-				g4x_dp_init(dev_priv, DP_B, PORT_B);
+				g4x_dp_init(display, DP_B, PORT_B);
 		}
 
 		/* Before G4X SDVOC doesn't have its own detect register */
@@ -8338,11 +8338,11 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 				g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
 			}
 			if (IS_G4X(dev_priv))
-				g4x_dp_init(dev_priv, DP_C, PORT_C);
+				g4x_dp_init(display, DP_C, PORT_C);
 		}
 
 		if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
-			g4x_dp_init(dev_priv, DP_D, PORT_D);
+			g4x_dp_init(display, DP_D, PORT_D);
 
 		if (SUPPORTS_TV(dev_priv))
 			intel_tv_init(display);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 75ff5592312f..98a6b57ac956 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -45,7 +45,7 @@ static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
 	enum pipe port_pipe;
 	bool state;
 
-	state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
+	state = g4x_dp_port_enabled(display, dp_reg, port, &port_pipe);
 
 	INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,
 				 "PCH DP %c enabled on transcoder %c, should be disabled\n",
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index ef6effaf82e0..617ce4993172 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -134,7 +134,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 		release_cl_override = display->platform.cherryview &&
 			!chv_phy_powergate_ch(display, phy, ch, true);
 
-		if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
+		if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(display))) {
 			drm_err(display->drm,
 				"Failed to force on PLL for pipe %c!\n",
 				pipe_name(pipe));
@@ -1225,11 +1225,10 @@ static void vlv_steal_power_sequencer(struct intel_display *display,
 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
-	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	enum pipe pipe;
 
-	if (g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
+	if (g4x_dp_port_enabled(display, intel_dp->output_reg,
 				encoder->port, &pipe))
 		return pipe;
 
@@ -1859,13 +1858,13 @@ void assert_pps_unlocked(struct intel_display *display, enum pipe pipe)
 			intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
 			break;
 		case PANEL_PORT_SELECT_DPA:
-			g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
+			g4x_dp_port_enabled(display, DP_A, PORT_A, &panel_pipe);
 			break;
 		case PANEL_PORT_SELECT_DPC:
-			g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
+			g4x_dp_port_enabled(display, PCH_DP_C, PORT_C, &panel_pipe);
 			break;
 		case PANEL_PORT_SELECT_DPD:
-			g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
+			g4x_dp_port_enabled(display, PCH_DP_D, PORT_D, &panel_pipe);
 			break;
 		default:
 			MISSING_CASE(port_sel);
-- 
2.39.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* RE: [PATCH 01/14] drm/i915/dp: convert g4x_dp.[ch] to struct intel display
  2025-02-12 16:36 ` [PATCH 01/14] drm/i915/dp: convert g4x_dp.[ch] to struct intel display Jani Nikula
@ 2025-02-13  8:48   ` Kandpal, Suraj
  2025-02-13  9:13     ` Jani Nikula
  0 siblings, 1 reply; 35+ messages in thread
From: Kandpal, Suraj @ 2025-02-13  8:48 UTC (permalink / raw)
  To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org
  Cc: Nikula, Jani



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Wednesday, February 12, 2025 10:07 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 01/14] drm/i915/dp: convert g4x_dp.[ch] to struct intel
> display
> 
> Going forward, struct intel_display is the main display device data pointer.
> Convert as much as possible of g4x_dp.[ch] to struct intel_display.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/g4x_dp.c         | 80 +++++++++----------
>  drivers/gpu/drm/i915/display/g4x_dp.h         | 14 ++--
>  drivers/gpu/drm/i915/display/intel_display.c  | 20 ++---
> .../gpu/drm/i915/display/intel_pch_display.c  |  2 +-
>  drivers/gpu/drm/i915/display/intel_pps.c      | 11 ++-
>  5 files changed, 61 insertions(+), 66 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> b/drivers/gpu/drm/i915/display/g4x_dp.c
> index d3b5ead188ba..cfc796607a78 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -51,28 +51,29 @@ static const struct dpll chv_dpll[] = {
>  	{ .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /*
> 27.0 */ },  };
> 
> -const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
> +const struct dpll *vlv_get_dpll(struct intel_display *display)
>  {
> -	return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0];
> +	return display->platform.cherryview ? &chv_dpll[0] : &vlv_dpll[0];
>  }
> 
>  static void g4x_dp_set_clock(struct intel_encoder *encoder,
>  			     struct intel_crtc_state *pipe_config)  {
> +	struct intel_display *display = to_intel_display(encoder);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	const struct dpll *divisor = NULL;
>  	int i, count = 0;
> 
> -	if (IS_G4X(dev_priv)) {
> +	if (display->platform.g4x) {
>  		divisor = g4x_dpll;
>  		count = ARRAY_SIZE(g4x_dpll);
>  	} else if (HAS_PCH_SPLIT(dev_priv)) {
>  		divisor = pch_dpll;
>  		count = ARRAY_SIZE(pch_dpll);
> -	} else if (IS_CHERRYVIEW(dev_priv)) {
> +	} else if (display->platform.cherryview) {
>  		divisor = chv_dpll;
>  		count = ARRAY_SIZE(chv_dpll);
> -	} else if (IS_VALLEYVIEW(dev_priv)) {
> +	} else if (display->platform.valleyview) {
>  		divisor = vlv_dpll;
>  		count = ARRAY_SIZE(vlv_dpll);
>  	}
> @@ -129,7 +130,7 @@ static void intel_dp_prepare(struct intel_encoder
> *encoder,
> 
>  	/* Split out the IBX/CPU vs CPT settings */
> 
> -	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> +	if (display->platform.ivybridge && port == PORT_A) {
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
>  			intel_dp->DP |= DP_SYNC_HS_HIGH;
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) @@
> -148,7 +149,7 @@ static void intel_dp_prepare(struct intel_encoder
> *encoder,
>  			     pipe_config->enhanced_framing ?
>  			     TRANS_DP_ENH_FRAMING : 0);
>  	} else {
> -		if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
> +		if (display->platform.g4x && pipe_config-
> >limited_color_range)
>  			intel_dp->DP |= DP_COLOR_RANGE_16_235;
> 
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) @@
> -160,7 +161,7 @@ static void intel_dp_prepare(struct intel_encoder
> *encoder,
>  		if (pipe_config->enhanced_framing)
>  			intel_dp->DP |= DP_ENHANCED_FRAMING;
> 
> -		if (IS_CHERRYVIEW(dev_priv))
> +		if (display->platform.cherryview)
>  			intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
>  		else
>  			intel_dp->DP |= DP_PIPE_SEL(crtc->pipe); @@ -180,9
> +181,8 @@ static void assert_dp_port(struct intel_dp *intel_dp, bool state)
> }  #define assert_dp_port_disabled(d) assert_dp_port((d), false)
> 
> -static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
> +static void assert_edp_pll(struct intel_display *display, bool state)
>  {
> -	struct intel_display *display = &dev_priv->display;
>  	bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE;
> 
>  	INTEL_DISPLAY_STATE_WARN(display, cur_state != state, @@ -201,7
> +201,7 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
> 
>  	assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
>  	assert_dp_port_disabled(intel_dp);
> -	assert_edp_pll_disabled(dev_priv);
> +	assert_edp_pll_disabled(display);
> 
>  	drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",
>  		    pipe_config->port_clock);
> @@ -223,7 +223,7 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
>  	 * 1. Wait for the start of vertical blank on the enabled pipe going to
> FDI
>  	 * 2. Program DP PLL enable
>  	 */
> -	if (IS_IRONLAKE(dev_priv))
> +	if (display->platform.ironlake)
>  		intel_wait_for_vblank_if_active(display, !crtc->pipe);
> 
>  	intel_dp->DP |= DP_PLL_ENABLE;
> @@ -242,7 +242,7 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp,
> 
>  	assert_transcoder_disabled(dev_priv, old_crtc_state-
> >cpu_transcoder);
>  	assert_dp_port_disabled(intel_dp);
> -	assert_edp_pll_enabled(dev_priv);
> +	assert_edp_pll_enabled(display);
> 
>  	drm_dbg_kms(display->drm, "disabling eDP PLL\n");
> 
> @@ -253,10 +253,9 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp,
>  	udelay(200);
>  }
> 
> -static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
> +static bool cpt_dp_port_selected(struct intel_display *display,
>  				 enum port port, enum pipe *pipe)
>  {
> -	struct intel_display *display = &dev_priv->display;
>  	enum pipe p;
> 
>  	for_each_pipe(display, p) {
> @@ -277,11 +276,11 @@ static bool cpt_dp_port_selected(struct
> drm_i915_private *dev_priv,
>  	return false;
>  }
> 
> -bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
> +bool g4x_dp_port_enabled(struct intel_display *display,
>  			 i915_reg_t dp_reg, enum port port,
>  			 enum pipe *pipe)
>  {
> -	struct intel_display *display = &dev_priv->display;
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	bool ret;
>  	u32 val;
> 
> @@ -290,11 +289,11 @@ bool g4x_dp_port_enabled(struct
> drm_i915_private *dev_priv,
>  	ret = val & DP_PORT_EN;
> 
>  	/* asserts want to know the pipe even if the port is disabled */
> -	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
> +	if (display->platform.ivybridge && port == PORT_A)
>  		*pipe = (val & DP_PIPE_SEL_MASK_IVB) >>
> DP_PIPE_SEL_SHIFT_IVB;
>  	else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
> -		ret &= cpt_dp_port_selected(dev_priv, port, pipe);
> -	else if (IS_CHERRYVIEW(dev_priv))
> +		ret &= cpt_dp_port_selected(display, port, pipe);
> +	else if (display->platform.cherryview)
>  		*pipe = (val & DP_PIPE_SEL_MASK_CHV) >>
> DP_PIPE_SEL_SHIFT_CHV;
>  	else
>  		*pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
> @@ -306,7 +305,6 @@ static bool intel_dp_get_hw_state(struct
> intel_encoder *encoder,
>  				  enum pipe *pipe)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	intel_wakeref_t wakeref;
>  	bool ret;
> @@ -316,7 +314,7 @@ static bool intel_dp_get_hw_state(struct
> intel_encoder *encoder,
>  	if (!wakeref)
>  		return false;
> 
> -	ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
> +	ret = g4x_dp_port_enabled(display, intel_dp->output_reg,
>  				  encoder->port, pipe);
> 
>  	intel_display_power_put(display, encoder->power_domain,
> wakeref); @@ -391,7 +389,7 @@ static void intel_dp_get_config(struct
> intel_encoder *encoder,
> 
>  	pipe_config->hw.adjusted_mode.flags |= flags;
> 
> -	if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
> +	if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235)
>  		pipe_config->limited_color_range = true;
> 
>  	pipe_config->lane_count =
> @@ -433,7 +431,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
> 
>  	drm_dbg_kms(display->drm, "\n");
> 
> -	if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
> +	if ((display->platform.ivybridge && port == PORT_A) ||
>  	    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
>  		intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
>  		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; @@ -479,7
> +477,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
> 
>  	msleep(intel_dp->pps.panel_power_down_delay);
> 
> -	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> +	if (display->platform.valleyview || display->platform.cherryview)
>  		vlv_pps_port_disable(encoder, old_crtc_state);  }
> 
> @@ -682,7 +680,6 @@ static void intel_enable_dp(struct intel_atomic_state
> *state,
>  			    const struct drm_connector_state *conn_state)  {
>  	struct intel_display *display = to_intel_display(state);
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	u32 dp_reg = intel_de_read(display, intel_dp->output_reg);
>  	intel_wakeref_t wakeref;
> @@ -691,7 +688,7 @@ static void intel_enable_dp(struct intel_atomic_state
> *state,
>  		return;
> 
>  	with_intel_pps_lock(intel_dp, wakeref) {
> -		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> +		if (display->platform.valleyview || display-
> >platform.cherryview)
>  			vlv_pps_port_enable_unlocked(encoder,
> pipe_config);
> 
>  		intel_dp_enable_port(intel_dp, pipe_config); @@ -701,10
> +698,10 @@ static void intel_enable_dp(struct intel_atomic_state *state,
>  		intel_pps_vdd_off_unlocked(intel_dp, true);
>  	}
> 
> -	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> +	if (display->platform.valleyview || display->platform.cherryview) {
>  		unsigned int lane_mask = 0x0;
> 
> -		if (IS_CHERRYVIEW(dev_priv))
> +		if (display->platform.cherryview)
>  			lane_mask =
> intel_dp_unused_lane_mask(pipe_config->lane_count);
> 
>  		vlv_wait_port_ready(display, dp_to_dig_port(intel_dp),
> lane_mask); @@ -1264,7 +1261,6 @@ static void
> intel_dp_encoder_destroy(struct drm_encoder *encoder)  static void
> intel_dp_encoder_reset(struct drm_encoder *encoder)  {
>  	struct intel_display *display = to_intel_display(encoder->dev);
> -	struct drm_i915_private *dev_priv = to_i915(encoder->dev);

I know this hasn't changed in this patch and is already there merged in code but a good chance to
Do to_intel_display(encoder) instead of encoder->dev
Otherwise
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

>  	struct intel_dp *intel_dp =
> enc_to_intel_dp(to_intel_encoder(encoder));
> 
>  	intel_dp->DP = intel_de_read(display, intel_dp->output_reg); @@ -
> 1272,7 +1268,7 @@ static void intel_dp_encoder_reset(struct drm_encoder
> *encoder)
>  	intel_dp->reset_link_params = true;
>  	intel_dp_invalidate_source_oui(intel_dp);
> 
> -	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> +	if (display->platform.valleyview || display->platform.cherryview)
>  		vlv_pps_pipe_reset(intel_dp);
> 
>  	intel_pps_encoder_reset(intel_dp);
> @@ -1283,10 +1279,10 @@ static const struct drm_encoder_funcs
> intel_dp_enc_funcs = {
>  	.destroy = intel_dp_encoder_destroy,
>  };
> 
> -bool g4x_dp_init(struct drm_i915_private *dev_priv,
> +bool g4x_dp_init(struct intel_display *display,
>  		 i915_reg_t output_reg, enum port port)  {
> -	struct intel_display *display = &dev_priv->display;
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	const struct intel_bios_encoder_data *devdata;
>  	struct intel_digital_port *dig_port;
>  	struct intel_encoder *intel_encoder;
> @@ -1337,14 +1333,14 @@ bool g4x_dp_init(struct drm_i915_private
> *dev_priv,
>  	intel_encoder->suspend = intel_dp_encoder_suspend;
>  	intel_encoder->suspend_complete = g4x_dp_suspend_complete;
>  	intel_encoder->shutdown = intel_dp_encoder_shutdown;
> -	if (IS_CHERRYVIEW(dev_priv)) {
> +	if (display->platform.cherryview) {
>  		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
>  		intel_encoder->pre_enable = chv_pre_enable_dp;
>  		intel_encoder->enable = vlv_enable_dp;
>  		intel_encoder->disable = vlv_disable_dp;
>  		intel_encoder->post_disable = chv_post_disable_dp;
>  		intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
> -	} else if (IS_VALLEYVIEW(dev_priv)) {
> +	} else if (display->platform.valleyview) {
>  		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
>  		intel_encoder->pre_enable = vlv_pre_enable_dp;
>  		intel_encoder->enable = vlv_enable_dp; @@ -1359,24
> +1355,24 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
>  	intel_encoder->audio_enable = g4x_dp_audio_enable;
>  	intel_encoder->audio_disable = g4x_dp_audio_disable;
> 
> -	if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
> +	if ((display->platform.ivybridge && port == PORT_A) ||
>  	    (HAS_PCH_CPT(dev_priv) && port != PORT_A))
>  		dig_port->dp.set_link_train = cpt_set_link_train;
>  	else
>  		dig_port->dp.set_link_train = g4x_set_link_train;
> 
> -	if (IS_CHERRYVIEW(dev_priv))
> +	if (display->platform.cherryview)
>  		intel_encoder->set_signal_levels = chv_set_signal_levels;
> -	else if (IS_VALLEYVIEW(dev_priv))
> +	else if (display->platform.valleyview)
>  		intel_encoder->set_signal_levels = vlv_set_signal_levels;
> -	else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
> +	else if (display->platform.ivybridge && port == PORT_A)
>  		intel_encoder->set_signal_levels =
> ivb_cpu_edp_set_signal_levels;
> -	else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A)
> +	else if (display->platform.sandybridge && port == PORT_A)
>  		intel_encoder->set_signal_levels =
> snb_cpu_edp_set_signal_levels;
>  	else
>  		intel_encoder->set_signal_levels = g4x_set_signal_levels;
> 
> -	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> +	if (display->platform.valleyview || display->platform.cherryview ||
>  	    (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
>  		dig_port->dp.preemph_max = intel_dp_preemph_max_3;
>  		dig_port->dp.voltage_max = intel_dp_voltage_max_3; @@ -
> 1390,7 +1386,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
> 
>  	intel_encoder->type = INTEL_OUTPUT_DP;
>  	intel_encoder->power_domain =
> intel_display_power_ddi_lanes_domain(display, port);
> -	if (IS_CHERRYVIEW(dev_priv)) {
> +	if (display->platform.cherryview) {
>  		if (port == PORT_D)
>  			intel_encoder->pipe_mask = BIT(PIPE_C);
>  		else
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.h
> b/drivers/gpu/drm/i915/display/g4x_dp.h
> index 839a251dc069..0b28951b8365 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.h
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.h
> @@ -12,30 +12,30 @@
> 
>  enum pipe;
>  enum port;
> -struct drm_i915_private;
>  struct intel_crtc_state;
> +struct intel_display;
>  struct intel_dp;
>  struct intel_encoder;
> 
>  #ifdef I915
> -const struct dpll *vlv_get_dpll(struct drm_i915_private *i915); -bool
> g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
> +const struct dpll *vlv_get_dpll(struct intel_display *display); bool
> +g4x_dp_port_enabled(struct intel_display *display,
>  			 i915_reg_t dp_reg, enum port port,
>  			 enum pipe *pipe);
> -bool g4x_dp_init(struct drm_i915_private *dev_priv,
> +bool g4x_dp_init(struct intel_display *display,
>  		 i915_reg_t output_reg, enum port port);  #else -static inline
> const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
> +static inline const struct dpll *vlv_get_dpll(struct intel_display
> +*display)
>  {
>  	return NULL;
>  }
> -static inline bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
> +static inline bool g4x_dp_port_enabled(struct intel_display *display,
>  				       i915_reg_t dp_reg, int port,
>  				       enum pipe *pipe)
>  {
>  	return false;
>  }
> -static inline bool g4x_dp_init(struct drm_i915_private *dev_priv,
> +static inline bool g4x_dp_init(struct intel_display *display,
>  			       i915_reg_t output_reg, int port)  {
>  	return false;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 6c1e7441313e..e5ceedf56335 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8229,7 +8229,7 @@ void intel_setup_outputs(struct drm_i915_private
> *dev_priv)
>  		dpd_is_edp = intel_dp_is_port_edp(display, PORT_D);
> 
>  		if (ilk_has_edp_a(dev_priv))
> -			g4x_dp_init(dev_priv, DP_A, PORT_A);
> +			g4x_dp_init(display, DP_A, PORT_A);
> 
>  		if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED)
> {
>  			/* PCH SDVOB multiplex with HDMIB */ @@ -8237,7
> +8237,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
>  			if (!found)
>  				g4x_hdmi_init(dev_priv, PCH_HDMIB,
> PORT_B);
>  			if (!found && (intel_de_read(dev_priv, PCH_DP_B) &
> DP_DETECTED))
> -				g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
> +				g4x_dp_init(display, PCH_DP_B, PORT_B);
>  		}
> 
>  		if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
> @@ -8247,10 +8247,10 @@ void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
>  			g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
> 
>  		if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
> -			g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
> +			g4x_dp_init(display, PCH_DP_C, PORT_C);
> 
>  		if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
> -			g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
> +			g4x_dp_init(display, PCH_DP_D, PORT_D);
>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		bool has_edp, has_port;
> 
> @@ -8275,14 +8275,14 @@ void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
>  		has_edp = intel_dp_is_port_edp(display, PORT_B);
>  		has_port = intel_bios_is_port_present(display, PORT_B);
>  		if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED ||
> has_port)
> -			has_edp &= g4x_dp_init(dev_priv, VLV_DP_B,
> PORT_B);
> +			has_edp &= g4x_dp_init(display, VLV_DP_B,
> PORT_B);
>  		if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED
> || has_port) && !has_edp)
>  			g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
> 
>  		has_edp = intel_dp_is_port_edp(display, PORT_C);
>  		has_port = intel_bios_is_port_present(display, PORT_C);
>  		if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED ||
> has_port)
> -			has_edp &= g4x_dp_init(dev_priv, VLV_DP_C,
> PORT_C);
> +			has_edp &= g4x_dp_init(display, VLV_DP_C,
> PORT_C);
>  		if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED
> || has_port) && !has_edp)
>  			g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
> 
> @@ -8293,7 +8293,7 @@ void intel_setup_outputs(struct drm_i915_private
> *dev_priv)
>  			 */
>  			has_port = intel_bios_is_port_present(display,
> PORT_D);
>  			if (intel_de_read(dev_priv, CHV_DP_D) &
> DP_DETECTED || has_port)
> -				g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
> +				g4x_dp_init(display, CHV_DP_D, PORT_D);
>  			if (intel_de_read(dev_priv, CHV_HDMID) &
> SDVO_DETECTED || has_port)
>  				g4x_hdmi_init(dev_priv, CHV_HDMID,
> PORT_D);
>  		}
> @@ -8320,7 +8320,7 @@ void intel_setup_outputs(struct drm_i915_private
> *dev_priv)
>  			}
> 
>  			if (!found && IS_G4X(dev_priv))
> -				g4x_dp_init(dev_priv, DP_B, PORT_B);
> +				g4x_dp_init(display, DP_B, PORT_B);
>  		}
> 
>  		/* Before G4X SDVOC doesn't have its own detect register */
> @@ -8338,11 +8338,11 @@ void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
>  				g4x_hdmi_init(dev_priv, GEN4_HDMIC,
> PORT_C);
>  			}
>  			if (IS_G4X(dev_priv))
> -				g4x_dp_init(dev_priv, DP_C, PORT_C);
> +				g4x_dp_init(display, DP_C, PORT_C);
>  		}
> 
>  		if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) &
> DP_DETECTED))
> -			g4x_dp_init(dev_priv, DP_D, PORT_D);
> +			g4x_dp_init(display, DP_D, PORT_D);
> 
>  		if (SUPPORTS_TV(dev_priv))
>  			intel_tv_init(display);
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
> b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 75ff5592312f..98a6b57ac956 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -45,7 +45,7 @@ static void assert_pch_dp_disabled(struct
> drm_i915_private *dev_priv,
>  	enum pipe port_pipe;
>  	bool state;
> 
> -	state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
> +	state = g4x_dp_port_enabled(display, dp_reg, port, &port_pipe);
> 
>  	INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,
>  				 "PCH DP %c enabled on transcoder %c,
> should be disabled\n", diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
> b/drivers/gpu/drm/i915/display/intel_pps.c
> index ef6effaf82e0..617ce4993172 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -134,7 +134,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
>  		release_cl_override = display->platform.cherryview &&
>  			!chv_phy_powergate_ch(display, phy, ch, true);
> 
> -		if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
> +		if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(display))) {
>  			drm_err(display->drm,
>  				"Failed to force on PLL for pipe %c!\n",
>  				pipe_name(pipe));
> @@ -1225,11 +1225,10 @@ static void vlv_steal_power_sequencer(struct
> intel_display *display,  static enum pipe vlv_active_pipe(struct intel_dp
> *intel_dp)  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> -	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	enum pipe pipe;
> 
> -	if (g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
> +	if (g4x_dp_port_enabled(display, intel_dp->output_reg,
>  				encoder->port, &pipe))
>  		return pipe;
> 
> @@ -1859,13 +1858,13 @@ void assert_pps_unlocked(struct intel_display
> *display, enum pipe pipe)
>  			intel_lvds_port_enabled(dev_priv, PCH_LVDS,
> &panel_pipe);
>  			break;
>  		case PANEL_PORT_SELECT_DPA:
> -			g4x_dp_port_enabled(dev_priv, DP_A, PORT_A,
> &panel_pipe);
> +			g4x_dp_port_enabled(display, DP_A, PORT_A,
> &panel_pipe);
>  			break;
>  		case PANEL_PORT_SELECT_DPC:
> -			g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C,
> &panel_pipe);
> +			g4x_dp_port_enabled(display, PCH_DP_C, PORT_C,
> &panel_pipe);
>  			break;
>  		case PANEL_PORT_SELECT_DPD:
> -			g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D,
> &panel_pipe);
> +			g4x_dp_port_enabled(display, PCH_DP_D, PORT_D,
> &panel_pipe);
>  			break;
>  		default:
>  			MISSING_CASE(port_sel);
> --
> 2.39.5


^ permalink raw reply	[flat|nested] 35+ messages in thread

* RE: [PATCH 01/14] drm/i915/dp: convert g4x_dp.[ch] to struct intel display
  2025-02-13  8:48   ` Kandpal, Suraj
@ 2025-02-13  9:13     ` Jani Nikula
  2025-02-13  9:19       ` Kandpal, Suraj
  0 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2025-02-13  9:13 UTC (permalink / raw)
  To: Kandpal, Suraj, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org

On Thu, 13 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
>> Nikula
>> Sent: Wednesday, February 12, 2025 10:07 PM
>> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>
>> Subject: [PATCH 01/14] drm/i915/dp: convert g4x_dp.[ch] to struct intel
>> display
>>
>> Going forward, struct intel_display is the main display device data pointer.
>> Convert as much as possible of g4x_dp.[ch] to struct intel_display.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/g4x_dp.c         | 80 +++++++++----------
>>  drivers/gpu/drm/i915/display/g4x_dp.h         | 14 ++--
>>  drivers/gpu/drm/i915/display/intel_display.c  | 20 ++---
>> .../gpu/drm/i915/display/intel_pch_display.c  |  2 +-
>>  drivers/gpu/drm/i915/display/intel_pps.c      | 11 ++-
>>  5 files changed, 61 insertions(+), 66 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
>> b/drivers/gpu/drm/i915/display/g4x_dp.c
>> index d3b5ead188ba..cfc796607a78 100644
>> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
>> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
>> @@ -51,28 +51,29 @@ static const struct dpll chv_dpll[] = {
>>       { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /*
>> 27.0 */ },  };
>>
>> -const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
>> +const struct dpll *vlv_get_dpll(struct intel_display *display)
>>  {
>> -     return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0];
>> +     return display->platform.cherryview ? &chv_dpll[0] : &vlv_dpll[0];
>>  }
>>
>>  static void g4x_dp_set_clock(struct intel_encoder *encoder,
>>                            struct intel_crtc_state *pipe_config)  {
>> +     struct intel_display *display = to_intel_display(encoder);
>>       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>       const struct dpll *divisor = NULL;
>>       int i, count = 0;
>>
>> -     if (IS_G4X(dev_priv)) {
>> +     if (display->platform.g4x) {
>>               divisor = g4x_dpll;
>>               count = ARRAY_SIZE(g4x_dpll);
>>       } else if (HAS_PCH_SPLIT(dev_priv)) {
>>               divisor = pch_dpll;
>>               count = ARRAY_SIZE(pch_dpll);
>> -     } else if (IS_CHERRYVIEW(dev_priv)) {
>> +     } else if (display->platform.cherryview) {
>>               divisor = chv_dpll;
>>               count = ARRAY_SIZE(chv_dpll);
>> -     } else if (IS_VALLEYVIEW(dev_priv)) {
>> +     } else if (display->platform.valleyview) {
>>               divisor = vlv_dpll;
>>               count = ARRAY_SIZE(vlv_dpll);
>>       }
>> @@ -129,7 +130,7 @@ static void intel_dp_prepare(struct intel_encoder
>> *encoder,
>>
>>       /* Split out the IBX/CPU vs CPT settings */
>>
>> -     if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
>> +     if (display->platform.ivybridge && port == PORT_A) {
>>               if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
>>                       intel_dp->DP |= DP_SYNC_HS_HIGH;
>>               if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) @@
>> -148,7 +149,7 @@ static void intel_dp_prepare(struct intel_encoder
>> *encoder,
>>                            pipe_config->enhanced_framing ?
>>                            TRANS_DP_ENH_FRAMING : 0);
>>       } else {
>> -             if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
>> +             if (display->platform.g4x && pipe_config-
>> >limited_color_range)
>>                       intel_dp->DP |= DP_COLOR_RANGE_16_235;
>>
>>               if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) @@
>> -160,7 +161,7 @@ static void intel_dp_prepare(struct intel_encoder
>> *encoder,
>>               if (pipe_config->enhanced_framing)
>>                       intel_dp->DP |= DP_ENHANCED_FRAMING;
>>
>> -             if (IS_CHERRYVIEW(dev_priv))
>> +             if (display->platform.cherryview)
>>                       intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
>>               else
>>                       intel_dp->DP |= DP_PIPE_SEL(crtc->pipe); @@ -180,9
>> +181,8 @@ static void assert_dp_port(struct intel_dp *intel_dp, bool state)
>> }  #define assert_dp_port_disabled(d) assert_dp_port((d), false)
>>
>> -static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
>> +static void assert_edp_pll(struct intel_display *display, bool state)
>>  {
>> -     struct intel_display *display = &dev_priv->display;
>>       bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE;
>>
>>       INTEL_DISPLAY_STATE_WARN(display, cur_state != state, @@ -201,7
>> +201,7 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
>>
>>       assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
>>       assert_dp_port_disabled(intel_dp);
>> -     assert_edp_pll_disabled(dev_priv);
>> +     assert_edp_pll_disabled(display);
>>
>>       drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",
>>                   pipe_config->port_clock);
>> @@ -223,7 +223,7 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
>>        * 1. Wait for the start of vertical blank on the enabled pipe going to
>> FDI
>>        * 2. Program DP PLL enable
>>        */
>> -     if (IS_IRONLAKE(dev_priv))
>> +     if (display->platform.ironlake)
>>               intel_wait_for_vblank_if_active(display, !crtc->pipe);
>>
>>       intel_dp->DP |= DP_PLL_ENABLE;
>> @@ -242,7 +242,7 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp,
>>
>>       assert_transcoder_disabled(dev_priv, old_crtc_state-
>> >cpu_transcoder);
>>       assert_dp_port_disabled(intel_dp);
>> -     assert_edp_pll_enabled(dev_priv);
>> +     assert_edp_pll_enabled(display);
>>
>>       drm_dbg_kms(display->drm, "disabling eDP PLL\n");
>>
>> @@ -253,10 +253,9 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp,
>>       udelay(200);
>>  }
>>
>> -static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
>> +static bool cpt_dp_port_selected(struct intel_display *display,
>>                                enum port port, enum pipe *pipe)
>>  {
>> -     struct intel_display *display = &dev_priv->display;
>>       enum pipe p;
>>
>>       for_each_pipe(display, p) {
>> @@ -277,11 +276,11 @@ static bool cpt_dp_port_selected(struct
>> drm_i915_private *dev_priv,
>>       return false;
>>  }
>>
>> -bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
>> +bool g4x_dp_port_enabled(struct intel_display *display,
>>                        i915_reg_t dp_reg, enum port port,
>>                        enum pipe *pipe)
>>  {
>> -     struct intel_display *display = &dev_priv->display;
>> +     struct drm_i915_private *dev_priv = to_i915(display->drm);
>>       bool ret;
>>       u32 val;
>>
>> @@ -290,11 +289,11 @@ bool g4x_dp_port_enabled(struct
>> drm_i915_private *dev_priv,
>>       ret = val & DP_PORT_EN;
>>
>>       /* asserts want to know the pipe even if the port is disabled */
>> -     if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
>> +     if (display->platform.ivybridge && port == PORT_A)
>>               *pipe = (val & DP_PIPE_SEL_MASK_IVB) >>
>> DP_PIPE_SEL_SHIFT_IVB;
>>       else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
>> -             ret &= cpt_dp_port_selected(dev_priv, port, pipe);
>> -     else if (IS_CHERRYVIEW(dev_priv))
>> +             ret &= cpt_dp_port_selected(display, port, pipe);
>> +     else if (display->platform.cherryview)
>>               *pipe = (val & DP_PIPE_SEL_MASK_CHV) >>
>> DP_PIPE_SEL_SHIFT_CHV;
>>       else
>>               *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
>> @@ -306,7 +305,6 @@ static bool intel_dp_get_hw_state(struct
>> intel_encoder *encoder,
>>                                 enum pipe *pipe)
>>  {
>>       struct intel_display *display = to_intel_display(encoder);
>> -     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>       struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>       intel_wakeref_t wakeref;
>>       bool ret;
>> @@ -316,7 +314,7 @@ static bool intel_dp_get_hw_state(struct
>> intel_encoder *encoder,
>>       if (!wakeref)
>>               return false;
>>
>> -     ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
>> +     ret = g4x_dp_port_enabled(display, intel_dp->output_reg,
>>                                 encoder->port, pipe);
>>
>>       intel_display_power_put(display, encoder->power_domain,
>> wakeref); @@ -391,7 +389,7 @@ static void intel_dp_get_config(struct
>> intel_encoder *encoder,
>>
>>       pipe_config->hw.adjusted_mode.flags |= flags;
>>
>> -     if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
>> +     if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235)
>>               pipe_config->limited_color_range = true;
>>
>>       pipe_config->lane_count =
>> @@ -433,7 +431,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
>>
>>       drm_dbg_kms(display->drm, "\n");
>>
>> -     if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
>> +     if ((display->platform.ivybridge && port == PORT_A) ||
>>           (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
>>               intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
>>               intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; @@ -479,7
>> +477,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
>>
>>       msleep(intel_dp->pps.panel_power_down_delay);
>>
>> -     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> +     if (display->platform.valleyview || display->platform.cherryview)
>>               vlv_pps_port_disable(encoder, old_crtc_state);  }
>>
>> @@ -682,7 +680,6 @@ static void intel_enable_dp(struct intel_atomic_state
>> *state,
>>                           const struct drm_connector_state *conn_state)  {
>>       struct intel_display *display = to_intel_display(state);
>> -     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>       struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>       u32 dp_reg = intel_de_read(display, intel_dp->output_reg);
>>       intel_wakeref_t wakeref;
>> @@ -691,7 +688,7 @@ static void intel_enable_dp(struct intel_atomic_state
>> *state,
>>               return;
>>
>>       with_intel_pps_lock(intel_dp, wakeref) {
>> -             if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> +             if (display->platform.valleyview || display-
>> >platform.cherryview)
>>                       vlv_pps_port_enable_unlocked(encoder,
>> pipe_config);
>>
>>               intel_dp_enable_port(intel_dp, pipe_config); @@ -701,10
>> +698,10 @@ static void intel_enable_dp(struct intel_atomic_state *state,
>>               intel_pps_vdd_off_unlocked(intel_dp, true);
>>       }
>>
>> -     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>> +     if (display->platform.valleyview || display->platform.cherryview) {
>>               unsigned int lane_mask = 0x0;
>>
>> -             if (IS_CHERRYVIEW(dev_priv))
>> +             if (display->platform.cherryview)
>>                       lane_mask =
>> intel_dp_unused_lane_mask(pipe_config->lane_count);
>>
>>               vlv_wait_port_ready(display, dp_to_dig_port(intel_dp),
>> lane_mask); @@ -1264,7 +1261,6 @@ static void
>> intel_dp_encoder_destroy(struct drm_encoder *encoder)  static void
>> intel_dp_encoder_reset(struct drm_encoder *encoder)  {
>>       struct intel_display *display = to_intel_display(encoder->dev);
>> -     struct drm_i915_private *dev_priv = to_i915(encoder->dev);
>
> I know this hasn't changed in this patch and is already there merged in code but a good chance to
> Do to_intel_display(encoder) instead of encoder->dev

to_intel_display() intentionally doesn't handle drm_encoder, so can't.

> Otherwise
> LGTM,
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

Thanks, but I've just merged the series with Ville's Reviewed-by.

BR,
Jani.

>
>>       struct intel_dp *intel_dp =
>> enc_to_intel_dp(to_intel_encoder(encoder));
>>
>>       intel_dp->DP = intel_de_read(display, intel_dp->output_reg); @@ -
>> 1272,7 +1268,7 @@ static void intel_dp_encoder_reset(struct drm_encoder
>> *encoder)
>>       intel_dp->reset_link_params = true;
>>       intel_dp_invalidate_source_oui(intel_dp);
>>
>> -     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> +     if (display->platform.valleyview || display->platform.cherryview)
>>               vlv_pps_pipe_reset(intel_dp);
>>
>>       intel_pps_encoder_reset(intel_dp);
>> @@ -1283,10 +1279,10 @@ static const struct drm_encoder_funcs
>> intel_dp_enc_funcs = {
>>       .destroy = intel_dp_encoder_destroy,
>>  };
>>
>> -bool g4x_dp_init(struct drm_i915_private *dev_priv,
>> +bool g4x_dp_init(struct intel_display *display,
>>                i915_reg_t output_reg, enum port port)  {
>> -     struct intel_display *display = &dev_priv->display;
>> +     struct drm_i915_private *dev_priv = to_i915(display->drm);
>>       const struct intel_bios_encoder_data *devdata;
>>       struct intel_digital_port *dig_port;
>>       struct intel_encoder *intel_encoder;
>> @@ -1337,14 +1333,14 @@ bool g4x_dp_init(struct drm_i915_private
>> *dev_priv,
>>       intel_encoder->suspend = intel_dp_encoder_suspend;
>>       intel_encoder->suspend_complete = g4x_dp_suspend_complete;
>>       intel_encoder->shutdown = intel_dp_encoder_shutdown;
>> -     if (IS_CHERRYVIEW(dev_priv)) {
>> +     if (display->platform.cherryview) {
>>               intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
>>               intel_encoder->pre_enable = chv_pre_enable_dp;
>>               intel_encoder->enable = vlv_enable_dp;
>>               intel_encoder->disable = vlv_disable_dp;
>>               intel_encoder->post_disable = chv_post_disable_dp;
>>               intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
>> -     } else if (IS_VALLEYVIEW(dev_priv)) {
>> +     } else if (display->platform.valleyview) {
>>               intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
>>               intel_encoder->pre_enable = vlv_pre_enable_dp;
>>               intel_encoder->enable = vlv_enable_dp; @@ -1359,24
>> +1355,24 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
>>       intel_encoder->audio_enable = g4x_dp_audio_enable;
>>       intel_encoder->audio_disable = g4x_dp_audio_disable;
>>
>> -     if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
>> +     if ((display->platform.ivybridge && port == PORT_A) ||
>>           (HAS_PCH_CPT(dev_priv) && port != PORT_A))
>>               dig_port->dp.set_link_train = cpt_set_link_train;
>>       else
>>               dig_port->dp.set_link_train = g4x_set_link_train;
>>
>> -     if (IS_CHERRYVIEW(dev_priv))
>> +     if (display->platform.cherryview)
>>               intel_encoder->set_signal_levels = chv_set_signal_levels;
>> -     else if (IS_VALLEYVIEW(dev_priv))
>> +     else if (display->platform.valleyview)
>>               intel_encoder->set_signal_levels = vlv_set_signal_levels;
>> -     else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
>> +     else if (display->platform.ivybridge && port == PORT_A)
>>               intel_encoder->set_signal_levels =
>> ivb_cpu_edp_set_signal_levels;
>> -     else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A)
>> +     else if (display->platform.sandybridge && port == PORT_A)
>>               intel_encoder->set_signal_levels =
>> snb_cpu_edp_set_signal_levels;
>>       else
>>               intel_encoder->set_signal_levels = g4x_set_signal_levels;
>>
>> -     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
>> +     if (display->platform.valleyview || display->platform.cherryview ||
>>           (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
>>               dig_port->dp.preemph_max = intel_dp_preemph_max_3;
>>               dig_port->dp.voltage_max = intel_dp_voltage_max_3; @@ -
>> 1390,7 +1386,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
>>
>>       intel_encoder->type = INTEL_OUTPUT_DP;
>>       intel_encoder->power_domain =
>> intel_display_power_ddi_lanes_domain(display, port);
>> -     if (IS_CHERRYVIEW(dev_priv)) {
>> +     if (display->platform.cherryview) {
>>               if (port == PORT_D)
>>                       intel_encoder->pipe_mask = BIT(PIPE_C);
>>               else
>> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.h
>> b/drivers/gpu/drm/i915/display/g4x_dp.h
>> index 839a251dc069..0b28951b8365 100644
>> --- a/drivers/gpu/drm/i915/display/g4x_dp.h
>> +++ b/drivers/gpu/drm/i915/display/g4x_dp.h
>> @@ -12,30 +12,30 @@
>>
>>  enum pipe;
>>  enum port;
>> -struct drm_i915_private;
>>  struct intel_crtc_state;
>> +struct intel_display;
>>  struct intel_dp;
>>  struct intel_encoder;
>>
>>  #ifdef I915
>> -const struct dpll *vlv_get_dpll(struct drm_i915_private *i915); -bool
>> g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
>> +const struct dpll *vlv_get_dpll(struct intel_display *display); bool
>> +g4x_dp_port_enabled(struct intel_display *display,
>>                        i915_reg_t dp_reg, enum port port,
>>                        enum pipe *pipe);
>> -bool g4x_dp_init(struct drm_i915_private *dev_priv,
>> +bool g4x_dp_init(struct intel_display *display,
>>                i915_reg_t output_reg, enum port port);  #else -static inline
>> const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
>> +static inline const struct dpll *vlv_get_dpll(struct intel_display
>> +*display)
>>  {
>>       return NULL;
>>  }
>> -static inline bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
>> +static inline bool g4x_dp_port_enabled(struct intel_display *display,
>>                                      i915_reg_t dp_reg, int port,
>>                                      enum pipe *pipe)
>>  {
>>       return false;
>>  }
>> -static inline bool g4x_dp_init(struct drm_i915_private *dev_priv,
>> +static inline bool g4x_dp_init(struct intel_display *display,
>>                              i915_reg_t output_reg, int port)  {
>>       return false;
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index 6c1e7441313e..e5ceedf56335 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -8229,7 +8229,7 @@ void intel_setup_outputs(struct drm_i915_private
>> *dev_priv)
>>               dpd_is_edp = intel_dp_is_port_edp(display, PORT_D);
>>
>>               if (ilk_has_edp_a(dev_priv))
>> -                     g4x_dp_init(dev_priv, DP_A, PORT_A);
>> +                     g4x_dp_init(display, DP_A, PORT_A);
>>
>>               if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED)
>> {
>>                       /* PCH SDVOB multiplex with HDMIB */ @@ -8237,7
>> +8237,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
>>                       if (!found)
>>                               g4x_hdmi_init(dev_priv, PCH_HDMIB,
>> PORT_B);
>>                       if (!found && (intel_de_read(dev_priv, PCH_DP_B) &
>> DP_DETECTED))
>> -                             g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
>> +                             g4x_dp_init(display, PCH_DP_B, PORT_B);
>>               }
>>
>>               if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
>> @@ -8247,10 +8247,10 @@ void intel_setup_outputs(struct
>> drm_i915_private *dev_priv)
>>                       g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
>>
>>               if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
>> -                     g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
>> +                     g4x_dp_init(display, PCH_DP_C, PORT_C);
>>
>>               if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
>> -                     g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
>> +                     g4x_dp_init(display, PCH_DP_D, PORT_D);
>>       } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>>               bool has_edp, has_port;
>>
>> @@ -8275,14 +8275,14 @@ void intel_setup_outputs(struct
>> drm_i915_private *dev_priv)
>>               has_edp = intel_dp_is_port_edp(display, PORT_B);
>>               has_port = intel_bios_is_port_present(display, PORT_B);
>>               if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED ||
>> has_port)
>> -                     has_edp &= g4x_dp_init(dev_priv, VLV_DP_B,
>> PORT_B);
>> +                     has_edp &= g4x_dp_init(display, VLV_DP_B,
>> PORT_B);
>>               if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED
>> || has_port) && !has_edp)
>>                       g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
>>
>>               has_edp = intel_dp_is_port_edp(display, PORT_C);
>>               has_port = intel_bios_is_port_present(display, PORT_C);
>>               if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED ||
>> has_port)
>> -                     has_edp &= g4x_dp_init(dev_priv, VLV_DP_C,
>> PORT_C);
>> +                     has_edp &= g4x_dp_init(display, VLV_DP_C,
>> PORT_C);
>>               if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED
>> || has_port) && !has_edp)
>>                       g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
>>
>> @@ -8293,7 +8293,7 @@ void intel_setup_outputs(struct drm_i915_private
>> *dev_priv)
>>                        */
>>                       has_port = intel_bios_is_port_present(display,
>> PORT_D);
>>                       if (intel_de_read(dev_priv, CHV_DP_D) &
>> DP_DETECTED || has_port)
>> -                             g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
>> +                             g4x_dp_init(display, CHV_DP_D, PORT_D);
>>                       if (intel_de_read(dev_priv, CHV_HDMID) &
>> SDVO_DETECTED || has_port)
>>                               g4x_hdmi_init(dev_priv, CHV_HDMID,
>> PORT_D);
>>               }
>> @@ -8320,7 +8320,7 @@ void intel_setup_outputs(struct drm_i915_private
>> *dev_priv)
>>                       }
>>
>>                       if (!found && IS_G4X(dev_priv))
>> -                             g4x_dp_init(dev_priv, DP_B, PORT_B);
>> +                             g4x_dp_init(display, DP_B, PORT_B);
>>               }
>>
>>               /* Before G4X SDVOC doesn't have its own detect register */
>> @@ -8338,11 +8338,11 @@ void intel_setup_outputs(struct
>> drm_i915_private *dev_priv)
>>                               g4x_hdmi_init(dev_priv, GEN4_HDMIC,
>> PORT_C);
>>                       }
>>                       if (IS_G4X(dev_priv))
>> -                             g4x_dp_init(dev_priv, DP_C, PORT_C);
>> +                             g4x_dp_init(display, DP_C, PORT_C);
>>               }
>>
>>               if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) &
>> DP_DETECTED))
>> -                     g4x_dp_init(dev_priv, DP_D, PORT_D);
>> +                     g4x_dp_init(display, DP_D, PORT_D);
>>
>>               if (SUPPORTS_TV(dev_priv))
>>                       intel_tv_init(display);
>> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
>> b/drivers/gpu/drm/i915/display/intel_pch_display.c
>> index 75ff5592312f..98a6b57ac956 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
>> @@ -45,7 +45,7 @@ static void assert_pch_dp_disabled(struct
>> drm_i915_private *dev_priv,
>>       enum pipe port_pipe;
>>       bool state;
>>
>> -     state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
>> +     state = g4x_dp_port_enabled(display, dp_reg, port, &port_pipe);
>>
>>       INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,
>>                                "PCH DP %c enabled on transcoder %c,
>> should be disabled\n", diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
>> b/drivers/gpu/drm/i915/display/intel_pps.c
>> index ef6effaf82e0..617ce4993172 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> @@ -134,7 +134,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
>>               release_cl_override = display->platform.cherryview &&
>>                       !chv_phy_powergate_ch(display, phy, ch, true);
>>
>> -             if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
>> +             if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(display))) {
>>                       drm_err(display->drm,
>>                               "Failed to force on PLL for pipe %c!\n",
>>                               pipe_name(pipe));
>> @@ -1225,11 +1225,10 @@ static void vlv_steal_power_sequencer(struct
>> intel_display *display,  static enum pipe vlv_active_pipe(struct intel_dp
>> *intel_dp)  {
>>       struct intel_display *display = to_intel_display(intel_dp);
>> -     struct drm_i915_private *dev_priv = to_i915(display->drm);
>>       struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>>       enum pipe pipe;
>>
>> -     if (g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
>> +     if (g4x_dp_port_enabled(display, intel_dp->output_reg,
>>                               encoder->port, &pipe))
>>               return pipe;
>>
>> @@ -1859,13 +1858,13 @@ void assert_pps_unlocked(struct intel_display
>> *display, enum pipe pipe)
>>                       intel_lvds_port_enabled(dev_priv, PCH_LVDS,
>> &panel_pipe);
>>                       break;
>>               case PANEL_PORT_SELECT_DPA:
>> -                     g4x_dp_port_enabled(dev_priv, DP_A, PORT_A,
>> &panel_pipe);
>> +                     g4x_dp_port_enabled(display, DP_A, PORT_A,
>> &panel_pipe);
>>                       break;
>>               case PANEL_PORT_SELECT_DPC:
>> -                     g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C,
>> &panel_pipe);
>> +                     g4x_dp_port_enabled(display, PCH_DP_C, PORT_C,
>> &panel_pipe);
>>                       break;
>>               case PANEL_PORT_SELECT_DPD:
>> -                     g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D,
>> &panel_pipe);
>> +                     g4x_dp_port_enabled(display, PCH_DP_D, PORT_D,
>> &panel_pipe);
>>                       break;
>>               default:
>>                       MISSING_CASE(port_sel);
>> --
>> 2.39.5
>

-- 
Jani Nikula, Intel

^ permalink raw reply	[flat|nested] 35+ messages in thread

* RE: [PATCH 01/14] drm/i915/dp: convert g4x_dp.[ch] to struct intel display
  2025-02-13  9:13     ` Jani Nikula
@ 2025-02-13  9:19       ` Kandpal, Suraj
  0 siblings, 0 replies; 35+ messages in thread
From: Kandpal, Suraj @ 2025-02-13  9:19 UTC (permalink / raw)
  To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org



> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, February 13, 2025 2:43 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Subject: RE: [PATCH 01/14] drm/i915/dp: convert g4x_dp.[ch] to struct intel
> display
> 
> On Thu, 13 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
> >> -----Original Message-----
> >> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> >> Of Jani Nikula
> >> Sent: Wednesday, February 12, 2025 10:07 PM
> >> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> >> Cc: Nikula, Jani <jani.nikula@intel.com>
> >> Subject: [PATCH 01/14] drm/i915/dp: convert g4x_dp.[ch] to struct
> >> intel display
> >>
> >> Going forward, struct intel_display is the main display device data pointer.
> >> Convert as much as possible of g4x_dp.[ch] to struct intel_display.
> >>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/g4x_dp.c         | 80 +++++++++----------
> >>  drivers/gpu/drm/i915/display/g4x_dp.h         | 14 ++--
> >>  drivers/gpu/drm/i915/display/intel_display.c  | 20 ++---
> >> .../gpu/drm/i915/display/intel_pch_display.c  |  2 +-
> >>  drivers/gpu/drm/i915/display/intel_pps.c      | 11 ++-
> >>  5 files changed, 61 insertions(+), 66 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> >> b/drivers/gpu/drm/i915/display/g4x_dp.c
> >> index d3b5ead188ba..cfc796607a78 100644
> >> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> >> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> >> @@ -51,28 +51,29 @@ static const struct dpll chv_dpll[] = {
> >>       { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 =
> >> 0x6c00000 /*
> >> 27.0 */ },  };
> >>
> >> -const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
> >> +const struct dpll *vlv_get_dpll(struct intel_display *display)
> >>  {
> >> -     return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0];
> >> +     return display->platform.cherryview ? &chv_dpll[0] :
> >> + &vlv_dpll[0];
> >>  }
> >>
> >>  static void g4x_dp_set_clock(struct intel_encoder *encoder,
> >>                            struct intel_crtc_state *pipe_config)  {
> >> +     struct intel_display *display = to_intel_display(encoder);
> >>       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >>       const struct dpll *divisor = NULL;
> >>       int i, count = 0;
> >>
> >> -     if (IS_G4X(dev_priv)) {
> >> +     if (display->platform.g4x) {
> >>               divisor = g4x_dpll;
> >>               count = ARRAY_SIZE(g4x_dpll);
> >>       } else if (HAS_PCH_SPLIT(dev_priv)) {
> >>               divisor = pch_dpll;
> >>               count = ARRAY_SIZE(pch_dpll);
> >> -     } else if (IS_CHERRYVIEW(dev_priv)) {
> >> +     } else if (display->platform.cherryview) {
> >>               divisor = chv_dpll;
> >>               count = ARRAY_SIZE(chv_dpll);
> >> -     } else if (IS_VALLEYVIEW(dev_priv)) {
> >> +     } else if (display->platform.valleyview) {
> >>               divisor = vlv_dpll;
> >>               count = ARRAY_SIZE(vlv_dpll);
> >>       }
> >> @@ -129,7 +130,7 @@ static void intel_dp_prepare(struct intel_encoder
> >> *encoder,
> >>
> >>       /* Split out the IBX/CPU vs CPT settings */
> >>
> >> -     if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> >> +     if (display->platform.ivybridge && port == PORT_A) {
> >>               if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> >>                       intel_dp->DP |= DP_SYNC_HS_HIGH;
> >>               if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) @@
> >> -148,7 +149,7 @@ static void intel_dp_prepare(struct intel_encoder
> >> *encoder,
> >>                            pipe_config->enhanced_framing ?
> >>                            TRANS_DP_ENH_FRAMING : 0);
> >>       } else {
> >> -             if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
> >> +             if (display->platform.g4x && pipe_config-
> >> >limited_color_range)
> >>                       intel_dp->DP |= DP_COLOR_RANGE_16_235;
> >>
> >>               if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) @@
> >> -160,7 +161,7 @@ static void intel_dp_prepare(struct intel_encoder
> >> *encoder,
> >>               if (pipe_config->enhanced_framing)
> >>                       intel_dp->DP |= DP_ENHANCED_FRAMING;
> >>
> >> -             if (IS_CHERRYVIEW(dev_priv))
> >> +             if (display->platform.cherryview)
> >>                       intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
> >>               else
> >>                       intel_dp->DP |= DP_PIPE_SEL(crtc->pipe); @@
> >> -180,9
> >> +181,8 @@ static void assert_dp_port(struct intel_dp *intel_dp, bool
> >> +state)
> >> }  #define assert_dp_port_disabled(d) assert_dp_port((d), false)
> >>
> >> -static void assert_edp_pll(struct drm_i915_private *dev_priv, bool
> >> state)
> >> +static void assert_edp_pll(struct intel_display *display, bool
> >> +state)
> >>  {
> >> -     struct intel_display *display = &dev_priv->display;
> >>       bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE;
> >>
> >>       INTEL_DISPLAY_STATE_WARN(display, cur_state != state, @@ -201,7
> >> +201,7 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
> >>
> >>       assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
> >>       assert_dp_port_disabled(intel_dp);
> >> -     assert_edp_pll_disabled(dev_priv);
> >> +     assert_edp_pll_disabled(display);
> >>
> >>       drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",
> >>                   pipe_config->port_clock); @@ -223,7 +223,7 @@
> >> static void ilk_edp_pll_on(struct intel_dp *intel_dp,
> >>        * 1. Wait for the start of vertical blank on the enabled pipe
> >> going to FDI
> >>        * 2. Program DP PLL enable
> >>        */
> >> -     if (IS_IRONLAKE(dev_priv))
> >> +     if (display->platform.ironlake)
> >>               intel_wait_for_vblank_if_active(display, !crtc->pipe);
> >>
> >>       intel_dp->DP |= DP_PLL_ENABLE;
> >> @@ -242,7 +242,7 @@ static void ilk_edp_pll_off(struct intel_dp
> >> *intel_dp,
> >>
> >>       assert_transcoder_disabled(dev_priv, old_crtc_state-
> >> >cpu_transcoder);
> >>       assert_dp_port_disabled(intel_dp);
> >> -     assert_edp_pll_enabled(dev_priv);
> >> +     assert_edp_pll_enabled(display);
> >>
> >>       drm_dbg_kms(display->drm, "disabling eDP PLL\n");
> >>
> >> @@ -253,10 +253,9 @@ static void ilk_edp_pll_off(struct intel_dp
> *intel_dp,
> >>       udelay(200);
> >>  }
> >>
> >> -static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
> >> +static bool cpt_dp_port_selected(struct intel_display *display,
> >>                                enum port port, enum pipe *pipe)  {
> >> -     struct intel_display *display = &dev_priv->display;
> >>       enum pipe p;
> >>
> >>       for_each_pipe(display, p) {
> >> @@ -277,11 +276,11 @@ static bool cpt_dp_port_selected(struct
> >> drm_i915_private *dev_priv,
> >>       return false;
> >>  }
> >>
> >> -bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
> >> +bool g4x_dp_port_enabled(struct intel_display *display,
> >>                        i915_reg_t dp_reg, enum port port,
> >>                        enum pipe *pipe)  {
> >> -     struct intel_display *display = &dev_priv->display;
> >> +     struct drm_i915_private *dev_priv = to_i915(display->drm);
> >>       bool ret;
> >>       u32 val;
> >>
> >> @@ -290,11 +289,11 @@ bool g4x_dp_port_enabled(struct
> >> drm_i915_private *dev_priv,
> >>       ret = val & DP_PORT_EN;
> >>
> >>       /* asserts want to know the pipe even if the port is disabled */
> >> -     if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
> >> +     if (display->platform.ivybridge && port == PORT_A)
> >>               *pipe = (val & DP_PIPE_SEL_MASK_IVB) >>
> >> DP_PIPE_SEL_SHIFT_IVB;
> >>       else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
> >> -             ret &= cpt_dp_port_selected(dev_priv, port, pipe);
> >> -     else if (IS_CHERRYVIEW(dev_priv))
> >> +             ret &= cpt_dp_port_selected(display, port, pipe);
> >> +     else if (display->platform.cherryview)
> >>               *pipe = (val & DP_PIPE_SEL_MASK_CHV) >>
> >> DP_PIPE_SEL_SHIFT_CHV;
> >>       else
> >>               *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
> >> @@ -306,7 +305,6 @@ static bool intel_dp_get_hw_state(struct
> >> intel_encoder *encoder,
> >>                                 enum pipe *pipe)  {
> >>       struct intel_display *display = to_intel_display(encoder);
> >> -     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >>       struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >>       intel_wakeref_t wakeref;
> >>       bool ret;
> >> @@ -316,7 +314,7 @@ static bool intel_dp_get_hw_state(struct
> >> intel_encoder *encoder,
> >>       if (!wakeref)
> >>               return false;
> >>
> >> -     ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
> >> +     ret = g4x_dp_port_enabled(display, intel_dp->output_reg,
> >>                                 encoder->port, pipe);
> >>
> >>       intel_display_power_put(display, encoder->power_domain,
> >> wakeref); @@ -391,7 +389,7 @@ static void intel_dp_get_config(struct
> >> intel_encoder *encoder,
> >>
> >>       pipe_config->hw.adjusted_mode.flags |= flags;
> >>
> >> -     if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
> >> +     if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235)
> >>               pipe_config->limited_color_range = true;
> >>
> >>       pipe_config->lane_count =
> >> @@ -433,7 +431,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
> >>
> >>       drm_dbg_kms(display->drm, "\n");
> >>
> >> -     if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
> >> +     if ((display->platform.ivybridge && port == PORT_A) ||
> >>           (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
> >>               intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
> >>               intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; @@ -479,7
> >> +477,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
> >>
> >>       msleep(intel_dp->pps.panel_power_down_delay);
> >>
> >> -     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> >> +     if (display->platform.valleyview ||
> >> + display->platform.cherryview)
> >>               vlv_pps_port_disable(encoder, old_crtc_state);  }
> >>
> >> @@ -682,7 +680,6 @@ static void intel_enable_dp(struct
> >> intel_atomic_state *state,
> >>                           const struct drm_connector_state *conn_state)  {
> >>       struct intel_display *display = to_intel_display(state);
> >> -     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >>       struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >>       u32 dp_reg = intel_de_read(display, intel_dp->output_reg);
> >>       intel_wakeref_t wakeref;
> >> @@ -691,7 +688,7 @@ static void intel_enable_dp(struct
> >> intel_atomic_state *state,
> >>               return;
> >>
> >>       with_intel_pps_lock(intel_dp, wakeref) {
> >> -             if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> >> +             if (display->platform.valleyview || display-
> >> >platform.cherryview)
> >>                       vlv_pps_port_enable_unlocked(encoder,
> >> pipe_config);
> >>
> >>               intel_dp_enable_port(intel_dp, pipe_config); @@ -701,10
> >> +698,10 @@ static void intel_enable_dp(struct intel_atomic_state
> >> +*state,
> >>               intel_pps_vdd_off_unlocked(intel_dp, true);
> >>       }
> >>
> >> -     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> >> +     if (display->platform.valleyview ||
> >> + display->platform.cherryview) {
> >>               unsigned int lane_mask = 0x0;
> >>
> >> -             if (IS_CHERRYVIEW(dev_priv))
> >> +             if (display->platform.cherryview)
> >>                       lane_mask =
> >> intel_dp_unused_lane_mask(pipe_config->lane_count);
> >>
> >>               vlv_wait_port_ready(display, dp_to_dig_port(intel_dp),
> >> lane_mask); @@ -1264,7 +1261,6 @@ static void
> >> intel_dp_encoder_destroy(struct drm_encoder *encoder)  static void
> >> intel_dp_encoder_reset(struct drm_encoder *encoder)  {
> >>       struct intel_display *display = to_intel_display(encoder->dev);
> >> -     struct drm_i915_private *dev_priv = to_i915(encoder->dev);
> >
> > I know this hasn't changed in this patch and is already there merged
> > in code but a good chance to Do to_intel_display(encoder) instead of
> > encoder->dev
> 
> to_intel_display() intentionally doesn't handle drm_encoder, so can't.
> 
> > Otherwise
> > LGTM,
> > Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> 
> Thanks, but I've just merged the series with Ville's Reviewed-by.

Ohkay didn't read this till I got to the 10th patch

Regards,
Suraj Kandpal

> 
> BR,
> Jani.
> 
> >
> >>       struct intel_dp *intel_dp =
> >> enc_to_intel_dp(to_intel_encoder(encoder));
> >>
> >>       intel_dp->DP = intel_de_read(display, intel_dp->output_reg); @@
> >> -
> >> 1272,7 +1268,7 @@ static void intel_dp_encoder_reset(struct
> >> drm_encoder
> >> *encoder)
> >>       intel_dp->reset_link_params = true;
> >>       intel_dp_invalidate_source_oui(intel_dp);
> >>
> >> -     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> >> +     if (display->platform.valleyview ||
> >> + display->platform.cherryview)
> >>               vlv_pps_pipe_reset(intel_dp);
> >>
> >>       intel_pps_encoder_reset(intel_dp);
> >> @@ -1283,10 +1279,10 @@ static const struct drm_encoder_funcs
> >> intel_dp_enc_funcs = {
> >>       .destroy = intel_dp_encoder_destroy,  };
> >>
> >> -bool g4x_dp_init(struct drm_i915_private *dev_priv,
> >> +bool g4x_dp_init(struct intel_display *display,
> >>                i915_reg_t output_reg, enum port port)  {
> >> -     struct intel_display *display = &dev_priv->display;
> >> +     struct drm_i915_private *dev_priv = to_i915(display->drm);
> >>       const struct intel_bios_encoder_data *devdata;
> >>       struct intel_digital_port *dig_port;
> >>       struct intel_encoder *intel_encoder; @@ -1337,14 +1333,14 @@
> >> bool g4x_dp_init(struct drm_i915_private *dev_priv,
> >>       intel_encoder->suspend = intel_dp_encoder_suspend;
> >>       intel_encoder->suspend_complete = g4x_dp_suspend_complete;
> >>       intel_encoder->shutdown = intel_dp_encoder_shutdown;
> >> -     if (IS_CHERRYVIEW(dev_priv)) {
> >> +     if (display->platform.cherryview) {
> >>               intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
> >>               intel_encoder->pre_enable = chv_pre_enable_dp;
> >>               intel_encoder->enable = vlv_enable_dp;
> >>               intel_encoder->disable = vlv_disable_dp;
> >>               intel_encoder->post_disable = chv_post_disable_dp;
> >>               intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
> >> -     } else if (IS_VALLEYVIEW(dev_priv)) {
> >> +     } else if (display->platform.valleyview) {
> >>               intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
> >>               intel_encoder->pre_enable = vlv_pre_enable_dp;
> >>               intel_encoder->enable = vlv_enable_dp; @@ -1359,24
> >> +1355,24 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
> >>       intel_encoder->audio_enable = g4x_dp_audio_enable;
> >>       intel_encoder->audio_disable = g4x_dp_audio_disable;
> >>
> >> -     if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
> >> +     if ((display->platform.ivybridge && port == PORT_A) ||
> >>           (HAS_PCH_CPT(dev_priv) && port != PORT_A))
> >>               dig_port->dp.set_link_train = cpt_set_link_train;
> >>       else
> >>               dig_port->dp.set_link_train = g4x_set_link_train;
> >>
> >> -     if (IS_CHERRYVIEW(dev_priv))
> >> +     if (display->platform.cherryview)
> >>               intel_encoder->set_signal_levels = chv_set_signal_levels;
> >> -     else if (IS_VALLEYVIEW(dev_priv))
> >> +     else if (display->platform.valleyview)
> >>               intel_encoder->set_signal_levels = vlv_set_signal_levels;
> >> -     else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
> >> +     else if (display->platform.ivybridge && port == PORT_A)
> >>               intel_encoder->set_signal_levels =
> >> ivb_cpu_edp_set_signal_levels;
> >> -     else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A)
> >> +     else if (display->platform.sandybridge && port == PORT_A)
> >>               intel_encoder->set_signal_levels =
> >> snb_cpu_edp_set_signal_levels;
> >>       else
> >>               intel_encoder->set_signal_levels =
> >> g4x_set_signal_levels;
> >>
> >> -     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> >> +     if (display->platform.valleyview ||
> >> + display->platform.cherryview ||
> >>           (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
> >>               dig_port->dp.preemph_max = intel_dp_preemph_max_3;
> >>               dig_port->dp.voltage_max = intel_dp_voltage_max_3; @@ -
> >> 1390,7 +1386,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
> >>
> >>       intel_encoder->type = INTEL_OUTPUT_DP;
> >>       intel_encoder->power_domain =
> >> intel_display_power_ddi_lanes_domain(display, port);
> >> -     if (IS_CHERRYVIEW(dev_priv)) {
> >> +     if (display->platform.cherryview) {
> >>               if (port == PORT_D)
> >>                       intel_encoder->pipe_mask = BIT(PIPE_C);
> >>               else
> >> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.h
> >> b/drivers/gpu/drm/i915/display/g4x_dp.h
> >> index 839a251dc069..0b28951b8365 100644
> >> --- a/drivers/gpu/drm/i915/display/g4x_dp.h
> >> +++ b/drivers/gpu/drm/i915/display/g4x_dp.h
> >> @@ -12,30 +12,30 @@
> >>
> >>  enum pipe;
> >>  enum port;
> >> -struct drm_i915_private;
> >>  struct intel_crtc_state;
> >> +struct intel_display;
> >>  struct intel_dp;
> >>  struct intel_encoder;
> >>
> >>  #ifdef I915
> >> -const struct dpll *vlv_get_dpll(struct drm_i915_private *i915);
> >> -bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
> >> +const struct dpll *vlv_get_dpll(struct intel_display *display); bool
> >> +g4x_dp_port_enabled(struct intel_display *display,
> >>                        i915_reg_t dp_reg, enum port port,
> >>                        enum pipe *pipe); -bool g4x_dp_init(struct
> >> drm_i915_private *dev_priv,
> >> +bool g4x_dp_init(struct intel_display *display,
> >>                i915_reg_t output_reg, enum port port);  #else -static
> >> inline const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
> >> +static inline const struct dpll *vlv_get_dpll(struct intel_display
> >> +*display)
> >>  {
> >>       return NULL;
> >>  }
> >> -static inline bool g4x_dp_port_enabled(struct drm_i915_private
> >> *dev_priv,
> >> +static inline bool g4x_dp_port_enabled(struct intel_display
> >> +*display,
> >>                                      i915_reg_t dp_reg, int port,
> >>                                      enum pipe *pipe)  {
> >>       return false;
> >>  }
> >> -static inline bool g4x_dp_init(struct drm_i915_private *dev_priv,
> >> +static inline bool g4x_dp_init(struct intel_display *display,
> >>                              i915_reg_t output_reg, int port)  {
> >>       return false;
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> >> b/drivers/gpu/drm/i915/display/intel_display.c
> >> index 6c1e7441313e..e5ceedf56335 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -8229,7 +8229,7 @@ void intel_setup_outputs(struct
> >> drm_i915_private
> >> *dev_priv)
> >>               dpd_is_edp = intel_dp_is_port_edp(display, PORT_D);
> >>
> >>               if (ilk_has_edp_a(dev_priv))
> >> -                     g4x_dp_init(dev_priv, DP_A, PORT_A);
> >> +                     g4x_dp_init(display, DP_A, PORT_A);
> >>
> >>               if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED)
> >> {
> >>                       /* PCH SDVOB multiplex with HDMIB */ @@ -8237,7
> >> +8237,7 @@ void intel_setup_outputs(struct drm_i915_private
> >> +*dev_priv)
> >>                       if (!found)
> >>                               g4x_hdmi_init(dev_priv, PCH_HDMIB,
> >> PORT_B);
> >>                       if (!found && (intel_de_read(dev_priv,
> >> PCH_DP_B) &
> >> DP_DETECTED))
> >> -                             g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
> >> +                             g4x_dp_init(display, PCH_DP_B, PORT_B);
> >>               }
> >>
> >>               if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
> >> @@ -8247,10 +8247,10 @@ void intel_setup_outputs(struct
> >> drm_i915_private *dev_priv)
> >>                       g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
> >>
> >>               if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
> >> -                     g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
> >> +                     g4x_dp_init(display, PCH_DP_C, PORT_C);
> >>
> >>               if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
> >> -                     g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
> >> +                     g4x_dp_init(display, PCH_DP_D, PORT_D);
> >>       } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> >>               bool has_edp, has_port;
> >>
> >> @@ -8275,14 +8275,14 @@ void intel_setup_outputs(struct
> >> drm_i915_private *dev_priv)
> >>               has_edp = intel_dp_is_port_edp(display, PORT_B);
> >>               has_port = intel_bios_is_port_present(display, PORT_B);
> >>               if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED ||
> >> has_port)
> >> -                     has_edp &= g4x_dp_init(dev_priv, VLV_DP_B,
> >> PORT_B);
> >> +                     has_edp &= g4x_dp_init(display, VLV_DP_B,
> >> PORT_B);
> >>               if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED
> >> || has_port) && !has_edp)
> >>                       g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
> >>
> >>               has_edp = intel_dp_is_port_edp(display, PORT_C);
> >>               has_port = intel_bios_is_port_present(display, PORT_C);
> >>               if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED ||
> >> has_port)
> >> -                     has_edp &= g4x_dp_init(dev_priv, VLV_DP_C,
> >> PORT_C);
> >> +                     has_edp &= g4x_dp_init(display, VLV_DP_C,
> >> PORT_C);
> >>               if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED
> >> || has_port) && !has_edp)
> >>                       g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
> >>
> >> @@ -8293,7 +8293,7 @@ void intel_setup_outputs(struct
> >> drm_i915_private
> >> *dev_priv)
> >>                        */
> >>                       has_port = intel_bios_is_port_present(display,
> >> PORT_D);
> >>                       if (intel_de_read(dev_priv, CHV_DP_D) &
> >> DP_DETECTED || has_port)
> >> -                             g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
> >> +                             g4x_dp_init(display, CHV_DP_D, PORT_D);
> >>                       if (intel_de_read(dev_priv, CHV_HDMID) &
> >> SDVO_DETECTED || has_port)
> >>                               g4x_hdmi_init(dev_priv, CHV_HDMID,
> >> PORT_D);
> >>               }
> >> @@ -8320,7 +8320,7 @@ void intel_setup_outputs(struct
> >> drm_i915_private
> >> *dev_priv)
> >>                       }
> >>
> >>                       if (!found && IS_G4X(dev_priv))
> >> -                             g4x_dp_init(dev_priv, DP_B, PORT_B);
> >> +                             g4x_dp_init(display, DP_B, PORT_B);
> >>               }
> >>
> >>               /* Before G4X SDVOC doesn't have its own detect
> >> register */ @@ -8338,11 +8338,11 @@ void intel_setup_outputs(struct
> >> drm_i915_private *dev_priv)
> >>                               g4x_hdmi_init(dev_priv, GEN4_HDMIC,
> >> PORT_C);
> >>                       }
> >>                       if (IS_G4X(dev_priv))
> >> -                             g4x_dp_init(dev_priv, DP_C, PORT_C);
> >> +                             g4x_dp_init(display, DP_C, PORT_C);
> >>               }
> >>
> >>               if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D)
> >> &
> >> DP_DETECTED))
> >> -                     g4x_dp_init(dev_priv, DP_D, PORT_D);
> >> +                     g4x_dp_init(display, DP_D, PORT_D);
> >>
> >>               if (SUPPORTS_TV(dev_priv))
> >>                       intel_tv_init(display); diff --git
> >> a/drivers/gpu/drm/i915/display/intel_pch_display.c
> >> b/drivers/gpu/drm/i915/display/intel_pch_display.c
> >> index 75ff5592312f..98a6b57ac956 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> >> @@ -45,7 +45,7 @@ static void assert_pch_dp_disabled(struct
> >> drm_i915_private *dev_priv,
> >>       enum pipe port_pipe;
> >>       bool state;
> >>
> >> -     state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
> >> +     state = g4x_dp_port_enabled(display, dp_reg, port, &port_pipe);
> >>
> >>       INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,
> >>                                "PCH DP %c enabled on transcoder %c,
> >> should be disabled\n", diff --git
> >> a/drivers/gpu/drm/i915/display/intel_pps.c
> >> b/drivers/gpu/drm/i915/display/intel_pps.c
> >> index ef6effaf82e0..617ce4993172 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> >> @@ -134,7 +134,7 @@ vlv_power_sequencer_kick(struct intel_dp
> *intel_dp)
> >>               release_cl_override = display->platform.cherryview &&
> >>                       !chv_phy_powergate_ch(display, phy, ch, true);
> >>
> >> -             if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
> >> +             if (vlv_force_pll_on(dev_priv, pipe,
> >> + vlv_get_dpll(display))) {
> >>                       drm_err(display->drm,
> >>                               "Failed to force on PLL for pipe %c!\n",
> >>                               pipe_name(pipe)); @@ -1225,11 +1225,10
> >> @@ static void vlv_steal_power_sequencer(struct intel_display
> >> *display,  static enum pipe vlv_active_pipe(struct intel_dp
> >> *intel_dp)  {
> >>       struct intel_display *display = to_intel_display(intel_dp);
> >> -     struct drm_i915_private *dev_priv = to_i915(display->drm);
> >>       struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> >>       enum pipe pipe;
> >>
> >> -     if (g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
> >> +     if (g4x_dp_port_enabled(display, intel_dp->output_reg,
> >>                               encoder->port, &pipe))
> >>               return pipe;
> >>
> >> @@ -1859,13 +1858,13 @@ void assert_pps_unlocked(struct intel_display
> >> *display, enum pipe pipe)
> >>                       intel_lvds_port_enabled(dev_priv, PCH_LVDS,
> >> &panel_pipe);
> >>                       break;
> >>               case PANEL_PORT_SELECT_DPA:
> >> -                     g4x_dp_port_enabled(dev_priv, DP_A, PORT_A,
> >> &panel_pipe);
> >> +                     g4x_dp_port_enabled(display, DP_A, PORT_A,
> >> &panel_pipe);
> >>                       break;
> >>               case PANEL_PORT_SELECT_DPC:
> >> -                     g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C,
> >> &panel_pipe);
> >> +                     g4x_dp_port_enabled(display, PCH_DP_C, PORT_C,
> >> &panel_pipe);
> >>                       break;
> >>               case PANEL_PORT_SELECT_DPD:
> >> -                     g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D,
> >> &panel_pipe);
> >> +                     g4x_dp_port_enabled(display, PCH_DP_D, PORT_D,
> >> &panel_pipe);
> >>                       break;
> >>               default:
> >>                       MISSING_CASE(port_sel);
> >> --
> >> 2.39.5
> >
> 
> --
> Jani Nikula, Intel

^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 02/14] drm/i915/hdmi: convert g4x_hdmi.[ch] to struct intel_display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
  2025-02-12 16:36 ` [PATCH 01/14] drm/i915/dp: convert g4x_dp.[ch] to struct intel display Jani Nikula
@ 2025-02-12 16:36 ` Jani Nikula
  2025-02-13  8:55   ` Kandpal, Suraj
  2025-02-12 16:36 ` [PATCH 03/14] drm/i915/ips: convert hsw_ips.c " Jani Nikula
                   ` (16 subsequent siblings)
  18 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2025-02-12 16:36 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula

Going forward, struct intel_display is the main display device data
pointer. Convert as much as possible of g4x_hdmi.[ch] to struct
intel_display.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_hdmi.c      | 139 +++++++++----------
 drivers/gpu/drm/i915/display/g4x_hdmi.h      |   6 +-
 drivers/gpu/drm/i915/display/intel_display.c |  16 +--
 3 files changed, 79 insertions(+), 82 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 9e1ca7767392..6670cf101b9a 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -27,8 +27,8 @@
 static void intel_hdmi_prepare(struct intel_encoder *encoder,
 			       const struct intel_crtc_state *crtc_state)
 {
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_display *display = to_intel_display(encoder);
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
@@ -54,13 +54,13 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder,
 
 	if (HAS_PCH_CPT(dev_priv))
 		hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
-	else if (IS_CHERRYVIEW(dev_priv))
+	else if (display->platform.cherryview)
 		hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 	else
 		hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 
-	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val);
-	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
+	intel_de_write(display, intel_hdmi->hdmi_reg, hdmi_val);
+	intel_de_posting_read(display, intel_hdmi->hdmi_reg);
 }
 
 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
@@ -132,6 +132,7 @@ static int g4x_hdmi_compute_config(struct intel_encoder *encoder,
 				   struct intel_crtc_state *crtc_state,
 				   struct drm_connector_state *conn_state)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
@@ -142,7 +143,7 @@ static int g4x_hdmi_compute_config(struct intel_encoder *encoder,
 			return -EINVAL;
 	}
 
-	if (IS_G4X(i915))
+	if (display->platform.g4x)
 		crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc);
 	else
 		crtc_state->has_hdmi_sink =
@@ -154,15 +155,15 @@ static int g4x_hdmi_compute_config(struct intel_encoder *encoder,
 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 				  struct intel_crtc_state *pipe_config)
 {
+	struct intel_display *display = to_intel_display(encoder);
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
 	u32 tmp, flags = 0;
 	int dotclock;
 
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
 
-	tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
+	tmp = intel_de_read(display, intel_hdmi->hdmi_reg);
 
 	if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 		flags |= DRM_MODE_FLAG_PHSYNC;
@@ -222,33 +223,32 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
 static void g4x_hdmi_enable_port(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *pipe_config)
 {
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 	u32 temp;
 
-	temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
+	temp = intel_de_read(display, intel_hdmi->hdmi_reg);
 
 	temp |= SDVO_ENABLE;
 
-	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
-	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
+	intel_de_write(display, intel_hdmi->hdmi_reg, temp);
+	intel_de_posting_read(display, intel_hdmi->hdmi_reg);
 }
 
 static void g4x_hdmi_audio_enable(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
 
 	if (!crtc_state->has_audio)
 		return;
 
-	drm_WARN_ON(&i915->drm, !crtc_state->has_hdmi_sink);
+	drm_WARN_ON(display->drm, !crtc_state->has_hdmi_sink);
 
 	/* Enable audio presence detect */
-	intel_de_rmw(i915, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE);
+	intel_de_rmw(display, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE);
 
 	intel_audio_codec_enable(encoder, crtc_state, conn_state);
 }
@@ -257,7 +257,7 @@ static void g4x_hdmi_audio_disable(struct intel_encoder *encoder,
 				   const struct intel_crtc_state *old_crtc_state,
 				   const struct drm_connector_state *old_conn_state)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
 
 	if (!old_crtc_state->has_audio)
@@ -266,7 +266,7 @@ static void g4x_hdmi_audio_disable(struct intel_encoder *encoder,
 	intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
 
 	/* Disable audio presence detect */
-	intel_de_rmw(i915, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0);
+	intel_de_rmw(display, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0);
 }
 
 static void g4x_enable_hdmi(struct intel_atomic_state *state,
@@ -282,12 +282,11 @@ static void ibx_enable_hdmi(struct intel_atomic_state *state,
 			    const struct intel_crtc_state *pipe_config,
 			    const struct drm_connector_state *conn_state)
 {
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 	u32 temp;
 
-	temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
+	temp = intel_de_read(display, intel_hdmi->hdmi_reg);
 
 	temp |= SDVO_ENABLE;
 
@@ -295,10 +294,10 @@ static void ibx_enable_hdmi(struct intel_atomic_state *state,
 	 * HW workaround, need to write this twice for issue
 	 * that may result in first write getting masked.
 	 */
-	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
-	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
-	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
-	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
+	intel_de_write(display, intel_hdmi->hdmi_reg, temp);
+	intel_de_posting_read(display, intel_hdmi->hdmi_reg);
+	intel_de_write(display, intel_hdmi->hdmi_reg, temp);
+	intel_de_posting_read(display, intel_hdmi->hdmi_reg);
 
 	/*
 	 * HW workaround, need to toggle enable bit off and on
@@ -309,18 +308,18 @@ static void ibx_enable_hdmi(struct intel_atomic_state *state,
 	 */
 	if (pipe_config->pipe_bpp > 24 &&
 	    pipe_config->pixel_multiplier > 1) {
-		intel_de_write(dev_priv, intel_hdmi->hdmi_reg,
+		intel_de_write(display, intel_hdmi->hdmi_reg,
 			       temp & ~SDVO_ENABLE);
-		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
+		intel_de_posting_read(display, intel_hdmi->hdmi_reg);
 
 		/*
 		 * HW workaround, need to write this twice for issue
 		 * that may result in first write getting masked.
 		 */
-		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
-		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
-		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
-		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
+		intel_de_write(display, intel_hdmi->hdmi_reg, temp);
+		intel_de_posting_read(display, intel_hdmi->hdmi_reg);
+		intel_de_write(display, intel_hdmi->hdmi_reg, temp);
+		intel_de_posting_read(display, intel_hdmi->hdmi_reg);
 	}
 }
 
@@ -329,14 +328,13 @@ static void cpt_enable_hdmi(struct intel_atomic_state *state,
 			    const struct intel_crtc_state *pipe_config,
 			    const struct drm_connector_state *conn_state)
 {
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 	enum pipe pipe = crtc->pipe;
 	u32 temp;
 
-	temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
+	temp = intel_de_read(display, intel_hdmi->hdmi_reg);
 
 	temp |= SDVO_ENABLE;
 
@@ -351,24 +349,24 @@ static void cpt_enable_hdmi(struct intel_atomic_state *state,
 	 */
 
 	if (pipe_config->pipe_bpp > 24) {
-		intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe),
+		intel_de_rmw(display, TRANS_CHICKEN1(pipe),
 			     0, TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
 
 		temp &= ~SDVO_COLOR_FORMAT_MASK;
 		temp |= SDVO_COLOR_FORMAT_8bpc;
 	}
 
-	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
-	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
+	intel_de_write(display, intel_hdmi->hdmi_reg, temp);
+	intel_de_posting_read(display, intel_hdmi->hdmi_reg);
 
 	if (pipe_config->pipe_bpp > 24) {
 		temp &= ~SDVO_COLOR_FORMAT_MASK;
 		temp |= HDMI_COLOR_FORMAT_12bpc;
 
-		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
-		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
+		intel_de_write(display, intel_hdmi->hdmi_reg, temp);
+		intel_de_posting_read(display, intel_hdmi->hdmi_reg);
 
-		intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe),
+		intel_de_rmw(display, TRANS_CHICKEN1(pipe),
 			     TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE, 0);
 	}
 }
@@ -386,19 +384,18 @@ static void intel_disable_hdmi(struct intel_atomic_state *state,
 			       const struct drm_connector_state *old_conn_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 	struct intel_digital_port *dig_port =
 		hdmi_to_dig_port(intel_hdmi);
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	u32 temp;
 
-	temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
+	temp = intel_de_read(display, intel_hdmi->hdmi_reg);
 
 	temp &= ~SDVO_ENABLE;
-	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
-	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
+	intel_de_write(display, intel_hdmi->hdmi_reg, temp);
+	intel_de_posting_read(display, intel_hdmi->hdmi_reg);
 
 	/*
 	 * HW workaround for IBX, we need to move the port
@@ -419,14 +416,14 @@ static void intel_disable_hdmi(struct intel_atomic_state *state,
 		 * HW workaround, need to write this twice for issue
 		 * that may result in first write getting masked.
 		 */
-		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
-		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
-		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
-		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
+		intel_de_write(display, intel_hdmi->hdmi_reg, temp);
+		intel_de_posting_read(display, intel_hdmi->hdmi_reg);
+		intel_de_write(display, intel_hdmi->hdmi_reg, temp);
+		intel_de_posting_read(display, intel_hdmi->hdmi_reg);
 
 		temp &= ~SDVO_ENABLE;
-		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
-		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
+		intel_de_write(display, intel_hdmi->hdmi_reg, temp);
+		intel_de_posting_read(display, intel_hdmi->hdmi_reg);
 
 		intel_wait_for_vblank_if_active(display, PIPE_A);
 		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
@@ -544,8 +541,8 @@ static void chv_hdmi_post_disable(struct intel_atomic_state *state,
 				  const struct intel_crtc_state *old_crtc_state,
 				  const struct drm_connector_state *old_conn_state)
 {
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_display *display = to_intel_display(encoder);
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 
 	vlv_dpio_get(dev_priv);
 
@@ -614,7 +611,7 @@ intel_hdmi_hotplug(struct intel_encoder *encoder,
 int g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
 				    struct drm_atomic_state *state)
 {
-	struct drm_i915_private *i915 = to_i915(state->dev);
+	struct intel_display *display = to_intel_display(connector->dev);
 	struct drm_connector_list_iter conn_iter;
 	struct drm_connector *conn;
 	int ret;
@@ -623,7 +620,7 @@ int g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
 	if (ret)
 		return ret;
 
-	if (!IS_G4X(i915))
+	if (!display->platform.g4x)
 		return 0;
 
 	if (!intel_connector_needs_modeset(to_intel_atomic_state(state), connector))
@@ -637,7 +634,7 @@ int g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
 	 *
 	 * See also g4x_compute_has_hdmi_sink().
 	 */
-	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+	drm_connector_list_iter_begin(display->drm, &conn_iter);
 	drm_for_each_connector_iter(conn, &conn_iter) {
 		struct drm_connector_state *conn_state;
 		struct drm_crtc_state *crtc_state;
@@ -646,7 +643,7 @@ int g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
 		if (!connector_is_hdmi(conn))
 			continue;
 
-		drm_dbg_kms(&i915->drm, "Adding [CONNECTOR:%d:%s]\n",
+		drm_dbg_kms(display->drm, "Adding [CONNECTOR:%d:%s]\n",
 			    conn->base.id, conn->name);
 
 		conn_state = drm_atomic_get_connector_state(state, conn);
@@ -671,24 +668,24 @@ int g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
 	return ret;
 }
 
-static bool is_hdmi_port_valid(struct drm_i915_private *i915, enum port port)
+static bool is_hdmi_port_valid(struct intel_display *display, enum port port)
 {
-	if (IS_G4X(i915) || IS_VALLEYVIEW(i915))
+	if (display->platform.g4x || display->platform.valleyview)
 		return port == PORT_B || port == PORT_C;
 	else
 		return port == PORT_B || port == PORT_C || port == PORT_D;
 }
 
-static bool assert_hdmi_port_valid(struct drm_i915_private *i915, enum port port)
+static bool assert_hdmi_port_valid(struct intel_display *display, enum port port)
 {
-	return !drm_WARN(&i915->drm, !is_hdmi_port_valid(i915, port),
+	return !drm_WARN(display->drm, !is_hdmi_port_valid(display, port),
 			 "Platform does not support HDMI %c\n", port_name(port));
 }
 
-bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
+bool g4x_hdmi_init(struct intel_display *display,
 		   i915_reg_t hdmi_reg, enum port port)
 {
-	struct intel_display *display = &dev_priv->display;
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	const struct intel_bios_encoder_data *devdata;
 	struct intel_digital_port *dig_port;
 	struct intel_encoder *intel_encoder;
@@ -697,14 +694,14 @@ bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
 	if (!assert_port_valid(dev_priv, port))
 		return false;
 
-	if (!assert_hdmi_port_valid(dev_priv, port))
+	if (!assert_hdmi_port_valid(display, port))
 		return false;
 
 	devdata = intel_bios_encoder_data_lookup(display, port);
 
 	/* FIXME bail? */
 	if (!devdata)
-		drm_dbg_kms(&dev_priv->drm, "No VBT child device for HDMI-%c\n",
+		drm_dbg_kms(display->drm, "No VBT child device for HDMI-%c\n",
 			    port_name(port));
 
 	dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
@@ -723,7 +720,7 @@ bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
 
 	mutex_init(&dig_port->hdcp_mutex);
 
-	if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
+	if (drm_encoder_init(display->drm, &intel_encoder->base,
 			     &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
 			     "HDMI %c", port_name(port)))
 		goto err_encoder_init;
@@ -738,13 +735,13 @@ bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
 	}
 	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
 	intel_encoder->get_config = intel_hdmi_get_config;
-	if (IS_CHERRYVIEW(dev_priv)) {
+	if (display->platform.cherryview) {
 		intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
 		intel_encoder->pre_enable = chv_hdmi_pre_enable;
 		intel_encoder->enable = vlv_enable_hdmi;
 		intel_encoder->post_disable = chv_hdmi_post_disable;
 		intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
-	} else if (IS_VALLEYVIEW(dev_priv)) {
+	} else if (display->platform.valleyview) {
 		intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
 		intel_encoder->pre_enable = vlv_hdmi_pre_enable;
 		intel_encoder->enable = vlv_enable_hdmi;
@@ -765,7 +762,7 @@ bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
 	intel_encoder->type = INTEL_OUTPUT_HDMI;
 	intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);
 	intel_encoder->port = port;
-	if (IS_CHERRYVIEW(dev_priv)) {
+	if (display->platform.cherryview) {
 		if (port == PORT_D)
 			intel_encoder->pipe_mask = BIT(PIPE_C);
 		else
@@ -780,7 +777,7 @@ bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
 	 * to work on real hardware. And since g4x can send infoframes to
 	 * only one port anyway, nothing is lost by allowing it.
 	 */
-	if (IS_G4X(dev_priv))
+	if (display->platform.g4x)
 		intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI);
 
 	dig_port->hdmi.hdmi_reg = hdmi_reg;
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.h b/drivers/gpu/drm/i915/display/g4x_hdmi.h
index a52e8986ec7a..039d2bdba06c 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.h
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.h
@@ -13,15 +13,15 @@
 enum port;
 struct drm_atomic_state;
 struct drm_connector;
-struct drm_i915_private;
+struct intel_display;
 
 #ifdef I915
-bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
+bool g4x_hdmi_init(struct intel_display *display,
 		   i915_reg_t hdmi_reg, enum port port);
 int g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
 				    struct drm_atomic_state *state);
 #else
-static inline bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
+static inline bool g4x_hdmi_init(struct intel_display *display,
 				 i915_reg_t hdmi_reg, int port)
 {
 	return false;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e5ceedf56335..b8c57a5d26a0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8235,16 +8235,16 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 			/* PCH SDVOB multiplex with HDMIB */
 			found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
 			if (!found)
-				g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
+				g4x_hdmi_init(display, PCH_HDMIB, PORT_B);
 			if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
 				g4x_dp_init(display, PCH_DP_B, PORT_B);
 		}
 
 		if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
-			g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
+			g4x_hdmi_init(display, PCH_HDMIC, PORT_C);
 
 		if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
-			g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
+			g4x_hdmi_init(display, PCH_HDMID, PORT_D);
 
 		if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
 			g4x_dp_init(display, PCH_DP_C, PORT_C);
@@ -8277,14 +8277,14 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
 			has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B);
 		if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
-			g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
+			g4x_hdmi_init(display, VLV_HDMIB, PORT_B);
 
 		has_edp = intel_dp_is_port_edp(display, PORT_C);
 		has_port = intel_bios_is_port_present(display, PORT_C);
 		if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
 			has_edp &= g4x_dp_init(display, VLV_DP_C, PORT_C);
 		if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
-			g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
+			g4x_hdmi_init(display, VLV_HDMIC, PORT_C);
 
 		if (IS_CHERRYVIEW(dev_priv)) {
 			/*
@@ -8295,7 +8295,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 			if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
 				g4x_dp_init(display, CHV_DP_D, PORT_D);
 			if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
-				g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
+				g4x_hdmi_init(display, CHV_HDMID, PORT_D);
 		}
 
 		vlv_dsi_init(dev_priv);
@@ -8316,7 +8316,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 			if (!found && IS_G4X(dev_priv)) {
 				drm_dbg_kms(&dev_priv->drm,
 					    "probing HDMI on SDVOB\n");
-				g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
+				g4x_hdmi_init(display, GEN4_HDMIB, PORT_B);
 			}
 
 			if (!found && IS_G4X(dev_priv))
@@ -8335,7 +8335,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 			if (IS_G4X(dev_priv)) {
 				drm_dbg_kms(&dev_priv->drm,
 					    "probing HDMI on SDVOC\n");
-				g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
+				g4x_hdmi_init(display, GEN4_HDMIC, PORT_C);
 			}
 			if (IS_G4X(dev_priv))
 				g4x_dp_init(display, DP_C, PORT_C);
-- 
2.39.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* RE: [PATCH 02/14] drm/i915/hdmi: convert g4x_hdmi.[ch] to struct intel_display
  2025-02-12 16:36 ` [PATCH 02/14] drm/i915/hdmi: convert g4x_hdmi.[ch] to struct intel_display Jani Nikula
@ 2025-02-13  8:55   ` Kandpal, Suraj
  2025-02-13  9:15     ` Jani Nikula
  0 siblings, 1 reply; 35+ messages in thread
From: Kandpal, Suraj @ 2025-02-13  8:55 UTC (permalink / raw)
  To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org
  Cc: Nikula, Jani



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Wednesday, February 12, 2025 10:07 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 02/14] drm/i915/hdmi: convert g4x_hdmi.[ch] to struct
> intel_display
> 
> Going forward, struct intel_display is the main display device data pointer.
> Convert as much as possible of g4x_hdmi.[ch] to struct intel_display.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/g4x_hdmi.c      | 139 +++++++++----------
>  drivers/gpu/drm/i915/display/g4x_hdmi.h      |   6 +-
>  drivers/gpu/drm/i915/display/intel_display.c |  16 +--
>  3 files changed, 79 insertions(+), 82 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> index 9e1ca7767392..6670cf101b9a 100644
> --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> @@ -27,8 +27,8 @@
>  static void intel_hdmi_prepare(struct intel_encoder *encoder,
>  			       const struct intel_crtc_state *crtc_state)  {
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_display *display = to_intel_display(encoder);
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);

Nit: If we are changing having a change here why not rename it to i915 too.
It's going to be useless in future since we want to remove drm_i915_private
Usage altogether but in the meantime why not follow the i915 naming convention.

Otherwise LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>  	const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode; @@ -54,13 +54,13 @@ static void
> intel_hdmi_prepare(struct intel_encoder *encoder,
> 
>  	if (HAS_PCH_CPT(dev_priv))
>  		hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
> -	else if (IS_CHERRYVIEW(dev_priv))
> +	else if (display->platform.cherryview)
>  		hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
>  	else
>  		hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
> 
> -	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val);
> -	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
> +	intel_de_write(display, intel_hdmi->hdmi_reg, hdmi_val);
> +	intel_de_posting_read(display, intel_hdmi->hdmi_reg);
>  }
> 
>  static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, @@ -
> 132,6 +132,7 @@ static int g4x_hdmi_compute_config(struct intel_encoder
> *encoder,
>  				   struct intel_crtc_state *crtc_state,
>  				   struct drm_connector_state *conn_state)  {
> +	struct intel_display *display = to_intel_display(encoder);
>  	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state-
> >uapi.state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev); @@ -
> 142,7 +143,7 @@ static int g4x_hdmi_compute_config(struct intel_encoder
> *encoder,
>  			return -EINVAL;
>  	}
> 
> -	if (IS_G4X(i915))
> +	if (display->platform.g4x)
>  		crtc_state->has_hdmi_sink =
> g4x_compute_has_hdmi_sink(state, crtc);
>  	else
>  		crtc_state->has_hdmi_sink =
> @@ -154,15 +155,15 @@ static int g4x_hdmi_compute_config(struct
> intel_encoder *encoder,  static void intel_hdmi_get_config(struct
> intel_encoder *encoder,
>  				  struct intel_crtc_state *pipe_config)  {
> +	struct intel_display *display = to_intel_display(encoder);
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
>  	u32 tmp, flags = 0;
>  	int dotclock;
> 
>  	pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
> 
> -	tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
> +	tmp = intel_de_read(display, intel_hdmi->hdmi_reg);
> 
>  	if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
>  		flags |= DRM_MODE_FLAG_PHSYNC;
> @@ -222,33 +223,32 @@ static void intel_hdmi_get_config(struct
> intel_encoder *encoder,  static void g4x_hdmi_enable_port(struct
> intel_encoder *encoder,
>  				 const struct intel_crtc_state *pipe_config)  {
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_display *display = to_intel_display(encoder);
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>  	u32 temp;
> 
> -	temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
> +	temp = intel_de_read(display, intel_hdmi->hdmi_reg);
> 
>  	temp |= SDVO_ENABLE;
> 
> -	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
> -	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
> +	intel_de_write(display, intel_hdmi->hdmi_reg, temp);
> +	intel_de_posting_read(display, intel_hdmi->hdmi_reg);
>  }
> 
>  static void g4x_hdmi_audio_enable(struct intel_encoder *encoder,
>  				  const struct intel_crtc_state *crtc_state,
>  				  const struct drm_connector_state
> *conn_state)  {
> -	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +	struct intel_display *display = to_intel_display(encoder);
>  	struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
> 
>  	if (!crtc_state->has_audio)
>  		return;
> 
> -	drm_WARN_ON(&i915->drm, !crtc_state->has_hdmi_sink);
> +	drm_WARN_ON(display->drm, !crtc_state->has_hdmi_sink);
> 
>  	/* Enable audio presence detect */
> -	intel_de_rmw(i915, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE);
> +	intel_de_rmw(display, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE);
> 
>  	intel_audio_codec_enable(encoder, crtc_state, conn_state);  } @@ -
> 257,7 +257,7 @@ static void g4x_hdmi_audio_disable(struct intel_encoder
> *encoder,
>  				   const struct intel_crtc_state *old_crtc_state,
>  				   const struct drm_connector_state
> *old_conn_state)  {
> -	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +	struct intel_display *display = to_intel_display(encoder);
>  	struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
> 
>  	if (!old_crtc_state->has_audio)
> @@ -266,7 +266,7 @@ static void g4x_hdmi_audio_disable(struct
> intel_encoder *encoder,
>  	intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
> 
>  	/* Disable audio presence detect */
> -	intel_de_rmw(i915, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0);
> +	intel_de_rmw(display, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0);
>  }
> 
>  static void g4x_enable_hdmi(struct intel_atomic_state *state, @@ -282,12
> +282,11 @@ static void ibx_enable_hdmi(struct intel_atomic_state *state,
>  			    const struct intel_crtc_state *pipe_config,
>  			    const struct drm_connector_state *conn_state)  {
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_display *display = to_intel_display(encoder);
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>  	u32 temp;
> 
> -	temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
> +	temp = intel_de_read(display, intel_hdmi->hdmi_reg);
> 
>  	temp |= SDVO_ENABLE;
> 
> @@ -295,10 +294,10 @@ static void ibx_enable_hdmi(struct
> intel_atomic_state *state,
>  	 * HW workaround, need to write this twice for issue
>  	 * that may result in first write getting masked.
>  	 */
> -	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
> -	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
> -	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
> -	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
> +	intel_de_write(display, intel_hdmi->hdmi_reg, temp);
> +	intel_de_posting_read(display, intel_hdmi->hdmi_reg);
> +	intel_de_write(display, intel_hdmi->hdmi_reg, temp);
> +	intel_de_posting_read(display, intel_hdmi->hdmi_reg);
> 
>  	/*
>  	 * HW workaround, need to toggle enable bit off and on @@ -
> 309,18 +308,18 @@ static void ibx_enable_hdmi(struct intel_atomic_state
> *state,
>  	 */
>  	if (pipe_config->pipe_bpp > 24 &&
>  	    pipe_config->pixel_multiplier > 1) {
> -		intel_de_write(dev_priv, intel_hdmi->hdmi_reg,
> +		intel_de_write(display, intel_hdmi->hdmi_reg,
>  			       temp & ~SDVO_ENABLE);
> -		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
> +		intel_de_posting_read(display, intel_hdmi->hdmi_reg);
> 
>  		/*
>  		 * HW workaround, need to write this twice for issue
>  		 * that may result in first write getting masked.
>  		 */
> -		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
> -		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
> -		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
> -		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
> +		intel_de_write(display, intel_hdmi->hdmi_reg, temp);
> +		intel_de_posting_read(display, intel_hdmi->hdmi_reg);
> +		intel_de_write(display, intel_hdmi->hdmi_reg, temp);
> +		intel_de_posting_read(display, intel_hdmi->hdmi_reg);
>  	}
>  }
> 
> @@ -329,14 +328,13 @@ static void cpt_enable_hdmi(struct
> intel_atomic_state *state,
>  			    const struct intel_crtc_state *pipe_config,
>  			    const struct drm_connector_state *conn_state)  {
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_display *display = to_intel_display(encoder);
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>  	enum pipe pipe = crtc->pipe;
>  	u32 temp;
> 
> -	temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
> +	temp = intel_de_read(display, intel_hdmi->hdmi_reg);
> 
>  	temp |= SDVO_ENABLE;
> 
> @@ -351,24 +349,24 @@ static void cpt_enable_hdmi(struct
> intel_atomic_state *state,
>  	 */
> 
>  	if (pipe_config->pipe_bpp > 24) {
> -		intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe),
> +		intel_de_rmw(display, TRANS_CHICKEN1(pipe),
>  			     0, TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
> 
>  		temp &= ~SDVO_COLOR_FORMAT_MASK;
>  		temp |= SDVO_COLOR_FORMAT_8bpc;
>  	}
> 
> -	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
> -	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
> +	intel_de_write(display, intel_hdmi->hdmi_reg, temp);
> +	intel_de_posting_read(display, intel_hdmi->hdmi_reg);
> 
>  	if (pipe_config->pipe_bpp > 24) {
>  		temp &= ~SDVO_COLOR_FORMAT_MASK;
>  		temp |= HDMI_COLOR_FORMAT_12bpc;
> 
> -		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
> -		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
> +		intel_de_write(display, intel_hdmi->hdmi_reg, temp);
> +		intel_de_posting_read(display, intel_hdmi->hdmi_reg);
> 
> -		intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe),
> +		intel_de_rmw(display, TRANS_CHICKEN1(pipe),
>  			     TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE, 0);
>  	}
>  }
> @@ -386,19 +384,18 @@ static void intel_disable_hdmi(struct
> intel_atomic_state *state,
>  			       const struct drm_connector_state
> *old_conn_state)  {
>  	struct intel_display *display = to_intel_display(encoder);
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>  	struct intel_digital_port *dig_port =
>  		hdmi_to_dig_port(intel_hdmi);
>  	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	u32 temp;
> 
> -	temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
> +	temp = intel_de_read(display, intel_hdmi->hdmi_reg);
> 
>  	temp &= ~SDVO_ENABLE;
> -	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
> -	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
> +	intel_de_write(display, intel_hdmi->hdmi_reg, temp);
> +	intel_de_posting_read(display, intel_hdmi->hdmi_reg);
> 
>  	/*
>  	 * HW workaround for IBX, we need to move the port @@ -419,14
> +416,14 @@ static void intel_disable_hdmi(struct intel_atomic_state *state,
>  		 * HW workaround, need to write this twice for issue
>  		 * that may result in first write getting masked.
>  		 */
> -		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
> -		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
> -		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
> -		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
> +		intel_de_write(display, intel_hdmi->hdmi_reg, temp);
> +		intel_de_posting_read(display, intel_hdmi->hdmi_reg);
> +		intel_de_write(display, intel_hdmi->hdmi_reg, temp);
> +		intel_de_posting_read(display, intel_hdmi->hdmi_reg);
> 
>  		temp &= ~SDVO_ENABLE;
> -		intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
> -		intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
> +		intel_de_write(display, intel_hdmi->hdmi_reg, temp);
> +		intel_de_posting_read(display, intel_hdmi->hdmi_reg);
> 
>  		intel_wait_for_vblank_if_active(display, PIPE_A);
>  		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A,
> true); @@ -544,8 +541,8 @@ static void chv_hdmi_post_disable(struct
> intel_atomic_state *state,
>  				  const struct intel_crtc_state *old_crtc_state,
>  				  const struct drm_connector_state
> *old_conn_state)  {
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_display *display = to_intel_display(encoder);
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
> 
>  	vlv_dpio_get(dev_priv);
> 
> @@ -614,7 +611,7 @@ intel_hdmi_hotplug(struct intel_encoder *encoder,
> int g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
>  				    struct drm_atomic_state *state)  {
> -	struct drm_i915_private *i915 = to_i915(state->dev);
> +	struct intel_display *display = to_intel_display(connector->dev);
>  	struct drm_connector_list_iter conn_iter;
>  	struct drm_connector *conn;
>  	int ret;
> @@ -623,7 +620,7 @@ int g4x_hdmi_connector_atomic_check(struct
> drm_connector *connector,
>  	if (ret)
>  		return ret;
> 
> -	if (!IS_G4X(i915))
> +	if (!display->platform.g4x)
>  		return 0;
> 
>  	if (!intel_connector_needs_modeset(to_intel_atomic_state(state),
> connector)) @@ -637,7 +634,7 @@ int
> g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
>  	 *
>  	 * See also g4x_compute_has_hdmi_sink().
>  	 */
> -	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> +	drm_connector_list_iter_begin(display->drm, &conn_iter);
>  	drm_for_each_connector_iter(conn, &conn_iter) {
>  		struct drm_connector_state *conn_state;
>  		struct drm_crtc_state *crtc_state;
> @@ -646,7 +643,7 @@ int g4x_hdmi_connector_atomic_check(struct
> drm_connector *connector,
>  		if (!connector_is_hdmi(conn))
>  			continue;
> 
> -		drm_dbg_kms(&i915->drm, "Adding
> [CONNECTOR:%d:%s]\n",
> +		drm_dbg_kms(display->drm, "Adding
> [CONNECTOR:%d:%s]\n",
>  			    conn->base.id, conn->name);
> 
>  		conn_state = drm_atomic_get_connector_state(state, conn);
> @@ -671,24 +668,24 @@ int g4x_hdmi_connector_atomic_check(struct
> drm_connector *connector,
>  	return ret;
>  }
> 
> -static bool is_hdmi_port_valid(struct drm_i915_private *i915, enum port
> port)
> +static bool is_hdmi_port_valid(struct intel_display *display, enum port
> +port)
>  {
> -	if (IS_G4X(i915) || IS_VALLEYVIEW(i915))
> +	if (display->platform.g4x || display->platform.valleyview)
>  		return port == PORT_B || port == PORT_C;
>  	else
>  		return port == PORT_B || port == PORT_C || port ==
> PORT_D;  }
> 
> -static bool assert_hdmi_port_valid(struct drm_i915_private *i915, enum
> port port)
> +static bool assert_hdmi_port_valid(struct intel_display *display, enum
> +port port)
>  {
> -	return !drm_WARN(&i915->drm, !is_hdmi_port_valid(i915, port),
> +	return !drm_WARN(display->drm, !is_hdmi_port_valid(display,
> port),
>  			 "Platform does not support HDMI %c\n",
> port_name(port));  }
> 
> -bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
> +bool g4x_hdmi_init(struct intel_display *display,
>  		   i915_reg_t hdmi_reg, enum port port)  {
> -	struct intel_display *display = &dev_priv->display;
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	const struct intel_bios_encoder_data *devdata;
>  	struct intel_digital_port *dig_port;
>  	struct intel_encoder *intel_encoder;
> @@ -697,14 +694,14 @@ bool g4x_hdmi_init(struct drm_i915_private
> *dev_priv,
>  	if (!assert_port_valid(dev_priv, port))
>  		return false;
> 
> -	if (!assert_hdmi_port_valid(dev_priv, port))
> +	if (!assert_hdmi_port_valid(display, port))
>  		return false;
> 
>  	devdata = intel_bios_encoder_data_lookup(display, port);
> 
>  	/* FIXME bail? */
>  	if (!devdata)
> -		drm_dbg_kms(&dev_priv->drm, "No VBT child device for
> HDMI-%c\n",
> +		drm_dbg_kms(display->drm, "No VBT child device for HDMI-
> %c\n",
>  			    port_name(port));
> 
>  	dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); @@ -723,7
> +720,7 @@ bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
> 
>  	mutex_init(&dig_port->hdcp_mutex);
> 
> -	if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
> +	if (drm_encoder_init(display->drm, &intel_encoder->base,
>  			     &intel_hdmi_enc_funcs,
> DRM_MODE_ENCODER_TMDS,
>  			     "HDMI %c", port_name(port)))
>  		goto err_encoder_init;
> @@ -738,13 +735,13 @@ bool g4x_hdmi_init(struct drm_i915_private
> *dev_priv,
>  	}
>  	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
>  	intel_encoder->get_config = intel_hdmi_get_config;
> -	if (IS_CHERRYVIEW(dev_priv)) {
> +	if (display->platform.cherryview) {
>  		intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
>  		intel_encoder->pre_enable = chv_hdmi_pre_enable;
>  		intel_encoder->enable = vlv_enable_hdmi;
>  		intel_encoder->post_disable = chv_hdmi_post_disable;
>  		intel_encoder->post_pll_disable =
> chv_hdmi_post_pll_disable;
> -	} else if (IS_VALLEYVIEW(dev_priv)) {
> +	} else if (display->platform.valleyview) {
>  		intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
>  		intel_encoder->pre_enable = vlv_hdmi_pre_enable;
>  		intel_encoder->enable = vlv_enable_hdmi; @@ -765,7
> +762,7 @@ bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
>  	intel_encoder->type = INTEL_OUTPUT_HDMI;
>  	intel_encoder->power_domain =
> intel_display_power_ddi_lanes_domain(display, port);
>  	intel_encoder->port = port;
> -	if (IS_CHERRYVIEW(dev_priv)) {
> +	if (display->platform.cherryview) {
>  		if (port == PORT_D)
>  			intel_encoder->pipe_mask = BIT(PIPE_C);
>  		else
> @@ -780,7 +777,7 @@ bool g4x_hdmi_init(struct drm_i915_private
> *dev_priv,
>  	 * to work on real hardware. And since g4x can send infoframes to
>  	 * only one port anyway, nothing is lost by allowing it.
>  	 */
> -	if (IS_G4X(dev_priv))
> +	if (display->platform.g4x)
>  		intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI);
> 
>  	dig_port->hdmi.hdmi_reg = hdmi_reg;
> diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.h
> b/drivers/gpu/drm/i915/display/g4x_hdmi.h
> index a52e8986ec7a..039d2bdba06c 100644
> --- a/drivers/gpu/drm/i915/display/g4x_hdmi.h
> +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.h
> @@ -13,15 +13,15 @@
>  enum port;
>  struct drm_atomic_state;
>  struct drm_connector;
> -struct drm_i915_private;
> +struct intel_display;
> 
>  #ifdef I915
> -bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
> +bool g4x_hdmi_init(struct intel_display *display,
>  		   i915_reg_t hdmi_reg, enum port port);  int
> g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
>  				    struct drm_atomic_state *state);  #else -
> static inline bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
> +static inline bool g4x_hdmi_init(struct intel_display *display,
>  				 i915_reg_t hdmi_reg, int port)
>  {
>  	return false;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e5ceedf56335..b8c57a5d26a0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8235,16 +8235,16 @@ void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
>  			/* PCH SDVOB multiplex with HDMIB */
>  			found = intel_sdvo_init(dev_priv, PCH_SDVOB,
> PORT_B);
>  			if (!found)
> -				g4x_hdmi_init(dev_priv, PCH_HDMIB,
> PORT_B);
> +				g4x_hdmi_init(display, PCH_HDMIB,
> PORT_B);
>  			if (!found && (intel_de_read(dev_priv, PCH_DP_B) &
> DP_DETECTED))
>  				g4x_dp_init(display, PCH_DP_B, PORT_B);
>  		}
> 
>  		if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
> -			g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
> +			g4x_hdmi_init(display, PCH_HDMIC, PORT_C);
> 
>  		if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) &
> SDVO_DETECTED)
> -			g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
> +			g4x_hdmi_init(display, PCH_HDMID, PORT_D);
> 
>  		if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
>  			g4x_dp_init(display, PCH_DP_C, PORT_C); @@ -
> 8277,14 +8277,14 @@ void intel_setup_outputs(struct drm_i915_private
> *dev_priv)
>  		if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED ||
> has_port)
>  			has_edp &= g4x_dp_init(display, VLV_DP_B,
> PORT_B);
>  		if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED
> || has_port) && !has_edp)
> -			g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
> +			g4x_hdmi_init(display, VLV_HDMIB, PORT_B);
> 
>  		has_edp = intel_dp_is_port_edp(display, PORT_C);
>  		has_port = intel_bios_is_port_present(display, PORT_C);
>  		if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED ||
> has_port)
>  			has_edp &= g4x_dp_init(display, VLV_DP_C,
> PORT_C);
>  		if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED
> || has_port) && !has_edp)
> -			g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
> +			g4x_hdmi_init(display, VLV_HDMIC, PORT_C);
> 
>  		if (IS_CHERRYVIEW(dev_priv)) {
>  			/*
> @@ -8295,7 +8295,7 @@ void intel_setup_outputs(struct drm_i915_private
> *dev_priv)
>  			if (intel_de_read(dev_priv, CHV_DP_D) &
> DP_DETECTED || has_port)
>  				g4x_dp_init(display, CHV_DP_D, PORT_D);
>  			if (intel_de_read(dev_priv, CHV_HDMID) &
> SDVO_DETECTED || has_port)
> -				g4x_hdmi_init(dev_priv, CHV_HDMID,
> PORT_D);
> +				g4x_hdmi_init(display, CHV_HDMID,
> PORT_D);
>  		}
> 
>  		vlv_dsi_init(dev_priv);
> @@ -8316,7 +8316,7 @@ void intel_setup_outputs(struct drm_i915_private
> *dev_priv)
>  			if (!found && IS_G4X(dev_priv)) {
>  				drm_dbg_kms(&dev_priv->drm,
>  					    "probing HDMI on SDVOB\n");
> -				g4x_hdmi_init(dev_priv, GEN4_HDMIB,
> PORT_B);
> +				g4x_hdmi_init(display, GEN4_HDMIB,
> PORT_B);
>  			}
> 
>  			if (!found && IS_G4X(dev_priv))
> @@ -8335,7 +8335,7 @@ void intel_setup_outputs(struct drm_i915_private
> *dev_priv)
>  			if (IS_G4X(dev_priv)) {
>  				drm_dbg_kms(&dev_priv->drm,
>  					    "probing HDMI on SDVOC\n");
> -				g4x_hdmi_init(dev_priv, GEN4_HDMIC,
> PORT_C);
> +				g4x_hdmi_init(display, GEN4_HDMIC,
> PORT_C);
>  			}
>  			if (IS_G4X(dev_priv))
>  				g4x_dp_init(display, DP_C, PORT_C);
> --
> 2.39.5


^ permalink raw reply	[flat|nested] 35+ messages in thread

* RE: [PATCH 02/14] drm/i915/hdmi: convert g4x_hdmi.[ch] to struct intel_display
  2025-02-13  8:55   ` Kandpal, Suraj
@ 2025-02-13  9:15     ` Jani Nikula
  0 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2025-02-13  9:15 UTC (permalink / raw)
  To: Kandpal, Suraj, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org

On Thu, 13 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
>> Nikula
>> Sent: Wednesday, February 12, 2025 10:07 PM
>> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>
>> Subject: [PATCH 02/14] drm/i915/hdmi: convert g4x_hdmi.[ch] to struct
>> intel_display
>>
>> Going forward, struct intel_display is the main display device data pointer.
>> Convert as much as possible of g4x_hdmi.[ch] to struct intel_display.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/g4x_hdmi.c      | 139 +++++++++----------
>>  drivers/gpu/drm/i915/display/g4x_hdmi.h      |   6 +-
>>  drivers/gpu/drm/i915/display/intel_display.c |  16 +--
>>  3 files changed, 79 insertions(+), 82 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c
>> b/drivers/gpu/drm/i915/display/g4x_hdmi.c
>> index 9e1ca7767392..6670cf101b9a 100644
>> --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
>> +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
>> @@ -27,8 +27,8 @@
>>  static void intel_hdmi_prepare(struct intel_encoder *encoder,
>>                              const struct intel_crtc_state *crtc_state)  {
>> -     struct drm_device *dev = encoder->base.dev;
>> -     struct drm_i915_private *dev_priv = to_i915(dev);
>> +     struct intel_display *display = to_intel_display(encoder);
>> +     struct drm_i915_private *dev_priv = to_i915(display->drm);
>
> Nit: If we are changing having a change here why not rename it to i915 too.
> It's going to be useless in future since we want to remove drm_i915_private
> Usage altogether but in the meantime why not follow the i915 naming convention.

I'm keeping it dev_priv to avoid unrelated changes below. And as you
say, all of them will need to be removed anyway.

>
> Otherwise LGTM,
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
>>       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>       struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>>       const struct drm_display_mode *adjusted_mode = &crtc_state-
>> >hw.adjusted_mode; @@ -54,13 +54,13 @@ static void
>> intel_hdmi_prepare(struct intel_encoder *encoder,
>>
>>       if (HAS_PCH_CPT(dev_priv))
>>               hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
>> -     else if (IS_CHERRYVIEW(dev_priv))
>> +     else if (display->platform.cherryview)
>>               hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
>>       else
>>               hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
>>
>> -     intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val);
>> -     intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
>> +     intel_de_write(display, intel_hdmi->hdmi_reg, hdmi_val);
>> +     intel_de_posting_read(display, intel_hdmi->hdmi_reg);
>>  }
>>
>>  static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, @@ -
>> 132,6 +132,7 @@ static int g4x_hdmi_compute_config(struct intel_encoder
>> *encoder,
>>                                  struct intel_crtc_state *crtc_state,
>>                                  struct drm_connector_state *conn_state)  {
>> +     struct intel_display *display = to_intel_display(encoder);
>>       struct intel_atomic_state *state = to_intel_atomic_state(crtc_state-
>> >uapi.state);
>>       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>       struct drm_i915_private *i915 = to_i915(encoder->base.dev); @@ -
>> 142,7 +143,7 @@ static int g4x_hdmi_compute_config(struct intel_encoder
>> *encoder,
>>                       return -EINVAL;
>>       }
>>
>> -     if (IS_G4X(i915))
>> +     if (display->platform.g4x)
>>               crtc_state->has_hdmi_sink =
>> g4x_compute_has_hdmi_sink(state, crtc);
>>       else
>>               crtc_state->has_hdmi_sink =
>> @@ -154,15 +155,15 @@ static int g4x_hdmi_compute_config(struct
>> intel_encoder *encoder,  static void intel_hdmi_get_config(struct
>> intel_encoder *encoder,
>>                                 struct intel_crtc_state *pipe_config)  {
>> +     struct intel_display *display = to_intel_display(encoder);
>> +     struct drm_i915_private *dev_priv = to_i915(display->drm);
>>       struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>> -     struct drm_device *dev = encoder->base.dev;
>> -     struct drm_i915_private *dev_priv = to_i915(dev);
>>       u32 tmp, flags = 0;
>>       int dotclock;
>>
>>       pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
>>
>> -     tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
>> +     tmp = intel_de_read(display, intel_hdmi->hdmi_reg);
>>
>>       if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
>>               flags |= DRM_MODE_FLAG_PHSYNC;
>> @@ -222,33 +223,32 @@ static void intel_hdmi_get_config(struct
>> intel_encoder *encoder,  static void g4x_hdmi_enable_port(struct
>> intel_encoder *encoder,
>>                                const struct intel_crtc_state *pipe_config)  {
>> -     struct drm_device *dev = encoder->base.dev;
>> -     struct drm_i915_private *dev_priv = to_i915(dev);
>> +     struct intel_display *display = to_intel_display(encoder);
>>       struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>>       u32 temp;
>>
>> -     temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
>> +     temp = intel_de_read(display, intel_hdmi->hdmi_reg);
>>
>>       temp |= SDVO_ENABLE;
>>
>> -     intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
>> -     intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
>> +     intel_de_write(display, intel_hdmi->hdmi_reg, temp);
>> +     intel_de_posting_read(display, intel_hdmi->hdmi_reg);
>>  }
>>
>>  static void g4x_hdmi_audio_enable(struct intel_encoder *encoder,
>>                                 const struct intel_crtc_state *crtc_state,
>>                                 const struct drm_connector_state
>> *conn_state)  {
>> -     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> +     struct intel_display *display = to_intel_display(encoder);
>>       struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
>>
>>       if (!crtc_state->has_audio)
>>               return;
>>
>> -     drm_WARN_ON(&i915->drm, !crtc_state->has_hdmi_sink);
>> +     drm_WARN_ON(display->drm, !crtc_state->has_hdmi_sink);
>>
>>       /* Enable audio presence detect */
>> -     intel_de_rmw(i915, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE);
>> +     intel_de_rmw(display, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE);
>>
>>       intel_audio_codec_enable(encoder, crtc_state, conn_state);  } @@ -
>> 257,7 +257,7 @@ static void g4x_hdmi_audio_disable(struct intel_encoder
>> *encoder,
>>                                  const struct intel_crtc_state *old_crtc_state,
>>                                  const struct drm_connector_state
>> *old_conn_state)  {
>> -     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> +     struct intel_display *display = to_intel_display(encoder);
>>       struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
>>
>>       if (!old_crtc_state->has_audio)
>> @@ -266,7 +266,7 @@ static void g4x_hdmi_audio_disable(struct
>> intel_encoder *encoder,
>>       intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
>>
>>       /* Disable audio presence detect */
>> -     intel_de_rmw(i915, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0);
>> +     intel_de_rmw(display, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0);
>>  }
>>
>>  static void g4x_enable_hdmi(struct intel_atomic_state *state, @@ -282,12
>> +282,11 @@ static void ibx_enable_hdmi(struct intel_atomic_state *state,
>>                           const struct intel_crtc_state *pipe_config,
>>                           const struct drm_connector_state *conn_state)  {
>> -     struct drm_device *dev = encoder->base.dev;
>> -     struct drm_i915_private *dev_priv = to_i915(dev);
>> +     struct intel_display *display = to_intel_display(encoder);
>>       struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>>       u32 temp;
>>
>> -     temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
>> +     temp = intel_de_read(display, intel_hdmi->hdmi_reg);
>>
>>       temp |= SDVO_ENABLE;
>>
>> @@ -295,10 +294,10 @@ static void ibx_enable_hdmi(struct
>> intel_atomic_state *state,
>>        * HW workaround, need to write this twice for issue
>>        * that may result in first write getting masked.
>>        */
>> -     intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
>> -     intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
>> -     intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
>> -     intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
>> +     intel_de_write(display, intel_hdmi->hdmi_reg, temp);
>> +     intel_de_posting_read(display, intel_hdmi->hdmi_reg);
>> +     intel_de_write(display, intel_hdmi->hdmi_reg, temp);
>> +     intel_de_posting_read(display, intel_hdmi->hdmi_reg);
>>
>>       /*
>>        * HW workaround, need to toggle enable bit off and on @@ -
>> 309,18 +308,18 @@ static void ibx_enable_hdmi(struct intel_atomic_state
>> *state,
>>        */
>>       if (pipe_config->pipe_bpp > 24 &&
>>           pipe_config->pixel_multiplier > 1) {
>> -             intel_de_write(dev_priv, intel_hdmi->hdmi_reg,
>> +             intel_de_write(display, intel_hdmi->hdmi_reg,
>>                              temp & ~SDVO_ENABLE);
>> -             intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
>> +             intel_de_posting_read(display, intel_hdmi->hdmi_reg);
>>
>>               /*
>>                * HW workaround, need to write this twice for issue
>>                * that may result in first write getting masked.
>>                */
>> -             intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
>> -             intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
>> -             intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
>> -             intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
>> +             intel_de_write(display, intel_hdmi->hdmi_reg, temp);
>> +             intel_de_posting_read(display, intel_hdmi->hdmi_reg);
>> +             intel_de_write(display, intel_hdmi->hdmi_reg, temp);
>> +             intel_de_posting_read(display, intel_hdmi->hdmi_reg);
>>       }
>>  }
>>
>> @@ -329,14 +328,13 @@ static void cpt_enable_hdmi(struct
>> intel_atomic_state *state,
>>                           const struct intel_crtc_state *pipe_config,
>>                           const struct drm_connector_state *conn_state)  {
>> -     struct drm_device *dev = encoder->base.dev;
>> -     struct drm_i915_private *dev_priv = to_i915(dev);
>> +     struct intel_display *display = to_intel_display(encoder);
>>       struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>>       struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>>       enum pipe pipe = crtc->pipe;
>>       u32 temp;
>>
>> -     temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
>> +     temp = intel_de_read(display, intel_hdmi->hdmi_reg);
>>
>>       temp |= SDVO_ENABLE;
>>
>> @@ -351,24 +349,24 @@ static void cpt_enable_hdmi(struct
>> intel_atomic_state *state,
>>        */
>>
>>       if (pipe_config->pipe_bpp > 24) {
>> -             intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe),
>> +             intel_de_rmw(display, TRANS_CHICKEN1(pipe),
>>                            0, TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
>>
>>               temp &= ~SDVO_COLOR_FORMAT_MASK;
>>               temp |= SDVO_COLOR_FORMAT_8bpc;
>>       }
>>
>> -     intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
>> -     intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
>> +     intel_de_write(display, intel_hdmi->hdmi_reg, temp);
>> +     intel_de_posting_read(display, intel_hdmi->hdmi_reg);
>>
>>       if (pipe_config->pipe_bpp > 24) {
>>               temp &= ~SDVO_COLOR_FORMAT_MASK;
>>               temp |= HDMI_COLOR_FORMAT_12bpc;
>>
>> -             intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
>> -             intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
>> +             intel_de_write(display, intel_hdmi->hdmi_reg, temp);
>> +             intel_de_posting_read(display, intel_hdmi->hdmi_reg);
>>
>> -             intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe),
>> +             intel_de_rmw(display, TRANS_CHICKEN1(pipe),
>>                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE, 0);
>>       }
>>  }
>> @@ -386,19 +384,18 @@ static void intel_disable_hdmi(struct
>> intel_atomic_state *state,
>>                              const struct drm_connector_state
>> *old_conn_state)  {
>>       struct intel_display *display = to_intel_display(encoder);
>> -     struct drm_device *dev = encoder->base.dev;
>> -     struct drm_i915_private *dev_priv = to_i915(dev);
>> +     struct drm_i915_private *dev_priv = to_i915(display->drm);
>>       struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>>       struct intel_digital_port *dig_port =
>>               hdmi_to_dig_port(intel_hdmi);
>>       struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>>       u32 temp;
>>
>> -     temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
>> +     temp = intel_de_read(display, intel_hdmi->hdmi_reg);
>>
>>       temp &= ~SDVO_ENABLE;
>> -     intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
>> -     intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
>> +     intel_de_write(display, intel_hdmi->hdmi_reg, temp);
>> +     intel_de_posting_read(display, intel_hdmi->hdmi_reg);
>>
>>       /*
>>        * HW workaround for IBX, we need to move the port @@ -419,14
>> +416,14 @@ static void intel_disable_hdmi(struct intel_atomic_state *state,
>>                * HW workaround, need to write this twice for issue
>>                * that may result in first write getting masked.
>>                */
>> -             intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
>> -             intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
>> -             intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
>> -             intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
>> +             intel_de_write(display, intel_hdmi->hdmi_reg, temp);
>> +             intel_de_posting_read(display, intel_hdmi->hdmi_reg);
>> +             intel_de_write(display, intel_hdmi->hdmi_reg, temp);
>> +             intel_de_posting_read(display, intel_hdmi->hdmi_reg);
>>
>>               temp &= ~SDVO_ENABLE;
>> -             intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
>> -             intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
>> +             intel_de_write(display, intel_hdmi->hdmi_reg, temp);
>> +             intel_de_posting_read(display, intel_hdmi->hdmi_reg);
>>
>>               intel_wait_for_vblank_if_active(display, PIPE_A);
>>               intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A,
>> true); @@ -544,8 +541,8 @@ static void chv_hdmi_post_disable(struct
>> intel_atomic_state *state,
>>                                 const struct intel_crtc_state *old_crtc_state,
>>                                 const struct drm_connector_state
>> *old_conn_state)  {
>> -     struct drm_device *dev = encoder->base.dev;
>> -     struct drm_i915_private *dev_priv = to_i915(dev);
>> +     struct intel_display *display = to_intel_display(encoder);
>> +     struct drm_i915_private *dev_priv = to_i915(display->drm);
>>
>>       vlv_dpio_get(dev_priv);
>>
>> @@ -614,7 +611,7 @@ intel_hdmi_hotplug(struct intel_encoder *encoder,
>> int g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
>>                                   struct drm_atomic_state *state)  {
>> -     struct drm_i915_private *i915 = to_i915(state->dev);
>> +     struct intel_display *display = to_intel_display(connector->dev);
>>       struct drm_connector_list_iter conn_iter;
>>       struct drm_connector *conn;
>>       int ret;
>> @@ -623,7 +620,7 @@ int g4x_hdmi_connector_atomic_check(struct
>> drm_connector *connector,
>>       if (ret)
>>               return ret;
>>
>> -     if (!IS_G4X(i915))
>> +     if (!display->platform.g4x)
>>               return 0;
>>
>>       if (!intel_connector_needs_modeset(to_intel_atomic_state(state),
>> connector)) @@ -637,7 +634,7 @@ int
>> g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
>>        *
>>        * See also g4x_compute_has_hdmi_sink().
>>        */
>> -     drm_connector_list_iter_begin(&i915->drm, &conn_iter);
>> +     drm_connector_list_iter_begin(display->drm, &conn_iter);
>>       drm_for_each_connector_iter(conn, &conn_iter) {
>>               struct drm_connector_state *conn_state;
>>               struct drm_crtc_state *crtc_state;
>> @@ -646,7 +643,7 @@ int g4x_hdmi_connector_atomic_check(struct
>> drm_connector *connector,
>>               if (!connector_is_hdmi(conn))
>>                       continue;
>>
>> -             drm_dbg_kms(&i915->drm, "Adding
>> [CONNECTOR:%d:%s]\n",
>> +             drm_dbg_kms(display->drm, "Adding
>> [CONNECTOR:%d:%s]\n",
>>                           conn->base.id, conn->name);
>>
>>               conn_state = drm_atomic_get_connector_state(state, conn);
>> @@ -671,24 +668,24 @@ int g4x_hdmi_connector_atomic_check(struct
>> drm_connector *connector,
>>       return ret;
>>  }
>>
>> -static bool is_hdmi_port_valid(struct drm_i915_private *i915, enum port
>> port)
>> +static bool is_hdmi_port_valid(struct intel_display *display, enum port
>> +port)
>>  {
>> -     if (IS_G4X(i915) || IS_VALLEYVIEW(i915))
>> +     if (display->platform.g4x || display->platform.valleyview)
>>               return port == PORT_B || port == PORT_C;
>>       else
>>               return port == PORT_B || port == PORT_C || port ==
>> PORT_D;  }
>>
>> -static bool assert_hdmi_port_valid(struct drm_i915_private *i915, enum
>> port port)
>> +static bool assert_hdmi_port_valid(struct intel_display *display, enum
>> +port port)
>>  {
>> -     return !drm_WARN(&i915->drm, !is_hdmi_port_valid(i915, port),
>> +     return !drm_WARN(display->drm, !is_hdmi_port_valid(display,
>> port),
>>                        "Platform does not support HDMI %c\n",
>> port_name(port));  }
>>
>> -bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
>> +bool g4x_hdmi_init(struct intel_display *display,
>>                  i915_reg_t hdmi_reg, enum port port)  {
>> -     struct intel_display *display = &dev_priv->display;
>> +     struct drm_i915_private *dev_priv = to_i915(display->drm);
>>       const struct intel_bios_encoder_data *devdata;
>>       struct intel_digital_port *dig_port;
>>       struct intel_encoder *intel_encoder;
>> @@ -697,14 +694,14 @@ bool g4x_hdmi_init(struct drm_i915_private
>> *dev_priv,
>>       if (!assert_port_valid(dev_priv, port))
>>               return false;
>>
>> -     if (!assert_hdmi_port_valid(dev_priv, port))
>> +     if (!assert_hdmi_port_valid(display, port))
>>               return false;
>>
>>       devdata = intel_bios_encoder_data_lookup(display, port);
>>
>>       /* FIXME bail? */
>>       if (!devdata)
>> -             drm_dbg_kms(&dev_priv->drm, "No VBT child device for
>> HDMI-%c\n",
>> +             drm_dbg_kms(display->drm, "No VBT child device for HDMI-
>> %c\n",
>>                           port_name(port));
>>
>>       dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); @@ -723,7
>> +720,7 @@ bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
>>
>>       mutex_init(&dig_port->hdcp_mutex);
>>
>> -     if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
>> +     if (drm_encoder_init(display->drm, &intel_encoder->base,
>>                            &intel_hdmi_enc_funcs,
>> DRM_MODE_ENCODER_TMDS,
>>                            "HDMI %c", port_name(port)))
>>               goto err_encoder_init;
>> @@ -738,13 +735,13 @@ bool g4x_hdmi_init(struct drm_i915_private
>> *dev_priv,
>>       }
>>       intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
>>       intel_encoder->get_config = intel_hdmi_get_config;
>> -     if (IS_CHERRYVIEW(dev_priv)) {
>> +     if (display->platform.cherryview) {
>>               intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
>>               intel_encoder->pre_enable = chv_hdmi_pre_enable;
>>               intel_encoder->enable = vlv_enable_hdmi;
>>               intel_encoder->post_disable = chv_hdmi_post_disable;
>>               intel_encoder->post_pll_disable =
>> chv_hdmi_post_pll_disable;
>> -     } else if (IS_VALLEYVIEW(dev_priv)) {
>> +     } else if (display->platform.valleyview) {
>>               intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
>>               intel_encoder->pre_enable = vlv_hdmi_pre_enable;
>>               intel_encoder->enable = vlv_enable_hdmi; @@ -765,7
>> +762,7 @@ bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
>>       intel_encoder->type = INTEL_OUTPUT_HDMI;
>>       intel_encoder->power_domain =
>> intel_display_power_ddi_lanes_domain(display, port);
>>       intel_encoder->port = port;
>> -     if (IS_CHERRYVIEW(dev_priv)) {
>> +     if (display->platform.cherryview) {
>>               if (port == PORT_D)
>>                       intel_encoder->pipe_mask = BIT(PIPE_C);
>>               else
>> @@ -780,7 +777,7 @@ bool g4x_hdmi_init(struct drm_i915_private
>> *dev_priv,
>>        * to work on real hardware. And since g4x can send infoframes to
>>        * only one port anyway, nothing is lost by allowing it.
>>        */
>> -     if (IS_G4X(dev_priv))
>> +     if (display->platform.g4x)
>>               intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI);
>>
>>       dig_port->hdmi.hdmi_reg = hdmi_reg;
>> diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.h
>> b/drivers/gpu/drm/i915/display/g4x_hdmi.h
>> index a52e8986ec7a..039d2bdba06c 100644
>> --- a/drivers/gpu/drm/i915/display/g4x_hdmi.h
>> +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.h
>> @@ -13,15 +13,15 @@
>>  enum port;
>>  struct drm_atomic_state;
>>  struct drm_connector;
>> -struct drm_i915_private;
>> +struct intel_display;
>>
>>  #ifdef I915
>> -bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
>> +bool g4x_hdmi_init(struct intel_display *display,
>>                  i915_reg_t hdmi_reg, enum port port);  int
>> g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
>>                                   struct drm_atomic_state *state);  #else -
>> static inline bool g4x_hdmi_init(struct drm_i915_private *dev_priv,
>> +static inline bool g4x_hdmi_init(struct intel_display *display,
>>                                i915_reg_t hdmi_reg, int port)
>>  {
>>       return false;
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index e5ceedf56335..b8c57a5d26a0 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -8235,16 +8235,16 @@ void intel_setup_outputs(struct
>> drm_i915_private *dev_priv)
>>                       /* PCH SDVOB multiplex with HDMIB */
>>                       found = intel_sdvo_init(dev_priv, PCH_SDVOB,
>> PORT_B);
>>                       if (!found)
>> -                             g4x_hdmi_init(dev_priv, PCH_HDMIB,
>> PORT_B);
>> +                             g4x_hdmi_init(display, PCH_HDMIB,
>> PORT_B);
>>                       if (!found && (intel_de_read(dev_priv, PCH_DP_B) &
>> DP_DETECTED))
>>                               g4x_dp_init(display, PCH_DP_B, PORT_B);
>>               }
>>
>>               if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
>> -                     g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
>> +                     g4x_hdmi_init(display, PCH_HDMIC, PORT_C);
>>
>>               if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) &
>> SDVO_DETECTED)
>> -                     g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
>> +                     g4x_hdmi_init(display, PCH_HDMID, PORT_D);
>>
>>               if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
>>                       g4x_dp_init(display, PCH_DP_C, PORT_C); @@ -
>> 8277,14 +8277,14 @@ void intel_setup_outputs(struct drm_i915_private
>> *dev_priv)
>>               if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED ||
>> has_port)
>>                       has_edp &= g4x_dp_init(display, VLV_DP_B,
>> PORT_B);
>>               if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED
>> || has_port) && !has_edp)
>> -                     g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
>> +                     g4x_hdmi_init(display, VLV_HDMIB, PORT_B);
>>
>>               has_edp = intel_dp_is_port_edp(display, PORT_C);
>>               has_port = intel_bios_is_port_present(display, PORT_C);
>>               if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED ||
>> has_port)
>>                       has_edp &= g4x_dp_init(display, VLV_DP_C,
>> PORT_C);
>>               if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED
>> || has_port) && !has_edp)
>> -                     g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
>> +                     g4x_hdmi_init(display, VLV_HDMIC, PORT_C);
>>
>>               if (IS_CHERRYVIEW(dev_priv)) {
>>                       /*
>> @@ -8295,7 +8295,7 @@ void intel_setup_outputs(struct drm_i915_private
>> *dev_priv)
>>                       if (intel_de_read(dev_priv, CHV_DP_D) &
>> DP_DETECTED || has_port)
>>                               g4x_dp_init(display, CHV_DP_D, PORT_D);
>>                       if (intel_de_read(dev_priv, CHV_HDMID) &
>> SDVO_DETECTED || has_port)
>> -                             g4x_hdmi_init(dev_priv, CHV_HDMID,
>> PORT_D);
>> +                             g4x_hdmi_init(display, CHV_HDMID,
>> PORT_D);
>>               }
>>
>>               vlv_dsi_init(dev_priv);
>> @@ -8316,7 +8316,7 @@ void intel_setup_outputs(struct drm_i915_private
>> *dev_priv)
>>                       if (!found && IS_G4X(dev_priv)) {
>>                               drm_dbg_kms(&dev_priv->drm,
>>                                           "probing HDMI on SDVOB\n");
>> -                             g4x_hdmi_init(dev_priv, GEN4_HDMIB,
>> PORT_B);
>> +                             g4x_hdmi_init(display, GEN4_HDMIB,
>> PORT_B);
>>                       }
>>
>>                       if (!found && IS_G4X(dev_priv))
>> @@ -8335,7 +8335,7 @@ void intel_setup_outputs(struct drm_i915_private
>> *dev_priv)
>>                       if (IS_G4X(dev_priv)) {
>>                               drm_dbg_kms(&dev_priv->drm,
>>                                           "probing HDMI on SDVOC\n");
>> -                             g4x_hdmi_init(dev_priv, GEN4_HDMIC,
>> PORT_C);
>> +                             g4x_hdmi_init(display, GEN4_HDMIC,
>> PORT_C);
>>                       }
>>                       if (IS_G4X(dev_priv))
>>                               g4x_dp_init(display, DP_C, PORT_C);
>> --
>> 2.39.5
>

-- 
Jani Nikula, Intel

^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 03/14] drm/i915/ips: convert hsw_ips.c to struct intel_display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
  2025-02-12 16:36 ` [PATCH 01/14] drm/i915/dp: convert g4x_dp.[ch] to struct intel display Jani Nikula
  2025-02-12 16:36 ` [PATCH 02/14] drm/i915/hdmi: convert g4x_hdmi.[ch] to struct intel_display Jani Nikula
@ 2025-02-12 16:36 ` Jani Nikula
  2025-02-13  8:56   ` Kandpal, Suraj
  2025-02-12 16:36 ` [PATCH 04/14] drm/i915/display: convert assert_transcoder*() " Jani Nikula
                   ` (15 subsequent siblings)
  18 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2025-02-12 16:36 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula

Going forward, struct intel_display is the main display device data
pointer. Convert as much as possible of hsw_ips.c to struct
intel_display.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/hsw_ips.c | 26 ++++++++++++--------------
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index d02c328bf902..674a0e5f0858 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -36,7 +36,7 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
 	if (display->ips.false_color)
 		val |= IPS_FALSE_COLOR;
 
-	if (IS_BROADWELL(i915)) {
+	if (display->platform.broadwell) {
 		drm_WARN_ON(display->drm,
 			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,
 					    val | IPS_PCODE_CONTROL));
@@ -71,7 +71,7 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
 	if (!crtc_state->ips_enabled)
 		return need_vblank_wait;
 
-	if (IS_BROADWELL(i915)) {
+	if (display->platform.broadwell) {
 		drm_WARN_ON(display->drm,
 			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0));
 		/*
@@ -96,7 +96,7 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
 static bool hsw_ips_need_disable(struct intel_atomic_state *state,
 				 struct intel_crtc *crtc)
 {
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	struct intel_display *display = to_intel_display(state);
 	const struct intel_crtc_state *old_crtc_state =
 		intel_atomic_get_old_crtc_state(state, crtc);
 	const struct intel_crtc_state *new_crtc_state =
@@ -114,7 +114,7 @@ static bool hsw_ips_need_disable(struct intel_atomic_state *state,
 	 *
 	 * Disable IPS before we program the LUT.
 	 */
-	if (IS_HASWELL(i915) &&
+	if (display->platform.haswell &&
 	    intel_crtc_needs_color_update(new_crtc_state) &&
 	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
 		return true;
@@ -137,7 +137,7 @@ bool hsw_ips_pre_update(struct intel_atomic_state *state,
 static bool hsw_ips_need_enable(struct intel_atomic_state *state,
 				struct intel_crtc *crtc)
 {
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	struct intel_display *display = to_intel_display(state);
 	const struct intel_crtc_state *old_crtc_state =
 		intel_atomic_get_old_crtc_state(state, crtc);
 	const struct intel_crtc_state *new_crtc_state =
@@ -155,7 +155,7 @@ static bool hsw_ips_need_enable(struct intel_atomic_state *state,
 	 *
 	 * Re-enable IPS after the LUT has been programmed.
 	 */
-	if (IS_HASWELL(i915) &&
+	if (display->platform.haswell &&
 	    intel_crtc_needs_color_update(new_crtc_state) &&
 	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
 		return true;
@@ -194,7 +194,6 @@ static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 
 	/* IPS only exists on ULT machines and is tied to pipe A. */
 	if (!hsw_crtc_supports_ips(crtc))
@@ -213,7 +212,7 @@ static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state
 	 *
 	 * Should measure whether using a lower cdclk w/o IPS
 	 */
-	if (IS_BROADWELL(i915) &&
+	if (display->platform.broadwell &&
 	    crtc_state->pixel_rate > display->cdclk.max_cdclk_freq * 95 / 100)
 		return false;
 
@@ -222,9 +221,9 @@ static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state
 
 int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_display *display = to_intel_display(crtc_state);
 
-	if (!IS_BROADWELL(i915))
+	if (!display->platform.broadwell)
 		return 0;
 
 	if (!hsw_crtc_state_ips_capable(crtc_state))
@@ -237,7 +236,7 @@ int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)
 int hsw_ips_compute_config(struct intel_atomic_state *state,
 			   struct intel_crtc *crtc)
 {
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	struct intel_display *display = to_intel_display(state);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 
@@ -259,7 +258,7 @@ int hsw_ips_compute_config(struct intel_atomic_state *state,
 	if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
 		return 0;
 
-	if (IS_BROADWELL(i915)) {
+	if (display->platform.broadwell) {
 		const struct intel_cdclk_state *cdclk_state;
 
 		cdclk_state = intel_atomic_get_cdclk_state(state);
@@ -280,12 +279,11 @@ void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 
 	if (!hsw_crtc_supports_ips(crtc))
 		return;
 
-	if (IS_HASWELL(i915)) {
+	if (display->platform.haswell) {
 		crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;
 	} else {
 		/*
-- 
2.39.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* RE: [PATCH 03/14] drm/i915/ips: convert hsw_ips.c to struct intel_display
  2025-02-12 16:36 ` [PATCH 03/14] drm/i915/ips: convert hsw_ips.c " Jani Nikula
@ 2025-02-13  8:56   ` Kandpal, Suraj
  0 siblings, 0 replies; 35+ messages in thread
From: Kandpal, Suraj @ 2025-02-13  8:56 UTC (permalink / raw)
  To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org
  Cc: Nikula, Jani



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Wednesday, February 12, 2025 10:07 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 03/14] drm/i915/ips: convert hsw_ips.c to struct
> intel_display
> 
> Going forward, struct intel_display is the main display device data pointer.
> Convert as much as possible of hsw_ips.c to struct intel_display.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/hsw_ips.c | 26 ++++++++++++--------------
>  1 file changed, 12 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c
> b/drivers/gpu/drm/i915/display/hsw_ips.c
> index d02c328bf902..674a0e5f0858 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> @@ -36,7 +36,7 @@ static void hsw_ips_enable(const struct intel_crtc_state
> *crtc_state)
>  	if (display->ips.false_color)
>  		val |= IPS_FALSE_COLOR;
> 
> -	if (IS_BROADWELL(i915)) {
> +	if (display->platform.broadwell) {
>  		drm_WARN_ON(display->drm,
>  			    snb_pcode_write(&i915->uncore,
> DISPLAY_IPS_CONTROL,
>  					    val | IPS_PCODE_CONTROL));
> @@ -71,7 +71,7 @@ bool hsw_ips_disable(const struct intel_crtc_state
> *crtc_state)
>  	if (!crtc_state->ips_enabled)
>  		return need_vblank_wait;
> 
> -	if (IS_BROADWELL(i915)) {
> +	if (display->platform.broadwell) {
>  		drm_WARN_ON(display->drm,
>  			    snb_pcode_write(&i915->uncore,
> DISPLAY_IPS_CONTROL, 0));
>  		/*
> @@ -96,7 +96,7 @@ bool hsw_ips_disable(const struct intel_crtc_state
> *crtc_state)  static bool hsw_ips_need_disable(struct intel_atomic_state
> *state,
>  				 struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	struct intel_display *display = to_intel_display(state);
>  	const struct intel_crtc_state *old_crtc_state =
>  		intel_atomic_get_old_crtc_state(state, crtc);
>  	const struct intel_crtc_state *new_crtc_state = @@ -114,7 +114,7
> @@ static bool hsw_ips_need_disable(struct intel_atomic_state *state,
>  	 *
>  	 * Disable IPS before we program the LUT.
>  	 */
> -	if (IS_HASWELL(i915) &&
> +	if (display->platform.haswell &&
>  	    intel_crtc_needs_color_update(new_crtc_state) &&
>  	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
>  		return true;
> @@ -137,7 +137,7 @@ bool hsw_ips_pre_update(struct intel_atomic_state
> *state,  static bool hsw_ips_need_enable(struct intel_atomic_state *state,
>  				struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	struct intel_display *display = to_intel_display(state);
>  	const struct intel_crtc_state *old_crtc_state =
>  		intel_atomic_get_old_crtc_state(state, crtc);
>  	const struct intel_crtc_state *new_crtc_state = @@ -155,7 +155,7
> @@ static bool hsw_ips_need_enable(struct intel_atomic_state *state,
>  	 *
>  	 * Re-enable IPS after the LUT has been programmed.
>  	 */
> -	if (IS_HASWELL(i915) &&
> +	if (display->platform.haswell &&
>  	    intel_crtc_needs_color_update(new_crtc_state) &&
>  	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
>  		return true;
> @@ -194,7 +194,6 @@ static bool hsw_crtc_state_ips_capable(const struct
> intel_crtc_state *crtc_state  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> 
>  	/* IPS only exists on ULT machines and is tied to pipe A. */
>  	if (!hsw_crtc_supports_ips(crtc))
> @@ -213,7 +212,7 @@ static bool hsw_crtc_state_ips_capable(const struct
> intel_crtc_state *crtc_state
>  	 *
>  	 * Should measure whether using a lower cdclk w/o IPS
>  	 */
> -	if (IS_BROADWELL(i915) &&
> +	if (display->platform.broadwell &&
>  	    crtc_state->pixel_rate > display->cdclk.max_cdclk_freq * 95 / 100)
>  		return false;
> 
> @@ -222,9 +221,9 @@ static bool hsw_crtc_state_ips_capable(const struct
> intel_crtc_state *crtc_state
> 
>  int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)  {
> -	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +	struct intel_display *display = to_intel_display(crtc_state);
> 
> -	if (!IS_BROADWELL(i915))
> +	if (!display->platform.broadwell)
>  		return 0;
> 
>  	if (!hsw_crtc_state_ips_capable(crtc_state))
> @@ -237,7 +236,7 @@ int hsw_ips_min_cdclk(const struct intel_crtc_state
> *crtc_state)  int hsw_ips_compute_config(struct intel_atomic_state *state,
>  			   struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	struct intel_display *display = to_intel_display(state);
>  	struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> 
> @@ -259,7 +258,7 @@ int hsw_ips_compute_config(struct
> intel_atomic_state *state,
>  	if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
>  		return 0;
> 
> -	if (IS_BROADWELL(i915)) {
> +	if (display->platform.broadwell) {
>  		const struct intel_cdclk_state *cdclk_state;
> 
>  		cdclk_state = intel_atomic_get_cdclk_state(state);
> @@ -280,12 +279,11 @@ void hsw_ips_get_config(struct intel_crtc_state
> *crtc_state)  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> 
>  	if (!hsw_crtc_supports_ips(crtc))
>  		return;
> 
> -	if (IS_HASWELL(i915)) {
> +	if (display->platform.haswell) {
>  		crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) &
> IPS_ENABLE;
>  	} else {
>  		/*
> --
> 2.39.5


^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 04/14] drm/i915/display: convert assert_transcoder*() to struct intel_display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
                   ` (2 preceding siblings ...)
  2025-02-12 16:36 ` [PATCH 03/14] drm/i915/ips: convert hsw_ips.c " Jani Nikula
@ 2025-02-12 16:36 ` Jani Nikula
  2025-02-13  8:58   ` Kandpal, Suraj
  2025-02-12 16:36 ` [PATCH 05/14] drm/i915/display: convert assert_port_valid() " Jani Nikula
                   ` (14 subsequent siblings)
  18 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2025-02-12 16:36 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula

Going forward, struct intel_display is the main display device data
pointer. Convert the assert_transcoder*() helpers to struct
intel_display, allowing further conversions elsewhere.

Do a few small opportunistic conversions right away.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c        |  7 ++--
 drivers/gpu/drm/i915/display/intel_display.c | 34 +++++++++-----------
 drivers/gpu/drm/i915/display/intel_display.h |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll.c    | 30 +++++++++--------
 drivers/gpu/drm/i915/display/intel_fdi.c     |  3 +-
 drivers/gpu/drm/i915/display/intel_tv.c      |  3 +-
 6 files changed, 38 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index cfc796607a78..f50ab9a3f3e9 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -197,9 +197,8 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
+	assert_transcoder_disabled(display, pipe_config->cpu_transcoder);
 	assert_dp_port_disabled(intel_dp);
 	assert_edp_pll_disabled(display);
 
@@ -237,10 +236,8 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp,
 			    const struct intel_crtc_state *old_crtc_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
+	assert_transcoder_disabled(display, old_crtc_state->cpu_transcoder);
 	assert_dp_port_disabled(intel_dp);
 	assert_edp_pll_enabled(display);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b8c57a5d26a0..a95564b499ea 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -419,23 +419,22 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 	}
 }
 
-void assert_transcoder(struct drm_i915_private *dev_priv,
+void assert_transcoder(struct intel_display *display,
 		       enum transcoder cpu_transcoder, bool state)
 {
-	struct intel_display *display = &dev_priv->display;
 	bool cur_state;
 	enum intel_display_power_domain power_domain;
 	intel_wakeref_t wakeref;
 
 	/* we keep both pipes enabled on 830 */
-	if (IS_I830(dev_priv))
+	if (display->platform.i830)
 		state = true;
 
 	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 	wakeref = intel_display_power_get_if_enabled(display, power_domain);
 	if (wakeref) {
-		u32 val = intel_de_read(dev_priv,
-					TRANSCONF(dev_priv, cpu_transcoder));
+		u32 val = intel_de_read(display,
+					TRANSCONF(display, cpu_transcoder));
 		cur_state = !!(val & TRANSCONF_ENABLE);
 
 		intel_display_power_put(display, power_domain, wakeref);
@@ -1968,8 +1967,8 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
 
 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	if (!crtc_state->gmch_pfit.control)
 		return;
@@ -1978,18 +1977,18 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
 	 * The panel fitter should only be adjusted whilst the pipe is disabled,
 	 * according to register description and PRM.
 	 */
-	drm_WARN_ON(&dev_priv->drm,
-		    intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_ENABLE);
-	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
+	drm_WARN_ON(display->drm,
+		    intel_de_read(display, PFIT_CONTROL(display)) & PFIT_ENABLE);
+	assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
 
-	intel_de_write(dev_priv, PFIT_PGM_RATIOS(dev_priv),
+	intel_de_write(display, PFIT_PGM_RATIOS(display),
 		       crtc_state->gmch_pfit.pgm_ratios);
-	intel_de_write(dev_priv, PFIT_CONTROL(dev_priv),
+	intel_de_write(display, PFIT_CONTROL(display),
 		       crtc_state->gmch_pfit.control);
 
 	/* Border color in case we don't scale up to the full screen. Black by
 	 * default, change to something else for debugging. */
-	intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
+	intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);
 }
 
 /* Prefer intel_encoder_is_combo() */
@@ -2300,17 +2299,16 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
 
 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_display *display = to_intel_display(old_crtc_state);
 
 	if (!old_crtc_state->gmch_pfit.control)
 		return;
 
-	assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
+	assert_transcoder_disabled(display, old_crtc_state->cpu_transcoder);
 
-	drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
-		    intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)));
-	intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), 0);
+	drm_dbg_kms(display->drm, "disabling pfit, current: 0x%08x\n",
+		    intel_de_read(display, PFIT_CONTROL(display)));
+	intel_de_write(display, PFIT_CONTROL(display), 0);
 }
 
 static void i9xx_crtc_disable(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index e594492bade7..503e2ea1d029 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -574,7 +574,7 @@ int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
 void intel_hpd_poll_fini(struct drm_i915_private *i915);
 
 /* modesetting asserts */
-void assert_transcoder(struct drm_i915_private *dev_priv,
+void assert_transcoder(struct intel_display *display,
 		       enum transcoder cpu_transcoder, bool state);
 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index cc19cd51ab4d..08a30e5aafce 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1843,7 +1843,7 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	int i;
 
-	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
+	assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
 
 	/* PLL is protected by panel, make sure we can write it */
 	if (i9xx_has_pps(dev_priv))
@@ -2024,7 +2024,7 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
 	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
 	enum pipe pipe = crtc->pipe;
 
-	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
+	assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
 
 	/* PLL is protected by panel, make sure we can write it */
 	assert_pps_unlocked(display, pipe);
@@ -2171,7 +2171,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
 	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
 	enum pipe pipe = crtc->pipe;
 
-	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
+	assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
 
 	/* PLL is protected by panel, make sure we can write it */
 	assert_pps_unlocked(display, pipe);
@@ -2253,36 +2253,38 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
 
 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
+	struct intel_display *display = &dev_priv->display;
 	u32 val;
 
 	/* Make sure the pipe isn't still relying on us */
-	assert_transcoder_disabled(dev_priv, (enum transcoder)pipe);
+	assert_transcoder_disabled(display, (enum transcoder)pipe);
 
 	val = DPLL_INTEGRATED_REF_CLK_VLV |
 		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 	if (pipe != PIPE_A)
 		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 
-	intel_de_write(dev_priv, DPLL(dev_priv, pipe), val);
-	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
+	intel_de_write(display, DPLL(display, pipe), val);
+	intel_de_posting_read(display, DPLL(display, pipe));
 }
 
 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
+	struct intel_display *display = &dev_priv->display;
 	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 	enum dpio_phy phy = vlv_pipe_to_phy(pipe);
 	u32 val;
 
 	/* Make sure the pipe isn't still relying on us */
-	assert_transcoder_disabled(dev_priv, (enum transcoder)pipe);
+	assert_transcoder_disabled(display, (enum transcoder)pipe);
 
 	val = DPLL_SSC_REF_CLK_CHV |
 		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 	if (pipe != PIPE_A)
 		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 
-	intel_de_write(dev_priv, DPLL(dev_priv, pipe), val);
-	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
+	intel_de_write(display, DPLL(display, pipe), val);
+	intel_de_posting_read(display, DPLL(display, pipe));
 
 	vlv_dpio_get(dev_priv);
 
@@ -2296,19 +2298,19 @@ void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 
 void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
 	/* Don't disable pipe or pipe PLLs if needed */
-	if (IS_I830(dev_priv))
+	if (display->platform.i830)
 		return;
 
 	/* Make sure the pipe isn't still relying on us */
-	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
+	assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
 
-	intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS);
-	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
+	intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);
+	intel_de_posting_read(display, DPLL(display, pipe));
 }
 
 
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 9ebe80bfaab6..024d0c7e0a88 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -511,6 +511,7 @@ void intel_fdi_normal_train(struct intel_crtc *crtc)
 static void ilk_fdi_link_train(struct intel_crtc *crtc,
 			       const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc);
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	enum pipe pipe = crtc->pipe;
@@ -525,7 +526,7 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
 		       intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK);
 
 	/* FDI needs bits from pipe first */
-	assert_transcoder_enabled(dev_priv, crtc_state->cpu_transcoder);
+	assert_transcoder_enabled(display, crtc_state->cpu_transcoder);
 
 	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
 	   for train result */
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
index 1c50732a099d..7838c92f8ded 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -1436,7 +1436,6 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
 				const struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct intel_tv *intel_tv = enc_to_tv(encoder);
 	const struct intel_tv_connector_state *tv_conn_state =
@@ -1543,7 +1542,7 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
 		intel_de_write(display, TV_CLR_LEVEL,
 			       ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
 
-	assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
+	assert_transcoder_disabled(display, pipe_config->cpu_transcoder);
 
 	/* Filter ctl must be set before TV_WIN_SIZE */
 	tv_filter_ctl = TV_AUTO_SCALE;
-- 
2.39.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* RE: [PATCH 04/14] drm/i915/display: convert assert_transcoder*() to struct intel_display
  2025-02-12 16:36 ` [PATCH 04/14] drm/i915/display: convert assert_transcoder*() " Jani Nikula
@ 2025-02-13  8:58   ` Kandpal, Suraj
  0 siblings, 0 replies; 35+ messages in thread
From: Kandpal, Suraj @ 2025-02-13  8:58 UTC (permalink / raw)
  To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org
  Cc: Nikula, Jani



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Wednesday, February 12, 2025 10:07 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 04/14] drm/i915/display: convert assert_transcoder*() to
> struct intel_display
> 
> Going forward, struct intel_display is the main display device data pointer.
> Convert the assert_transcoder*() helpers to struct intel_display, allowing
> further conversions elsewhere.
> 
> Do a few small opportunistic conversions right away.
> 

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/g4x_dp.c        |  7 ++--
>  drivers/gpu/drm/i915/display/intel_display.c | 34 +++++++++-----------
> drivers/gpu/drm/i915/display/intel_display.h |  2 +-
>  drivers/gpu/drm/i915/display/intel_dpll.c    | 30 +++++++++--------
>  drivers/gpu/drm/i915/display/intel_fdi.c     |  3 +-
>  drivers/gpu/drm/i915/display/intel_tv.c      |  3 +-
>  6 files changed, 38 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> b/drivers/gpu/drm/i915/display/g4x_dp.c
> index cfc796607a78..f50ab9a3f3e9 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -197,9 +197,8 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
> {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> 
> -	assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
> +	assert_transcoder_disabled(display, pipe_config->cpu_transcoder);
>  	assert_dp_port_disabled(intel_dp);
>  	assert_edp_pll_disabled(display);
> 
> @@ -237,10 +236,8 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp,
>  			    const struct intel_crtc_state *old_crtc_state)  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> 
> -	assert_transcoder_disabled(dev_priv, old_crtc_state-
> >cpu_transcoder);
> +	assert_transcoder_disabled(display, old_crtc_state-
> >cpu_transcoder);
>  	assert_dp_port_disabled(intel_dp);
>  	assert_edp_pll_enabled(display);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b8c57a5d26a0..a95564b499ea 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -419,23 +419,22 @@ intel_wait_for_pipe_off(const struct
> intel_crtc_state *old_crtc_state)
>  	}
>  }
> 
> -void assert_transcoder(struct drm_i915_private *dev_priv,
> +void assert_transcoder(struct intel_display *display,
>  		       enum transcoder cpu_transcoder, bool state)  {
> -	struct intel_display *display = &dev_priv->display;
>  	bool cur_state;
>  	enum intel_display_power_domain power_domain;
>  	intel_wakeref_t wakeref;
> 
>  	/* we keep both pipes enabled on 830 */
> -	if (IS_I830(dev_priv))
> +	if (display->platform.i830)
>  		state = true;
> 
>  	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
>  	wakeref = intel_display_power_get_if_enabled(display,
> power_domain);
>  	if (wakeref) {
> -		u32 val = intel_de_read(dev_priv,
> -					TRANSCONF(dev_priv,
> cpu_transcoder));
> +		u32 val = intel_de_read(display,
> +					TRANSCONF(display,
> cpu_transcoder));
>  		cur_state = !!(val & TRANSCONF_ENABLE);
> 
>  		intel_display_power_put(display, power_domain, wakeref);
> @@ -1968,8 +1967,8 @@ static void hsw_crtc_disable(struct
> intel_atomic_state *state,
> 
>  static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)  {
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> 
>  	if (!crtc_state->gmch_pfit.control)
>  		return;
> @@ -1978,18 +1977,18 @@ static void i9xx_pfit_enable(const struct
> intel_crtc_state *crtc_state)
>  	 * The panel fitter should only be adjusted whilst the pipe is
> disabled,
>  	 * according to register description and PRM.
>  	 */
> -	drm_WARN_ON(&dev_priv->drm,
> -		    intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) &
> PFIT_ENABLE);
> -	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
> +	drm_WARN_ON(display->drm,
> +		    intel_de_read(display, PFIT_CONTROL(display)) &
> PFIT_ENABLE);
> +	assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
> 
> -	intel_de_write(dev_priv, PFIT_PGM_RATIOS(dev_priv),
> +	intel_de_write(display, PFIT_PGM_RATIOS(display),
>  		       crtc_state->gmch_pfit.pgm_ratios);
> -	intel_de_write(dev_priv, PFIT_CONTROL(dev_priv),
> +	intel_de_write(display, PFIT_CONTROL(display),
>  		       crtc_state->gmch_pfit.control);
> 
>  	/* Border color in case we don't scale up to the full screen. Black by
>  	 * default, change to something else for debugging. */
> -	intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
> +	intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);
>  }
> 
>  /* Prefer intel_encoder_is_combo() */
> @@ -2300,17 +2299,16 @@ static void i9xx_crtc_enable(struct
> intel_atomic_state *state,
> 
>  static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)  {
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct intel_display *display = to_intel_display(old_crtc_state);
> 
>  	if (!old_crtc_state->gmch_pfit.control)
>  		return;
> 
> -	assert_transcoder_disabled(dev_priv, old_crtc_state-
> >cpu_transcoder);
> +	assert_transcoder_disabled(display, old_crtc_state-
> >cpu_transcoder);
> 
> -	drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
> -		    intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)));
> -	intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), 0);
> +	drm_dbg_kms(display->drm, "disabling pfit, current: 0x%08x\n",
> +		    intel_de_read(display, PFIT_CONTROL(display)));
> +	intel_de_write(display, PFIT_CONTROL(display), 0);
>  }
> 
>  static void i9xx_crtc_disable(struct intel_atomic_state *state, diff --git
> a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index e594492bade7..503e2ea1d029 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -574,7 +574,7 @@ int intel_atomic_commit(struct drm_device *dev,
> struct drm_atomic_state *_state,  void intel_hpd_poll_fini(struct
> drm_i915_private *i915);
> 
>  /* modesetting asserts */
> -void assert_transcoder(struct drm_i915_private *dev_priv,
> +void assert_transcoder(struct intel_display *display,
>  		       enum transcoder cpu_transcoder, bool state);  #define
> assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)  #define
> assert_transcoder_disabled(d, t) assert_transcoder(d, t, false) diff --git
> a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index cc19cd51ab4d..08a30e5aafce 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1843,7 +1843,7 @@ void i9xx_enable_pll(const struct intel_crtc_state
> *crtc_state)
>  	enum pipe pipe = crtc->pipe;
>  	int i;
> 
> -	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
> +	assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
> 
>  	/* PLL is protected by panel, make sure we can write it */
>  	if (i9xx_has_pps(dev_priv))
> @@ -2024,7 +2024,7 @@ void vlv_enable_pll(const struct intel_crtc_state
> *crtc_state)
>  	const struct i9xx_dpll_hw_state *hw_state = &crtc_state-
> >dpll_hw_state.i9xx;
>  	enum pipe pipe = crtc->pipe;
> 
> -	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
> +	assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
> 
>  	/* PLL is protected by panel, make sure we can write it */
>  	assert_pps_unlocked(display, pipe);
> @@ -2171,7 +2171,7 @@ void chv_enable_pll(const struct intel_crtc_state
> *crtc_state)
>  	const struct i9xx_dpll_hw_state *hw_state = &crtc_state-
> >dpll_hw_state.i9xx;
>  	enum pipe pipe = crtc->pipe;
> 
> -	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
> +	assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
> 
>  	/* PLL is protected by panel, make sure we can write it */
>  	assert_pps_unlocked(display, pipe);
> @@ -2253,36 +2253,38 @@ int vlv_force_pll_on(struct drm_i915_private
> *dev_priv, enum pipe pipe,
> 
>  void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)  {
> +	struct intel_display *display = &dev_priv->display;
>  	u32 val;
> 
>  	/* Make sure the pipe isn't still relying on us */
> -	assert_transcoder_disabled(dev_priv, (enum transcoder)pipe);
> +	assert_transcoder_disabled(display, (enum transcoder)pipe);
> 
>  	val = DPLL_INTEGRATED_REF_CLK_VLV |
>  		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
>  	if (pipe != PIPE_A)
>  		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
> 
> -	intel_de_write(dev_priv, DPLL(dev_priv, pipe), val);
> -	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
> +	intel_de_write(display, DPLL(display, pipe), val);
> +	intel_de_posting_read(display, DPLL(display, pipe));
>  }
> 
>  void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)  {
> +	struct intel_display *display = &dev_priv->display;
>  	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
>  	enum dpio_phy phy = vlv_pipe_to_phy(pipe);
>  	u32 val;
> 
>  	/* Make sure the pipe isn't still relying on us */
> -	assert_transcoder_disabled(dev_priv, (enum transcoder)pipe);
> +	assert_transcoder_disabled(display, (enum transcoder)pipe);
> 
>  	val = DPLL_SSC_REF_CLK_CHV |
>  		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
>  	if (pipe != PIPE_A)
>  		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
> 
> -	intel_de_write(dev_priv, DPLL(dev_priv, pipe), val);
> -	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
> +	intel_de_write(display, DPLL(display, pipe), val);
> +	intel_de_posting_read(display, DPLL(display, pipe));
> 
>  	vlv_dpio_get(dev_priv);
> 
> @@ -2296,19 +2298,19 @@ void chv_disable_pll(struct drm_i915_private
> *dev_priv, enum pipe pipe)
> 
>  void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)  {
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
> 
>  	/* Don't disable pipe or pipe PLLs if needed */
> -	if (IS_I830(dev_priv))
> +	if (display->platform.i830)
>  		return;
> 
>  	/* Make sure the pipe isn't still relying on us */
> -	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
> +	assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
> 
> -	intel_de_write(dev_priv, DPLL(dev_priv, pipe),
> DPLL_VGA_MODE_DIS);
> -	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
> +	intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);
> +	intel_de_posting_read(display, DPLL(display, pipe));
>  }
> 
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
> b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 9ebe80bfaab6..024d0c7e0a88 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -511,6 +511,7 @@ void intel_fdi_normal_train(struct intel_crtc *crtc)
> static void ilk_fdi_link_train(struct intel_crtc *crtc,
>  			       const struct intel_crtc_state *crtc_state)  {
> +	struct intel_display *display = to_intel_display(crtc);
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	enum pipe pipe = crtc->pipe;
> @@ -525,7 +526,7 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
>  		       intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe))
> & TU_SIZE_MASK);
> 
>  	/* FDI needs bits from pipe first */
> -	assert_transcoder_enabled(dev_priv, crtc_state->cpu_transcoder);
> +	assert_transcoder_enabled(display, crtc_state->cpu_transcoder);
> 
>  	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
>  	   for train result */
> diff --git a/drivers/gpu/drm/i915/display/intel_tv.c
> b/drivers/gpu/drm/i915/display/intel_tv.c
> index 1c50732a099d..7838c92f8ded 100644
> --- a/drivers/gpu/drm/i915/display/intel_tv.c
> +++ b/drivers/gpu/drm/i915/display/intel_tv.c
> @@ -1436,7 +1436,6 @@ static void intel_tv_pre_enable(struct
> intel_atomic_state *state,
>  				const struct drm_connector_state
> *conn_state)  {
>  	struct intel_display *display = to_intel_display(encoder);
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	struct intel_tv *intel_tv = enc_to_tv(encoder);
>  	const struct intel_tv_connector_state *tv_conn_state = @@ -1543,7
> +1542,7 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
>  		intel_de_write(display, TV_CLR_LEVEL,
>  			       ((video_levels->black << TV_BLACK_LEVEL_SHIFT)
> | (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
> 
> -	assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
> +	assert_transcoder_disabled(display, pipe_config->cpu_transcoder);
> 
>  	/* Filter ctl must be set before TV_WIN_SIZE */
>  	tv_filter_ctl = TV_AUTO_SCALE;
> --
> 2.39.5


^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 05/14] drm/i915/display: convert assert_port_valid() to struct intel_display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
                   ` (3 preceding siblings ...)
  2025-02-12 16:36 ` [PATCH 04/14] drm/i915/display: convert assert_transcoder*() " Jani Nikula
@ 2025-02-12 16:36 ` Jani Nikula
  2025-02-13  8:59   ` Kandpal, Suraj
  2025-02-12 16:36 ` [PATCH 06/14] drm/i915/hpd: drop dev_priv parameter from intel_hpd_pin_default() Jani Nikula
                   ` (13 subsequent siblings)
  18 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2025-02-12 16:36 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula

Going forward, struct intel_display is the main display device data
pointer. Convert the assert_port_valid() helper to struct intel_display,
allowing further conversions elsewhere.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c        | 2 +-
 drivers/gpu/drm/i915/display/g4x_hdmi.c      | 2 +-
 drivers/gpu/drm/i915/display/intel_crt.c     | 2 +-
 drivers/gpu/drm/i915/display/intel_ddi.c     | 2 +-
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
 drivers/gpu/drm/i915/display/intel_display.h | 2 +-
 drivers/gpu/drm/i915/display/intel_dvo.c     | 2 +-
 drivers/gpu/drm/i915/display/intel_sdvo.c    | 3 ++-
 8 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index f50ab9a3f3e9..b6cb5c74a32e 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -1286,7 +1286,7 @@ bool g4x_dp_init(struct intel_display *display,
 	struct drm_encoder *encoder;
 	struct intel_connector *intel_connector;
 
-	if (!assert_port_valid(dev_priv, port))
+	if (!assert_port_valid(display, port))
 		return false;
 
 	devdata = intel_bios_encoder_data_lookup(display, port);
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 6670cf101b9a..5b2df1014c10 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -691,7 +691,7 @@ bool g4x_hdmi_init(struct intel_display *display,
 	struct intel_encoder *intel_encoder;
 	struct intel_connector *intel_connector;
 
-	if (!assert_port_valid(dev_priv, port))
+	if (!assert_port_valid(display, port))
 		return false;
 
 	if (!assert_hdmi_port_valid(display, port))
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index aa46c14ce225..396846025922 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -1099,7 +1099,7 @@ void intel_crt_init(struct intel_display *display)
 	connector->base.polled = connector->polled;
 
 	if (HAS_DDI(display)) {
-		assert_port_valid(dev_priv, PORT_E);
+		assert_port_valid(display, PORT_E);
 
 		crt->base.port = PORT_E;
 		crt->base.get_config = hsw_crt_get_config;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2c05742d8fd1..ab382adaba56 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5132,7 +5132,7 @@ void intel_ddi_init(struct intel_display *display,
 		return;
 	}
 
-	if (!assert_port_valid(dev_priv, port))
+	if (!assert_port_valid(display, port))
 		return;
 
 	if (port_in_use(dev_priv, port)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a95564b499ea..2a8f53f06463 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8188,9 +8188,9 @@ static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
 	return true;
 }
 
-bool assert_port_valid(struct drm_i915_private *i915, enum port port)
+bool assert_port_valid(struct intel_display *display, enum port port)
 {
-	return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)->port_mask & BIT(port)),
+	return !drm_WARN(display->drm, !(DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)),
 			 "Platform does not support port %c\n", port_name(port));
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 503e2ea1d029..9439da737f5b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -579,7 +579,7 @@ void assert_transcoder(struct intel_display *display,
 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
 
-bool assert_port_valid(struct drm_i915_private *i915, enum port port);
+bool assert_port_valid(struct intel_display *display, enum port port);
 
 /*
  * Use INTEL_DISPLAY_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index c310698a1a86..29f8788fb26a 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -524,7 +524,7 @@ void intel_dvo_init(struct drm_i915_private *i915)
 		return;
 	}
 
-	assert_port_valid(i915, intel_dvo->dev.port);
+	assert_port_valid(display, intel_dvo->dev.port);
 
 	encoder->type = INTEL_OUTPUT_DVO;
 	encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 6ebd099d8861..0c3aa2e7b78b 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -3386,11 +3386,12 @@ static bool assert_sdvo_port_valid(struct drm_i915_private *dev_priv,
 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
 		     i915_reg_t sdvo_reg, enum port port)
 {
+	struct intel_display *display = &dev_priv->display;
 	struct intel_encoder *intel_encoder;
 	struct intel_sdvo *intel_sdvo;
 	int i;
 
-	if (!assert_port_valid(dev_priv, port))
+	if (!assert_port_valid(display, port))
 		return false;
 
 	if (!assert_sdvo_port_valid(dev_priv, port))
-- 
2.39.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* RE: [PATCH 05/14] drm/i915/display: convert assert_port_valid() to struct intel_display
  2025-02-12 16:36 ` [PATCH 05/14] drm/i915/display: convert assert_port_valid() " Jani Nikula
@ 2025-02-13  8:59   ` Kandpal, Suraj
  0 siblings, 0 replies; 35+ messages in thread
From: Kandpal, Suraj @ 2025-02-13  8:59 UTC (permalink / raw)
  To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org
  Cc: Nikula, Jani



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Wednesday, February 12, 2025 10:07 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 05/14] drm/i915/display: convert assert_port_valid() to
> struct intel_display
> 
> Going forward, struct intel_display is the main display device data pointer.
> Convert the assert_port_valid() helper to struct intel_display, allowing
> further conversions elsewhere.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/g4x_dp.c        | 2 +-
>  drivers/gpu/drm/i915/display/g4x_hdmi.c      | 2 +-
>  drivers/gpu/drm/i915/display/intel_crt.c     | 2 +-
>  drivers/gpu/drm/i915/display/intel_ddi.c     | 2 +-
>  drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
>  drivers/gpu/drm/i915/display/intel_dvo.c     | 2 +-
>  drivers/gpu/drm/i915/display/intel_sdvo.c    | 3 ++-
>  8 files changed, 10 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> b/drivers/gpu/drm/i915/display/g4x_dp.c
> index f50ab9a3f3e9..b6cb5c74a32e 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -1286,7 +1286,7 @@ bool g4x_dp_init(struct intel_display *display,
>  	struct drm_encoder *encoder;
>  	struct intel_connector *intel_connector;
> 
> -	if (!assert_port_valid(dev_priv, port))
> +	if (!assert_port_valid(display, port))
>  		return false;
> 
>  	devdata = intel_bios_encoder_data_lookup(display, port); diff --git
> a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> index 6670cf101b9a..5b2df1014c10 100644
> --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> @@ -691,7 +691,7 @@ bool g4x_hdmi_init(struct intel_display *display,
>  	struct intel_encoder *intel_encoder;
>  	struct intel_connector *intel_connector;
> 
> -	if (!assert_port_valid(dev_priv, port))
> +	if (!assert_port_valid(display, port))
>  		return false;
> 
>  	if (!assert_hdmi_port_valid(display, port)) diff --git
> a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index aa46c14ce225..396846025922 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -1099,7 +1099,7 @@ void intel_crt_init(struct intel_display *display)
>  	connector->base.polled = connector->polled;
> 
>  	if (HAS_DDI(display)) {
> -		assert_port_valid(dev_priv, PORT_E);
> +		assert_port_valid(display, PORT_E);
> 
>  		crt->base.port = PORT_E;
>  		crt->base.get_config = hsw_crt_get_config; diff --git
> a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 2c05742d8fd1..ab382adaba56 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -5132,7 +5132,7 @@ void intel_ddi_init(struct intel_display *display,
>  		return;
>  	}
> 
> -	if (!assert_port_valid(dev_priv, port))
> +	if (!assert_port_valid(display, port))
>  		return;
> 
>  	if (port_in_use(dev_priv, port)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index a95564b499ea..2a8f53f06463 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8188,9 +8188,9 @@ static bool intel_ddi_crt_present(struct
> drm_i915_private *dev_priv)
>  	return true;
>  }
> 
> -bool assert_port_valid(struct drm_i915_private *i915, enum port port)
> +bool assert_port_valid(struct intel_display *display, enum port port)
>  {
> -	return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)-
> >port_mask & BIT(port)),
> +	return !drm_WARN(display->drm,
> +!(DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)),
>  			 "Platform does not support port %c\n",
> port_name(port));  }
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 503e2ea1d029..9439da737f5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -579,7 +579,7 @@ void assert_transcoder(struct intel_display *display,
> #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
> #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
> 
> -bool assert_port_valid(struct drm_i915_private *i915, enum port port);
> +bool assert_port_valid(struct intel_display *display, enum port port);
> 
>  /*
>   * Use INTEL_DISPLAY_STATE_WARN(x) (rather than WARN() and
> WARN_ON()) for hw diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c
> b/drivers/gpu/drm/i915/display/intel_dvo.c
> index c310698a1a86..29f8788fb26a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -524,7 +524,7 @@ void intel_dvo_init(struct drm_i915_private *i915)
>  		return;
>  	}
> 
> -	assert_port_valid(i915, intel_dvo->dev.port);
> +	assert_port_valid(display, intel_dvo->dev.port);
> 
>  	encoder->type = INTEL_OUTPUT_DVO;
>  	encoder->power_domain = POWER_DOMAIN_PORT_OTHER; diff --git
> a/drivers/gpu/drm/i915/display/intel_sdvo.c
> b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index 6ebd099d8861..0c3aa2e7b78b 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -3386,11 +3386,12 @@ static bool assert_sdvo_port_valid(struct
> drm_i915_private *dev_priv,  bool intel_sdvo_init(struct drm_i915_private
> *dev_priv,
>  		     i915_reg_t sdvo_reg, enum port port)  {
> +	struct intel_display *display = &dev_priv->display;
>  	struct intel_encoder *intel_encoder;
>  	struct intel_sdvo *intel_sdvo;
>  	int i;
> 
> -	if (!assert_port_valid(dev_priv, port))
> +	if (!assert_port_valid(display, port))
>  		return false;
> 
>  	if (!assert_sdvo_port_valid(dev_priv, port))
> --
> 2.39.5


^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 06/14] drm/i915/hpd: drop dev_priv parameter from intel_hpd_pin_default()
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
                   ` (4 preceding siblings ...)
  2025-02-12 16:36 ` [PATCH 05/14] drm/i915/display: convert assert_port_valid() " Jani Nikula
@ 2025-02-12 16:36 ` Jani Nikula
  2025-02-13  9:01   ` Kandpal, Suraj
  2025-02-12 16:36 ` [PATCH 07/14] drm/i915/display: convert intel_set_{cpu, pch}_fifo_underrun_reporting() to intel_display Jani Nikula
                   ` (12 subsequent siblings)
  18 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2025-02-12 16:36 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula

The function doesn't use the parameter for anything. Drop it.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c        | 2 +-
 drivers/gpu/drm/i915/display/g4x_hdmi.c      | 2 +-
 drivers/gpu/drm/i915/display/intel_ddi.c     | 2 +-
 drivers/gpu/drm/i915/display/intel_hotplug.c | 4 +---
 drivers/gpu/drm/i915/display/intel_hotplug.h | 3 +--
 5 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index b6cb5c74a32e..4b51a4e47f63 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -1393,7 +1393,7 @@ bool g4x_dp_init(struct intel_display *display,
 	}
 	intel_encoder->cloneable = 0;
 	intel_encoder->port = port;
-	intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
+	intel_encoder->hpd_pin = intel_hpd_pin_default(port);
 
 	dig_port->hpd_pulse = intel_dp_hpd_pulse;
 
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 5b2df1014c10..1cd2e68e6ec5 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -771,7 +771,7 @@ bool g4x_hdmi_init(struct intel_display *display,
 		intel_encoder->pipe_mask = ~0;
 	}
 	intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG);
-	intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
+	intel_encoder->hpd_pin = intel_hpd_pin_default(port);
 	/*
 	 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
 	 * to work on real hardware. And since g4x can send infoframes to
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ab382adaba56..ce7097937d70 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5368,7 +5368,7 @@ void intel_ddi_init(struct intel_display *display,
 	else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
 		encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
 	else
-		encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
+		encoder->hpd_pin = intel_hpd_pin_default(port);
 
 	ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
 
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index d2e0002c5dc3..9c935afc60aa 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -82,15 +82,13 @@
 
 /**
  * intel_hpd_pin_default - return default pin associated with certain port.
- * @dev_priv: private driver data pointer
  * @port: the hpd port to get associated pin
  *
  * It is only valid and used by digital port encoder.
  *
  * Return pin that is associatade with @port.
  */
-enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
-				   enum port port)
+enum hpd_pin intel_hpd_pin_default(enum port port)
 {
 	return HPD_PORT_A + port - PORT_A;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h b/drivers/gpu/drm/i915/display/intel_hotplug.h
index a17253ddec83..d2ca9d2f1d39 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.h
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.h
@@ -24,8 +24,7 @@ void intel_hpd_trigger_irq(struct intel_digital_port *dig_port);
 void intel_hpd_init(struct drm_i915_private *dev_priv);
 void intel_hpd_init_early(struct drm_i915_private *i915);
 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
-enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
-				   enum port port);
+enum hpd_pin intel_hpd_pin_default(enum port port);
 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
 void intel_hpd_debugfs_register(struct drm_i915_private *i915);
-- 
2.39.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* RE: [PATCH 06/14] drm/i915/hpd: drop dev_priv parameter from intel_hpd_pin_default()
  2025-02-12 16:36 ` [PATCH 06/14] drm/i915/hpd: drop dev_priv parameter from intel_hpd_pin_default() Jani Nikula
@ 2025-02-13  9:01   ` Kandpal, Suraj
  0 siblings, 0 replies; 35+ messages in thread
From: Kandpal, Suraj @ 2025-02-13  9:01 UTC (permalink / raw)
  To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org
  Cc: Nikula, Jani



> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Wednesday, February 12, 2025 10:07 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 06/14] drm/i915/hpd: drop dev_priv parameter from
> intel_hpd_pin_default()
> 
> The function doesn't use the parameter for anything. Drop it.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/g4x_dp.c        | 2 +-
>  drivers/gpu/drm/i915/display/g4x_hdmi.c      | 2 +-
>  drivers/gpu/drm/i915/display/intel_ddi.c     | 2 +-
>  drivers/gpu/drm/i915/display/intel_hotplug.c | 4 +---
> drivers/gpu/drm/i915/display/intel_hotplug.h | 3 +--
>  5 files changed, 5 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> b/drivers/gpu/drm/i915/display/g4x_dp.c
> index b6cb5c74a32e..4b51a4e47f63 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -1393,7 +1393,7 @@ bool g4x_dp_init(struct intel_display *display,
>  	}
>  	intel_encoder->cloneable = 0;
>  	intel_encoder->port = port;
> -	intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
> +	intel_encoder->hpd_pin = intel_hpd_pin_default(port);
> 
>  	dig_port->hpd_pulse = intel_dp_hpd_pulse;
> 
> diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> index 5b2df1014c10..1cd2e68e6ec5 100644
> --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> @@ -771,7 +771,7 @@ bool g4x_hdmi_init(struct intel_display *display,
>  		intel_encoder->pipe_mask = ~0;
>  	}
>  	intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG);
> -	intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
> +	intel_encoder->hpd_pin = intel_hpd_pin_default(port);
>  	/*
>  	 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
>  	 * to work on real hardware. And since g4x can send infoframes to
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index ab382adaba56..ce7097937d70 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -5368,7 +5368,7 @@ void intel_ddi_init(struct intel_display *display,
>  	else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
>  		encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
>  	else
> -		encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
> +		encoder->hpd_pin = intel_hpd_pin_default(port);
> 
>  	ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index d2e0002c5dc3..9c935afc60aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -82,15 +82,13 @@
> 
>  /**
>   * intel_hpd_pin_default - return default pin associated with certain port.
> - * @dev_priv: private driver data pointer
>   * @port: the hpd port to get associated pin
>   *
>   * It is only valid and used by digital port encoder.
>   *
>   * Return pin that is associatade with @port.
>   */
> -enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
> -				   enum port port)
> +enum hpd_pin intel_hpd_pin_default(enum port port)
>  {
>  	return HPD_PORT_A + port - PORT_A;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h
> b/drivers/gpu/drm/i915/display/intel_hotplug.h
> index a17253ddec83..d2ca9d2f1d39 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.h
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.h
> @@ -24,8 +24,7 @@ void intel_hpd_trigger_irq(struct intel_digital_port
> *dig_port);  void intel_hpd_init(struct drm_i915_private *dev_priv);  void
> intel_hpd_init_early(struct drm_i915_private *i915);  void
> intel_hpd_cancel_work(struct drm_i915_private *dev_priv); -enum hpd_pin
> intel_hpd_pin_default(struct drm_i915_private *dev_priv,
> -				   enum port port);
> +enum hpd_pin intel_hpd_pin_default(enum port port);
>  bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin
> pin);  void intel_hpd_enable(struct drm_i915_private *dev_priv, enum
> hpd_pin pin);  void intel_hpd_debugfs_register(struct drm_i915_private
> *i915);
> --
> 2.39.5


^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 07/14] drm/i915/display: convert intel_set_{cpu, pch}_fifo_underrun_reporting() to intel_display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
                   ` (5 preceding siblings ...)
  2025-02-12 16:36 ` [PATCH 06/14] drm/i915/hpd: drop dev_priv parameter from intel_hpd_pin_default() Jani Nikula
@ 2025-02-12 16:36 ` Jani Nikula
  2025-02-13  9:03   ` Kandpal, Suraj
  2025-02-12 16:36 ` [PATCH 08/14] drm/i915/sdvo: convert intel_sdvo.[ch] to struct intel_display Jani Nikula
                   ` (11 subsequent siblings)
  18 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2025-02-12 16:36 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula

Going forward, struct intel_display is the main display device data
pointer. Convert intel_set_cpu_fifo_underrun_reporting() and
intel_set_pch_fifo_underrun_reporting() to struct intel_display, along
with some of the call chains from there.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c         |  8 +-
 drivers/gpu/drm/i915/display/g4x_hdmi.c       |  8 +-
 drivers/gpu/drm/i915/display/intel_crt.c      | 17 ++--
 drivers/gpu/drm/i915/display/intel_ddi.c      |  3 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 43 +++++-----
 .../drm/i915/display/intel_fifo_underrun.c    | 84 +++++++++----------
 .../drm/i915/display/intel_fifo_underrun.h    |  7 +-
 drivers/gpu/drm/i915/display/intel_sdvo.c     |  8 +-
 drivers/gpu/drm/i915/display/vlv_dsi.c        |  2 +-
 9 files changed, 89 insertions(+), 91 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 4b51a4e47f63..0cb98cb043c6 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -453,8 +453,8 @@ intel_dp_link_down(struct intel_encoder *encoder,
 		 * We get CPU/PCH FIFO underruns on the other pipe when
 		 * doing the workaround. Sweep them under the rug.
 		 */
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
-		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
+		intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);
+		intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
 
 		/* always enable with pattern 1 (as per spec) */
 		intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
@@ -468,8 +468,8 @@ intel_dp_link_down(struct intel_encoder *encoder,
 		intel_de_posting_read(display, intel_dp->output_reg);
 
 		intel_wait_for_vblank_if_active(display, PIPE_A);
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
-		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
+		intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);
+		intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
 	}
 
 	msleep(intel_dp->pps.panel_power_down_delay);
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 1cd2e68e6ec5..089f1a4d7720 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -407,8 +407,8 @@ static void intel_disable_hdmi(struct intel_atomic_state *state,
 		 * We get CPU/PCH FIFO underruns on the other pipe when
 		 * doing the workaround. Sweep them under the rug.
 		 */
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
-		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
+		intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);
+		intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
 
 		temp &= ~SDVO_PIPE_SEL_MASK;
 		temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
@@ -426,8 +426,8 @@ static void intel_disable_hdmi(struct intel_atomic_state *state,
 		intel_de_posting_read(display, intel_hdmi->hdmi_reg);
 
 		intel_wait_for_vblank_if_active(display, PIPE_A);
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
-		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
+		intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);
+		intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
 	}
 
 	dig_port->set_infoframes(encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 396846025922..8eedae1d7684 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -250,11 +250,10 @@ static void hsw_disable_crt(struct intel_atomic_state *state,
 			    const struct drm_connector_state *old_conn_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
 
-	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
+	intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
 }
 
 static void hsw_post_disable_crt(struct intel_atomic_state *state,
@@ -264,7 +263,6 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
 {
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	intel_crtc_vblank_off(old_crtc_state);
 
@@ -284,7 +282,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
 
 	drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
 
-	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
+	intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
 }
 
 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
@@ -293,11 +291,10 @@ static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
 				   const struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
 
-	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
+	intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
 }
 
 static void hsw_pre_enable_crt(struct intel_atomic_state *state,
@@ -306,13 +303,12 @@ static void hsw_pre_enable_crt(struct intel_atomic_state *state,
 			       const struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
 
 	drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
 
-	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
+	intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
 
 	hsw_fdi_link_train(encoder, crtc_state);
 
@@ -325,7 +321,6 @@ static void hsw_enable_crt(struct intel_atomic_state *state,
 			   const struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
 
@@ -343,8 +338,8 @@ static void hsw_enable_crt(struct intel_atomic_state *state,
 
 	intel_crtc_wait_for_next_vblank(crtc);
 	intel_crtc_wait_for_next_vblank(crtc);
-	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
+	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
+	intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
 }
 
 static void intel_enable_crt(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ce7097937d70..900e066b2478 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3013,13 +3013,14 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state,
 				 const struct intel_crtc_state *crtc_state,
 				 const struct drm_connector_state *conn_state)
 {
+	struct intel_display *display = to_intel_display(state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
 	drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
 
-	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
+	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
 
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 		intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2a8f53f06463..9bcbd52f23cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -774,6 +774,7 @@ void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 				  struct intel_plane *plane)
 {
+	struct intel_display *display = to_intel_display(crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_crtc_state *crtc_state =
 		to_intel_crtc_state(crtc->base.state);
@@ -817,7 +818,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 	 * So disable underrun reporting before all the planes get disabled.
 	 */
 	if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
+		intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false);
 
 	intel_plane_disable_arm(NULL, plane, crtc_state);
 	intel_plane_initial_vblank_wait(crtc);
@@ -1305,6 +1306,7 @@ static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
 static void intel_pre_plane_update(struct intel_atomic_state *state,
 				   struct intel_crtc *crtc)
 {
+	struct intel_display *display = to_intel_display(state);
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	const struct intel_crtc_state *old_crtc_state =
 		intel_atomic_get_old_crtc_state(state, crtc);
@@ -1406,7 +1408,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 	 * vs. the old plane configuration.
 	 */
 	if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
+		intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
 
 	/*
 	 * WA for platforms where async address update enable bit
@@ -1645,6 +1647,7 @@ static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 static void ilk_crtc_enable(struct intel_atomic_state *state,
 			    struct intel_crtc *crtc)
 {
+	struct intel_display *display = to_intel_display(crtc);
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1663,8 +1666,8 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
 	 *
 	 * Spurious PCH underruns also occur during PCH enabling.
 	 */
-	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
+	intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
+	intel_set_pch_fifo_underrun_reporting(display, pipe, false);
 
 	ilk_configure_cpu_transcoder(new_crtc_state);
 
@@ -1712,8 +1715,8 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
 		intel_crtc_wait_for_next_vblank(crtc);
 		intel_crtc_wait_for_next_vblank(crtc);
 	}
-	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
+	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
+	intel_set_pch_fifo_underrun_reporting(display, pipe, true);
 }
 
 /* Display WA #1180: WaDisableScalarClockGating: glk */
@@ -1901,9 +1904,9 @@ void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
 static void ilk_crtc_disable(struct intel_atomic_state *state,
 			     struct intel_crtc *crtc)
 {
+	struct intel_display *display = to_intel_display(crtc);
 	const struct intel_crtc_state *old_crtc_state =
 		intel_atomic_get_old_crtc_state(state, crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
 	/*
@@ -1911,8 +1914,8 @@ static void ilk_crtc_disable(struct intel_atomic_state *state,
 	 * pipe is already disabled, but FDI RX/TX is still enabled.
 	 * Happens at least with VGA+HDMI cloning. Suppress them.
 	 */
-	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
+	intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
+	intel_set_pch_fifo_underrun_reporting(display, pipe, false);
 
 	intel_encoders_disable(state, crtc);
 
@@ -1930,8 +1933,8 @@ static void ilk_crtc_disable(struct intel_atomic_state *state,
 	if (old_crtc_state->has_pch_encoder)
 		ilk_pch_post_disable(state, crtc);
 
-	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
+	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
+	intel_set_pch_fifo_underrun_reporting(display, pipe, true);
 
 	intel_disable_shared_dpll(old_crtc_state);
 }
@@ -2211,6 +2214,7 @@ static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_st
 static void valleyview_crtc_enable(struct intel_atomic_state *state,
 				   struct intel_crtc *crtc)
 {
+	struct intel_display *display = to_intel_display(crtc);
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2233,7 +2237,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
 
 	crtc->active = true;
 
-	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
+	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
 
 	intel_encoders_pre_pll_enable(state, crtc);
 
@@ -2259,6 +2263,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
 static void i9xx_crtc_enable(struct intel_atomic_state *state,
 			     struct intel_crtc *crtc)
 {
+	struct intel_display *display = to_intel_display(crtc);
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2274,7 +2279,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
 	crtc->active = true;
 
 	if (DISPLAY_VER(dev_priv) != 2)
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
+		intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
 
 	intel_encoders_pre_enable(state, crtc);
 
@@ -2349,7 +2354,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
 	intel_encoders_post_pll_disable(state, crtc);
 
 	if (DISPLAY_VER(dev_priv) != 2)
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
+		intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
 
 	if (!dev_priv->display.funcs.wm->initial_watermarks)
 		intel_update_watermarks(dev_priv);
@@ -7069,16 +7074,16 @@ static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
 				  struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_display *display = to_intel_display(crtc);
 
-	if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
+	if (DISPLAY_VER(display) != 2 || crtc_state->active_planes)
+		intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);
 
 	if (crtc_state->has_pch_encoder) {
 		enum pipe pch_transcoder =
 			intel_crtc_pch_transcoder(crtc);
 
-		intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
+		intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, true);
 	}
 }
 
@@ -7921,7 +7926,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		 * vs. the new plane configuration.
 		 */
 		if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
-			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
+			intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);
 
 		intel_optimize_watermarks(state, crtc);
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index 18fcdbe1248a..cf70dab4881b 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -55,10 +55,9 @@
  * The code also supports underrun detection on the PCH transcoder.
  */
 
-static bool ivb_can_enable_err_int(struct drm_device *dev)
+static bool ivb_can_enable_err_int(struct intel_display *display)
 {
-	struct intel_display *display = to_intel_display(dev);
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	struct intel_crtc *crtc;
 	enum pipe pipe;
 
@@ -74,10 +73,9 @@ static bool ivb_can_enable_err_int(struct drm_device *dev)
 	return true;
 }
 
-static bool cpt_can_enable_serr_int(struct drm_device *dev)
+static bool cpt_can_enable_serr_int(struct intel_display *display)
 {
-	struct intel_display *display = to_intel_display(dev);
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	enum pipe pipe;
 	struct intel_crtc *crtc;
 
@@ -113,11 +111,11 @@ static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
 	drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));
 }
 
-static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
+static void i9xx_set_fifo_underrun_reporting(struct intel_display *display,
 					     enum pipe pipe,
 					     bool enable, bool old)
 {
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	i915_reg_t reg = PIPESTAT(dev_priv, pipe);
 
 	lockdep_assert_held(&dev_priv->irq_lock);
@@ -135,10 +133,10 @@ static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
 	}
 }
 
-static void ilk_set_fifo_underrun_reporting(struct drm_device *dev,
+static void ilk_set_fifo_underrun_reporting(struct intel_display *display,
 					    enum pipe pipe, bool enable)
 {
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	u32 bit = (pipe == PIPE_A) ?
 		DE_PIPEA_FIFO_UNDERRUN : DE_PIPEB_FIFO_UNDERRUN;
 
@@ -167,16 +165,16 @@ static void ivb_check_fifo_underruns(struct intel_crtc *crtc)
 	drm_err(&dev_priv->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));
 }
 
-static void ivb_set_fifo_underrun_reporting(struct drm_device *dev,
+static void ivb_set_fifo_underrun_reporting(struct intel_display *display,
 					    enum pipe pipe, bool enable,
 					    bool old)
 {
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	if (enable) {
 		intel_de_write(dev_priv, GEN7_ERR_INT,
 			       ERR_INT_FIFO_UNDERRUN(pipe));
 
-		if (!ivb_can_enable_err_int(dev))
+		if (!ivb_can_enable_err_int(display))
 			return;
 
 		ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
@@ -192,10 +190,10 @@ static void ivb_set_fifo_underrun_reporting(struct drm_device *dev,
 	}
 }
 
-static void bdw_set_fifo_underrun_reporting(struct drm_device *dev,
+static void bdw_set_fifo_underrun_reporting(struct intel_display *display,
 					    enum pipe pipe, bool enable)
 {
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 
 	if (enable)
 		bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
@@ -203,11 +201,11 @@ static void bdw_set_fifo_underrun_reporting(struct drm_device *dev,
 		bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
 }
 
-static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
+static void ibx_set_fifo_underrun_reporting(struct intel_display *display,
 					    enum pipe pch_transcoder,
 					    bool enable)
 {
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	u32 bit = (pch_transcoder == PIPE_A) ?
 		SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
 
@@ -238,17 +236,17 @@ static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
 		pipe_name(pch_transcoder));
 }
 
-static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
+static void cpt_set_fifo_underrun_reporting(struct intel_display *display,
 					    enum pipe pch_transcoder,
 					    bool enable, bool old)
 {
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 
 	if (enable) {
 		intel_de_write(dev_priv, SERR_INT,
 			       SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
 
-		if (!cpt_can_enable_serr_int(dev))
+		if (!cpt_can_enable_serr_int(display))
 			return;
 
 		ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
@@ -264,11 +262,10 @@ static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
 	}
 }
 
-static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
+static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,
 						    enum pipe pipe, bool enable)
 {
-	struct intel_display *display = to_intel_display(dev);
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
 	bool old;
 
@@ -277,21 +274,21 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 	old = !crtc->cpu_fifo_underrun_disabled;
 	crtc->cpu_fifo_underrun_disabled = !enable;
 
-	if (HAS_GMCH(dev_priv))
-		i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
-	else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
-		ilk_set_fifo_underrun_reporting(dev, pipe, enable);
-	else if (DISPLAY_VER(dev_priv) == 7)
-		ivb_set_fifo_underrun_reporting(dev, pipe, enable, old);
-	else if (DISPLAY_VER(dev_priv) >= 8)
-		bdw_set_fifo_underrun_reporting(dev, pipe, enable);
+	if (HAS_GMCH(display))
+		i9xx_set_fifo_underrun_reporting(display, pipe, enable, old);
+	else if (display->platform.ironlake || display->platform.sandybridge)
+		ilk_set_fifo_underrun_reporting(display, pipe, enable);
+	else if (DISPLAY_VER(display) == 7)
+		ivb_set_fifo_underrun_reporting(display, pipe, enable, old);
+	else if (DISPLAY_VER(display) >= 8)
+		bdw_set_fifo_underrun_reporting(display, pipe, enable);
 
 	return old;
 }
 
 /**
  * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrun reporting state
- * @dev_priv: i915 device instance
+ * @display: display device instance
  * @pipe: (CPU) pipe to set state for
  * @enable: whether underruns should be reported or not
  *
@@ -305,15 +302,15 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
  *
  * Returns the previous state of underrun reporting.
  */
-bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
+bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,
 					   enum pipe pipe, bool enable)
 {
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	unsigned long flags;
 	bool ret;
 
 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
-	ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe,
-						      enable);
+	ret = __intel_set_cpu_fifo_underrun_reporting(display, pipe, enable);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 
 	return ret;
@@ -321,7 +318,7 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 
 /**
  * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state
- * @dev_priv: i915 device instance
+ * @display: display device instance
  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
  * @enable: whether underruns should be reported or not
  *
@@ -333,13 +330,12 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
  *
  * Returns the previous state of underrun reporting.
  */
-bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
+bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
 					   enum pipe pch_transcoder,
 					   bool enable)
 {
-	struct intel_display *display = &dev_priv->display;
-	struct intel_crtc *crtc =
-		intel_crtc_for_pipe(display, pch_transcoder);
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
+	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pch_transcoder);
 	unsigned long flags;
 	bool old;
 
@@ -358,11 +354,11 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 	crtc->pch_fifo_underrun_disabled = !enable;
 
 	if (HAS_PCH_IBX(dev_priv))
-		ibx_set_fifo_underrun_reporting(&dev_priv->drm,
+		ibx_set_fifo_underrun_reporting(display,
 						pch_transcoder,
 						enable);
 	else
-		cpt_set_fifo_underrun_reporting(&dev_priv->drm,
+		cpt_set_fifo_underrun_reporting(display,
 						pch_transcoder,
 						enable, old);
 
@@ -394,7 +390,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 	    crtc->cpu_fifo_underrun_disabled)
 		return;
 
-	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
+	if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) {
 		trace_intel_cpu_fifo_underrun(display, pipe);
 
 		drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
@@ -417,7 +413,7 @@ void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 {
 	struct intel_display *display = &dev_priv->display;
 
-	if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder,
+	if (intel_set_pch_fifo_underrun_reporting(display, pch_transcoder,
 						  false)) {
 		trace_intel_pch_fifo_underrun(display, pch_transcoder);
 		drm_err(&dev_priv->drm, "PCH transcoder %c FIFO underrun\n",
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.h b/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
index b00d8abebcf9..8302080c2313 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
@@ -8,15 +8,16 @@
 
 #include <linux/types.h>
 
+enum pipe;
 struct drm_i915_private;
 struct intel_crtc;
-enum pipe;
+struct intel_display;
 
 void intel_init_fifo_underrun_reporting(struct drm_i915_private *i915,
 					struct intel_crtc *crtc, bool enable);
-bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
+bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,
 					   enum pipe pipe, bool enable);
-bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
+bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
 					   enum pipe pch_transcoder,
 					   bool enable);
 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 0c3aa2e7b78b..46203d796fcc 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -1864,8 +1864,8 @@ static void intel_disable_sdvo(struct intel_atomic_state *state,
 		 * We get CPU/PCH FIFO underruns on the other pipe when
 		 * doing the workaround. Sweep them under the rug.
 		 */
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
-		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
+		intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);
+		intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
 
 		temp &= ~SDVO_PIPE_SEL_MASK;
 		temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
@@ -1875,8 +1875,8 @@ static void intel_disable_sdvo(struct intel_atomic_state *state,
 		intel_sdvo_write_sdvox(intel_sdvo, temp);
 
 		intel_wait_for_vblank_if_active(display, PIPE_A);
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
-		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
+		intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);
+		intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index f6be1cd5d270..d68876fe782c 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -739,7 +739,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state,
 
 	intel_dsi_wait_panel_power_cycle(intel_dsi);
 
-	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
+	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
 
 	/*
 	 * The BIOS may leave the PLL in a wonky state where it doesn't
-- 
2.39.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* RE: [PATCH 07/14] drm/i915/display: convert intel_set_{cpu, pch}_fifo_underrun_reporting() to intel_display
  2025-02-12 16:36 ` [PATCH 07/14] drm/i915/display: convert intel_set_{cpu, pch}_fifo_underrun_reporting() to intel_display Jani Nikula
@ 2025-02-13  9:03   ` Kandpal, Suraj
  0 siblings, 0 replies; 35+ messages in thread
From: Kandpal, Suraj @ 2025-02-13  9:03 UTC (permalink / raw)
  To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org
  Cc: Nikula, Jani



> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Wednesday, February 12, 2025 10:07 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 07/14] drm/i915/display: convert intel_set_{cpu,
> pch}_fifo_underrun_reporting() to intel_display
> 
> Going forward, struct intel_display is the main display device data pointer.
> Convert intel_set_cpu_fifo_underrun_reporting() and
> intel_set_pch_fifo_underrun_reporting() to struct intel_display, along with
> some of the call chains from there.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/g4x_dp.c         |  8 +-
>  drivers/gpu/drm/i915/display/g4x_hdmi.c       |  8 +-
>  drivers/gpu/drm/i915/display/intel_crt.c      | 17 ++--
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  3 +-
>  drivers/gpu/drm/i915/display/intel_display.c  | 43 +++++-----
>  .../drm/i915/display/intel_fifo_underrun.c    | 84 +++++++++----------
>  .../drm/i915/display/intel_fifo_underrun.h    |  7 +-
>  drivers/gpu/drm/i915/display/intel_sdvo.c     |  8 +-
>  drivers/gpu/drm/i915/display/vlv_dsi.c        |  2 +-
>  9 files changed, 89 insertions(+), 91 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 4b51a4e47f63..0cb98cb043c6 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -453,8 +453,8 @@ intel_dp_link_down(struct intel_encoder *encoder,
>  		 * We get CPU/PCH FIFO underruns on the other pipe when
>  		 * doing the workaround. Sweep them under the rug.
>  		 */
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A,
> false);
> -		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A,
> false);
> +		intel_set_cpu_fifo_underrun_reporting(display, PIPE_A,
> false);
> +		intel_set_pch_fifo_underrun_reporting(display, PIPE_A,
> false);
> 
>  		/* always enable with pattern 1 (as per spec) */
>  		intel_dp->DP &= ~(DP_PIPE_SEL_MASK |
> DP_LINK_TRAIN_MASK); @@ -468,8 +468,8 @@ intel_dp_link_down(struct
> intel_encoder *encoder,
>  		intel_de_posting_read(display, intel_dp->output_reg);
> 
>  		intel_wait_for_vblank_if_active(display, PIPE_A);
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A,
> true);
> -		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A,
> true);
> +		intel_set_cpu_fifo_underrun_reporting(display, PIPE_A,
> true);
> +		intel_set_pch_fifo_underrun_reporting(display, PIPE_A,
> true);
>  	}
> 
>  	msleep(intel_dp->pps.panel_power_down_delay);
> diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> index 1cd2e68e6ec5..089f1a4d7720 100644
> --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> @@ -407,8 +407,8 @@ static void intel_disable_hdmi(struct
> intel_atomic_state *state,
>  		 * We get CPU/PCH FIFO underruns on the other pipe when
>  		 * doing the workaround. Sweep them under the rug.
>  		 */
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A,
> false);
> -		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A,
> false);
> +		intel_set_cpu_fifo_underrun_reporting(display, PIPE_A,
> false);
> +		intel_set_pch_fifo_underrun_reporting(display, PIPE_A,
> false);
> 
>  		temp &= ~SDVO_PIPE_SEL_MASK;
>  		temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); @@ -
> 426,8 +426,8 @@ static void intel_disable_hdmi(struct intel_atomic_state
> *state,
>  		intel_de_posting_read(display, intel_hdmi->hdmi_reg);
> 
>  		intel_wait_for_vblank_if_active(display, PIPE_A);
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A,
> true);
> -		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A,
> true);
> +		intel_set_cpu_fifo_underrun_reporting(display, PIPE_A,
> true);
> +		intel_set_pch_fifo_underrun_reporting(display, PIPE_A,
> true);
>  	}
> 
>  	dig_port->set_infoframes(encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index 396846025922..8eedae1d7684 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -250,11 +250,10 @@ static void hsw_disable_crt(struct
> intel_atomic_state *state,
>  			    const struct drm_connector_state
> *old_conn_state)  {
>  	struct intel_display *display = to_intel_display(encoder);
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 
>  	drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
> 
> -	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
> +	intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
>  }
> 
>  static void hsw_post_disable_crt(struct intel_atomic_state *state, @@ -
> 264,7 +263,6 @@ static void hsw_post_disable_crt(struct intel_atomic_state
> *state,  {
>  	struct intel_display *display = to_intel_display(encoder);
>  	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 
>  	intel_crtc_vblank_off(old_crtc_state);
> 
> @@ -284,7 +282,7 @@ static void hsw_post_disable_crt(struct
> intel_atomic_state *state,
> 
>  	drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
> 
> -	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
> +	intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
>  }
> 
>  static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state, @@ -
> 293,11 +291,10 @@ static void hsw_pre_pll_enable_crt(struct
> intel_atomic_state *state,
>  				   const struct drm_connector_state
> *conn_state)  {
>  	struct intel_display *display = to_intel_display(encoder);
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 
>  	drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
> 
> -	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
> +	intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
>  }
> 
>  static void hsw_pre_enable_crt(struct intel_atomic_state *state, @@ -
> 306,13 +303,12 @@ static void hsw_pre_enable_crt(struct
> intel_atomic_state *state,
>  			       const struct drm_connector_state *conn_state)  {
>  	struct intel_display *display = to_intel_display(encoder);
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum pipe pipe = crtc->pipe;
> 
>  	drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
> 
> -	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> +	intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
> 
>  	hsw_fdi_link_train(encoder, crtc_state);
> 
> @@ -325,7 +321,6 @@ static void hsw_enable_crt(struct intel_atomic_state
> *state,
>  			   const struct drm_connector_state *conn_state)  {
>  	struct intel_display *display = to_intel_display(encoder);
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum pipe pipe = crtc->pipe;
> 
> @@ -343,8 +338,8 @@ static void hsw_enable_crt(struct intel_atomic_state
> *state,
> 
>  	intel_crtc_wait_for_next_vblank(crtc);
>  	intel_crtc_wait_for_next_vblank(crtc);
> -	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> -	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
> +	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
> +	intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
>  }
> 
>  static void intel_enable_crt(struct intel_atomic_state *state, diff --git
> a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index ce7097937d70..900e066b2478 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3013,13 +3013,14 @@ static void intel_ddi_pre_enable(struct
> intel_atomic_state *state,
>  				 const struct intel_crtc_state *crtc_state,
>  				 const struct drm_connector_state
> *conn_state)  {
> +	struct intel_display *display = to_intel_display(state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
> 
>  	drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
> 
> -	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> +	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
> 
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
>  		intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, diff --
> git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 2a8f53f06463..9bcbd52f23cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -774,6 +774,7 @@ void intel_plane_fixup_bitmasks(struct
> intel_crtc_state *crtc_state)  void intel_plane_disable_noatomic(struct
> intel_crtc *crtc,
>  				  struct intel_plane *plane)
>  {
> +	struct intel_display *display = to_intel_display(crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_crtc_state *crtc_state =
>  		to_intel_crtc_state(crtc->base.state);
> @@ -817,7 +818,7 @@ void intel_plane_disable_noatomic(struct intel_crtc
> *crtc,
>  	 * So disable underrun reporting before all the planes get disabled.
>  	 */
>  	if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe,
> false);
> +		intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe,
> false);
> 
>  	intel_plane_disable_arm(NULL, plane, crtc_state);
>  	intel_plane_initial_vblank_wait(crtc);
> @@ -1305,6 +1306,7 @@ static void intel_crtc_async_flip_disable_wa(struct
> intel_atomic_state *state,  static void intel_pre_plane_update(struct
> intel_atomic_state *state,
>  				   struct intel_crtc *crtc)
>  {
> +	struct intel_display *display = to_intel_display(state);
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  	const struct intel_crtc_state *old_crtc_state =
>  		intel_atomic_get_old_crtc_state(state, crtc); @@ -1406,7
> +1408,7 @@ static void intel_pre_plane_update(struct intel_atomic_state
> *state,
>  	 * vs. the old plane configuration.
>  	 */
>  	if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state,
> new_crtc_state))
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
> false);
> +		intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
> 
>  	/*
>  	 * WA for platforms where async address update enable bit @@ -
> 1645,6 +1647,7 @@ static void ilk_configure_cpu_transcoder(const struct
> intel_crtc_state *crtc_sta  static void ilk_crtc_enable(struct intel_atomic_state
> *state,
>  			    struct intel_crtc *crtc)
>  {
> +	struct intel_display *display = to_intel_display(crtc);
>  	const struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -
> 1663,8 +1666,8 @@ static void ilk_crtc_enable(struct intel_atomic_state
> *state,
>  	 *
>  	 * Spurious PCH underruns also occur during PCH enabling.
>  	 */
> -	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> -	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
> +	intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
> +	intel_set_pch_fifo_underrun_reporting(display, pipe, false);
> 
>  	ilk_configure_cpu_transcoder(new_crtc_state);
> 
> @@ -1712,8 +1715,8 @@ static void ilk_crtc_enable(struct
> intel_atomic_state *state,
>  		intel_crtc_wait_for_next_vblank(crtc);
>  		intel_crtc_wait_for_next_vblank(crtc);
>  	}
> -	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> -	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
> +	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
> +	intel_set_pch_fifo_underrun_reporting(display, pipe, true);
>  }
> 
>  /* Display WA #1180: WaDisableScalarClockGating: glk */ @@ -1901,9
> +1904,9 @@ void ilk_pfit_disable(const struct intel_crtc_state
> *old_crtc_state)  static void ilk_crtc_disable(struct intel_atomic_state *state,
>  			     struct intel_crtc *crtc)
>  {
> +	struct intel_display *display = to_intel_display(crtc);
>  	const struct intel_crtc_state *old_crtc_state =
>  		intel_atomic_get_old_crtc_state(state, crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
> 
>  	/*
> @@ -1911,8 +1914,8 @@ static void ilk_crtc_disable(struct
> intel_atomic_state *state,
>  	 * pipe is already disabled, but FDI RX/TX is still enabled.
>  	 * Happens at least with VGA+HDMI cloning. Suppress them.
>  	 */
> -	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> -	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
> +	intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
> +	intel_set_pch_fifo_underrun_reporting(display, pipe, false);
> 
>  	intel_encoders_disable(state, crtc);
> 
> @@ -1930,8 +1933,8 @@ static void ilk_crtc_disable(struct
> intel_atomic_state *state,
>  	if (old_crtc_state->has_pch_encoder)
>  		ilk_pch_post_disable(state, crtc);
> 
> -	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> -	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
> +	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
> +	intel_set_pch_fifo_underrun_reporting(display, pipe, true);
> 
>  	intel_disable_shared_dpll(old_crtc_state);
>  }
> @@ -2211,6 +2214,7 @@ static void i9xx_configure_cpu_transcoder(const
> struct intel_crtc_state *crtc_st  static void valleyview_crtc_enable(struct
> intel_atomic_state *state,
>  				   struct intel_crtc *crtc)
>  {
> +	struct intel_display *display = to_intel_display(crtc);
>  	const struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -
> 2233,7 +2237,7 @@ static void valleyview_crtc_enable(struct
> intel_atomic_state *state,
> 
>  	crtc->active = true;
> 
> -	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> +	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
> 
>  	intel_encoders_pre_pll_enable(state, crtc);
> 
> @@ -2259,6 +2263,7 @@ static void valleyview_crtc_enable(struct
> intel_atomic_state *state,  static void i9xx_crtc_enable(struct
> intel_atomic_state *state,
>  			     struct intel_crtc *crtc)
>  {
> +	struct intel_display *display = to_intel_display(crtc);
>  	const struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -
> 2274,7 +2279,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state
> *state,
>  	crtc->active = true;
> 
>  	if (DISPLAY_VER(dev_priv) != 2)
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> +		intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
> 
>  	intel_encoders_pre_enable(state, crtc);
> 
> @@ -2349,7 +2354,7 @@ static void i9xx_crtc_disable(struct
> intel_atomic_state *state,
>  	intel_encoders_post_pll_disable(state, crtc);
> 
>  	if (DISPLAY_VER(dev_priv) != 2)
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
> false);
> +		intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
> 
>  	if (!dev_priv->display.funcs.wm->initial_watermarks)
>  		intel_update_watermarks(dev_priv);
> @@ -7069,16 +7074,16 @@ static int intel_atomic_prepare_commit(struct
> intel_atomic_state *state)  void intel_crtc_arm_fifo_underrun(struct
> intel_crtc *crtc,
>  				  struct intel_crtc_state *crtc_state)  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct intel_display *display = to_intel_display(crtc);
> 
> -	if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe,
> true);
> +	if (DISPLAY_VER(display) != 2 || crtc_state->active_planes)
> +		intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe,
> true);
> 
>  	if (crtc_state->has_pch_encoder) {
>  		enum pipe pch_transcoder =
>  			intel_crtc_pch_transcoder(crtc);
> 
> -		intel_set_pch_fifo_underrun_reporting(dev_priv,
> pch_transcoder, true);
> +		intel_set_pch_fifo_underrun_reporting(display,
> pch_transcoder, true);
>  	}
>  }
> 
> @@ -7921,7 +7926,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
>  		 * vs. the new plane configuration.
>  		 */
>  		if (DISPLAY_VER(dev_priv) == 2 &&
> planes_enabling(old_crtc_state, new_crtc_state))
> -			intel_set_cpu_fifo_underrun_reporting(dev_priv,
> crtc->pipe, true);
> +			intel_set_cpu_fifo_underrun_reporting(display, crtc-
> >pipe, true);
> 
>  		intel_optimize_watermarks(state, crtc);
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index 18fcdbe1248a..cf70dab4881b 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -55,10 +55,9 @@
>   * The code also supports underrun detection on the PCH transcoder.
>   */
> 
> -static bool ivb_can_enable_err_int(struct drm_device *dev)
> +static bool ivb_can_enable_err_int(struct intel_display *display)
>  {
> -	struct intel_display *display = to_intel_display(dev);
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);

I think the same Nit as before can we call it i915

But LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

>  	struct intel_crtc *crtc;
>  	enum pipe pipe;
> 
> @@ -74,10 +73,9 @@ static bool ivb_can_enable_err_int(struct drm_device
> *dev)
>  	return true;
>  }
> 
> -static bool cpt_can_enable_serr_int(struct drm_device *dev)
> +static bool cpt_can_enable_serr_int(struct intel_display *display)
>  {
> -	struct intel_display *display = to_intel_display(dev);
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	enum pipe pipe;
>  	struct intel_crtc *crtc;
> 
> @@ -113,11 +111,11 @@ static void i9xx_check_fifo_underruns(struct
> intel_crtc *crtc)
>  	drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc-
> >pipe));  }
> 
> -static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
> +static void i9xx_set_fifo_underrun_reporting(struct intel_display
> +*display,
>  					     enum pipe pipe,
>  					     bool enable, bool old)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	i915_reg_t reg = PIPESTAT(dev_priv, pipe);
> 
>  	lockdep_assert_held(&dev_priv->irq_lock);
> @@ -135,10 +133,10 @@ static void
> i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
>  	}
>  }
> 
> -static void ilk_set_fifo_underrun_reporting(struct drm_device *dev,
> +static void ilk_set_fifo_underrun_reporting(struct intel_display
> +*display,
>  					    enum pipe pipe, bool enable)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	u32 bit = (pipe == PIPE_A) ?
>  		DE_PIPEA_FIFO_UNDERRUN : DE_PIPEB_FIFO_UNDERRUN;
> 
> @@ -167,16 +165,16 @@ static void ivb_check_fifo_underruns(struct
> intel_crtc *crtc)
>  	drm_err(&dev_priv->drm, "fifo underrun on pipe %c\n",
> pipe_name(pipe));  }
> 
> -static void ivb_set_fifo_underrun_reporting(struct drm_device *dev,
> +static void ivb_set_fifo_underrun_reporting(struct intel_display
> +*display,
>  					    enum pipe pipe, bool enable,
>  					    bool old)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	if (enable) {
>  		intel_de_write(dev_priv, GEN7_ERR_INT,
>  			       ERR_INT_FIFO_UNDERRUN(pipe));
> 
> -		if (!ivb_can_enable_err_int(dev))
> +		if (!ivb_can_enable_err_int(display))
>  			return;
> 
>  		ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB); @@ -
> 192,10 +190,10 @@ static void ivb_set_fifo_underrun_reporting(struct
> drm_device *dev,
>  	}
>  }
> 
> -static void bdw_set_fifo_underrun_reporting(struct drm_device *dev,
> +static void bdw_set_fifo_underrun_reporting(struct intel_display
> +*display,
>  					    enum pipe pipe, bool enable)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
> 
>  	if (enable)
>  		bdw_enable_pipe_irq(dev_priv, pipe,
> GEN8_PIPE_FIFO_UNDERRUN); @@ -203,11 +201,11 @@ static void
> bdw_set_fifo_underrun_reporting(struct drm_device *dev,
>  		bdw_disable_pipe_irq(dev_priv, pipe,
> GEN8_PIPE_FIFO_UNDERRUN);  }
> 
> -static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
> +static void ibx_set_fifo_underrun_reporting(struct intel_display
> +*display,
>  					    enum pipe pch_transcoder,
>  					    bool enable)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	u32 bit = (pch_transcoder == PIPE_A) ?
>  		SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
> 
> @@ -238,17 +236,17 @@ static void cpt_check_pch_fifo_underruns(struct
> intel_crtc *crtc)
>  		pipe_name(pch_transcoder));
>  }
> 
> -static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
> +static void cpt_set_fifo_underrun_reporting(struct intel_display
> +*display,
>  					    enum pipe pch_transcoder,
>  					    bool enable, bool old)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
> 
>  	if (enable) {
>  		intel_de_write(dev_priv, SERR_INT,
> 
> SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
> 
> -		if (!cpt_can_enable_serr_int(dev))
> +		if (!cpt_can_enable_serr_int(display))
>  			return;
> 
>  		ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
> @@ -264,11 +262,10 @@ static void cpt_set_fifo_underrun_reporting(struct
> drm_device *dev,
>  	}
>  }
> 
> -static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device
> *dev,
> +static bool __intel_set_cpu_fifo_underrun_reporting(struct
> +intel_display *display,
>  						    enum pipe pipe, bool
> enable)
>  {
> -	struct intel_display *display = to_intel_display(dev);
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
>  	bool old;
> 
> @@ -277,21 +274,21 @@ static bool
> __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
>  	old = !crtc->cpu_fifo_underrun_disabled;
>  	crtc->cpu_fifo_underrun_disabled = !enable;
> 
> -	if (HAS_GMCH(dev_priv))
> -		i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
> -	else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
> -		ilk_set_fifo_underrun_reporting(dev, pipe, enable);
> -	else if (DISPLAY_VER(dev_priv) == 7)
> -		ivb_set_fifo_underrun_reporting(dev, pipe, enable, old);
> -	else if (DISPLAY_VER(dev_priv) >= 8)
> -		bdw_set_fifo_underrun_reporting(dev, pipe, enable);
> +	if (HAS_GMCH(display))
> +		i9xx_set_fifo_underrun_reporting(display, pipe, enable, old);
> +	else if (display->platform.ironlake || display->platform.sandybridge)
> +		ilk_set_fifo_underrun_reporting(display, pipe, enable);
> +	else if (DISPLAY_VER(display) == 7)
> +		ivb_set_fifo_underrun_reporting(display, pipe, enable, old);
> +	else if (DISPLAY_VER(display) >= 8)
> +		bdw_set_fifo_underrun_reporting(display, pipe, enable);
> 
>  	return old;
>  }
> 
>  /**
>   * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrun reporting
> state
> - * @dev_priv: i915 device instance
> + * @display: display device instance
>   * @pipe: (CPU) pipe to set state for
>   * @enable: whether underruns should be reported or not
>   *
> @@ -305,15 +302,15 @@ static bool
> __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
>   *
>   * Returns the previous state of underrun reporting.
>   */
> -bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
> *dev_priv,
> +bool intel_set_cpu_fifo_underrun_reporting(struct intel_display
> +*display,
>  					   enum pipe pipe, bool enable)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	unsigned long flags;
>  	bool ret;
> 
>  	spin_lock_irqsave(&dev_priv->irq_lock, flags);
> -	ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm,
> pipe,
> -						      enable);
> +	ret = __intel_set_cpu_fifo_underrun_reporting(display, pipe,
> enable);
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
> 
>  	return ret;
> @@ -321,7 +318,7 @@ bool intel_set_cpu_fifo_underrun_reporting(struct
> drm_i915_private *dev_priv,
> 
>  /**
>   * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting
> state
> - * @dev_priv: i915 device instance
> + * @display: display device instance
>   * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
>   * @enable: whether underruns should be reported or not
>   *
> @@ -333,13 +330,12 @@ bool
> intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
>   *
>   * Returns the previous state of underrun reporting.
>   */
> -bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
> *dev_priv,
> +bool intel_set_pch_fifo_underrun_reporting(struct intel_display
> +*display,
>  					   enum pipe pch_transcoder,
>  					   bool enable)
>  {
> -	struct intel_display *display = &dev_priv->display;
> -	struct intel_crtc *crtc =
> -		intel_crtc_for_pipe(display, pch_transcoder);
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
> +	struct intel_crtc *crtc = intel_crtc_for_pipe(display,
> +pch_transcoder);
>  	unsigned long flags;
>  	bool old;
> 
> @@ -358,11 +354,11 @@ bool
> intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
>  	crtc->pch_fifo_underrun_disabled = !enable;
> 
>  	if (HAS_PCH_IBX(dev_priv))
> -		ibx_set_fifo_underrun_reporting(&dev_priv->drm,
> +		ibx_set_fifo_underrun_reporting(display,
>  						pch_transcoder,
>  						enable);
>  	else
> -		cpt_set_fifo_underrun_reporting(&dev_priv->drm,
> +		cpt_set_fifo_underrun_reporting(display,
>  						pch_transcoder,
>  						enable, old);
> 
> @@ -394,7 +390,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct
> drm_i915_private *dev_priv,
>  	    crtc->cpu_fifo_underrun_disabled)
>  		return;
> 
> -	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
> +	if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) {
>  		trace_intel_cpu_fifo_underrun(display, pipe);
> 
>  		drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n",
> pipe_name(pipe)); @@ -417,7 +413,7 @@ void
> intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,  {
>  	struct intel_display *display = &dev_priv->display;
> 
> -	if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder,
> +	if (intel_set_pch_fifo_underrun_reporting(display, pch_transcoder,
>  						  false)) {
>  		trace_intel_pch_fifo_underrun(display, pch_transcoder);
>  		drm_err(&dev_priv->drm, "PCH transcoder %c FIFO
> underrun\n", diff --git
> a/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
> b/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
> index b00d8abebcf9..8302080c2313 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
> @@ -8,15 +8,16 @@
> 
>  #include <linux/types.h>
> 
> +enum pipe;
>  struct drm_i915_private;
>  struct intel_crtc;
> -enum pipe;
> +struct intel_display;
> 
>  void intel_init_fifo_underrun_reporting(struct drm_i915_private *i915,
>  					struct intel_crtc *crtc, bool enable); -
> bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
> *dev_priv,
> +bool intel_set_cpu_fifo_underrun_reporting(struct intel_display
> +*display,
>  					   enum pipe pipe, bool enable);
> -bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
> *dev_priv,
> +bool intel_set_pch_fifo_underrun_reporting(struct intel_display
> +*display,
>  					   enum pipe pch_transcoder,
>  					   bool enable);
>  void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
> *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c
> b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index 0c3aa2e7b78b..46203d796fcc 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -1864,8 +1864,8 @@ static void intel_disable_sdvo(struct
> intel_atomic_state *state,
>  		 * We get CPU/PCH FIFO underruns on the other pipe when
>  		 * doing the workaround. Sweep them under the rug.
>  		 */
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A,
> false);
> -		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A,
> false);
> +		intel_set_cpu_fifo_underrun_reporting(display, PIPE_A,
> false);
> +		intel_set_pch_fifo_underrun_reporting(display, PIPE_A,
> false);
> 
>  		temp &= ~SDVO_PIPE_SEL_MASK;
>  		temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); @@ -
> 1875,8 +1875,8 @@ static void intel_disable_sdvo(struct intel_atomic_state
> *state,
>  		intel_sdvo_write_sdvox(intel_sdvo, temp);
> 
>  		intel_wait_for_vblank_if_active(display, PIPE_A);
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A,
> true);
> -		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A,
> true);
> +		intel_set_cpu_fifo_underrun_reporting(display, PIPE_A,
> true);
> +		intel_set_pch_fifo_underrun_reporting(display, PIPE_A,
> true);
>  	}
>  }
> 
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
> b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index f6be1cd5d270..d68876fe782c 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -739,7 +739,7 @@ static void intel_dsi_pre_enable(struct
> intel_atomic_state *state,
> 
>  	intel_dsi_wait_panel_power_cycle(intel_dsi);
> 
> -	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> +	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
> 
>  	/*
>  	 * The BIOS may leave the PLL in a wonky state where it doesn't
> --
> 2.39.5


^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 08/14] drm/i915/sdvo: convert intel_sdvo.[ch] to struct intel_display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
                   ` (6 preceding siblings ...)
  2025-02-12 16:36 ` [PATCH 07/14] drm/i915/display: convert intel_set_{cpu, pch}_fifo_underrun_reporting() to intel_display Jani Nikula
@ 2025-02-12 16:36 ` Jani Nikula
  2025-02-13  9:13   ` Kandpal, Suraj
  2025-02-12 16:36 ` [PATCH 09/14] drm/i915/display: convert intel_cpu_transcoder_mode_valid() to intel_display Jani Nikula
                   ` (10 subsequent siblings)
  18 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2025-02-12 16:36 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula

Going forward, struct intel_display is the main display device data
pointer. Convert as much as possible of intel_sdvo.[ch] to struct
intel_display.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_hdmi.c       |   3 +-
 drivers/gpu/drm/i915/display/intel_display.c  |   6 +-
 .../gpu/drm/i915/display/intel_pch_display.c  |   2 +-
 drivers/gpu/drm/i915/display/intel_sdvo.c     | 281 +++++++++---------
 drivers/gpu/drm/i915/display/intel_sdvo.h     |  10 +-
 5 files changed, 150 insertions(+), 152 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 089f1a4d7720..5c5eb3d621c8 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -67,7 +67,6 @@ static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 				    enum pipe *pipe)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 	intel_wakeref_t wakeref;
 	bool ret;
@@ -77,7 +76,7 @@ static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 	if (!wakeref)
 		return false;
 
-	ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
+	ret = intel_sdvo_port_enabled(display, intel_hdmi->hdmi_reg, pipe);
 
 	intel_display_power_put(display, encoder->power_domain, wakeref);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9bcbd52f23cf..e1186f46088d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8236,7 +8236,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 
 		if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
 			/* PCH SDVOB multiplex with HDMIB */
-			found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
+			found = intel_sdvo_init(display, PCH_SDVOB, PORT_B);
 			if (!found)
 				g4x_hdmi_init(display, PCH_HDMIB, PORT_B);
 			if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
@@ -8315,7 +8315,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 
 		if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
 			drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
-			found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
+			found = intel_sdvo_init(display, GEN3_SDVOB, PORT_B);
 			if (!found && IS_G4X(dev_priv)) {
 				drm_dbg_kms(&dev_priv->drm,
 					    "probing HDMI on SDVOB\n");
@@ -8330,7 +8330,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
 
 		if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
 			drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
-			found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
+			found = intel_sdvo_init(display, GEN3_SDVOC, PORT_C);
 		}
 
 		if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 98a6b57ac956..1abe0a784570 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -65,7 +65,7 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
 	enum pipe port_pipe;
 	bool state;
 
-	state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
+	state = intel_sdvo_port_enabled(display, hdmi_reg, &port_pipe);
 
 	INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,
 				 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 46203d796fcc..1ae766212e8a 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -213,29 +213,29 @@ intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  */
 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
 {
-	struct drm_device *dev = intel_sdvo->base.base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	u32 bval = val, cval = val;
 	int i;
 
 	if (HAS_PCH_SPLIT(dev_priv)) {
-		intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
-		intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
+		intel_de_write(display, intel_sdvo->sdvo_reg, val);
+		intel_de_posting_read(display, intel_sdvo->sdvo_reg);
 		/*
 		 * HW workaround, need to write this twice for issue
 		 * that may result in first write getting masked.
 		 */
 		if (HAS_PCH_IBX(dev_priv)) {
-			intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
-			intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
+			intel_de_write(display, intel_sdvo->sdvo_reg, val);
+			intel_de_posting_read(display, intel_sdvo->sdvo_reg);
 		}
 		return;
 	}
 
 	if (intel_sdvo->base.port == PORT_B)
-		cval = intel_de_read(dev_priv, GEN3_SDVOC);
+		cval = intel_de_read(display, GEN3_SDVOC);
 	else
-		bval = intel_de_read(dev_priv, GEN3_SDVOB);
+		bval = intel_de_read(display, GEN3_SDVOB);
 
 	/*
 	 * Write the registers twice for luck. Sometimes,
@@ -243,17 +243,17 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
 	 * The BIOS does this too. Yay, magic
 	 */
 	for (i = 0; i < 2; i++) {
-		intel_de_write(dev_priv, GEN3_SDVOB, bval);
-		intel_de_posting_read(dev_priv, GEN3_SDVOB);
+		intel_de_write(display, GEN3_SDVOB, bval);
+		intel_de_posting_read(display, GEN3_SDVOB);
 
-		intel_de_write(dev_priv, GEN3_SDVOC, cval);
-		intel_de_posting_read(dev_priv, GEN3_SDVOC);
+		intel_de_write(display, GEN3_SDVOC, cval);
+		intel_de_posting_read(display, GEN3_SDVOC);
 	}
 }
 
 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
 {
-	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	struct i2c_msg msgs[] = {
 		{
 			.addr = intel_sdvo->target_addr,
@@ -273,7 +273,7 @@ static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
 	if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
 		return true;
 
-	drm_dbg_kms(&i915->drm, "i2c transfer returned %d\n", ret);
+	drm_dbg_kms(display->drm, "i2c transfer returned %d\n", ret);
 	return false;
 }
 
@@ -415,7 +415,7 @@ static const char *sdvo_cmd_name(u8 cmd)
 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
 				   const void *args, int args_len)
 {
-	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	const char *cmd_name;
 	int i, pos = 0;
 	char buffer[64];
@@ -436,10 +436,10 @@ static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
 	else
 		BUF_PRINT("(%02X)", cmd);
 
-	drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
+	drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1);
 #undef BUF_PRINT
 
-	drm_dbg_kms(&dev_priv->drm, "%s: W: %02X %s\n", SDVO_NAME(intel_sdvo),
+	drm_dbg_kms(display->drm, "%s: W: %02X %s\n", SDVO_NAME(intel_sdvo),
 		    cmd, buffer);
 }
 
@@ -465,7 +465,7 @@ static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
 				   const void *args, int args_len,
 				   bool unlocked)
 {
-	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	u8 *buf, status;
 	struct i2c_msg *msgs;
 	int i, ret = true;
@@ -515,13 +515,13 @@ static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
 	else
 		ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
 	if (ret < 0) {
-		drm_dbg_kms(&i915->drm, "I2c transfer returned %d\n", ret);
+		drm_dbg_kms(display->drm, "I2c transfer returned %d\n", ret);
 		ret = false;
 		goto out;
 	}
 	if (ret != i+3) {
 		/* failure in I2C transfer */
-		drm_dbg_kms(&i915->drm, "I2c transfer returned %d/%d\n", ret, i+3);
+		drm_dbg_kms(display->drm, "I2c transfer returned %d/%d\n", ret, i + 3);
 		ret = false;
 	}
 
@@ -540,7 +540,7 @@ static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
 				     void *response, int response_len)
 {
-	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	const char *cmd_status;
 	u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
 	u8 status;
@@ -605,15 +605,15 @@ static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
 		BUF_PRINT(" %02X", ((u8 *)response)[i]);
 	}
 
-	drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
+	drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1);
 #undef BUF_PRINT
 
-	drm_dbg_kms(&dev_priv->drm, "%s: R: %s\n",
+	drm_dbg_kms(display->drm, "%s: R: %s\n",
 		    SDVO_NAME(intel_sdvo), buffer);
 	return true;
 
 log_fail:
-	drm_dbg_kms(&dev_priv->drm, "%s: R: ... failed %s\n",
+	drm_dbg_kms(display->drm, "%s: R: ... failed %s\n",
 		    SDVO_NAME(intel_sdvo), buffer);
 	return false;
 }
@@ -1009,7 +1009,7 @@ static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
 				       unsigned int if_index, u8 tx_rate,
 				       const u8 *data, unsigned int length)
 {
-	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	u8 set_buf_index[2] = { if_index, 0 };
 	u8 hbuf_size, tmp[8];
 	int i;
@@ -1022,7 +1022,7 @@ static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
 	if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
 		return false;
 
-	drm_dbg_kms(&i915->drm,
+	drm_dbg_kms(display->drm,
 		    "writing sdvo hbuf: %i, length %u, hbuf_size: %i\n",
 		    if_index, length, hbuf_size);
 
@@ -1049,7 +1049,7 @@ static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo,
 					 unsigned int if_index,
 					 u8 *data, unsigned int length)
 {
-	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	u8 set_buf_index[2] = { if_index, 0 };
 	u8 hbuf_size, tx_rate, av_split;
 	int i;
@@ -1079,7 +1079,7 @@ static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo,
 	if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
 		return false;
 
-	drm_dbg_kms(&i915->drm,
+	drm_dbg_kms(display->drm,
 		    "reading sdvo hbuf: %i, length %u, hbuf_size: %i\n",
 		    if_index, length, hbuf_size);
 
@@ -1100,7 +1100,7 @@ static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
 					     struct intel_crtc_state *crtc_state,
 					     struct drm_connector_state *conn_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
@@ -1126,7 +1126,7 @@ static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
 					   HDMI_QUANTIZATION_RANGE_FULL);
 
 	ret = hdmi_avi_infoframe_check(frame);
-	if (drm_WARN_ON(&dev_priv->drm, ret))
+	if (drm_WARN_ON(display->drm, ret))
 		return false;
 
 	return true;
@@ -1135,7 +1135,7 @@ static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
 					 const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
 	const union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
 	ssize_t len;
@@ -1144,12 +1144,12 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
 	     intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0)
 		return true;
 
-	if (drm_WARN_ON(&dev_priv->drm,
+	if (drm_WARN_ON(display->drm,
 			frame->any.type != HDMI_INFOFRAME_TYPE_AVI))
 		return false;
 
 	len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data));
-	if (drm_WARN_ON(&dev_priv->drm, len < 0))
+	if (drm_WARN_ON(display->drm, len < 0))
 		return false;
 
 	return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
@@ -1160,7 +1160,7 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
 static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo,
 					 struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
 	union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
 	ssize_t len;
@@ -1172,7 +1172,7 @@ static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo,
 	len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
 					sdvo_data, sizeof(sdvo_data));
 	if (len < 0) {
-		drm_dbg_kms(&i915->drm, "failed to read AVI infoframe\n");
+		drm_dbg_kms(display->drm, "failed to read AVI infoframe\n");
 		return;
 	} else if (len == 0) {
 		return;
@@ -1183,12 +1183,12 @@ static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo,
 
 	ret = hdmi_infoframe_unpack(frame, sdvo_data, len);
 	if (ret) {
-		drm_dbg_kms(&i915->drm, "Failed to unpack AVI infoframe\n");
+		drm_dbg_kms(display->drm, "Failed to unpack AVI infoframe\n");
 		return;
 	}
 
 	if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI)
-		drm_dbg_kms(&i915->drm,
+		drm_dbg_kms(display->drm,
 			    "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
 			    frame->any.type, HDMI_INFOFRAME_TYPE_AVI);
 }
@@ -1196,7 +1196,7 @@ static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo,
 static void intel_sdvo_get_eld(struct intel_sdvo *intel_sdvo,
 			       struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	ssize_t len;
 	u8 val;
 
@@ -1212,7 +1212,7 @@ static void intel_sdvo_get_eld(struct intel_sdvo *intel_sdvo,
 	len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD,
 					crtc_state->eld, sizeof(crtc_state->eld));
 	if (len < 0)
-		drm_dbg_kms(&i915->drm, "failed to read ELD\n");
+		drm_dbg_kms(display->drm, "failed to read ELD\n");
 }
 
 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
@@ -1282,7 +1282,7 @@ intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
 
 static int i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
 {
-	struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev);
+	struct intel_display *display = to_intel_display(pipe_config);
 	unsigned int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
 	struct dpll *clock = &pipe_config->dpll;
 
@@ -1303,7 +1303,7 @@ static int i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
 		clock->m1 = 12;
 		clock->m2 = 8;
 	} else {
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(display->drm,
 			    "SDVO TV clock out of range: %i\n", dotclock);
 		return -EINVAL;
 	}
@@ -1359,6 +1359,7 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
 				     struct intel_crtc_state *pipe_config,
 				     struct drm_connector_state *conn_state)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
 	struct intel_sdvo_connector *intel_sdvo_connector =
@@ -1366,13 +1367,13 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	struct drm_display_mode *mode = &pipe_config->hw.mode;
 
-	if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) {
+	if (HAS_PCH_SPLIT(i915)) {
 		pipe_config->has_pch_encoder = true;
 		if (!intel_fdi_compute_pipe_bpp(pipe_config))
 			return -EINVAL;
 	}
 
-	drm_dbg_kms(&i915->drm, "forcing bpc to 8 for SDVO\n");
+	drm_dbg_kms(display->drm, "forcing bpc to 8 for SDVO\n");
 	/* FIXME: Don't increase pipe_bpp */
 	pipe_config->pipe_bpp = 8*3;
 	pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
@@ -1451,7 +1452,7 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
 
 	if (!intel_sdvo_compute_avi_infoframe(intel_sdvo,
 					      pipe_config, conn_state)) {
-		drm_dbg_kms(&i915->drm, "bad AVI infoframe\n");
+		drm_dbg_kms(display->drm, "bad AVI infoframe\n");
 		return -EINVAL;
 	}
 
@@ -1525,6 +1526,7 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state,
 				  const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state)
 {
+	struct intel_display *display = to_intel_display(intel_encoder);
 	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
@@ -1570,7 +1572,7 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state,
 		intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
 	}
 	if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
-		drm_info(&dev_priv->drm,
+		drm_info(display->drm,
 			 "Setting output timings on %s failed\n",
 			 SDVO_NAME(intel_sdvo));
 
@@ -1600,13 +1602,13 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state,
 	if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector))
 		input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
 	if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
-		drm_info(&dev_priv->drm,
+		drm_info(display->drm,
 			 "Setting input timings on %s failed\n",
 			 SDVO_NAME(intel_sdvo));
 
 	switch (crtc_state->pixel_multiplier) {
 	default:
-		drm_WARN(&dev_priv->drm, 1,
+		drm_WARN(display->drm, 1,
 			 "unknown pixel multiplier specified\n");
 		fallthrough;
 	case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
@@ -1617,14 +1619,14 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state,
 		return;
 
 	/* Set the SDVO control regs. */
-	if (DISPLAY_VER(dev_priv) >= 4) {
+	if (DISPLAY_VER(display) >= 4) {
 		/* The real mode polarity is set by the SDVO commands, using
 		 * struct intel_sdvo_dtd. */
 		sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
-		if (DISPLAY_VER(dev_priv) < 5)
+		if (DISPLAY_VER(display) < 5)
 			sdvox |= SDVO_BORDER_ENABLE;
 	} else {
-		sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
+		sdvox = intel_de_read(display, intel_sdvo->sdvo_reg);
 		if (intel_sdvo->base.port == PORT_B)
 			sdvox &= SDVOB_PRESERVE_MASK;
 		else
@@ -1637,10 +1639,10 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state,
 	else
 		sdvox |= SDVO_PIPE_SEL(crtc->pipe);
 
-	if (DISPLAY_VER(dev_priv) >= 4) {
+	if (DISPLAY_VER(display) >= 4) {
 		/* done in crtc_mode_set as the dpll_md reg must be written early */
-	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
-		   IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
+	} else if (display->platform.i945g || display->platform.i945gm ||
+		   display->platform.g33 || display->platform.pineview) {
 		/* done in crtc_mode_set as it lives inside the dpll register */
 	} else {
 		sdvox |= (crtc_state->pixel_multiplier - 1)
@@ -1648,7 +1650,7 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state,
 	}
 
 	if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
-	    DISPLAY_VER(dev_priv) < 5)
+	    DISPLAY_VER(display) < 5)
 		sdvox |= SDVO_STALL_SELECT;
 	intel_sdvo_write_sdvox(intel_sdvo, sdvox);
 }
@@ -1665,17 +1667,18 @@ static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
 	return active_outputs & intel_sdvo_connector->output_flag;
 }
 
-bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
+bool intel_sdvo_port_enabled(struct intel_display *display,
 			     i915_reg_t sdvo_reg, enum pipe *pipe)
 {
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	u32 val;
 
-	val = intel_de_read(dev_priv, sdvo_reg);
+	val = intel_de_read(display, sdvo_reg);
 
 	/* asserts want to know the pipe even if the port is disabled */
 	if (HAS_PCH_CPT(dev_priv))
 		*pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT;
-	else if (IS_CHERRYVIEW(dev_priv))
+	else if (display->platform.cherryview)
 		*pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV;
 	else
 		*pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT;
@@ -1686,14 +1689,14 @@ bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
 				    enum pipe *pipe)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
 	u16 active_outputs = 0;
 	bool ret;
 
 	intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
 
-	ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe);
+	ret = intel_sdvo_port_enabled(display, intel_sdvo->sdvo_reg, pipe);
 
 	return ret || active_outputs;
 }
@@ -1701,8 +1704,7 @@ static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
 static void intel_sdvo_get_config(struct intel_encoder *encoder,
 				  struct intel_crtc_state *pipe_config)
 {
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
 	struct intel_sdvo_dtd dtd;
 	int encoder_pixel_multiplier = 0;
@@ -1713,7 +1715,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
 
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO);
 
-	sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
+	sdvox = intel_de_read(display, intel_sdvo->sdvo_reg);
 
 	ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
 	if (!ret) {
@@ -1721,7 +1723,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
 		 * Some sdvo encoders are not spec compliant and don't
 		 * implement the mandatory get_timings function.
 		 */
-		drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n");
+		drm_dbg_kms(display->drm, "failed to retrieve SDVO DTD\n");
 		pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
 	} else {
 		if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
@@ -1744,7 +1746,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
 	 * encoder->get_config we so already have a valid pixel multiplier on all
 	 * other platforms.
 	 */
-	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
+	if (display->platform.i915g || display->platform.i915gm) {
 		pipe_config->pixel_multiplier =
 			((sdvox & SDVO_PORT_MULTIPLY_MASK)
 			 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
@@ -1773,7 +1775,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
 		}
 	}
 
-	drm_WARN(dev,
+	drm_WARN(display->drm,
 		 encoder_pixel_multiplier != pipe_config->pixel_multiplier,
 		 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
 		 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
@@ -1849,7 +1851,7 @@ static void intel_disable_sdvo(struct intel_atomic_state *state,
 		intel_sdvo_set_encoder_power_state(intel_sdvo,
 						   DRM_MODE_DPMS_OFF);
 
-	temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
+	temp = intel_de_read(display, intel_sdvo->sdvo_reg);
 
 	temp &= ~SDVO_ENABLE;
 	intel_sdvo_write_sdvox(intel_sdvo, temp);
@@ -1900,8 +1902,7 @@ static void intel_enable_sdvo(struct intel_atomic_state *state,
 			      const struct intel_crtc_state *pipe_config,
 			      const struct drm_connector_state *conn_state)
 {
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
 	struct intel_sdvo_connector *intel_sdvo_connector =
 		to_intel_sdvo_connector(conn_state->connector);
@@ -1911,7 +1912,7 @@ static void intel_enable_sdvo(struct intel_atomic_state *state,
 	int i;
 	bool success;
 
-	temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
+	temp = intel_de_read(display, intel_sdvo->sdvo_reg);
 	temp |= SDVO_ENABLE;
 	intel_sdvo_write_sdvox(intel_sdvo, temp);
 
@@ -1926,7 +1927,7 @@ static void intel_enable_sdvo(struct intel_atomic_state *state,
 	 * a given it the status is a success, we succeeded.
 	 */
 	if (success && !input1) {
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(display->drm,
 			    "First %s output reported failure to sync\n",
 			    SDVO_NAME(intel_sdvo));
 	}
@@ -1941,12 +1942,13 @@ static enum drm_mode_status
 intel_sdvo_mode_valid(struct drm_connector *connector,
 		      const struct drm_display_mode *mode)
 {
+	struct intel_display *display = to_intel_display(connector->dev);
 	struct drm_i915_private *i915 = to_i915(connector->dev);
 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
 	struct intel_sdvo_connector *intel_sdvo_connector =
 		to_intel_sdvo_connector(connector);
 	bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state);
-	int max_dotclk = i915->display.cdclk.max_dotclk_freq;
+	int max_dotclk = display->cdclk.max_dotclk_freq;
 	enum drm_mode_status status;
 	int clock = mode->clock;
 
@@ -1982,14 +1984,15 @@ intel_sdvo_mode_valid(struct drm_connector *connector,
 
 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
 {
-	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
+
 	BUILD_BUG_ON(sizeof(*caps) != 8);
 	if (!intel_sdvo_get_value(intel_sdvo,
 				  SDVO_CMD_GET_DEVICE_CAPS,
 				  caps, sizeof(*caps)))
 		return false;
 
-	drm_dbg_kms(&i915->drm, "SDVO capabilities:\n"
+	drm_dbg_kms(display->drm, "SDVO capabilities:\n"
 		    "  vendor_id: %d\n"
 		    "  device_id: %d\n"
 		    "  device_rev_id: %d\n"
@@ -2031,17 +2034,17 @@ static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo)
 
 static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
 {
-	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	u16 hotplug;
 
-	if (!I915_HAS_HOTPLUG(dev_priv))
+	if (!I915_HAS_HOTPLUG(display))
 		return 0;
 
 	/*
 	 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
 	 * on the line.
 	 */
-	if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
+	if (display->platform.i945g || display->platform.i945gm)
 		return 0;
 
 	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
@@ -2138,13 +2141,12 @@ static enum drm_connector_status
 intel_sdvo_detect(struct drm_connector *connector, bool force)
 {
 	struct intel_display *display = to_intel_display(connector->dev);
-	struct drm_i915_private *i915 = to_i915(connector->dev);
 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
 	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
 	enum drm_connector_status ret;
 	u16 response;
 
-	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
+	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
 		    connector->base.id, connector->name);
 
 	if (!intel_display_device_enabled(display))
@@ -2162,7 +2164,7 @@ intel_sdvo_detect(struct drm_connector *connector, bool force)
 				  &response, 2))
 		return connector_status_unknown;
 
-	drm_dbg_kms(&i915->drm, "SDVO response %d %d [%x]\n",
+	drm_dbg_kms(display->drm, "SDVO response %d %d [%x]\n",
 		    response & 0xff, response >> 8,
 		    intel_sdvo_connector->output_flag);
 
@@ -2301,7 +2303,6 @@ static int intel_sdvo_get_tv_modes(struct drm_connector *connector)
 {
 	struct intel_display *display = to_intel_display(connector->dev);
 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
-	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
 	struct intel_sdvo_connector *intel_sdvo_connector =
 		to_intel_sdvo_connector(connector);
 	const struct drm_connector_state *conn_state = connector->state;
@@ -2310,7 +2311,7 @@ static int intel_sdvo_get_tv_modes(struct drm_connector *connector)
 	int num_modes = 0;
 	int i;
 
-	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
+	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
 		    connector->base.id, connector->name);
 
 	if (!intel_display_driver_check_access(display))
@@ -2352,9 +2353,9 @@ static int intel_sdvo_get_tv_modes(struct drm_connector *connector)
 
 static int intel_sdvo_get_lvds_modes(struct drm_connector *connector)
 {
-	struct drm_i915_private *dev_priv = to_i915(connector->dev);
+	struct intel_display *display = to_intel_display(connector->dev);
 
-	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
+	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
 		    connector->base.id, connector->name);
 
 	return intel_panel_get_modes(to_intel_connector(connector));
@@ -2618,14 +2619,14 @@ static struct intel_sdvo_ddc *
 intel_sdvo_select_ddc_bus(struct intel_sdvo *sdvo,
 			  struct intel_sdvo_connector *connector)
 {
-	struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&sdvo->base);
 	const struct sdvo_device_mapping *mapping;
 	int ddc_bus;
 
 	if (sdvo->base.port == PORT_B)
-		mapping = &dev_priv->display.vbt.sdvo_mappings[0];
+		mapping = &display->vbt.sdvo_mappings[0];
 	else
-		mapping = &dev_priv->display.vbt.sdvo_mappings[1];
+		mapping = &display->vbt.sdvo_mappings[1];
 
 	if (mapping->initialized)
 		ddc_bus = (mapping->ddc_pin & 0xf0) >> 4;
@@ -2642,14 +2643,13 @@ static void
 intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
 {
 	struct intel_display *display = to_intel_display(&sdvo->base);
-	struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
 	const struct sdvo_device_mapping *mapping;
 	u8 pin;
 
 	if (sdvo->base.port == PORT_B)
-		mapping = &dev_priv->display.vbt.sdvo_mappings[0];
+		mapping = &display->vbt.sdvo_mappings[0];
 	else
-		mapping = &dev_priv->display.vbt.sdvo_mappings[1];
+		mapping = &display->vbt.sdvo_mappings[1];
 
 	if (mapping->initialized &&
 	    intel_gmbus_is_valid_pin(display, mapping->i2c_pin))
@@ -2657,7 +2657,7 @@ intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
 	else
 		pin = GMBUS_PIN_DPB;
 
-	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] I2C pin %d, target addr 0x%x\n",
+	drm_dbg_kms(display->drm, "[ENCODER:%d:%s] I2C pin %d, target addr 0x%x\n",
 		    sdvo->base.base.base.id, sdvo->base.base.name,
 		    pin, sdvo->target_addr);
 
@@ -2687,15 +2687,15 @@ intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo)
 static u8
 intel_sdvo_get_target_addr(struct intel_sdvo *sdvo)
 {
-	struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&sdvo->base);
 	const struct sdvo_device_mapping *my_mapping, *other_mapping;
 
 	if (sdvo->base.port == PORT_B) {
-		my_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
-		other_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
+		my_mapping = &display->vbt.sdvo_mappings[0];
+		other_mapping = &display->vbt.sdvo_mappings[1];
 	} else {
-		my_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
-		other_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
+		my_mapping = &display->vbt.sdvo_mappings[1];
+		other_mapping = &display->vbt.sdvo_mappings[0];
 	}
 
 	/* If the BIOS described our SDVO device, take advantage of it. */
@@ -2731,7 +2731,7 @@ static int
 intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
 			  struct intel_sdvo *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.base.dev);
+	struct intel_display *display = to_intel_display(&encoder->base);
 	struct intel_sdvo_ddc *ddc = NULL;
 	int ret;
 
@@ -2756,7 +2756,7 @@ intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
 	intel_connector_attach_encoder(&connector->base, &encoder->base);
 
 	if (ddc)
-		drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] using %s\n",
+		drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] using %s\n",
 			    connector->base.base.base.id, connector->base.base.name,
 			    ddc->ddc.name);
 
@@ -2799,14 +2799,14 @@ static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
 static bool
 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, u16 type)
 {
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	struct drm_encoder *encoder = &intel_sdvo->base.base;
 	struct drm_connector *connector;
 	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
-	struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
 	struct intel_connector *intel_connector;
 	struct intel_sdvo_connector *intel_sdvo_connector;
 
-	drm_dbg_kms(&i915->drm, "initialising DVI type 0x%x\n", type);
+	drm_dbg_kms(display->drm, "initialising DVI type 0x%x\n", type);
 
 	intel_sdvo_connector = intel_sdvo_connector_alloc();
 	if (!intel_sdvo_connector)
@@ -2852,13 +2852,13 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, u16 type)
 static bool
 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, u16 type)
 {
-	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	struct drm_encoder *encoder = &intel_sdvo->base.base;
 	struct drm_connector *connector;
 	struct intel_connector *intel_connector;
 	struct intel_sdvo_connector *intel_sdvo_connector;
 
-	drm_dbg_kms(&i915->drm, "initialising TV type 0x%x\n", type);
+	drm_dbg_kms(display->drm, "initialising TV type 0x%x\n", type);
 
 	intel_sdvo_connector = intel_sdvo_connector_alloc();
 	if (!intel_sdvo_connector)
@@ -2892,13 +2892,13 @@ intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, u16 type)
 static bool
 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, u16 type)
 {
-	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	struct drm_encoder *encoder = &intel_sdvo->base.base;
 	struct drm_connector *connector;
 	struct intel_connector *intel_connector;
 	struct intel_sdvo_connector *intel_sdvo_connector;
 
-	drm_dbg_kms(&i915->drm, "initialising analog type 0x%x\n", type);
+	drm_dbg_kms(display->drm, "initialising analog type 0x%x\n", type);
 
 	intel_sdvo_connector = intel_sdvo_connector_alloc();
 	if (!intel_sdvo_connector)
@@ -2926,12 +2926,11 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type)
 {
 	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	struct drm_encoder *encoder = &intel_sdvo->base.base;
-	struct drm_i915_private *i915 = to_i915(encoder->dev);
 	struct drm_connector *connector;
 	struct intel_connector *intel_connector;
 	struct intel_sdvo_connector *intel_sdvo_connector;
 
-	drm_dbg_kms(&i915->drm, "initialising LVDS type 0x%x\n", type);
+	drm_dbg_kms(display->drm, "initialising LVDS type 0x%x\n", type);
 
 	intel_sdvo_connector = intel_sdvo_connector_alloc();
 	if (!intel_sdvo_connector)
@@ -2961,12 +2960,12 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type)
 	intel_panel_add_vbt_sdvo_fixed_mode(intel_connector);
 
 	if (!intel_panel_preferred_fixed_mode(intel_connector)) {
-		mutex_lock(&i915->drm.mode_config.mutex);
+		mutex_lock(&display->drm->mode_config.mutex);
 
 		intel_ddc_get_modes(connector, connector->ddc);
 		intel_panel_add_edid_fixed_modes(intel_connector, false);
 
-		mutex_unlock(&i915->drm.mode_config.mutex);
+		mutex_unlock(&display->drm->mode_config.mutex);
 	}
 
 	intel_panel_init(intel_connector, NULL);
@@ -3015,7 +3014,7 @@ static bool intel_sdvo_output_init(struct intel_sdvo *sdvo, u16 type)
 static bool
 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo)
 {
-	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	static const u16 probe_order[] = {
 		SDVO_OUTPUT_TMDS0,
 		SDVO_OUTPUT_TMDS1,
@@ -3034,7 +3033,7 @@ intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo)
 	flags = intel_sdvo_filter_output_flags(intel_sdvo->caps.output_flags);
 
 	if (flags == 0) {
-		drm_dbg_kms(&i915->drm,
+		drm_dbg_kms(display->drm,
 			    "%s: Unknown SDVO output type (0x%04x)\n",
 			    SDVO_NAME(intel_sdvo), intel_sdvo->caps.output_flags);
 		return false;
@@ -3057,11 +3056,11 @@ intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo)
 
 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
 {
-	struct drm_device *dev = intel_sdvo->base.base.dev;
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	struct drm_connector *connector, *tmp;
 
 	list_for_each_entry_safe(connector, tmp,
-				 &dev->mode_config.connector_list, head) {
+				 &display->drm->mode_config.connector_list, head) {
 		if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) {
 			drm_connector_unregister(connector);
 			intel_connector_destroy(connector);
@@ -3073,7 +3072,7 @@ static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
 					  struct intel_sdvo_connector *intel_sdvo_connector,
 					  int type)
 {
-	struct drm_device *dev = intel_sdvo->base.base.dev;
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	struct intel_sdvo_tv_format format;
 	u32 format_map, i;
 
@@ -3098,7 +3097,7 @@ static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
 
 
 	intel_sdvo_connector->tv_format =
-		drm_property_create(dev, DRM_MODE_PROP_ENUM,
+		drm_property_create(display->drm, DRM_MODE_PROP_ENUM,
 				    "mode", intel_sdvo_connector->format_supported_num);
 	if (!intel_sdvo_connector->tv_format)
 		return false;
@@ -3120,12 +3119,12 @@ static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
 		    !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
 			return false; \
 		intel_sdvo_connector->name = \
-			drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
+			drm_property_create_range(display->drm, 0, #name, 0, data_value[0]); \
 		if (!intel_sdvo_connector->name) return false; \
 		state_assignment = response; \
 		drm_object_attach_property(&connector->base, \
 					   intel_sdvo_connector->name, 0); \
-		drm_dbg_kms(dev, #name ": max %d, default %d, current %d\n", \
+		drm_dbg_kms(display->drm, #name ": max %d, default %d, current %d\n", \
 			    data_value[0], data_value[1], response); \
 	} \
 } while (0)
@@ -3137,8 +3136,7 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
 				      struct intel_sdvo_connector *intel_sdvo_connector,
 				      struct intel_sdvo_enhancements_reply enhancements)
 {
-	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
-	struct drm_device *dev = intel_sdvo->base.base.dev;
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	struct drm_connector *connector = &intel_sdvo_connector->base.base;
 	struct drm_connector_state *conn_state = connector->state;
 	struct intel_sdvo_connector_state *sdvo_state =
@@ -3161,7 +3159,7 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
 
 		intel_sdvo_connector->max_hscan = data_value[0];
 		intel_sdvo_connector->left =
-			drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
+			drm_property_create_range(display->drm, 0, "left_margin", 0, data_value[0]);
 		if (!intel_sdvo_connector->left)
 			return false;
 
@@ -3169,13 +3167,13 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
 					   intel_sdvo_connector->left, 0);
 
 		intel_sdvo_connector->right =
-			drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
+			drm_property_create_range(display->drm, 0, "right_margin", 0, data_value[0]);
 		if (!intel_sdvo_connector->right)
 			return false;
 
 		drm_object_attach_property(&connector->base,
 					   intel_sdvo_connector->right, 0);
-		drm_dbg_kms(&i915->drm, "h_overscan: max %d, default %d, current %d\n",
+		drm_dbg_kms(display->drm, "h_overscan: max %d, default %d, current %d\n",
 			    data_value[0], data_value[1], response);
 	}
 
@@ -3194,7 +3192,7 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
 
 		intel_sdvo_connector->max_vscan = data_value[0];
 		intel_sdvo_connector->top =
-			drm_property_create_range(dev, 0,
+			drm_property_create_range(display->drm, 0,
 						  "top_margin", 0, data_value[0]);
 		if (!intel_sdvo_connector->top)
 			return false;
@@ -3203,14 +3201,14 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
 					   intel_sdvo_connector->top, 0);
 
 		intel_sdvo_connector->bottom =
-			drm_property_create_range(dev, 0,
+			drm_property_create_range(display->drm, 0,
 						  "bottom_margin", 0, data_value[0]);
 		if (!intel_sdvo_connector->bottom)
 			return false;
 
 		drm_object_attach_property(&connector->base,
 					   intel_sdvo_connector->bottom, 0);
-		drm_dbg_kms(&i915->drm, "v_overscan: max %d, default %d, current %d\n",
+		drm_dbg_kms(display->drm, "v_overscan: max %d, default %d, current %d\n",
 			    data_value[0], data_value[1], response);
 	}
 
@@ -3233,13 +3231,13 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
 
 		sdvo_state->tv.dot_crawl = response & 0x1;
 		intel_sdvo_connector->dot_crawl =
-			drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
+			drm_property_create_range(display->drm, 0, "dot_crawl", 0, 1);
 		if (!intel_sdvo_connector->dot_crawl)
 			return false;
 
 		drm_object_attach_property(&connector->base,
 					   intel_sdvo_connector->dot_crawl, 0);
-		drm_dbg_kms(&i915->drm, "dot crawl: current %d\n", response);
+		drm_dbg_kms(display->drm, "dot crawl: current %d\n", response);
 	}
 
 	return true;
@@ -3250,7 +3248,7 @@ intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
 					struct intel_sdvo_connector *intel_sdvo_connector,
 					struct intel_sdvo_enhancements_reply enhancements)
 {
-	struct drm_device *dev = intel_sdvo->base.base.dev;
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	struct drm_connector *connector = &intel_sdvo_connector->base.base;
 	u16 response, data_value[2];
 
@@ -3264,7 +3262,7 @@ intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
 					       struct intel_sdvo_connector *intel_sdvo_connector)
 {
-	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
+	struct intel_display *display = to_intel_display(&intel_sdvo->base);
 	union {
 		struct intel_sdvo_enhancements_reply reply;
 		u16 response;
@@ -3276,7 +3274,7 @@ static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
 				  SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
 				  &enhancements, sizeof(enhancements)) ||
 	    enhancements.response == 0) {
-		drm_dbg_kms(&i915->drm, "No enhancement is supported\n");
+		drm_dbg_kms(display->drm, "No enhancement is supported\n");
 		return true;
 	}
 
@@ -3351,8 +3349,8 @@ static int
 intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc,
 			  struct intel_sdvo *sdvo, int ddc_bus)
 {
-	struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
-	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+	struct intel_display *display = to_intel_display(&sdvo->base);
+	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
 
 	ddc->sdvo = sdvo;
 	ddc->ddc_bus = ddc_bus;
@@ -3368,25 +3366,26 @@ intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc,
 	return i2c_add_adapter(&ddc->ddc);
 }
 
-static bool is_sdvo_port_valid(struct drm_i915_private *dev_priv, enum port port)
+static bool is_sdvo_port_valid(struct intel_display *display, enum port port)
 {
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
+
 	if (HAS_PCH_SPLIT(dev_priv))
 		return port == PORT_B;
 	else
 		return port == PORT_B || port == PORT_C;
 }
 
-static bool assert_sdvo_port_valid(struct drm_i915_private *dev_priv,
-				   enum port port)
+static bool assert_sdvo_port_valid(struct intel_display *display, enum port port)
 {
-	return !drm_WARN(&dev_priv->drm, !is_sdvo_port_valid(dev_priv, port),
+	return !drm_WARN(display->drm, !is_sdvo_port_valid(display, port),
 			 "Platform does not support SDVO %c\n", port_name(port));
 }
 
-bool intel_sdvo_init(struct drm_i915_private *dev_priv,
+bool intel_sdvo_init(struct intel_display *display,
 		     i915_reg_t sdvo_reg, enum port port)
 {
-	struct intel_display *display = &dev_priv->display;
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	struct intel_encoder *intel_encoder;
 	struct intel_sdvo *intel_sdvo;
 	int i;
@@ -3394,7 +3393,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
 	if (!assert_port_valid(display, port))
 		return false;
 
-	if (!assert_sdvo_port_valid(dev_priv, port))
+	if (!assert_sdvo_port_valid(display, port))
 		return false;
 
 	intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
@@ -3407,7 +3406,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
 	intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
 	intel_encoder->port = port;
 
-	drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
+	drm_encoder_init(display->drm, &intel_encoder->base,
 			 &intel_sdvo_enc_funcs, 0,
 			 "SDVO %c", port_name(port));
 
@@ -3421,7 +3420,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
 		u8 byte;
 
 		if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
-			drm_dbg_kms(&dev_priv->drm,
+			drm_dbg_kms(display->drm,
 				    "No SDVO device found on %s\n",
 				    SDVO_NAME(intel_sdvo));
 			goto err;
@@ -3459,7 +3458,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
 	}
 
 	if (!intel_sdvo_output_setup(intel_sdvo)) {
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(display->drm,
 			    "SDVO output failed to setup on %s\n",
 			    SDVO_NAME(intel_sdvo));
 		/* Output_setup can leave behind connectors! */
@@ -3496,7 +3495,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
 						    &intel_sdvo->pixel_clock_max))
 		goto err_output;
 
-	drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, "
+	drm_dbg_kms(display->drm, "%s device VID/DID: %02X:%02X.%02X, "
 		    "clock range %dMHz - %dMHz, "
 		    "num inputs: %d, "
 		    "output 1: %c, output 2: %c\n",
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.h b/drivers/gpu/drm/i915/display/intel_sdvo.h
index d1815b4103d4..1a9e40fdd8a8 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.h
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.h
@@ -10,22 +10,22 @@
 
 #include "i915_reg_defs.h"
 
-struct drm_i915_private;
 enum pipe;
 enum port;
+struct intel_display;
 
 #ifdef I915
-bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
+bool intel_sdvo_port_enabled(struct intel_display *display,
 			     i915_reg_t sdvo_reg, enum pipe *pipe);
-bool intel_sdvo_init(struct drm_i915_private *dev_priv,
+bool intel_sdvo_init(struct intel_display *display,
 		     i915_reg_t reg, enum port port);
 #else
-static inline bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
+static inline bool intel_sdvo_port_enabled(struct intel_display *display,
 					   i915_reg_t sdvo_reg, enum pipe *pipe)
 {
 	return false;
 }
-static inline bool intel_sdvo_init(struct drm_i915_private *dev_priv,
+static inline bool intel_sdvo_init(struct intel_display *display,
 				   i915_reg_t reg, enum port port)
 {
 	return false;
-- 
2.39.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* RE: [PATCH 08/14] drm/i915/sdvo: convert intel_sdvo.[ch] to struct intel_display
  2025-02-12 16:36 ` [PATCH 08/14] drm/i915/sdvo: convert intel_sdvo.[ch] to struct intel_display Jani Nikula
@ 2025-02-13  9:13   ` Kandpal, Suraj
  2025-02-13 11:16     ` Jani Nikula
  0 siblings, 1 reply; 35+ messages in thread
From: Kandpal, Suraj @ 2025-02-13  9:13 UTC (permalink / raw)
  To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org
  Cc: Nikula, Jani



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Wednesday, February 12, 2025 10:07 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 08/14] drm/i915/sdvo: convert intel_sdvo.[ch] to struct
> intel_display
> 
> Going forward, struct intel_display is the main display device data pointer.
> Convert as much as possible of intel_sdvo.[ch] to struct intel_display.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/g4x_hdmi.c       |   3 +-
>  drivers/gpu/drm/i915/display/intel_display.c  |   6 +-
>  .../gpu/drm/i915/display/intel_pch_display.c  |   2 +-
>  drivers/gpu/drm/i915/display/intel_sdvo.c     | 281 +++++++++---------
>  drivers/gpu/drm/i915/display/intel_sdvo.h     |  10 +-
>  5 files changed, 150 insertions(+), 152 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> index 089f1a4d7720..5c5eb3d621c8 100644
> --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> @@ -67,7 +67,6 @@ static bool intel_hdmi_get_hw_state(struct
> intel_encoder *encoder,
>  				    enum pipe *pipe)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>  	intel_wakeref_t wakeref;
>  	bool ret;
> @@ -77,7 +76,7 @@ static bool intel_hdmi_get_hw_state(struct
> intel_encoder *encoder,
>  	if (!wakeref)
>  		return false;
> 
> -	ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg,
> pipe);
> +	ret = intel_sdvo_port_enabled(display, intel_hdmi->hdmi_reg, pipe);
> 
>  	intel_display_power_put(display, encoder->power_domain,
> wakeref);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 9bcbd52f23cf..e1186f46088d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8236,7 +8236,7 @@ void intel_setup_outputs(struct drm_i915_private
> *dev_priv)
> 
>  		if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED)
> {
>  			/* PCH SDVOB multiplex with HDMIB */
> -			found = intel_sdvo_init(dev_priv, PCH_SDVOB,
> PORT_B);
> +			found = intel_sdvo_init(display, PCH_SDVOB,
> PORT_B);
>  			if (!found)
>  				g4x_hdmi_init(display, PCH_HDMIB,
> PORT_B);
>  			if (!found && (intel_de_read(dev_priv, PCH_DP_B) &
> DP_DETECTED)) @@ -8315,7 +8315,7 @@ void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> 
>  		if (intel_de_read(dev_priv, GEN3_SDVOB) &
> SDVO_DETECTED) {
>  			drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
> -			found = intel_sdvo_init(dev_priv, GEN3_SDVOB,
> PORT_B);
> +			found = intel_sdvo_init(display, GEN3_SDVOB,
> PORT_B);
>  			if (!found && IS_G4X(dev_priv)) {
>  				drm_dbg_kms(&dev_priv->drm,
>  					    "probing HDMI on SDVOB\n");
> @@ -8330,7 +8330,7 @@ void intel_setup_outputs(struct drm_i915_private
> *dev_priv)
> 
>  		if (intel_de_read(dev_priv, GEN3_SDVOB) &
> SDVO_DETECTED) {
>  			drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
> -			found = intel_sdvo_init(dev_priv, GEN3_SDVOC,
> PORT_C);
> +			found = intel_sdvo_init(display, GEN3_SDVOC,
> PORT_C);
>  		}
> 
>  		if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) &
> SDVO_DETECTED)) { diff --git
> a/drivers/gpu/drm/i915/display/intel_pch_display.c
> b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 98a6b57ac956..1abe0a784570 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -65,7 +65,7 @@ static void assert_pch_hdmi_disabled(struct
> drm_i915_private *dev_priv,
>  	enum pipe port_pipe;
>  	bool state;
> 
> -	state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
> +	state = intel_sdvo_port_enabled(display, hdmi_reg, &port_pipe);
> 
>  	INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,
>  				 "PCH HDMI %c enabled on transcoder %c,
> should be disabled\n", diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c
> b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index 46203d796fcc..1ae766212e8a 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -213,29 +213,29 @@ intel_sdvo_create_enhance_property(struct
> intel_sdvo *intel_sdvo,
>   */
>  static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)  {
> -	struct drm_device *dev = intel_sdvo->base.base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	u32 bval = val, cval = val;
>  	int i;
> 
>  	if (HAS_PCH_SPLIT(dev_priv)) {
> -		intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
> -		intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
> +		intel_de_write(display, intel_sdvo->sdvo_reg, val);
> +		intel_de_posting_read(display, intel_sdvo->sdvo_reg);
>  		/*
>  		 * HW workaround, need to write this twice for issue
>  		 * that may result in first write getting masked.
>  		 */
>  		if (HAS_PCH_IBX(dev_priv)) {
> -			intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
> -			intel_de_posting_read(dev_priv, intel_sdvo-
> >sdvo_reg);
> +			intel_de_write(display, intel_sdvo->sdvo_reg, val);
> +			intel_de_posting_read(display, intel_sdvo-
> >sdvo_reg);
>  		}
>  		return;
>  	}
> 
>  	if (intel_sdvo->base.port == PORT_B)
> -		cval = intel_de_read(dev_priv, GEN3_SDVOC);
> +		cval = intel_de_read(display, GEN3_SDVOC);
>  	else
> -		bval = intel_de_read(dev_priv, GEN3_SDVOB);
> +		bval = intel_de_read(display, GEN3_SDVOB);
> 
>  	/*
>  	 * Write the registers twice for luck. Sometimes, @@ -243,17 +243,17
> @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32
> val)
>  	 * The BIOS does this too. Yay, magic
>  	 */
>  	for (i = 0; i < 2; i++) {
> -		intel_de_write(dev_priv, GEN3_SDVOB, bval);
> -		intel_de_posting_read(dev_priv, GEN3_SDVOB);
> +		intel_de_write(display, GEN3_SDVOB, bval);
> +		intel_de_posting_read(display, GEN3_SDVOB);
> 
> -		intel_de_write(dev_priv, GEN3_SDVOC, cval);
> -		intel_de_posting_read(dev_priv, GEN3_SDVOC);
> +		intel_de_write(display, GEN3_SDVOC, cval);
> +		intel_de_posting_read(display, GEN3_SDVOC);
>  	}
>  }
> 
>  static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8
> *ch)  {
> -	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	struct i2c_msg msgs[] = {
>  		{
>  			.addr = intel_sdvo->target_addr,
> @@ -273,7 +273,7 @@ static bool intel_sdvo_read_byte(struct intel_sdvo
> *intel_sdvo, u8 addr, u8 *ch)
>  	if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
>  		return true;
> 
> -	drm_dbg_kms(&i915->drm, "i2c transfer returned %d\n", ret);
> +	drm_dbg_kms(display->drm, "i2c transfer returned %d\n", ret);
>  	return false;
>  }
> 
> @@ -415,7 +415,7 @@ static const char *sdvo_cmd_name(u8 cmd)  static
> void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
>  				   const void *args, int args_len)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(intel_sdvo-
> >base.base.dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	const char *cmd_name;
>  	int i, pos = 0;
>  	char buffer[64];
> @@ -436,10 +436,10 @@ static void intel_sdvo_debug_write(struct
> intel_sdvo *intel_sdvo, u8 cmd,
>  	else
>  		BUF_PRINT("(%02X)", cmd);
> 
> -	drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
> +	drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1);
>  #undef BUF_PRINT
> 
> -	drm_dbg_kms(&dev_priv->drm, "%s: W: %02X %s\n",
> SDVO_NAME(intel_sdvo),
> +	drm_dbg_kms(display->drm, "%s: W: %02X %s\n",
> SDVO_NAME(intel_sdvo),
>  		    cmd, buffer);
>  }
> 
> @@ -465,7 +465,7 @@ static bool __intel_sdvo_write_cmd(struct intel_sdvo
> *intel_sdvo, u8 cmd,
>  				   const void *args, int args_len,
>  				   bool unlocked)
>  {
> -	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	u8 *buf, status;
>  	struct i2c_msg *msgs;
>  	int i, ret = true;
> @@ -515,13 +515,13 @@ static bool __intel_sdvo_write_cmd(struct
> intel_sdvo *intel_sdvo, u8 cmd,
>  	else
>  		ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
>  	if (ret < 0) {
> -		drm_dbg_kms(&i915->drm, "I2c transfer returned %d\n",
> ret);
> +		drm_dbg_kms(display->drm, "I2c transfer returned %d\n",
> ret);
>  		ret = false;
>  		goto out;
>  	}
>  	if (ret != i+3) {
>  		/* failure in I2C transfer */
> -		drm_dbg_kms(&i915->drm, "I2c transfer returned
> %d/%d\n", ret, i+3);
> +		drm_dbg_kms(display->drm, "I2c transfer returned
> %d/%d\n", ret, i +
> +3);
>  		ret = false;
>  	}
> 
> @@ -540,7 +540,7 @@ static bool intel_sdvo_write_cmd(struct intel_sdvo
> *intel_sdvo, u8 cmd,  static bool intel_sdvo_read_response(struct intel_sdvo
> *intel_sdvo,
>  				     void *response, int response_len)  {
> -	struct drm_i915_private *dev_priv = to_i915(intel_sdvo-
> >base.base.dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	const char *cmd_status;
>  	u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
>  	u8 status;
> @@ -605,15 +605,15 @@ static bool intel_sdvo_read_response(struct
> intel_sdvo *intel_sdvo,
>  		BUF_PRINT(" %02X", ((u8 *)response)[i]);
>  	}
> 
> -	drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
> +	drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1);
>  #undef BUF_PRINT
> 
> -	drm_dbg_kms(&dev_priv->drm, "%s: R: %s\n",
> +	drm_dbg_kms(display->drm, "%s: R: %s\n",
>  		    SDVO_NAME(intel_sdvo), buffer);
>  	return true;
> 
>  log_fail:
> -	drm_dbg_kms(&dev_priv->drm, "%s: R: ... failed %s\n",
> +	drm_dbg_kms(display->drm, "%s: R: ... failed %s\n",
>  		    SDVO_NAME(intel_sdvo), buffer);
>  	return false;
>  }
> @@ -1009,7 +1009,7 @@ static bool intel_sdvo_write_infoframe(struct
> intel_sdvo *intel_sdvo,
>  				       unsigned int if_index, u8 tx_rate,
>  				       const u8 *data, unsigned int length)  {
> -	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	u8 set_buf_index[2] = { if_index, 0 };
>  	u8 hbuf_size, tmp[8];
>  	int i;
> @@ -1022,7 +1022,7 @@ static bool intel_sdvo_write_infoframe(struct
> intel_sdvo *intel_sdvo,
>  	if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
>  		return false;
> 
> -	drm_dbg_kms(&i915->drm,
> +	drm_dbg_kms(display->drm,
>  		    "writing sdvo hbuf: %i, length %u, hbuf_size: %i\n",
>  		    if_index, length, hbuf_size);
> 
> @@ -1049,7 +1049,7 @@ static ssize_t intel_sdvo_read_infoframe(struct
> intel_sdvo *intel_sdvo,
>  					 unsigned int if_index,
>  					 u8 *data, unsigned int length)
>  {
> -	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	u8 set_buf_index[2] = { if_index, 0 };
>  	u8 hbuf_size, tx_rate, av_split;
>  	int i;
> @@ -1079,7 +1079,7 @@ static ssize_t intel_sdvo_read_infoframe(struct
> intel_sdvo *intel_sdvo,
>  	if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
>  		return false;
> 
> -	drm_dbg_kms(&i915->drm,
> +	drm_dbg_kms(display->drm,
>  		    "reading sdvo hbuf: %i, length %u, hbuf_size: %i\n",
>  		    if_index, length, hbuf_size);
> 
> @@ -1100,7 +1100,7 @@ static bool
> intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
>  					     struct intel_crtc_state *crtc_state,
>  					     struct drm_connector_state
> *conn_state)  {
> -	struct drm_i915_private *dev_priv = to_i915(intel_sdvo-
> >base.base.dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
> @@ -1126,7 +1126,7 @@ static bool
> intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
> 
> HDMI_QUANTIZATION_RANGE_FULL);
> 
>  	ret = hdmi_avi_infoframe_check(frame);
> -	if (drm_WARN_ON(&dev_priv->drm, ret))
> +	if (drm_WARN_ON(display->drm, ret))
>  		return false;
> 
>  	return true;
> @@ -1135,7 +1135,7 @@ static bool
> intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,  static bool
> intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
>  					 const struct intel_crtc_state
> *crtc_state)  {
> -	struct drm_i915_private *dev_priv = to_i915(intel_sdvo-
> >base.base.dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
>  	const union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
>  	ssize_t len;
> @@ -1144,12 +1144,12 @@ static bool intel_sdvo_set_avi_infoframe(struct
> intel_sdvo *intel_sdvo,
>  	     intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) ==
> 0)
>  		return true;
> 
> -	if (drm_WARN_ON(&dev_priv->drm,
> +	if (drm_WARN_ON(display->drm,
>  			frame->any.type != HDMI_INFOFRAME_TYPE_AVI))
>  		return false;
> 
>  	len = hdmi_infoframe_pack_only(frame, sdvo_data,
> sizeof(sdvo_data));
> -	if (drm_WARN_ON(&dev_priv->drm, len < 0))
> +	if (drm_WARN_ON(display->drm, len < 0))
>  		return false;
> 
>  	return intel_sdvo_write_infoframe(intel_sdvo,
> SDVO_HBUF_INDEX_AVI_IF, @@ -1160,7 +1160,7 @@ static bool
> intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,  static void
> intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo,
>  					 struct intel_crtc_state *crtc_state)  {
> -	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
>  	union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
>  	ssize_t len;
> @@ -1172,7 +1172,7 @@ static void intel_sdvo_get_avi_infoframe(struct
> intel_sdvo *intel_sdvo,
>  	len = intel_sdvo_read_infoframe(intel_sdvo,
> SDVO_HBUF_INDEX_AVI_IF,
>  					sdvo_data, sizeof(sdvo_data));
>  	if (len < 0) {
> -		drm_dbg_kms(&i915->drm, "failed to read AVI
> infoframe\n");
> +		drm_dbg_kms(display->drm, "failed to read AVI
> infoframe\n");
>  		return;
>  	} else if (len == 0) {
>  		return;
> @@ -1183,12 +1183,12 @@ static void intel_sdvo_get_avi_infoframe(struct
> intel_sdvo *intel_sdvo,
> 
>  	ret = hdmi_infoframe_unpack(frame, sdvo_data, len);
>  	if (ret) {
> -		drm_dbg_kms(&i915->drm, "Failed to unpack AVI
> infoframe\n");
> +		drm_dbg_kms(display->drm, "Failed to unpack AVI
> infoframe\n");
>  		return;
>  	}
> 
>  	if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI)
> -		drm_dbg_kms(&i915->drm,
> +		drm_dbg_kms(display->drm,
>  			    "Found the wrong infoframe type 0x%x (expected
> 0x%02x)\n",
>  			    frame->any.type, HDMI_INFOFRAME_TYPE_AVI);  }
> @@ -1196,7 +1196,7 @@ static void intel_sdvo_get_avi_infoframe(struct
> intel_sdvo *intel_sdvo,  static void intel_sdvo_get_eld(struct intel_sdvo
> *intel_sdvo,
>  			       struct intel_crtc_state *crtc_state)  {
> -	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	ssize_t len;
>  	u8 val;
> 
> @@ -1212,7 +1212,7 @@ static void intel_sdvo_get_eld(struct intel_sdvo
> *intel_sdvo,
>  	len = intel_sdvo_read_infoframe(intel_sdvo,
> SDVO_HBUF_INDEX_ELD,
>  					crtc_state->eld, sizeof(crtc_state-
> >eld));
>  	if (len < 0)
> -		drm_dbg_kms(&i915->drm, "failed to read ELD\n");
> +		drm_dbg_kms(display->drm, "failed to read ELD\n");
>  }
> 
>  static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo, @@ -
> 1282,7 +1282,7 @@ intel_sdvo_get_preferred_input_mode(struct
> intel_sdvo *intel_sdvo,
> 
>  static int i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)  {
> -	struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc-
> >dev);
> +	struct intel_display *display = to_intel_display(pipe_config);
>  	unsigned int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
>  	struct dpll *clock = &pipe_config->dpll;
> 
> @@ -1303,7 +1303,7 @@ static int i9xx_adjust_sdvo_tv_clock(struct
> intel_crtc_state *pipe_config)
>  		clock->m1 = 12;
>  		clock->m2 = 8;
>  	} else {
> -		drm_dbg_kms(&dev_priv->drm,
> +		drm_dbg_kms(display->drm,
>  			    "SDVO TV clock out of range: %i\n", dotclock);
>  		return -EINVAL;
>  	}
> @@ -1359,6 +1359,7 @@ static int intel_sdvo_compute_config(struct
> intel_encoder *encoder,
>  				     struct intel_crtc_state *pipe_config,
>  				     struct drm_connector_state *conn_state)
> {
> +	struct intel_display *display = to_intel_display(encoder);
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
>  	struct intel_sdvo_connector *intel_sdvo_connector = @@ -1366,13
> +1367,13 @@ static int intel_sdvo_compute_config(struct intel_encoder
> *encoder,
>  	struct drm_display_mode *adjusted_mode = &pipe_config-
> >hw.adjusted_mode;
>  	struct drm_display_mode *mode = &pipe_config->hw.mode;
> 
> -	if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) {
> +	if (HAS_PCH_SPLIT(i915)) {
>  		pipe_config->has_pch_encoder = true;
>  		if (!intel_fdi_compute_pipe_bpp(pipe_config))
>  			return -EINVAL;
>  	}
> 
> -	drm_dbg_kms(&i915->drm, "forcing bpc to 8 for SDVO\n");
> +	drm_dbg_kms(display->drm, "forcing bpc to 8 for SDVO\n");
>  	/* FIXME: Don't increase pipe_bpp */
>  	pipe_config->pipe_bpp = 8*3;
>  	pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; @@ -
> 1451,7 +1452,7 @@ static int intel_sdvo_compute_config(struct
> intel_encoder *encoder,
> 
>  	if (!intel_sdvo_compute_avi_infoframe(intel_sdvo,
>  					      pipe_config, conn_state)) {
> -		drm_dbg_kms(&i915->drm, "bad AVI infoframe\n");
> +		drm_dbg_kms(display->drm, "bad AVI infoframe\n");
>  		return -EINVAL;
>  	}
> 
> @@ -1525,6 +1526,7 @@ static void intel_sdvo_pre_enable(struct
> intel_atomic_state *state,
>  				  const struct intel_crtc_state *crtc_state,
>  				  const struct drm_connector_state
> *conn_state)  {
> +	struct intel_display *display = to_intel_display(intel_encoder);
>  	struct drm_i915_private *dev_priv = to_i915(intel_encoder-
> >base.dev);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode; @@ -1570,7 +1572,7 @@ static void
> intel_sdvo_pre_enable(struct intel_atomic_state *state,
>  		intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
>  	}
>  	if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
> -		drm_info(&dev_priv->drm,
> +		drm_info(display->drm,
>  			 "Setting output timings on %s failed\n",
>  			 SDVO_NAME(intel_sdvo));
> 
> @@ -1600,13 +1602,13 @@ static void intel_sdvo_pre_enable(struct
> intel_atomic_state *state,
>  	if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector))
>  		input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
>  	if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
> -		drm_info(&dev_priv->drm,
> +		drm_info(display->drm,
>  			 "Setting input timings on %s failed\n",
>  			 SDVO_NAME(intel_sdvo));
> 
>  	switch (crtc_state->pixel_multiplier) {
>  	default:
> -		drm_WARN(&dev_priv->drm, 1,
> +		drm_WARN(display->drm, 1,
>  			 "unknown pixel multiplier specified\n");
>  		fallthrough;
>  	case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; @@ -1617,14
> +1619,14 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state
> *state,
>  		return;
> 
>  	/* Set the SDVO control regs. */
> -	if (DISPLAY_VER(dev_priv) >= 4) {
> +	if (DISPLAY_VER(display) >= 4) {
>  		/* The real mode polarity is set by the SDVO commands,
> using
>  		 * struct intel_sdvo_dtd. */
>  		sdvox = SDVO_VSYNC_ACTIVE_HIGH |
> SDVO_HSYNC_ACTIVE_HIGH;
> -		if (DISPLAY_VER(dev_priv) < 5)
> +		if (DISPLAY_VER(display) < 5)
>  			sdvox |= SDVO_BORDER_ENABLE;
>  	} else {
> -		sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
> +		sdvox = intel_de_read(display, intel_sdvo->sdvo_reg);
>  		if (intel_sdvo->base.port == PORT_B)
>  			sdvox &= SDVOB_PRESERVE_MASK;
>  		else
> @@ -1637,10 +1639,10 @@ static void intel_sdvo_pre_enable(struct
> intel_atomic_state *state,
>  	else
>  		sdvox |= SDVO_PIPE_SEL(crtc->pipe);
> 
> -	if (DISPLAY_VER(dev_priv) >= 4) {
> +	if (DISPLAY_VER(display) >= 4) {
>  		/* done in crtc_mode_set as the dpll_md reg must be
> written early */
> -	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
> -		   IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
> +	} else if (display->platform.i945g || display->platform.i945gm ||
> +		   display->platform.g33 || display->platform.pineview) {
>  		/* done in crtc_mode_set as it lives inside the dpll register
> */
>  	} else {
>  		sdvox |= (crtc_state->pixel_multiplier - 1) @@ -1648,7
> +1650,7 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state
> *state,
>  	}
> 
>  	if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
> -	    DISPLAY_VER(dev_priv) < 5)
> +	    DISPLAY_VER(display) < 5)
>  		sdvox |= SDVO_STALL_SELECT;
>  	intel_sdvo_write_sdvox(intel_sdvo, sdvox);  } @@ -1665,17 +1667,18
> @@ static bool intel_sdvo_connector_get_hw_state(struct intel_connector
> *connector)
>  	return active_outputs & intel_sdvo_connector->output_flag;
>  }
> 
> -bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
> +bool intel_sdvo_port_enabled(struct intel_display *display,
>  			     i915_reg_t sdvo_reg, enum pipe *pipe)  {
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	u32 val;
> 
> -	val = intel_de_read(dev_priv, sdvo_reg);
> +	val = intel_de_read(display, sdvo_reg);
> 
>  	/* asserts want to know the pipe even if the port is disabled */
>  	if (HAS_PCH_CPT(dev_priv))
>  		*pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >>
> SDVO_PIPE_SEL_SHIFT_CPT;
> -	else if (IS_CHERRYVIEW(dev_priv))
> +	else if (display->platform.cherryview)
>  		*pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >>
> SDVO_PIPE_SEL_SHIFT_CHV;
>  	else
>  		*pipe = (val & SDVO_PIPE_SEL_MASK) >>
> SDVO_PIPE_SEL_SHIFT; @@ -1686,14 +1689,14 @@ bool
> intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,  static bool
> intel_sdvo_get_hw_state(struct intel_encoder *encoder,
>  				    enum pipe *pipe)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_display *display = to_intel_display(encoder);
>  	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
>  	u16 active_outputs = 0;
>  	bool ret;
> 
>  	intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
> 
> -	ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg,
> pipe);
> +	ret = intel_sdvo_port_enabled(display, intel_sdvo->sdvo_reg, pipe);
> 
>  	return ret || active_outputs;
>  }
> @@ -1701,8 +1704,7 @@ static bool intel_sdvo_get_hw_state(struct
> intel_encoder *encoder,  static void intel_sdvo_get_config(struct
> intel_encoder *encoder,
>  				  struct intel_crtc_state *pipe_config)  {
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_display *display = to_intel_display(encoder);
>  	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
>  	struct intel_sdvo_dtd dtd;
>  	int encoder_pixel_multiplier = 0;
> @@ -1713,7 +1715,7 @@ static void intel_sdvo_get_config(struct
> intel_encoder *encoder,
> 
>  	pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO);
> 
> -	sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
> +	sdvox = intel_de_read(display, intel_sdvo->sdvo_reg);
> 
>  	ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
>  	if (!ret) {
> @@ -1721,7 +1723,7 @@ static void intel_sdvo_get_config(struct
> intel_encoder *encoder,
>  		 * Some sdvo encoders are not spec compliant and don't
>  		 * implement the mandatory get_timings function.
>  		 */
> -		drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n");
> +		drm_dbg_kms(display->drm, "failed to retrieve SDVO
> DTD\n");
>  		pipe_config->quirks |=
> PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
>  	} else {
>  		if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) @@ -
> 1744,7 +1746,7 @@ static void intel_sdvo_get_config(struct intel_encoder
> *encoder,
>  	 * encoder->get_config we so already have a valid pixel multiplier on
> all
>  	 * other platforms.
>  	 */
> -	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
> +	if (display->platform.i915g || display->platform.i915gm) {
>  		pipe_config->pixel_multiplier =
>  			((sdvox & SDVO_PORT_MULTIPLY_MASK)
>  			 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
> @@ -1773,7 +1775,7 @@ static void intel_sdvo_get_config(struct
> intel_encoder *encoder,
>  		}
>  	}
> 
> -	drm_WARN(dev,
> +	drm_WARN(display->drm,
>  		 encoder_pixel_multiplier != pipe_config->pixel_multiplier,
>  		 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
>  		 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
> @@ -1849,7 +1851,7 @@ static void intel_disable_sdvo(struct
> intel_atomic_state *state,
>  		intel_sdvo_set_encoder_power_state(intel_sdvo,
>  						   DRM_MODE_DPMS_OFF);
> 
> -	temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
> +	temp = intel_de_read(display, intel_sdvo->sdvo_reg);
> 
>  	temp &= ~SDVO_ENABLE;
>  	intel_sdvo_write_sdvox(intel_sdvo, temp); @@ -1900,8 +1902,7 @@
> static void intel_enable_sdvo(struct intel_atomic_state *state,
>  			      const struct intel_crtc_state *pipe_config,
>  			      const struct drm_connector_state *conn_state)  {
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_display *display = to_intel_display(encoder);
>  	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
>  	struct intel_sdvo_connector *intel_sdvo_connector =
>  		to_intel_sdvo_connector(conn_state->connector);
> @@ -1911,7 +1912,7 @@ static void intel_enable_sdvo(struct
> intel_atomic_state *state,
>  	int i;
>  	bool success;
> 
> -	temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
> +	temp = intel_de_read(display, intel_sdvo->sdvo_reg);
>  	temp |= SDVO_ENABLE;
>  	intel_sdvo_write_sdvox(intel_sdvo, temp);
> 
> @@ -1926,7 +1927,7 @@ static void intel_enable_sdvo(struct
> intel_atomic_state *state,
>  	 * a given it the status is a success, we succeeded.
>  	 */
>  	if (success && !input1) {
> -		drm_dbg_kms(&dev_priv->drm,
> +		drm_dbg_kms(display->drm,
>  			    "First %s output reported failure to sync\n",
>  			    SDVO_NAME(intel_sdvo));
>  	}
> @@ -1941,12 +1942,13 @@ static enum drm_mode_status
> intel_sdvo_mode_valid(struct drm_connector *connector,
>  		      const struct drm_display_mode *mode)  {
> +	struct intel_display *display = to_intel_display(connector->dev);

Why not &i915->display and declare this after i915 declaration

Otherwise LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>


>  	struct drm_i915_private *i915 = to_i915(connector->dev);
>  	struct intel_sdvo *intel_sdvo =
> intel_attached_sdvo(to_intel_connector(connector));
>  	struct intel_sdvo_connector *intel_sdvo_connector =
>  		to_intel_sdvo_connector(connector);
>  	bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector,
> connector->state);
> -	int max_dotclk = i915->display.cdclk.max_dotclk_freq;
> +	int max_dotclk = display->cdclk.max_dotclk_freq;
>  	enum drm_mode_status status;
>  	int clock = mode->clock;
> 
> @@ -1982,14 +1984,15 @@ intel_sdvo_mode_valid(struct drm_connector
> *connector,
> 
>  static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct
> intel_sdvo_caps *caps)  {
> -	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
> +
>  	BUILD_BUG_ON(sizeof(*caps) != 8);
>  	if (!intel_sdvo_get_value(intel_sdvo,
>  				  SDVO_CMD_GET_DEVICE_CAPS,
>  				  caps, sizeof(*caps)))
>  		return false;
> 
> -	drm_dbg_kms(&i915->drm, "SDVO capabilities:\n"
> +	drm_dbg_kms(display->drm, "SDVO capabilities:\n"
>  		    "  vendor_id: %d\n"
>  		    "  device_id: %d\n"
>  		    "  device_rev_id: %d\n"
> @@ -2031,17 +2034,17 @@ static u8 intel_sdvo_get_colorimetry_cap(struct
> intel_sdvo *intel_sdvo)
> 
>  static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)  {
> -	struct drm_i915_private *dev_priv = to_i915(intel_sdvo-
> >base.base.dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	u16 hotplug;
> 
> -	if (!I915_HAS_HOTPLUG(dev_priv))
> +	if (!I915_HAS_HOTPLUG(display))
>  		return 0;
> 
>  	/*
>  	 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's
> noise
>  	 * on the line.
>  	 */
> -	if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
> +	if (display->platform.i945g || display->platform.i945gm)
>  		return 0;
> 
>  	if (!intel_sdvo_get_value(intel_sdvo,
> SDVO_CMD_GET_HOT_PLUG_SUPPORT, @@ -2138,13 +2141,12 @@ static
> enum drm_connector_status  intel_sdvo_detect(struct drm_connector
> *connector, bool force)  {
>  	struct intel_display *display = to_intel_display(connector->dev);
> -	struct drm_i915_private *i915 = to_i915(connector->dev);
>  	struct intel_sdvo *intel_sdvo =
> intel_attached_sdvo(to_intel_connector(connector));
>  	struct intel_sdvo_connector *intel_sdvo_connector =
> to_intel_sdvo_connector(connector);
>  	enum drm_connector_status ret;
>  	u16 response;
> 
> -	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
> +	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
>  		    connector->base.id, connector->name);
> 
>  	if (!intel_display_device_enabled(display))
> @@ -2162,7 +2164,7 @@ intel_sdvo_detect(struct drm_connector
> *connector, bool force)
>  				  &response, 2))
>  		return connector_status_unknown;
> 
> -	drm_dbg_kms(&i915->drm, "SDVO response %d %d [%x]\n",
> +	drm_dbg_kms(display->drm, "SDVO response %d %d [%x]\n",
>  		    response & 0xff, response >> 8,
>  		    intel_sdvo_connector->output_flag);
> 
> @@ -2301,7 +2303,6 @@ static int intel_sdvo_get_tv_modes(struct
> drm_connector *connector)  {
>  	struct intel_display *display = to_intel_display(connector->dev);
>  	struct intel_sdvo *intel_sdvo =
> intel_attached_sdvo(to_intel_connector(connector));
> -	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
>  	struct intel_sdvo_connector *intel_sdvo_connector =
>  		to_intel_sdvo_connector(connector);
>  	const struct drm_connector_state *conn_state = connector->state;
> @@ -2310,7 +2311,7 @@ static int intel_sdvo_get_tv_modes(struct
> drm_connector *connector)
>  	int num_modes = 0;
>  	int i;
> 
> -	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
> +	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
>  		    connector->base.id, connector->name);
> 
>  	if (!intel_display_driver_check_access(display))
> @@ -2352,9 +2353,9 @@ static int intel_sdvo_get_tv_modes(struct
> drm_connector *connector)
> 
>  static int intel_sdvo_get_lvds_modes(struct drm_connector *connector)  {
> -	struct drm_i915_private *dev_priv = to_i915(connector->dev);
> +	struct intel_display *display = to_intel_display(connector->dev);
> 
> -	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
> +	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
>  		    connector->base.id, connector->name);
> 
>  	return intel_panel_get_modes(to_intel_connector(connector));
> @@ -2618,14 +2619,14 @@ static struct intel_sdvo_ddc *
> intel_sdvo_select_ddc_bus(struct intel_sdvo *sdvo,
>  			  struct intel_sdvo_connector *connector)  {
> -	struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
> +	struct intel_display *display = to_intel_display(&sdvo->base);
>  	const struct sdvo_device_mapping *mapping;
>  	int ddc_bus;
> 
>  	if (sdvo->base.port == PORT_B)
> -		mapping = &dev_priv->display.vbt.sdvo_mappings[0];
> +		mapping = &display->vbt.sdvo_mappings[0];
>  	else
> -		mapping = &dev_priv->display.vbt.sdvo_mappings[1];
> +		mapping = &display->vbt.sdvo_mappings[1];
> 
>  	if (mapping->initialized)
>  		ddc_bus = (mapping->ddc_pin & 0xf0) >> 4; @@ -2642,14
> +2643,13 @@ static void  intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
> {
>  	struct intel_display *display = to_intel_display(&sdvo->base);
> -	struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
>  	const struct sdvo_device_mapping *mapping;
>  	u8 pin;
> 
>  	if (sdvo->base.port == PORT_B)
> -		mapping = &dev_priv->display.vbt.sdvo_mappings[0];
> +		mapping = &display->vbt.sdvo_mappings[0];
>  	else
> -		mapping = &dev_priv->display.vbt.sdvo_mappings[1];
> +		mapping = &display->vbt.sdvo_mappings[1];
> 
>  	if (mapping->initialized &&
>  	    intel_gmbus_is_valid_pin(display, mapping->i2c_pin)) @@ -2657,7
> +2657,7 @@ intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
>  	else
>  		pin = GMBUS_PIN_DPB;
> 
> -	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] I2C pin %d,
> target addr 0x%x\n",
> +	drm_dbg_kms(display->drm, "[ENCODER:%d:%s] I2C pin %d, target
> addr
> +0x%x\n",
>  		    sdvo->base.base.base.id, sdvo->base.base.name,
>  		    pin, sdvo->target_addr);
> 
> @@ -2687,15 +2687,15 @@ intel_sdvo_is_hdmi_connector(struct intel_sdvo
> *intel_sdvo)  static u8  intel_sdvo_get_target_addr(struct intel_sdvo *sdvo)
> {
> -	struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
> +	struct intel_display *display = to_intel_display(&sdvo->base);
>  	const struct sdvo_device_mapping *my_mapping, *other_mapping;
> 
>  	if (sdvo->base.port == PORT_B) {
> -		my_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
> -		other_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
> +		my_mapping = &display->vbt.sdvo_mappings[0];
> +		other_mapping = &display->vbt.sdvo_mappings[1];
>  	} else {
> -		my_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
> -		other_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
> +		my_mapping = &display->vbt.sdvo_mappings[1];
> +		other_mapping = &display->vbt.sdvo_mappings[0];
>  	}
> 
>  	/* If the BIOS described our SDVO device, take advantage of it. */
> @@ -2731,7 +2731,7 @@ static int  intel_sdvo_connector_init(struct
> intel_sdvo_connector *connector,
>  			  struct intel_sdvo *encoder)
>  {
> -	struct drm_i915_private *i915 = to_i915(encoder->base.base.dev);
> +	struct intel_display *display = to_intel_display(&encoder->base);
>  	struct intel_sdvo_ddc *ddc = NULL;
>  	int ret;
> 
> @@ -2756,7 +2756,7 @@ intel_sdvo_connector_init(struct
> intel_sdvo_connector *connector,
>  	intel_connector_attach_encoder(&connector->base, &encoder-
> >base);
> 
>  	if (ddc)
> -		drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] using
> %s\n",
> +		drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] using
> %s\n",
>  			    connector->base.base.base.id, connector-
> >base.base.name,
>  			    ddc->ddc.name);
> 
> @@ -2799,14 +2799,14 @@ static struct intel_sdvo_connector
> *intel_sdvo_connector_alloc(void)  static bool  intel_sdvo_dvi_init(struct
> intel_sdvo *intel_sdvo, u16 type)  {
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	struct drm_encoder *encoder = &intel_sdvo->base.base;
>  	struct drm_connector *connector;
>  	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
> -	struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
>  	struct intel_connector *intel_connector;
>  	struct intel_sdvo_connector *intel_sdvo_connector;
> 
> -	drm_dbg_kms(&i915->drm, "initialising DVI type 0x%x\n", type);
> +	drm_dbg_kms(display->drm, "initialising DVI type 0x%x\n", type);
> 
>  	intel_sdvo_connector = intel_sdvo_connector_alloc();
>  	if (!intel_sdvo_connector)
> @@ -2852,13 +2852,13 @@ intel_sdvo_dvi_init(struct intel_sdvo
> *intel_sdvo, u16 type)  static bool  intel_sdvo_tv_init(struct intel_sdvo
> *intel_sdvo, u16 type)  {
> -	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	struct drm_encoder *encoder = &intel_sdvo->base.base;
>  	struct drm_connector *connector;
>  	struct intel_connector *intel_connector;
>  	struct intel_sdvo_connector *intel_sdvo_connector;
> 
> -	drm_dbg_kms(&i915->drm, "initialising TV type 0x%x\n", type);
> +	drm_dbg_kms(display->drm, "initialising TV type 0x%x\n", type);
> 
>  	intel_sdvo_connector = intel_sdvo_connector_alloc();
>  	if (!intel_sdvo_connector)
> @@ -2892,13 +2892,13 @@ intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo,
> u16 type)  static bool  intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo,
> u16 type)  {
> -	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	struct drm_encoder *encoder = &intel_sdvo->base.base;
>  	struct drm_connector *connector;
>  	struct intel_connector *intel_connector;
>  	struct intel_sdvo_connector *intel_sdvo_connector;
> 
> -	drm_dbg_kms(&i915->drm, "initialising analog type 0x%x\n", type);
> +	drm_dbg_kms(display->drm, "initialising analog type 0x%x\n", type);
> 
>  	intel_sdvo_connector = intel_sdvo_connector_alloc();
>  	if (!intel_sdvo_connector)
> @@ -2926,12 +2926,11 @@ intel_sdvo_lvds_init(struct intel_sdvo
> *intel_sdvo, u16 type)  {
>  	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	struct drm_encoder *encoder = &intel_sdvo->base.base;
> -	struct drm_i915_private *i915 = to_i915(encoder->dev);
>  	struct drm_connector *connector;
>  	struct intel_connector *intel_connector;
>  	struct intel_sdvo_connector *intel_sdvo_connector;
> 
> -	drm_dbg_kms(&i915->drm, "initialising LVDS type 0x%x\n", type);
> +	drm_dbg_kms(display->drm, "initialising LVDS type 0x%x\n", type);
> 
>  	intel_sdvo_connector = intel_sdvo_connector_alloc();
>  	if (!intel_sdvo_connector)
> @@ -2961,12 +2960,12 @@ intel_sdvo_lvds_init(struct intel_sdvo
> *intel_sdvo, u16 type)
>  	intel_panel_add_vbt_sdvo_fixed_mode(intel_connector);
> 
>  	if (!intel_panel_preferred_fixed_mode(intel_connector)) {
> -		mutex_lock(&i915->drm.mode_config.mutex);
> +		mutex_lock(&display->drm->mode_config.mutex);
> 
>  		intel_ddc_get_modes(connector, connector->ddc);
>  		intel_panel_add_edid_fixed_modes(intel_connector, false);
> 
> -		mutex_unlock(&i915->drm.mode_config.mutex);
> +		mutex_unlock(&display->drm->mode_config.mutex);
>  	}
> 
>  	intel_panel_init(intel_connector, NULL); @@ -3015,7 +3014,7 @@
> static bool intel_sdvo_output_init(struct intel_sdvo *sdvo, u16 type)  static
> bool  intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo)  {
> -	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	static const u16 probe_order[] = {
>  		SDVO_OUTPUT_TMDS0,
>  		SDVO_OUTPUT_TMDS1,
> @@ -3034,7 +3033,7 @@ intel_sdvo_output_setup(struct intel_sdvo
> *intel_sdvo)
>  	flags = intel_sdvo_filter_output_flags(intel_sdvo-
> >caps.output_flags);
> 
>  	if (flags == 0) {
> -		drm_dbg_kms(&i915->drm,
> +		drm_dbg_kms(display->drm,
>  			    "%s: Unknown SDVO output type (0x%04x)\n",
>  			    SDVO_NAME(intel_sdvo), intel_sdvo-
> >caps.output_flags);
>  		return false;
> @@ -3057,11 +3056,11 @@ intel_sdvo_output_setup(struct intel_sdvo
> *intel_sdvo)
> 
>  static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)  {
> -	struct drm_device *dev = intel_sdvo->base.base.dev;
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	struct drm_connector *connector, *tmp;
> 
>  	list_for_each_entry_safe(connector, tmp,
> -				 &dev->mode_config.connector_list, head) {
> +				 &display->drm-
> >mode_config.connector_list, head) {
>  		if (intel_attached_encoder(to_intel_connector(connector))
> == &intel_sdvo->base) {
>  			drm_connector_unregister(connector);
>  			intel_connector_destroy(connector);
> @@ -3073,7 +3072,7 @@ static bool intel_sdvo_tv_create_property(struct
> intel_sdvo *intel_sdvo,
>  					  struct intel_sdvo_connector
> *intel_sdvo_connector,
>  					  int type)
>  {
> -	struct drm_device *dev = intel_sdvo->base.base.dev;
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	struct intel_sdvo_tv_format format;
>  	u32 format_map, i;
> 
> @@ -3098,7 +3097,7 @@ static bool intel_sdvo_tv_create_property(struct
> intel_sdvo *intel_sdvo,
> 
> 
>  	intel_sdvo_connector->tv_format =
> -		drm_property_create(dev, DRM_MODE_PROP_ENUM,
> +		drm_property_create(display->drm,
> DRM_MODE_PROP_ENUM,
>  				    "mode", intel_sdvo_connector-
> >format_supported_num);
>  	if (!intel_sdvo_connector->tv_format)
>  		return false;
> @@ -3120,12 +3119,12 @@ static bool intel_sdvo_tv_create_property(struct
> intel_sdvo *intel_sdvo,
>  		    !intel_sdvo_get_value(intel_sdvo,
> SDVO_CMD_GET_##NAME, &response, 2)) \
>  			return false; \
>  		intel_sdvo_connector->name = \
> -			drm_property_create_range(dev, 0, #name, 0,
> data_value[0]); \
> +			drm_property_create_range(display->drm, 0, #name,
> 0, data_value[0]);
> +\
>  		if (!intel_sdvo_connector->name) return false; \
>  		state_assignment = response; \
>  		drm_object_attach_property(&connector->base, \
>  					   intel_sdvo_connector->name, 0); \
> -		drm_dbg_kms(dev, #name ": max %d, default %d, current
> %d\n", \
> +		drm_dbg_kms(display->drm, #name ": max %d, default %d,
> current %d\n",
> +\
>  			    data_value[0], data_value[1], response); \
>  	} \
>  } while (0)
> @@ -3137,8 +3136,7 @@ intel_sdvo_create_enhance_property_tv(struct
> intel_sdvo *intel_sdvo,
>  				      struct intel_sdvo_connector
> *intel_sdvo_connector,
>  				      struct intel_sdvo_enhancements_reply
> enhancements)  {
> -	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
> -	struct drm_device *dev = intel_sdvo->base.base.dev;
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	struct drm_connector *connector = &intel_sdvo_connector-
> >base.base;
>  	struct drm_connector_state *conn_state = connector->state;
>  	struct intel_sdvo_connector_state *sdvo_state = @@ -3161,7
> +3159,7 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo
> *intel_sdvo,
> 
>  		intel_sdvo_connector->max_hscan = data_value[0];
>  		intel_sdvo_connector->left =
> -			drm_property_create_range(dev, 0, "left_margin", 0,
> data_value[0]);
> +			drm_property_create_range(display->drm, 0,
> "left_margin", 0,
> +data_value[0]);
>  		if (!intel_sdvo_connector->left)
>  			return false;
> 
> @@ -3169,13 +3167,13 @@ intel_sdvo_create_enhance_property_tv(struct
> intel_sdvo *intel_sdvo,
>  					   intel_sdvo_connector->left, 0);
> 
>  		intel_sdvo_connector->right =
> -			drm_property_create_range(dev, 0, "right_margin",
> 0, data_value[0]);
> +			drm_property_create_range(display->drm, 0,
> "right_margin", 0,
> +data_value[0]);
>  		if (!intel_sdvo_connector->right)
>  			return false;
> 
>  		drm_object_attach_property(&connector->base,
>  					   intel_sdvo_connector->right, 0);
> -		drm_dbg_kms(&i915->drm, "h_overscan: max %d, default
> %d, current %d\n",
> +		drm_dbg_kms(display->drm, "h_overscan: max %d, default
> %d, current
> +%d\n",
>  			    data_value[0], data_value[1], response);
>  	}
> 
> @@ -3194,7 +3192,7 @@ intel_sdvo_create_enhance_property_tv(struct
> intel_sdvo *intel_sdvo,
> 
>  		intel_sdvo_connector->max_vscan = data_value[0];
>  		intel_sdvo_connector->top =
> -			drm_property_create_range(dev, 0,
> +			drm_property_create_range(display->drm, 0,
>  						  "top_margin", 0,
> data_value[0]);
>  		if (!intel_sdvo_connector->top)
>  			return false;
> @@ -3203,14 +3201,14 @@ intel_sdvo_create_enhance_property_tv(struct
> intel_sdvo *intel_sdvo,
>  					   intel_sdvo_connector->top, 0);
> 
>  		intel_sdvo_connector->bottom =
> -			drm_property_create_range(dev, 0,
> +			drm_property_create_range(display->drm, 0,
>  						  "bottom_margin", 0,
> data_value[0]);
>  		if (!intel_sdvo_connector->bottom)
>  			return false;
> 
>  		drm_object_attach_property(&connector->base,
>  					   intel_sdvo_connector->bottom, 0);
> -		drm_dbg_kms(&i915->drm, "v_overscan: max %d, default
> %d, current %d\n",
> +		drm_dbg_kms(display->drm, "v_overscan: max %d, default
> %d, current
> +%d\n",
>  			    data_value[0], data_value[1], response);
>  	}
> 
> @@ -3233,13 +3231,13 @@ intel_sdvo_create_enhance_property_tv(struct
> intel_sdvo *intel_sdvo,
> 
>  		sdvo_state->tv.dot_crawl = response & 0x1;
>  		intel_sdvo_connector->dot_crawl =
> -			drm_property_create_range(dev, 0, "dot_crawl", 0,
> 1);
> +			drm_property_create_range(display->drm, 0,
> "dot_crawl", 0, 1);
>  		if (!intel_sdvo_connector->dot_crawl)
>  			return false;
> 
>  		drm_object_attach_property(&connector->base,
>  					   intel_sdvo_connector->dot_crawl,
> 0);
> -		drm_dbg_kms(&i915->drm, "dot crawl: current %d\n",
> response);
> +		drm_dbg_kms(display->drm, "dot crawl: current %d\n",
> response);
>  	}
> 
>  	return true;
> @@ -3250,7 +3248,7 @@ intel_sdvo_create_enhance_property_lvds(struct
> intel_sdvo *intel_sdvo,
>  					struct intel_sdvo_connector
> *intel_sdvo_connector,
>  					struct
> intel_sdvo_enhancements_reply enhancements)  {
> -	struct drm_device *dev = intel_sdvo->base.base.dev;
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	struct drm_connector *connector = &intel_sdvo_connector-
> >base.base;
>  	u16 response, data_value[2];
> 
> @@ -3264,7 +3262,7 @@ intel_sdvo_create_enhance_property_lvds(struct
> intel_sdvo *intel_sdvo,  static bool
> intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
>  					       struct intel_sdvo_connector
> *intel_sdvo_connector)  {
> -	struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
> +	struct intel_display *display = to_intel_display(&intel_sdvo->base);
>  	union {
>  		struct intel_sdvo_enhancements_reply reply;
>  		u16 response;
> @@ -3276,7 +3274,7 @@ static bool
> intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
> 
> SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
>  				  &enhancements, sizeof(enhancements)) ||
>  	    enhancements.response == 0) {
> -		drm_dbg_kms(&i915->drm, "No enhancement is
> supported\n");
> +		drm_dbg_kms(display->drm, "No enhancement is
> supported\n");
>  		return true;
>  	}
> 
> @@ -3351,8 +3349,8 @@ static int
>  intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc,
>  			  struct intel_sdvo *sdvo, int ddc_bus)  {
> -	struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
> -	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> +	struct intel_display *display = to_intel_display(&sdvo->base);
> +	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
> 
>  	ddc->sdvo = sdvo;
>  	ddc->ddc_bus = ddc_bus;
> @@ -3368,25 +3366,26 @@ intel_sdvo_init_ddc_proxy(struct
> intel_sdvo_ddc *ddc,
>  	return i2c_add_adapter(&ddc->ddc);
>  }
> 
> -static bool is_sdvo_port_valid(struct drm_i915_private *dev_priv, enum
> port port)
> +static bool is_sdvo_port_valid(struct intel_display *display, enum port
> +port)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
>  	if (HAS_PCH_SPLIT(dev_priv))
>  		return port == PORT_B;
>  	else
>  		return port == PORT_B || port == PORT_C;  }
> 
> -static bool assert_sdvo_port_valid(struct drm_i915_private *dev_priv,
> -				   enum port port)
> +static bool assert_sdvo_port_valid(struct intel_display *display, enum
> +port port)
>  {
> -	return !drm_WARN(&dev_priv->drm, !is_sdvo_port_valid(dev_priv,
> port),
> +	return !drm_WARN(display->drm, !is_sdvo_port_valid(display, port),
>  			 "Platform does not support SDVO %c\n",
> port_name(port));  }
> 
> -bool intel_sdvo_init(struct drm_i915_private *dev_priv,
> +bool intel_sdvo_init(struct intel_display *display,
>  		     i915_reg_t sdvo_reg, enum port port)  {
> -	struct intel_display *display = &dev_priv->display;
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	struct intel_encoder *intel_encoder;
>  	struct intel_sdvo *intel_sdvo;
>  	int i;
> @@ -3394,7 +3393,7 @@ bool intel_sdvo_init(struct drm_i915_private
> *dev_priv,
>  	if (!assert_port_valid(display, port))
>  		return false;
> 
> -	if (!assert_sdvo_port_valid(dev_priv, port))
> +	if (!assert_sdvo_port_valid(display, port))
>  		return false;
> 
>  	intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); @@ -3407,7
> +3406,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
>  	intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
>  	intel_encoder->port = port;
> 
> -	drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
> +	drm_encoder_init(display->drm, &intel_encoder->base,
>  			 &intel_sdvo_enc_funcs, 0,
>  			 "SDVO %c", port_name(port));
> 
> @@ -3421,7 +3420,7 @@ bool intel_sdvo_init(struct drm_i915_private
> *dev_priv,
>  		u8 byte;
> 
>  		if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
> -			drm_dbg_kms(&dev_priv->drm,
> +			drm_dbg_kms(display->drm,
>  				    "No SDVO device found on %s\n",
>  				    SDVO_NAME(intel_sdvo));
>  			goto err;
> @@ -3459,7 +3458,7 @@ bool intel_sdvo_init(struct drm_i915_private
> *dev_priv,
>  	}
> 
>  	if (!intel_sdvo_output_setup(intel_sdvo)) {
> -		drm_dbg_kms(&dev_priv->drm,
> +		drm_dbg_kms(display->drm,
>  			    "SDVO output failed to setup on %s\n",
>  			    SDVO_NAME(intel_sdvo));
>  		/* Output_setup can leave behind connectors! */ @@ -
> 3496,7 +3495,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
>  						    &intel_sdvo-
> >pixel_clock_max))
>  		goto err_output;
> 
> -	drm_dbg_kms(&dev_priv->drm, "%s device VID/DID:
> %02X:%02X.%02X, "
> +	drm_dbg_kms(display->drm, "%s device VID/DID: %02X:%02X.%02X, "
>  		    "clock range %dMHz - %dMHz, "
>  		    "num inputs: %d, "
>  		    "output 1: %c, output 2: %c\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.h
> b/drivers/gpu/drm/i915/display/intel_sdvo.h
> index d1815b4103d4..1a9e40fdd8a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.h
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.h
> @@ -10,22 +10,22 @@
> 
>  #include "i915_reg_defs.h"
> 
> -struct drm_i915_private;
>  enum pipe;
>  enum port;
> +struct intel_display;
> 
>  #ifdef I915
> -bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
> +bool intel_sdvo_port_enabled(struct intel_display *display,
>  			     i915_reg_t sdvo_reg, enum pipe *pipe); -bool
> intel_sdvo_init(struct drm_i915_private *dev_priv,
> +bool intel_sdvo_init(struct intel_display *display,
>  		     i915_reg_t reg, enum port port);  #else -static inline bool
> intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
> +static inline bool intel_sdvo_port_enabled(struct intel_display
> +*display,
>  					   i915_reg_t sdvo_reg, enum pipe
> *pipe)  {
>  	return false;
>  }
> -static inline bool intel_sdvo_init(struct drm_i915_private *dev_priv,
> +static inline bool intel_sdvo_init(struct intel_display *display,
>  				   i915_reg_t reg, enum port port)
>  {
>  	return false;
> --
> 2.39.5


^ permalink raw reply	[flat|nested] 35+ messages in thread

* RE: [PATCH 08/14] drm/i915/sdvo: convert intel_sdvo.[ch] to struct intel_display
  2025-02-13  9:13   ` Kandpal, Suraj
@ 2025-02-13 11:16     ` Jani Nikula
  0 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2025-02-13 11:16 UTC (permalink / raw)
  To: Kandpal, Suraj, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org

On Thu, 13 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> @@ -1941,12 +1942,13 @@ static enum drm_mode_status
>> intel_sdvo_mode_valid(struct drm_connector *connector,
>>                     const struct drm_display_mode *mode)  {
>> +     struct intel_display *display = to_intel_display(connector->dev);
>
> Why not &i915->display and declare this after i915 declaration

Because i915 will go away eventually, and I don't want to have to change
this line again.

BR,
Jani.


>
> Otherwise LGTM,
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
>
>>       struct drm_i915_private *i915 = to_i915(connector->dev);
>>       struct intel_sdvo *intel_sdvo =
>> intel_attached_sdvo(to_intel_connector(connector));
>>       struct intel_sdvo_connector *intel_sdvo_connector =
>>               to_intel_sdvo_connector(connector);
>>       bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector,
>> connector->state);
>> -     int max_dotclk = i915->display.cdclk.max_dotclk_freq;
>> +     int max_dotclk = display->cdclk.max_dotclk_freq;
>>       enum drm_mode_status status;
>>       int clock = mode->clock;
>>

-- 
Jani Nikula, Intel

^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 09/14] drm/i915/display: convert intel_cpu_transcoder_mode_valid() to intel_display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
                   ` (7 preceding siblings ...)
  2025-02-12 16:36 ` [PATCH 08/14] drm/i915/sdvo: convert intel_sdvo.[ch] to struct intel_display Jani Nikula
@ 2025-02-12 16:36 ` Jani Nikula
  2025-02-13  9:15   ` Kandpal, Suraj
  2025-02-12 16:36 ` [PATCH 10/14] drm/i915/display: convert intel_mode_valid_max_plane_size() " Jani Nikula
                   ` (9 subsequent siblings)
  18 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2025-02-12 16:36 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula

Going forward, struct intel_display is the main display device data
pointer. Convert the intel_cpu_transcoder_mode_valid()() helper to
struct intel_display, allowing further conversions elsewhere.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c       | 4 ++--
 drivers/gpu/drm/i915/display/intel_crt.c     | 2 +-
 drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
 drivers/gpu/drm/i915/display/intel_display.h | 2 +-
 drivers/gpu/drm/i915/display/intel_dp.c      | 2 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c  | 2 +-
 drivers/gpu/drm/i915/display/intel_dvo.c     | 6 +++---
 drivers/gpu/drm/i915/display/intel_hdmi.c    | 2 +-
 drivers/gpu/drm/i915/display/intel_lvds.c    | 6 +++---
 drivers/gpu/drm/i915/display/intel_sdvo.c    | 3 +--
 drivers/gpu/drm/i915/display/intel_tv.c      | 3 +--
 drivers/gpu/drm/i915/display/vlv_dsi.c       | 6 +++---
 12 files changed, 21 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 0f2a19690c18..1f0ff4000658 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1460,10 +1460,10 @@ static void gen11_dsi_post_disable(struct intel_atomic_state *state,
 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
 						 const struct drm_display_mode *mode)
 {
-	struct drm_i915_private *i915 = to_i915(connector->dev);
+	struct intel_display *display = to_intel_display(connector->dev);
 	enum drm_mode_status status;
 
-	status = intel_cpu_transcoder_mode_valid(i915, mode);
+	status = intel_cpu_transcoder_mode_valid(display, mode);
 	if (status != MODE_OK)
 		return status;
 
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 8eedae1d7684..321580b095e7 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -360,7 +360,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
 	enum drm_mode_status status;
 	int max_clock;
 
-	status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
+	status = intel_cpu_transcoder_mode_valid(display, mode);
 	if (status != MODE_OK)
 		return status;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e1186f46088d..7a25c84bfbac 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8464,14 +8464,14 @@ enum drm_mode_status intel_mode_valid(struct drm_device *dev,
 	return MODE_OK;
 }
 
-enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *dev_priv,
+enum drm_mode_status intel_cpu_transcoder_mode_valid(struct intel_display *display,
 						     const struct drm_display_mode *mode)
 {
 	/*
 	 * Additional transcoder timing limits,
 	 * excluding BXT/GLK DSI transcoders.
 	 */
-	if (DISPLAY_VER(dev_priv) >= 5) {
+	if (DISPLAY_VER(display) >= 5) {
 		if (mode->hdisplay < 64 ||
 		    mode->htotal - mode->hdisplay < 32)
 			return MODE_H_ILLEGAL;
@@ -8490,7 +8490,7 @@ enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *de
 	 * Cantiga+ cannot handle modes with a hsync front porch of 0.
 	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
 	 */
-	if ((DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) &&
+	if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) &&
 	    mode->hsync_start == mode->hdisplay)
 		return MODE_H_ILLEGAL;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 9439da737f5b..08e28ea179d2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -428,7 +428,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
 				const struct drm_display_mode *mode,
 				int num_joined_pipes);
 enum drm_mode_status
-intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915,
+intel_cpu_transcoder_mode_valid(struct intel_display *display,
 				const struct drm_display_mode *mode);
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9ed7d46143e9..61827b0fe95e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1407,7 +1407,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 	bool dsc = false;
 	int num_joined_pipes;
 
-	status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
+	status = intel_cpu_transcoder_mode_valid(display, mode);
 	if (status != MODE_OK)
 		return status;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 459440dd6e87..38804254980b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1481,7 +1481,7 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 		return 0;
 	}
 
-	*status = intel_cpu_transcoder_mode_valid(i915, mode);
+	*status = intel_cpu_transcoder_mode_valid(display, mode);
 	if (*status != MODE_OK)
 		return 0;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index 29f8788fb26a..c16fb34b737d 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -219,16 +219,16 @@ static enum drm_mode_status
 intel_dvo_mode_valid(struct drm_connector *_connector,
 		     const struct drm_display_mode *mode)
 {
+	struct intel_display *display = to_intel_display(_connector->dev);
 	struct intel_connector *connector = to_intel_connector(_connector);
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
 	const struct drm_display_mode *fixed_mode =
 		intel_panel_fixed_mode(connector, mode);
-	int max_dotclk = to_i915(connector->base.dev)->display.cdclk.max_dotclk_freq;
+	int max_dotclk = display->cdclk.max_dotclk_freq;
 	int target_clock = mode->clock;
 	enum drm_mode_status status;
 
-	status = intel_cpu_transcoder_mode_valid(i915, mode);
+	status = intel_cpu_transcoder_mode_valid(display, mode);
 	if (status != MODE_OK)
 		return status;
 
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 015110fc57a2..60572deeffb3 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2023,7 +2023,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
 	bool ycbcr_420_only;
 	enum intel_output_format sink_format;
 
-	status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
+	status = intel_cpu_transcoder_mode_valid(display, mode);
 	if (status != MODE_OK)
 		return status;
 
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 6b05db2c10ba..7ed8625193fe 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -394,14 +394,14 @@ static enum drm_mode_status
 intel_lvds_mode_valid(struct drm_connector *_connector,
 		      const struct drm_display_mode *mode)
 {
+	struct intel_display *display = to_intel_display(_connector->dev);
 	struct intel_connector *connector = to_intel_connector(_connector);
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 	const struct drm_display_mode *fixed_mode =
 		intel_panel_fixed_mode(connector, mode);
-	int max_pixclk = to_i915(connector->base.dev)->display.cdclk.max_dotclk_freq;
+	int max_pixclk = display->cdclk.max_dotclk_freq;
 	enum drm_mode_status status;
 
-	status = intel_cpu_transcoder_mode_valid(i915, mode);
+	status = intel_cpu_transcoder_mode_valid(display, mode);
 	if (status != MODE_OK)
 		return status;
 
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 1ae766212e8a..6e2d9929b4d7 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -1943,7 +1943,6 @@ intel_sdvo_mode_valid(struct drm_connector *connector,
 		      const struct drm_display_mode *mode)
 {
 	struct intel_display *display = to_intel_display(connector->dev);
-	struct drm_i915_private *i915 = to_i915(connector->dev);
 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
 	struct intel_sdvo_connector *intel_sdvo_connector =
 		to_intel_sdvo_connector(connector);
@@ -1952,7 +1951,7 @@ intel_sdvo_mode_valid(struct drm_connector *connector,
 	enum drm_mode_status status;
 	int clock = mode->clock;
 
-	status = intel_cpu_transcoder_mode_valid(i915, mode);
+	status = intel_cpu_transcoder_mode_valid(display, mode);
 	if (status != MODE_OK)
 		return status;
 
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
index 7838c92f8ded..5dbe857ea85b 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -960,12 +960,11 @@ intel_tv_mode_valid(struct drm_connector *connector,
 		    const struct drm_display_mode *mode)
 {
 	struct intel_display *display = to_intel_display(connector->dev);
-	struct drm_i915_private *i915 = to_i915(connector->dev);
 	const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
 	int max_dotclk = display->cdclk.max_dotclk_freq;
 	enum drm_mode_status status;
 
-	status = intel_cpu_transcoder_mode_valid(i915, mode);
+	status = intel_cpu_transcoder_mode_valid(display, mode);
 	if (status != MODE_OK)
 		return status;
 
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index d68876fe782c..7414794889e9 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1543,12 +1543,12 @@ static const struct drm_encoder_funcs intel_dsi_funcs = {
 static enum drm_mode_status vlv_dsi_mode_valid(struct drm_connector *connector,
 					       const struct drm_display_mode *mode)
 {
-	struct drm_i915_private *i915 = to_i915(connector->dev);
+	struct intel_display *display = to_intel_display(connector->dev);
 
-	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+	if (display->platform.valleyview || display->platform.cherryview) {
 		enum drm_mode_status status;
 
-		status = intel_cpu_transcoder_mode_valid(i915, mode);
+		status = intel_cpu_transcoder_mode_valid(display, mode);
 		if (status != MODE_OK)
 			return status;
 	}
-- 
2.39.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* RE: [PATCH 09/14] drm/i915/display: convert intel_cpu_transcoder_mode_valid() to intel_display
  2025-02-12 16:36 ` [PATCH 09/14] drm/i915/display: convert intel_cpu_transcoder_mode_valid() to intel_display Jani Nikula
@ 2025-02-13  9:15   ` Kandpal, Suraj
  0 siblings, 0 replies; 35+ messages in thread
From: Kandpal, Suraj @ 2025-02-13  9:15 UTC (permalink / raw)
  To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org
  Cc: Nikula, Jani



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Wednesday, February 12, 2025 10:07 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 09/14] drm/i915/display: convert
> intel_cpu_transcoder_mode_valid() to intel_display
> 
> Going forward, struct intel_display is the main display device data pointer.
> Convert the intel_cpu_transcoder_mode_valid()() helper to struct intel_display,
> allowing further conversions elsewhere.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c       | 4 ++--
>  drivers/gpu/drm/i915/display/intel_crt.c     | 2 +-
>  drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
>  drivers/gpu/drm/i915/display/intel_dp.c      | 2 +-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c  | 2 +-
>  drivers/gpu/drm/i915/display/intel_dvo.c     | 6 +++---
>  drivers/gpu/drm/i915/display/intel_hdmi.c    | 2 +-
>  drivers/gpu/drm/i915/display/intel_lvds.c    | 6 +++---
>  drivers/gpu/drm/i915/display/intel_sdvo.c    | 3 +--
>  drivers/gpu/drm/i915/display/intel_tv.c      | 3 +--
>  drivers/gpu/drm/i915/display/vlv_dsi.c       | 6 +++---
>  12 files changed, 21 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 0f2a19690c18..1f0ff4000658 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1460,10 +1460,10 @@ static void gen11_dsi_post_disable(struct
> intel_atomic_state *state,  static enum drm_mode_status
> gen11_dsi_mode_valid(struct drm_connector *connector,
>  						 const struct
> drm_display_mode *mode)  {
> -	struct drm_i915_private *i915 = to_i915(connector->dev);
> +	struct intel_display *display = to_intel_display(connector->dev);
>  	enum drm_mode_status status;
> 
> -	status = intel_cpu_transcoder_mode_valid(i915, mode);
> +	status = intel_cpu_transcoder_mode_valid(display, mode);
>  	if (status != MODE_OK)
>  		return status;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index 8eedae1d7684..321580b095e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -360,7 +360,7 @@ intel_crt_mode_valid(struct drm_connector
> *connector,
>  	enum drm_mode_status status;
>  	int max_clock;
> 
> -	status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
> +	status = intel_cpu_transcoder_mode_valid(display, mode);
>  	if (status != MODE_OK)
>  		return status;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e1186f46088d..7a25c84bfbac 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8464,14 +8464,14 @@ enum drm_mode_status intel_mode_valid(struct
> drm_device *dev,
>  	return MODE_OK;
>  }
> 
> -enum drm_mode_status intel_cpu_transcoder_mode_valid(struct
> drm_i915_private *dev_priv,
> +enum drm_mode_status intel_cpu_transcoder_mode_valid(struct
> +intel_display *display,
>  						     const struct
> drm_display_mode *mode)  {
>  	/*
>  	 * Additional transcoder timing limits,
>  	 * excluding BXT/GLK DSI transcoders.
>  	 */
> -	if (DISPLAY_VER(dev_priv) >= 5) {
> +	if (DISPLAY_VER(display) >= 5) {
>  		if (mode->hdisplay < 64 ||
>  		    mode->htotal - mode->hdisplay < 32)
>  			return MODE_H_ILLEGAL;
> @@ -8490,7 +8490,7 @@ enum drm_mode_status
> intel_cpu_transcoder_mode_valid(struct drm_i915_private *de
>  	 * Cantiga+ cannot handle modes with a hsync front porch of 0.
>  	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
>  	 */
> -	if ((DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) &&
> +	if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) &&
>  	    mode->hsync_start == mode->hdisplay)
>  		return MODE_H_ILLEGAL;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 9439da737f5b..08e28ea179d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -428,7 +428,7 @@ intel_mode_valid_max_plane_size(struct
> drm_i915_private *dev_priv,
>  				const struct drm_display_mode *mode,
>  				int num_joined_pipes);
>  enum drm_mode_status
> -intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915,
> +intel_cpu_transcoder_mode_valid(struct intel_display *display,
>  				const struct drm_display_mode *mode);
> enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
> bool is_trans_port_sync_mode(const struct intel_crtc_state *state); diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9ed7d46143e9..61827b0fe95e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1407,7 +1407,7 @@ intel_dp_mode_valid(struct drm_connector
> *_connector,
>  	bool dsc = false;
>  	int num_joined_pipes;
> 
> -	status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
> +	status = intel_cpu_transcoder_mode_valid(display, mode);
>  	if (status != MODE_OK)
>  		return status;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 459440dd6e87..38804254980b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1481,7 +1481,7 @@ mst_connector_mode_valid_ctx(struct
> drm_connector *_connector,
>  		return 0;
>  	}
> 
> -	*status = intel_cpu_transcoder_mode_valid(i915, mode);
> +	*status = intel_cpu_transcoder_mode_valid(display, mode);
>  	if (*status != MODE_OK)
>  		return 0;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c
> b/drivers/gpu/drm/i915/display/intel_dvo.c
> index 29f8788fb26a..c16fb34b737d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -219,16 +219,16 @@ static enum drm_mode_status
> intel_dvo_mode_valid(struct drm_connector *_connector,
>  		     const struct drm_display_mode *mode)  {
> +	struct intel_display *display = to_intel_display(_connector->dev);
>  	struct intel_connector *connector = to_intel_connector(_connector);
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
>  	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
>  	const struct drm_display_mode *fixed_mode =
>  		intel_panel_fixed_mode(connector, mode);
> -	int max_dotclk = to_i915(connector->base.dev)-
> >display.cdclk.max_dotclk_freq;
> +	int max_dotclk = display->cdclk.max_dotclk_freq;
>  	int target_clock = mode->clock;
>  	enum drm_mode_status status;
> 
> -	status = intel_cpu_transcoder_mode_valid(i915, mode);
> +	status = intel_cpu_transcoder_mode_valid(display, mode);
>  	if (status != MODE_OK)
>  		return status;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 015110fc57a2..60572deeffb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2023,7 +2023,7 @@ intel_hdmi_mode_valid(struct drm_connector
> *connector,
>  	bool ycbcr_420_only;
>  	enum intel_output_format sink_format;
> 
> -	status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
> +	status = intel_cpu_transcoder_mode_valid(display, mode);
>  	if (status != MODE_OK)
>  		return status;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c
> b/drivers/gpu/drm/i915/display/intel_lvds.c
> index 6b05db2c10ba..7ed8625193fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -394,14 +394,14 @@ static enum drm_mode_status
> intel_lvds_mode_valid(struct drm_connector *_connector,
>  		      const struct drm_display_mode *mode)  {
> +	struct intel_display *display = to_intel_display(_connector->dev);
>  	struct intel_connector *connector = to_intel_connector(_connector);
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
>  	const struct drm_display_mode *fixed_mode =
>  		intel_panel_fixed_mode(connector, mode);
> -	int max_pixclk = to_i915(connector->base.dev)-
> >display.cdclk.max_dotclk_freq;
> +	int max_pixclk = display->cdclk.max_dotclk_freq;
>  	enum drm_mode_status status;
> 
> -	status = intel_cpu_transcoder_mode_valid(i915, mode);
> +	status = intel_cpu_transcoder_mode_valid(display, mode);
>  	if (status != MODE_OK)
>  		return status;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c
> b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index 1ae766212e8a..6e2d9929b4d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -1943,7 +1943,6 @@ intel_sdvo_mode_valid(struct drm_connector
> *connector,
>  		      const struct drm_display_mode *mode)  {
>  	struct intel_display *display = to_intel_display(connector->dev);
> -	struct drm_i915_private *i915 = to_i915(connector->dev);
>  	struct intel_sdvo *intel_sdvo =
> intel_attached_sdvo(to_intel_connector(connector));
>  	struct intel_sdvo_connector *intel_sdvo_connector =
>  		to_intel_sdvo_connector(connector);
> @@ -1952,7 +1951,7 @@ intel_sdvo_mode_valid(struct drm_connector
> *connector,
>  	enum drm_mode_status status;
>  	int clock = mode->clock;
> 
> -	status = intel_cpu_transcoder_mode_valid(i915, mode);
> +	status = intel_cpu_transcoder_mode_valid(display, mode);
>  	if (status != MODE_OK)
>  		return status;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_tv.c
> b/drivers/gpu/drm/i915/display/intel_tv.c
> index 7838c92f8ded..5dbe857ea85b 100644
> --- a/drivers/gpu/drm/i915/display/intel_tv.c
> +++ b/drivers/gpu/drm/i915/display/intel_tv.c
> @@ -960,12 +960,11 @@ intel_tv_mode_valid(struct drm_connector
> *connector,
>  		    const struct drm_display_mode *mode)  {
>  	struct intel_display *display = to_intel_display(connector->dev);
> -	struct drm_i915_private *i915 = to_i915(connector->dev);
>  	const struct tv_mode *tv_mode = intel_tv_mode_find(connector-
> >state);
>  	int max_dotclk = display->cdclk.max_dotclk_freq;
>  	enum drm_mode_status status;
> 
> -	status = intel_cpu_transcoder_mode_valid(i915, mode);
> +	status = intel_cpu_transcoder_mode_valid(display, mode);
>  	if (status != MODE_OK)
>  		return status;
> 
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
> b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index d68876fe782c..7414794889e9 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -1543,12 +1543,12 @@ static const struct drm_encoder_funcs
> intel_dsi_funcs = {  static enum drm_mode_status vlv_dsi_mode_valid(struct
> drm_connector *connector,
>  					       const struct drm_display_mode
> *mode)  {
> -	struct drm_i915_private *i915 = to_i915(connector->dev);
> +	struct intel_display *display = to_intel_display(connector->dev);
> 
> -	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
> +	if (display->platform.valleyview || display->platform.cherryview) {
>  		enum drm_mode_status status;
> 
> -		status = intel_cpu_transcoder_mode_valid(i915, mode);
> +		status = intel_cpu_transcoder_mode_valid(display, mode);
>  		if (status != MODE_OK)
>  			return status;
>  	}
> --
> 2.39.5


^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 10/14] drm/i915/display: convert intel_mode_valid_max_plane_size() to intel_display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
                   ` (8 preceding siblings ...)
  2025-02-12 16:36 ` [PATCH 09/14] drm/i915/display: convert intel_cpu_transcoder_mode_valid() to intel_display Jani Nikula
@ 2025-02-12 16:36 ` Jani Nikula
  2025-02-13  9:16   ` Kandpal, Suraj
  2025-02-12 16:36 ` [PATCH 11/14] drm/i915/dsi: convert platform checks to display->platform.<platform> style Jani Nikula
                   ` (8 subsequent siblings)
  18 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2025-02-12 16:36 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula

Going forward, struct intel_display is the main display device data
pointer. Convert the intel_mode_valid_max_plane_size() helper to struct
intel_display, allowing further conversions elsewhere.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 ++++----
 drivers/gpu/drm/i915/display/intel_display.h | 2 +-
 drivers/gpu/drm/i915/display/intel_dp.c      | 3 +--
 drivers/gpu/drm/i915/display/intel_dp_mst.c  | 3 +--
 drivers/gpu/drm/i915/display/intel_dsi.c     | 8 ++++----
 drivers/gpu/drm/i915/display/intel_hdmi.c    | 3 +--
 6 files changed, 12 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7a25c84bfbac..0450fdf9d4de 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8498,7 +8498,7 @@ enum drm_mode_status intel_cpu_transcoder_mode_valid(struct intel_display *displ
 }
 
 enum drm_mode_status
-intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
+intel_mode_valid_max_plane_size(struct intel_display *display,
 				const struct drm_display_mode *mode,
 				int num_joined_pipes)
 {
@@ -8508,7 +8508,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
 	 * intel_mode_valid() should be
 	 * sufficient on older platforms.
 	 */
-	if (DISPLAY_VER(dev_priv) < 9)
+	if (DISPLAY_VER(display) < 9)
 		return MODE_OK;
 
 	/*
@@ -8516,10 +8516,10 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
 	 * plane so let's not advertize modes that are
 	 * too big for that.
 	 */
-	if (DISPLAY_VER(dev_priv) >= 30) {
+	if (DISPLAY_VER(display) >= 30) {
 		plane_width_max = 6144 * num_joined_pipes;
 		plane_height_max = 4800;
-	} else if (DISPLAY_VER(dev_priv) >= 11) {
+	} else if (DISPLAY_VER(display) >= 11) {
 		plane_width_max = 5120 * num_joined_pipes;
 		plane_height_max = 4320;
 	} else {
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 08e28ea179d2..f702425df305 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -424,7 +424,7 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
 u32 intel_plane_fb_max_stride(struct drm_device *drm,
 			      u32 pixel_format, u64 modifier);
 enum drm_mode_status
-intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
+intel_mode_valid_max_plane_size(struct intel_display *display,
 				const struct drm_display_mode *mode,
 				int num_joined_pipes);
 enum drm_mode_status
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 61827b0fe95e..29970baaf03e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1396,7 +1396,6 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 	struct intel_display *display = to_intel_display(_connector->dev);
 	struct intel_connector *connector = to_intel_connector(_connector);
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
-	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	const struct drm_display_mode *fixed_mode;
 	int target_clock = mode->clock;
 	int max_rate, mode_rate, max_lanes, max_link_clock;
@@ -1496,7 +1495,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 	if (status != MODE_OK)
 		return status;
 
-	return intel_mode_valid_max_plane_size(dev_priv, mode, num_joined_pipes);
+	return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
 }
 
 bool intel_dp_source_supports_tps3(struct intel_display *display)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 38804254980b..73a0a0f9b3d0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1462,7 +1462,6 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 {
 	struct intel_connector *connector = to_intel_connector(_connector);
 	struct intel_display *display = to_intel_display(connector);
-	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct intel_dp *intel_dp = connector->mst_port;
 	struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
 	struct drm_dp_mst_port *port = connector->port;
@@ -1565,7 +1564,7 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 		return 0;
 	}
 
-	*status = intel_mode_valid_max_plane_size(i915, mode, num_joined_pipes);
+	*status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
index c93a3cf75c52..403151175a87 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi.c
@@ -60,14 +60,14 @@ int intel_dsi_get_modes(struct drm_connector *connector)
 enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
 					  const struct drm_display_mode *mode)
 {
-	struct drm_i915_private *dev_priv = to_i915(connector->dev);
+	struct intel_display *display = to_intel_display(connector->dev);
 	struct intel_connector *intel_connector = to_intel_connector(connector);
 	const struct drm_display_mode *fixed_mode =
 		intel_panel_fixed_mode(intel_connector, mode);
-	int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq;
+	int max_dotclk = display->cdclk.max_dotclk_freq;
 	enum drm_mode_status status;
 
-	drm_dbg_kms(&dev_priv->drm, "\n");
+	drm_dbg_kms(display->drm, "\n");
 
 	status = intel_panel_mode_valid(intel_connector, mode);
 	if (status != MODE_OK)
@@ -76,7 +76,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
 	if (fixed_mode->clock > max_dotclk)
 		return MODE_CLOCK_HIGH;
 
-	return intel_mode_valid_max_plane_size(dev_priv, mode, 1);
+	return intel_mode_valid_max_plane_size(display, mode, 1);
 }
 
 struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 60572deeffb3..ed017d9de920 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2015,7 +2015,6 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
 {
 	struct intel_display *display = to_intel_display(connector->dev);
 	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
-	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	enum drm_mode_status status;
 	int clock = mode->clock;
 	int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq;
@@ -2068,7 +2067,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
 			return status;
 	}
 
-	return intel_mode_valid_max_plane_size(dev_priv, mode, 1);
+	return intel_mode_valid_max_plane_size(display, mode, 1);
 }
 
 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
-- 
2.39.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* RE: [PATCH 10/14] drm/i915/display: convert intel_mode_valid_max_plane_size() to intel_display
  2025-02-12 16:36 ` [PATCH 10/14] drm/i915/display: convert intel_mode_valid_max_plane_size() " Jani Nikula
@ 2025-02-13  9:16   ` Kandpal, Suraj
  0 siblings, 0 replies; 35+ messages in thread
From: Kandpal, Suraj @ 2025-02-13  9:16 UTC (permalink / raw)
  To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org
  Cc: Nikula, Jani



> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Wednesday, February 12, 2025 10:07 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH 10/14] drm/i915/display: convert
> intel_mode_valid_max_plane_size() to intel_display
> 
> Going forward, struct intel_display is the main display device data pointer.
> Convert the intel_mode_valid_max_plane_size() helper to struct intel_display,
> allowing further conversions elsewhere.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 8 ++++----
> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
>  drivers/gpu/drm/i915/display/intel_dp.c      | 3 +--
>  drivers/gpu/drm/i915/display/intel_dp_mst.c  | 3 +--
>  drivers/gpu/drm/i915/display/intel_dsi.c     | 8 ++++----
>  drivers/gpu/drm/i915/display/intel_hdmi.c    | 3 +--
>  6 files changed, 12 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 7a25c84bfbac..0450fdf9d4de 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8498,7 +8498,7 @@ enum drm_mode_status
> intel_cpu_transcoder_mode_valid(struct intel_display *displ  }
> 
>  enum drm_mode_status
> -intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> +intel_mode_valid_max_plane_size(struct intel_display *display,
>  				const struct drm_display_mode *mode,
>  				int num_joined_pipes)
>  {
> @@ -8508,7 +8508,7 @@ intel_mode_valid_max_plane_size(struct
> drm_i915_private *dev_priv,
>  	 * intel_mode_valid() should be
>  	 * sufficient on older platforms.
>  	 */
> -	if (DISPLAY_VER(dev_priv) < 9)
> +	if (DISPLAY_VER(display) < 9)
>  		return MODE_OK;
> 
>  	/*
> @@ -8516,10 +8516,10 @@ intel_mode_valid_max_plane_size(struct
> drm_i915_private *dev_priv,
>  	 * plane so let's not advertize modes that are
>  	 * too big for that.
>  	 */
> -	if (DISPLAY_VER(dev_priv) >= 30) {
> +	if (DISPLAY_VER(display) >= 30) {
>  		plane_width_max = 6144 * num_joined_pipes;
>  		plane_height_max = 4800;
> -	} else if (DISPLAY_VER(dev_priv) >= 11) {
> +	} else if (DISPLAY_VER(display) >= 11) {
>  		plane_width_max = 5120 * num_joined_pipes;
>  		plane_height_max = 4320;
>  	} else {
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 08e28ea179d2..f702425df305 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -424,7 +424,7 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
>  u32 intel_plane_fb_max_stride(struct drm_device *drm,
>  			      u32 pixel_format, u64 modifier);  enum
> drm_mode_status -intel_mode_valid_max_plane_size(struct drm_i915_private
> *dev_priv,
> +intel_mode_valid_max_plane_size(struct intel_display *display,
>  				const struct drm_display_mode *mode,
>  				int num_joined_pipes);
>  enum drm_mode_status
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 61827b0fe95e..29970baaf03e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1396,7 +1396,6 @@ intel_dp_mode_valid(struct drm_connector
> *_connector,
>  	struct intel_display *display = to_intel_display(_connector->dev);
>  	struct intel_connector *connector = to_intel_connector(_connector);
>  	struct intel_dp *intel_dp = intel_attached_dp(connector);
> -	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>  	const struct drm_display_mode *fixed_mode;
>  	int target_clock = mode->clock;
>  	int max_rate, mode_rate, max_lanes, max_link_clock; @@ -1496,7
> +1495,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>  	if (status != MODE_OK)
>  		return status;
> 
> -	return intel_mode_valid_max_plane_size(dev_priv, mode,
> num_joined_pipes);
> +	return intel_mode_valid_max_plane_size(display, mode,
> +num_joined_pipes);
>  }
> 
>  bool intel_dp_source_supports_tps3(struct intel_display *display) diff --git
> a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 38804254980b..73a0a0f9b3d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1462,7 +1462,6 @@ mst_connector_mode_valid_ctx(struct
> drm_connector *_connector,  {
>  	struct intel_connector *connector = to_intel_connector(_connector);
>  	struct intel_display *display = to_intel_display(connector);
> -	struct drm_i915_private *i915 = to_i915(display->drm);
>  	struct intel_dp *intel_dp = connector->mst_port;
>  	struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
>  	struct drm_dp_mst_port *port = connector->port; @@ -1565,7
> +1564,7 @@ mst_connector_mode_valid_ctx(struct drm_connector
> *_connector,
>  		return 0;
>  	}
> 
> -	*status = intel_mode_valid_max_plane_size(i915, mode,
> num_joined_pipes);
> +	*status = intel_mode_valid_max_plane_size(display, mode,
> +num_joined_pipes);
>  	return 0;
>  }
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c
> b/drivers/gpu/drm/i915/display/intel_dsi.c
> index c93a3cf75c52..403151175a87 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsi.c
> @@ -60,14 +60,14 @@ int intel_dsi_get_modes(struct drm_connector
> *connector)  enum drm_mode_status intel_dsi_mode_valid(struct
> drm_connector *connector,
>  					  const struct drm_display_mode
> *mode)  {
> -	struct drm_i915_private *dev_priv = to_i915(connector->dev);
> +	struct intel_display *display = to_intel_display(connector->dev);
>  	struct intel_connector *intel_connector =
> to_intel_connector(connector);
>  	const struct drm_display_mode *fixed_mode =
>  		intel_panel_fixed_mode(intel_connector, mode);
> -	int max_dotclk = to_i915(connector->dev)-
> >display.cdclk.max_dotclk_freq;
> +	int max_dotclk = display->cdclk.max_dotclk_freq;
>  	enum drm_mode_status status;
> 
> -	drm_dbg_kms(&dev_priv->drm, "\n");
> +	drm_dbg_kms(display->drm, "\n");
> 
>  	status = intel_panel_mode_valid(intel_connector, mode);
>  	if (status != MODE_OK)
> @@ -76,7 +76,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct
> drm_connector *connector,
>  	if (fixed_mode->clock > max_dotclk)
>  		return MODE_CLOCK_HIGH;
> 
> -	return intel_mode_valid_max_plane_size(dev_priv, mode, 1);
> +	return intel_mode_valid_max_plane_size(display, mode, 1);
>  }
> 
>  struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, diff --git
> a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 60572deeffb3..ed017d9de920 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2015,7 +2015,6 @@ intel_hdmi_mode_valid(struct drm_connector
> *connector,  {
>  	struct intel_display *display = to_intel_display(connector->dev);
>  	struct intel_hdmi *hdmi =
> intel_attached_hdmi(to_intel_connector(connector));
> -	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	enum drm_mode_status status;
>  	int clock = mode->clock;
>  	int max_dotclk = to_i915(connector->dev)-
> >display.cdclk.max_dotclk_freq;
> @@ -2068,7 +2067,7 @@ intel_hdmi_mode_valid(struct drm_connector
> *connector,
>  			return status;
>  	}
> 
> -	return intel_mode_valid_max_plane_size(dev_priv, mode, 1);
> +	return intel_mode_valid_max_plane_size(display, mode, 1);
>  }
> 
>  bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
> --
> 2.39.5


^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 11/14] drm/i915/dsi: convert platform checks to display->platform.<platform> style
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
                   ` (9 preceding siblings ...)
  2025-02-12 16:36 ` [PATCH 10/14] drm/i915/display: convert intel_mode_valid_max_plane_size() " Jani Nikula
@ 2025-02-12 16:36 ` Jani Nikula
  2025-02-12 16:36 ` [PATCH 12/14] drm/i915/combo-phy: convert intel_combo_phy.[ch] to struct intel_display Jani Nikula
                   ` (7 subsequent siblings)
  18 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2025-02-12 16:36 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula

These are stragglers from a time the display->platform mechanism didn't
exist. Finish the conversion.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 1f0ff4000658..e84a362b54c9 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -345,7 +345,6 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
 					  const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 	enum port port;
 	int afe_clk_khz;
@@ -354,7 +353,7 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
 
 	afe_clk_khz = afe_clk(encoder, crtc_state);
 
-	if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
+	if (display->platform.alderlake_s || display->platform.alderlake_p) {
 		theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK);
 		act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2);
 		esc_clk_div_m = act_word_clk * 8;
@@ -375,7 +374,7 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
 		intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port));
 	}
 
-	if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
+	if (display->platform.alderlake_s || display->platform.alderlake_p) {
 		for_each_dsi_port(port, intel_dsi->ports) {
 			intel_de_write(display, ADL_MIPIO_DW(port, 8),
 				       esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY);
@@ -426,7 +425,6 @@ static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 	enum phy phy;
 	u32 tmp;
@@ -451,7 +449,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 		intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
 
 		/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
-		if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) ||
+		if (display->platform.jasperlake || display->platform.elkhartlake ||
 		    (DISPLAY_VER(display) >= 12)) {
 			intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy),
 				     LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
@@ -533,7 +531,6 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
 			     const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 	enum port port;
 	enum phy phy;
@@ -563,7 +560,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
 		}
 	}
 
-	if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
+	if (display->platform.jasperlake || display->platform.elkhartlake) {
 		for_each_dsi_phy(phy, intel_dsi->phys)
 			intel_de_rmw(display, ICL_DPHY_CHKN(phy),
 				     0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
-- 
2.39.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* [PATCH 12/14] drm/i915/combo-phy: convert intel_combo_phy.[ch] to struct intel_display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
                   ` (10 preceding siblings ...)
  2025-02-12 16:36 ` [PATCH 11/14] drm/i915/dsi: convert platform checks to display->platform.<platform> style Jani Nikula
@ 2025-02-12 16:36 ` Jani Nikula
  2025-02-12 16:36 ` [PATCH 13/14] drm/i915/display: convert intel_fifo_underrun.[ch] " Jani Nikula
                   ` (6 subsequent siblings)
  18 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2025-02-12 16:36 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula

Going forward, struct intel_display is the main display device data
pointer. Convert as much as possible of intel_combo_phy.[ch] to struct
intel_display, along with intel_phy_is_combo() in intel_display.c.

Drive-by convert some drm_dbg() to drm_dbg_kms() while at it.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        |   6 +-
 .../gpu/drm/i915/display/intel_combo_phy.c    | 180 +++++++++---------
 .../gpu/drm/i915/display/intel_combo_phy.h    |   8 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |   4 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  14 +-
 drivers/gpu/drm/i915/display/intel_display.h  |   2 +-
 .../drm/i915/display/intel_display_power.c    |   5 +-
 .../i915/display/intel_display_power_well.c   |   3 +-
 8 files changed, 109 insertions(+), 113 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index e84a362b54c9..9600c2a346d4 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -31,8 +31,8 @@
 #include <drm/drm_mipi_dsi.h>
 #include <drm/drm_probe_helper.h>
 
-#include "i915_drv.h"
 #include "i915_reg.h"
+#include "i915_utils.h"
 #include "icl_dsi.h"
 #include "icl_dsi_regs.h"
 #include "intel_atomic.h"
@@ -413,12 +413,12 @@ static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
 
 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 	enum phy phy;
 
 	for_each_dsi_phy(phy, intel_dsi->phys)
-		intel_combo_phy_power_up_lanes(dev_priv, phy, true,
+		intel_combo_phy_power_up_lanes(display, phy, true,
 					       intel_dsi->lane_count, false);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 4fbe2e3542ca..17eea244cc83 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -3,20 +3,20 @@
  * Copyright © 2018 Intel Corporation
  */
 
-#include "i915_drv.h"
 #include "i915_reg.h"
+#include "i915_utils.h"
 #include "intel_combo_phy.h"
 #include "intel_combo_phy_regs.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
 
-#define for_each_combo_phy(__dev_priv, __phy) \
+#define for_each_combo_phy(__display, __phy) \
 	for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)	\
-		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
+		for_each_if(intel_phy_is_combo(__display, __phy))
 
-#define for_each_combo_phy_reverse(__dev_priv, __phy) \
+#define for_each_combo_phy_reverse(__display, __phy) \
 	for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
-		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
+		for_each_if(intel_phy_is_combo(__display, __phy))
 
 enum {
 	PROCMON_0_85V_DOT_0,
@@ -53,11 +53,11 @@ static const struct icl_procmon {
 };
 
 static const struct icl_procmon *
-icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
+icl_get_procmon_ref_values(struct intel_display *display, enum phy phy)
 {
 	u32 val;
 
-	val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy));
+	val = intel_de_read(display, ICL_PORT_COMP_DW3(phy));
 	switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
 	default:
 		MISSING_CASE(val);
@@ -75,57 +75,57 @@ icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
 	}
 }
 
-static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
+static void icl_set_procmon_ref_values(struct intel_display *display,
 				       enum phy phy)
 {
 	const struct icl_procmon *procmon;
 
-	procmon = icl_get_procmon_ref_values(dev_priv, phy);
+	procmon = icl_get_procmon_ref_values(display, phy);
 
-	intel_de_rmw(dev_priv, ICL_PORT_COMP_DW1(phy),
+	intel_de_rmw(display, ICL_PORT_COMP_DW1(phy),
 		     (0xff << 16) | 0xff, procmon->dw1);
 
-	intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9);
-	intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10);
+	intel_de_write(display, ICL_PORT_COMP_DW9(phy), procmon->dw9);
+	intel_de_write(display, ICL_PORT_COMP_DW10(phy), procmon->dw10);
 }
 
-static bool check_phy_reg(struct drm_i915_private *dev_priv,
+static bool check_phy_reg(struct intel_display *display,
 			  enum phy phy, i915_reg_t reg, u32 mask,
 			  u32 expected_val)
 {
-	u32 val = intel_de_read(dev_priv, reg);
+	u32 val = intel_de_read(display, reg);
 
 	if ((val & mask) != expected_val) {
-		drm_dbg(&dev_priv->drm,
-			"Combo PHY %c reg %08x state mismatch: "
-			"current %08x mask %08x expected %08x\n",
-			phy_name(phy),
-			reg.reg, val, mask, expected_val);
+		drm_dbg_kms(display->drm,
+			    "Combo PHY %c reg %08x state mismatch: "
+			    "current %08x mask %08x expected %08x\n",
+			    phy_name(phy),
+			    reg.reg, val, mask, expected_val);
 		return false;
 	}
 
 	return true;
 }
 
-static bool icl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
+static bool icl_verify_procmon_ref_values(struct intel_display *display,
 					  enum phy phy)
 {
 	const struct icl_procmon *procmon;
 	bool ret;
 
-	procmon = icl_get_procmon_ref_values(dev_priv, phy);
+	procmon = icl_get_procmon_ref_values(display, phy);
 
-	ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
+	ret = check_phy_reg(display, phy, ICL_PORT_COMP_DW1(phy),
 			    (0xff << 16) | 0xff, procmon->dw1);
-	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
+	ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW9(phy),
 			     -1U, procmon->dw9);
-	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
+	ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW10(phy),
 			     -1U, procmon->dw10);
 
 	return ret;
 }
 
-static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
+static bool has_phy_misc(struct intel_display *display, enum phy phy)
 {
 	/*
 	 * Some platforms only expect PHY_MISC to be programmed for PHY-A and
@@ -136,32 +136,30 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
 	 * that we program it for PHY A.
 	 */
 
-	if (IS_ALDERLAKE_S(i915))
+	if (display->platform.alderlake_s)
 		return phy == PHY_A;
-	else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) ||
-		 IS_ROCKETLAKE(i915) ||
-		 IS_DG1(i915))
+	else if ((display->platform.jasperlake || display->platform.elkhartlake) ||
+		 display->platform.rocketlake ||
+		 display->platform.dg1)
 		return phy < PHY_C;
 
 	return true;
 }
 
-static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
+static bool icl_combo_phy_enabled(struct intel_display *display,
 				  enum phy phy)
 {
 	/* The PHY C added by EHL has no PHY_MISC register */
-	if (!has_phy_misc(dev_priv, phy))
-		return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
+	if (!has_phy_misc(display, phy))
+		return intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
 	else
-		return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) &
+		return !(intel_de_read(display, ICL_PHY_MISC(phy)) &
 			 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
-			(intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
+			(intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
 }
 
-static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915)
+static bool ehl_vbt_ddi_d_present(struct intel_display *display)
 {
-	struct intel_display *display = &i915->display;
-
 	bool ddi_a_present = intel_bios_is_port_present(display, PORT_A);
 	bool ddi_d_present = intel_bios_is_port_present(display, PORT_D);
 	bool dsi_present = intel_bios_is_dsi_present(display, NULL);
@@ -181,13 +179,13 @@ static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915)
 	 * in the log and let the internal display win.
 	 */
 	if (ddi_d_present)
-		drm_err(&i915->drm,
+		drm_err(display->drm,
 			"VBT claims to have both internal and external displays on PHY A.  Configuring for internal.\n");
 
 	return false;
 }
 
-static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
+static bool phy_is_master(struct intel_display *display, enum phy phy)
 {
 	/*
 	 * Certain PHYs are connected to compensation resistors and act
@@ -207,64 +205,64 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
 	 */
 	if (phy == PHY_A)
 		return true;
-	else if (IS_ALDERLAKE_S(dev_priv))
+	else if (display->platform.alderlake_s)
 		return phy == PHY_D;
-	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+	else if (display->platform.dg1 || display->platform.rocketlake)
 		return phy == PHY_C;
 
 	return false;
 }
 
-static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
+static bool icl_combo_phy_verify_state(struct intel_display *display,
 				       enum phy phy)
 {
 	bool ret = true;
 	u32 expected_val = 0;
 
-	if (!icl_combo_phy_enabled(dev_priv, phy))
+	if (!icl_combo_phy_enabled(display, phy))
 		return false;
 
-	if (DISPLAY_VER(dev_priv) >= 12) {
-		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy),
+	if (DISPLAY_VER(display) >= 12) {
+		ret &= check_phy_reg(display, phy, ICL_PORT_TX_DW8_LN(0, phy),
 				     ICL_PORT_TX_DW8_ODCC_CLK_SEL |
 				     ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
 				     ICL_PORT_TX_DW8_ODCC_CLK_SEL |
 				     ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
 
-		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),
+		ret &= check_phy_reg(display, phy, ICL_PORT_PCS_DW1_LN(0, phy),
 				     DCC_MODE_SELECT_MASK, RUN_DCC_ONCE);
 	}
 
-	ret &= icl_verify_procmon_ref_values(dev_priv, phy);
+	ret &= icl_verify_procmon_ref_values(display, phy);
 
-	if (phy_is_master(dev_priv, phy)) {
-		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
+	if (phy_is_master(display, phy)) {
+		ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW8(phy),
 				     IREFGEN, IREFGEN);
 
-		if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
-			if (ehl_vbt_ddi_d_present(dev_priv))
+		if (display->platform.jasperlake || display->platform.elkhartlake) {
+			if (ehl_vbt_ddi_d_present(display))
 				expected_val = ICL_PHY_MISC_MUX_DDID;
 
-			ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy),
+			ret &= check_phy_reg(display, phy, ICL_PHY_MISC(phy),
 					     ICL_PHY_MISC_MUX_DDID,
 					     expected_val);
 		}
 	}
 
-	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
+	ret &= check_phy_reg(display, phy, ICL_PORT_CL_DW5(phy),
 			     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
 
 	return ret;
 }
 
-void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
+void intel_combo_phy_power_up_lanes(struct intel_display *display,
 				    enum phy phy, bool is_dsi,
 				    int lane_count, bool lane_reversal)
 {
 	u8 lane_mask;
 
 	if (is_dsi) {
-		drm_WARN_ON(&dev_priv->drm, lane_reversal);
+		drm_WARN_ON(display->drm, lane_reversal);
 
 		switch (lane_count) {
 		case 1:
@@ -302,28 +300,28 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
 		}
 	}
 
-	intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy),
+	intel_de_rmw(display, ICL_PORT_CL_DW10(phy),
 		     PWR_DOWN_LN_MASK, lane_mask);
 }
 
-static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
+static void icl_combo_phys_init(struct intel_display *display)
 {
 	enum phy phy;
 
-	for_each_combo_phy(dev_priv, phy) {
+	for_each_combo_phy(display, phy) {
 		const struct icl_procmon *procmon;
 		u32 val;
 
-		if (icl_combo_phy_verify_state(dev_priv, phy))
+		if (icl_combo_phy_verify_state(display, phy))
 			continue;
 
-		procmon = icl_get_procmon_ref_values(dev_priv, phy);
+		procmon = icl_get_procmon_ref_values(display, phy);
 
-		drm_dbg(&dev_priv->drm,
-			"Initializing combo PHY %c (Voltage/Process Info : %s)\n",
-			phy_name(phy), procmon->name);
+		drm_dbg_kms(display->drm,
+			    "Initializing combo PHY %c (Voltage/Process Info : %s)\n",
+			    phy_name(phy), procmon->name);
 
-		if (!has_phy_misc(dev_priv, phy))
+		if (!has_phy_misc(display, phy))
 			goto skip_phy_misc;
 
 		/*
@@ -334,84 +332,84 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 		 * based on whether our VBT indicates the presence of any
 		 * "internal" child devices.
 		 */
-		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
-		if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
+		val = intel_de_read(display, ICL_PHY_MISC(phy));
+		if ((display->platform.jasperlake || display->platform.elkhartlake) &&
 		    phy == PHY_A) {
 			val &= ~ICL_PHY_MISC_MUX_DDID;
 
-			if (ehl_vbt_ddi_d_present(dev_priv))
+			if (ehl_vbt_ddi_d_present(display))
 				val |= ICL_PHY_MISC_MUX_DDID;
 		}
 
 		val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
-		intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
+		intel_de_write(display, ICL_PHY_MISC(phy), val);
 
 skip_phy_misc:
-		if (DISPLAY_VER(dev_priv) >= 12) {
-			val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy));
+		if (DISPLAY_VER(display) >= 12) {
+			val = intel_de_read(display, ICL_PORT_TX_DW8_LN(0, phy));
 			val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
 			val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
 			val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
-			intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
+			intel_de_write(display, ICL_PORT_TX_DW8_GRP(phy), val);
 
-			val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
+			val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
 			val &= ~DCC_MODE_SELECT_MASK;
 			val |= RUN_DCC_ONCE;
-			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
+			intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val);
 		}
 
-		icl_set_procmon_ref_values(dev_priv, phy);
+		icl_set_procmon_ref_values(display, phy);
 
-		if (phy_is_master(dev_priv, phy))
-			intel_de_rmw(dev_priv, ICL_PORT_COMP_DW8(phy),
+		if (phy_is_master(display, phy))
+			intel_de_rmw(display, ICL_PORT_COMP_DW8(phy),
 				     0, IREFGEN);
 
-		intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT);
-		intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy),
+		intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT);
+		intel_de_rmw(display, ICL_PORT_CL_DW5(phy),
 			     0, CL_POWER_DOWN_ENABLE);
 	}
 }
 
-static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
+static void icl_combo_phys_uninit(struct intel_display *display)
 {
 	enum phy phy;
 
-	for_each_combo_phy_reverse(dev_priv, phy) {
+	for_each_combo_phy_reverse(display, phy) {
 		if (phy == PHY_A &&
-		    !icl_combo_phy_verify_state(dev_priv, phy)) {
-			if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) {
+		    !icl_combo_phy_verify_state(display, phy)) {
+			if (display->platform.tigerlake || display->platform.dg1) {
 				/*
 				 * A known problem with old ifwi:
 				 * https://gitlab.freedesktop.org/drm/intel/-/issues/2411
 				 * Suppress the warning for CI. Remove ASAP!
 				 */
-				drm_dbg_kms(&dev_priv->drm,
+				drm_dbg_kms(display->drm,
 					    "Combo PHY %c HW state changed unexpectedly\n",
 					    phy_name(phy));
 			} else {
-				drm_warn(&dev_priv->drm,
+				drm_warn(display->drm,
 					 "Combo PHY %c HW state changed unexpectedly\n",
 					 phy_name(phy));
 			}
 		}
 
-		if (!has_phy_misc(dev_priv, phy))
+		if (!has_phy_misc(display, phy))
 			goto skip_phy_misc;
 
-		intel_de_rmw(dev_priv, ICL_PHY_MISC(phy), 0,
+		intel_de_rmw(display, ICL_PHY_MISC(phy), 0,
 			     ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN);
 
 skip_phy_misc:
-		intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0);
+		intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0);
 	}
 }
 
-void intel_combo_phy_init(struct drm_i915_private *i915)
+void intel_combo_phy_init(struct intel_display *display)
 {
-	icl_combo_phys_init(i915);
+	icl_combo_phys_init(display);
 }
 
-void intel_combo_phy_uninit(struct drm_i915_private *i915)
+void intel_combo_phy_uninit(struct intel_display *display)
 {
-	icl_combo_phys_uninit(i915);
+	icl_combo_phys_uninit(display);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.h b/drivers/gpu/drm/i915/display/intel_combo_phy.h
index 660886f86c59..3f5dba78e533 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.h
@@ -8,12 +8,12 @@
 
 #include <linux/types.h>
 
-struct drm_i915_private;
 enum phy;
+struct intel_display;
 
-void intel_combo_phy_init(struct drm_i915_private *dev_priv);
-void intel_combo_phy_uninit(struct drm_i915_private *dev_priv);
-void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
+void intel_combo_phy_init(struct intel_display *display);
+void intel_combo_phy_uninit(struct intel_display *display);
+void intel_combo_phy_power_up_lanes(struct intel_display *display,
 				    enum phy phy, bool is_dsi,
 				    int lane_count, bool lane_reversal);
 
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 900e066b2478..5433279227e1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2437,13 +2437,13 @@ static void intel_ddi_disable_fec(struct intel_encoder *encoder,
 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
 				     const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
 	if (intel_encoder_is_combo(encoder)) {
 		enum phy phy = intel_encoder_to_phy(encoder);
 
-		intel_combo_phy_power_up_lanes(i915, phy, false,
+		intel_combo_phy_power_up_lanes(display, phy, false,
 					       crtc_state->lane_count,
 					       dig_port->lane_reversal);
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0450fdf9d4de..23d4e4c6bd6b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1995,17 +1995,17 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
 }
 
 /* Prefer intel_encoder_is_combo() */
-bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
+bool intel_phy_is_combo(struct intel_display *display, enum phy phy)
 {
 	if (phy == PHY_NONE)
 		return false;
-	else if (IS_ALDERLAKE_S(dev_priv))
+	else if (display->platform.alderlake_s)
 		return phy <= PHY_E;
-	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+	else if (display->platform.dg1 || display->platform.rocketlake)
 		return phy <= PHY_D;
-	else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
+	else if (display->platform.jasperlake || display->platform.elkhartlake)
 		return phy <= PHY_C;
-	else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
+	else if (display->platform.alderlake_p || IS_DISPLAY_VER(display, 11, 12))
 		return phy <= PHY_B;
 	else
 		/*
@@ -2085,9 +2085,9 @@ enum phy intel_encoder_to_phy(struct intel_encoder *encoder)
 
 bool intel_encoder_is_combo(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 
-	return intel_phy_is_combo(i915, intel_encoder_to_phy(encoder));
+	return intel_phy_is_combo(display, intel_encoder_to_phy(encoder));
 }
 
 bool intel_encoder_is_snps(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index f702425df305..d4a709588700 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -476,7 +476,7 @@ struct drm_display_mode *
 intel_encoder_current_mode(struct intel_encoder *encoder);
 void intel_encoder_get_config(struct intel_encoder *encoder,
 			      struct intel_crtc_state *crtc_state);
-bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
+bool intel_phy_is_combo(struct intel_display *display, enum phy phy);
 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index d93f43d145a9..396930937d98 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1651,7 +1651,7 @@ static void icl_display_core_init(struct intel_display *display,
 		return;
 
 	/* 2. Initialize all combo phys */
-	intel_combo_phy_init(dev_priv);
+	intel_combo_phy_init(display);
 
 	/*
 	 * 3. Enable Power Well 1 (PG1).
@@ -1714,7 +1714,6 @@ static void icl_display_core_init(struct intel_display *display,
 
 static void icl_display_core_uninit(struct intel_display *display)
 {
-	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	struct i915_power_domains *power_domains = &display->power.domains;
 	struct i915_power_well *well;
 
@@ -1747,7 +1746,7 @@ static void icl_display_core_uninit(struct intel_display *display)
 	mutex_unlock(&power_domains->lock);
 
 	/* 5. */
-	intel_combo_phy_uninit(dev_priv);
+	intel_combo_phy_uninit(display);
 }
 
 static void chv_phy_control_init(struct intel_display *display)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 6fbb94c8bfb3..5b60db597329 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -973,7 +973,6 @@ static void gen9_assert_dbuf_enabled(struct intel_display *display)
 
 void gen9_disable_dc_states(struct intel_display *display)
 {
-	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	struct i915_power_domains *power_domains = &display->power.domains;
 	struct intel_cdclk_config cdclk_config = {};
 	u32 old_state = power_domains->dc_state;
@@ -1013,7 +1012,7 @@ void gen9_disable_dc_states(struct intel_display *display)
 		 * PHY's HW context for port B is lost after DC transitions,
 		 * so we need to restore it manually.
 		 */
-		intel_combo_phy_init(dev_priv);
+		intel_combo_phy_init(display);
 }
 
 static void gen9_dc_off_power_well_enable(struct intel_display *display,
-- 
2.39.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* [PATCH 13/14] drm/i915/display: convert intel_fifo_underrun.[ch] to struct intel_display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
                   ` (11 preceding siblings ...)
  2025-02-12 16:36 ` [PATCH 12/14] drm/i915/combo-phy: convert intel_combo_phy.[ch] to struct intel_display Jani Nikula
@ 2025-02-12 16:36 ` Jani Nikula
  2025-02-12 16:36 ` [PATCH 14/14] drm/i915/display: convert i915_pipestat_enable_mask() " Jani Nikula
                   ` (5 subsequent siblings)
  18 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2025-02-12 16:36 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula

Going forward, struct intel_display is the main display device data
pointer. Convert as much as possible of intel_fifo_underrun.[ch] to
struct intel_display.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  4 +-
 .../gpu/drm/i915/display/intel_display_irq.c  | 18 ++--
 .../drm/i915/display/intel_fifo_underrun.c    | 93 ++++++++++---------
 .../drm/i915/display/intel_fifo_underrun.h    | 11 +--
 .../drm/i915/display/intel_modeset_setup.c    |  6 +-
 6 files changed, 67 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 89785da93603..5ecf7d1a5f18 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -328,7 +328,7 @@ int intel_crtc_init(struct intel_display *display, enum pipe pipe)
 	}
 	crtc->plane_ids_mask |= BIT(primary->id);
 
-	intel_init_fifo_underrun_reporting(dev_priv, crtc, false);
+	intel_init_fifo_underrun_reporting(display, crtc, false);
 
 	for_each_sprite(display, pipe, sprite) {
 		struct intel_plane *plane;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 23d4e4c6bd6b..b491a1638a00 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7954,8 +7954,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	}
 
 	/* Underruns don't always raise interrupts, so check manually */
-	intel_check_cpu_fifo_underruns(dev_priv);
-	intel_check_pch_fifo_underruns(dev_priv);
+	intel_check_cpu_fifo_underruns(display);
+	intel_check_pch_fifo_underruns(display);
 
 	if (state->modeset)
 		intel_verify_planes(state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 0f68b0a34ca9..b8fcf74bd3ac 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -562,7 +562,7 @@ void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
 			i9xx_pipe_crc_irq_handler(dev_priv, pipe);
 
 		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
-			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
+			intel_cpu_fifo_underrun_irq_handler(display, pipe);
 	}
 
 	if (blc_event || (iir & I915_ASLE_INTERRUPT))
@@ -587,7 +587,7 @@ void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
 			i9xx_pipe_crc_irq_handler(dev_priv, pipe);
 
 		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
-			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
+			intel_cpu_fifo_underrun_irq_handler(display, pipe);
 	}
 
 	if (blc_event || (iir & I915_ASLE_INTERRUPT))
@@ -614,7 +614,7 @@ void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
 			i9xx_pipe_crc_irq_handler(dev_priv, pipe);
 
 		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
-			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
+			intel_cpu_fifo_underrun_irq_handler(display, pipe);
 	}
 
 	if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
@@ -666,10 +666,10 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 			"PCH transcoder CRC error interrupt\n");
 
 	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
-		intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
+		intel_pch_fifo_underrun_irq_handler(display, PIPE_A);
 
 	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
-		intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
+		intel_pch_fifo_underrun_irq_handler(display, PIPE_B);
 }
 
 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
@@ -683,7 +683,7 @@ static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
 
 	for_each_pipe(dev_priv, pipe) {
 		if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
-			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
+			intel_cpu_fifo_underrun_irq_handler(display, pipe);
 
 		if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
 			if (IS_IVYBRIDGE(dev_priv))
@@ -707,7 +707,7 @@ static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
 
 	for_each_pipe(dev_priv, pipe)
 		if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
-			intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
+			intel_pch_fifo_underrun_irq_handler(display, pipe);
 
 	intel_de_write(display, SERR_INT, serr_int);
 }
@@ -776,7 +776,7 @@ void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)
 			flip_done_handler(dev_priv, pipe);
 
 		if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
-			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
+			intel_cpu_fifo_underrun_irq_handler(display, pipe);
 
 		if (de_iir & DE_PIPE_CRC_DONE(pipe))
 			i9xx_pipe_crc_irq_handler(dev_priv, pipe);
@@ -1228,7 +1228,7 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 			hsw_pipe_crc_irq_handler(dev_priv, pipe);
 
 		if (iir & GEN8_PIPE_FIFO_UNDERRUN)
-			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
+			intel_cpu_fifo_underrun_irq_handler(display, pipe);
 
 		fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
 		if (fault_errors)
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index cf70dab4881b..14b00988a81f 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -63,7 +63,7 @@ static bool ivb_can_enable_err_int(struct intel_display *display)
 
 	lockdep_assert_held(&dev_priv->irq_lock);
 
-	for_each_pipe(dev_priv, pipe) {
+	for_each_pipe(display, pipe) {
 		crtc = intel_crtc_for_pipe(display, pipe);
 
 		if (crtc->cpu_fifo_underrun_disabled)
@@ -81,7 +81,7 @@ static bool cpt_can_enable_serr_int(struct intel_display *display)
 
 	lockdep_assert_held(&dev_priv->irq_lock);
 
-	for_each_pipe(dev_priv, pipe) {
+	for_each_pipe(display, pipe) {
 		crtc = intel_crtc_for_pipe(display, pipe);
 
 		if (crtc->pch_fifo_underrun_disabled)
@@ -95,20 +95,20 @@ static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
 {
 	struct intel_display *display = to_intel_display(crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	i915_reg_t reg = PIPESTAT(dev_priv, crtc->pipe);
+	i915_reg_t reg = PIPESTAT(display, crtc->pipe);
 	u32 enable_mask;
 
 	lockdep_assert_held(&dev_priv->irq_lock);
 
-	if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
+	if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
 		return;
 
 	enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);
-	intel_de_write(dev_priv, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
-	intel_de_posting_read(dev_priv, reg);
+	intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
+	intel_de_posting_read(display, reg);
 
 	trace_intel_cpu_fifo_underrun(display, crtc->pipe);
-	drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));
+	drm_err(display->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));
 }
 
 static void i9xx_set_fifo_underrun_reporting(struct intel_display *display,
@@ -116,19 +116,19 @@ static void i9xx_set_fifo_underrun_reporting(struct intel_display *display,
 					     bool enable, bool old)
 {
 	struct drm_i915_private *dev_priv = to_i915(display->drm);
-	i915_reg_t reg = PIPESTAT(dev_priv, pipe);
+	i915_reg_t reg = PIPESTAT(display, pipe);
 
 	lockdep_assert_held(&dev_priv->irq_lock);
 
 	if (enable) {
 		u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
 
-		intel_de_write(dev_priv, reg,
+		intel_de_write(display, reg,
 			       enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
-		intel_de_posting_read(dev_priv, reg);
+		intel_de_posting_read(display, reg);
 	} else {
-		if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS)
-			drm_err(&dev_priv->drm, "pipe %c underrun\n",
+		if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS)
+			drm_err(display->drm, "pipe %c underrun\n",
 				pipe_name(pipe));
 	}
 }
@@ -151,18 +151,18 @@ static void ivb_check_fifo_underruns(struct intel_crtc *crtc)
 	struct intel_display *display = to_intel_display(crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT);
+	u32 err_int = intel_de_read(display, GEN7_ERR_INT);
 
 	lockdep_assert_held(&dev_priv->irq_lock);
 
 	if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)
 		return;
 
-	intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
-	intel_de_posting_read(dev_priv, GEN7_ERR_INT);
+	intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
+	intel_de_posting_read(display, GEN7_ERR_INT);
 
 	trace_intel_cpu_fifo_underrun(display, pipe);
-	drm_err(&dev_priv->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));
+	drm_err(display->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));
 }
 
 static void ivb_set_fifo_underrun_reporting(struct intel_display *display,
@@ -171,7 +171,7 @@ static void ivb_set_fifo_underrun_reporting(struct intel_display *display,
 {
 	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	if (enable) {
-		intel_de_write(dev_priv, GEN7_ERR_INT,
+		intel_de_write(display, GEN7_ERR_INT,
 			       ERR_INT_FIFO_UNDERRUN(pipe));
 
 		if (!ivb_can_enable_err_int(display))
@@ -182,8 +182,8 @@ static void ivb_set_fifo_underrun_reporting(struct intel_display *display,
 		ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 
 		if (old &&
-		    intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
-			drm_err(&dev_priv->drm,
+		    intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
+			drm_err(display->drm,
 				"uncleared fifo underrun on pipe %c\n",
 				pipe_name(pipe));
 		}
@@ -220,19 +220,19 @@ static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
 	struct intel_display *display = to_intel_display(crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pch_transcoder = crtc->pipe;
-	u32 serr_int = intel_de_read(dev_priv, SERR_INT);
+	u32 serr_int = intel_de_read(display, SERR_INT);
 
 	lockdep_assert_held(&dev_priv->irq_lock);
 
 	if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0)
 		return;
 
-	intel_de_write(dev_priv, SERR_INT,
+	intel_de_write(display, SERR_INT,
 		       SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
-	intel_de_posting_read(dev_priv, SERR_INT);
+	intel_de_posting_read(display, SERR_INT);
 
 	trace_intel_pch_fifo_underrun(display, pch_transcoder);
-	drm_err(&dev_priv->drm, "pch fifo underrun on pch transcoder %c\n",
+	drm_err(display->drm, "pch fifo underrun on pch transcoder %c\n",
 		pipe_name(pch_transcoder));
 }
 
@@ -243,7 +243,7 @@ static void cpt_set_fifo_underrun_reporting(struct intel_display *display,
 	struct drm_i915_private *dev_priv = to_i915(display->drm);
 
 	if (enable) {
-		intel_de_write(dev_priv, SERR_INT,
+		intel_de_write(display, SERR_INT,
 			       SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
 
 		if (!cpt_can_enable_serr_int(display))
@@ -253,9 +253,9 @@ static void cpt_set_fifo_underrun_reporting(struct intel_display *display,
 	} else {
 		ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 
-		if (old && intel_de_read(dev_priv, SERR_INT) &
+		if (old && intel_de_read(display, SERR_INT) &
 		    SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
-			drm_err(&dev_priv->drm,
+			drm_err(display->drm,
 				"uncleared pch fifo underrun on pch transcoder %c\n",
 				pipe_name(pch_transcoder));
 		}
@@ -368,17 +368,16 @@ bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
 
 /**
  * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
- * @dev_priv: i915 device instance
+ * @display: display device instance
  * @pipe: (CPU) pipe to set state for
  *
  * This handles a CPU fifo underrun interrupt, generating an underrun warning
  * into dmesg if underrun reporting is enabled and then disables the underrun
  * interrupt to avoid an irq storm.
  */
-void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
+void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
 					 enum pipe pipe)
 {
-	struct intel_display *display = &dev_priv->display;
 	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
 
 	/* We may be called too early in init, thanks BIOS! */
@@ -386,63 +385,62 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 		return;
 
 	/* GMCH can't disable fifo underruns, filter them. */
-	if (HAS_GMCH(dev_priv) &&
+	if (HAS_GMCH(display) &&
 	    crtc->cpu_fifo_underrun_disabled)
 		return;
 
 	if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) {
 		trace_intel_cpu_fifo_underrun(display, pipe);
 
-		drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
+		drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
 	}
 
-	intel_fbc_handle_fifo_underrun_irq(&dev_priv->display);
+	intel_fbc_handle_fifo_underrun_irq(display);
 }
 
 /**
  * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt
- * @dev_priv: i915 device instance
+ * @display: display device instance
  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
  *
  * This handles a PCH fifo underrun interrupt, generating an underrun warning
  * into dmesg if underrun reporting is enabled and then disables the underrun
  * interrupt to avoid an irq storm.
  */
-void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
+void intel_pch_fifo_underrun_irq_handler(struct intel_display *display,
 					 enum pipe pch_transcoder)
 {
-	struct intel_display *display = &dev_priv->display;
-
 	if (intel_set_pch_fifo_underrun_reporting(display, pch_transcoder,
 						  false)) {
 		trace_intel_pch_fifo_underrun(display, pch_transcoder);
-		drm_err(&dev_priv->drm, "PCH transcoder %c FIFO underrun\n",
+		drm_err(display->drm, "PCH transcoder %c FIFO underrun\n",
 			pipe_name(pch_transcoder));
 	}
 }
 
 /**
  * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately
- * @dev_priv: i915 device instance
+ * @display: display device instance
  *
  * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared
  * error interrupt may have been disabled, and so CPU fifo underruns won't
  * necessarily raise an interrupt, and on GMCH platforms where underruns never
  * raise an interrupt.
  */
-void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
+void intel_check_cpu_fifo_underruns(struct intel_display *display)
 {
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	struct intel_crtc *crtc;
 
 	spin_lock_irq(&dev_priv->irq_lock);
 
-	for_each_intel_crtc(&dev_priv->drm, crtc) {
+	for_each_intel_crtc(display->drm, crtc) {
 		if (crtc->cpu_fifo_underrun_disabled)
 			continue;
 
-		if (HAS_GMCH(dev_priv))
+		if (HAS_GMCH(display))
 			i9xx_check_fifo_underruns(crtc);
-		else if (DISPLAY_VER(dev_priv) == 7)
+		else if (DISPLAY_VER(display) == 7)
 			ivb_check_fifo_underruns(crtc);
 	}
 
@@ -451,19 +449,20 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
 
 /**
  * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately
- * @dev_priv: i915 device instance
+ * @display: display device instance
  *
  * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared
  * error interrupt may have been disabled, and so PCH fifo underruns won't
  * necessarily raise an interrupt.
  */
-void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
+void intel_check_pch_fifo_underruns(struct intel_display *display)
 {
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	struct intel_crtc *crtc;
 
 	spin_lock_irq(&dev_priv->irq_lock);
 
-	for_each_intel_crtc(&dev_priv->drm, crtc) {
+	for_each_intel_crtc(display->drm, crtc) {
 		if (crtc->pch_fifo_underrun_disabled)
 			continue;
 
@@ -474,10 +473,12 @@ void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
-void intel_init_fifo_underrun_reporting(struct drm_i915_private *i915,
+void intel_init_fifo_underrun_reporting(struct intel_display *display,
 					struct intel_crtc *crtc,
 					bool enable)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
+
 	crtc->cpu_fifo_underrun_disabled = !enable;
 
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.h b/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
index 8302080c2313..ebecc4347cfb 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
@@ -9,22 +9,21 @@
 #include <linux/types.h>
 
 enum pipe;
-struct drm_i915_private;
 struct intel_crtc;
 struct intel_display;
 
-void intel_init_fifo_underrun_reporting(struct drm_i915_private *i915,
+void intel_init_fifo_underrun_reporting(struct intel_display *display,
 					struct intel_crtc *crtc, bool enable);
 bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,
 					   enum pipe pipe, bool enable);
 bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
 					   enum pipe pch_transcoder,
 					   bool enable);
-void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
+void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
 					 enum pipe pipe);
-void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
+void intel_pch_fifo_underrun_irq_handler(struct intel_display *display,
 					 enum pipe pch_transcoder);
-void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
-void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
+void intel_check_cpu_fifo_underruns(struct intel_display *display);
+void intel_check_pch_fifo_underruns(struct intel_display *display);
 
 #endif /* __INTEL_FIFO_UNDERRUN_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index b4d1a18e9fd4..a5a00b3ce98f 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -454,8 +454,8 @@ static struct intel_connector *intel_encoder_find_connector(struct intel_encoder
 
 static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 
 	/*
 	 * We start out with underrun reporting disabled on active
@@ -470,9 +470,9 @@ static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state
 	 * No protection against concurrent access is required - at
 	 * worst a fifo underrun happens which also sets this to false.
 	 */
-	intel_init_fifo_underrun_reporting(i915, crtc,
+	intel_init_fifo_underrun_reporting(display, crtc,
 					   !crtc_state->hw.active &&
-					   !HAS_GMCH(i915));
+					   !HAS_GMCH(display));
 }
 
 static bool intel_sanitize_crtc(struct intel_crtc *crtc,
-- 
2.39.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* [PATCH 14/14] drm/i915/display: convert i915_pipestat_enable_mask() to struct intel_display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
                   ` (12 preceding siblings ...)
  2025-02-12 16:36 ` [PATCH 13/14] drm/i915/display: convert intel_fifo_underrun.[ch] " Jani Nikula
@ 2025-02-12 16:36 ` Jani Nikula
  2025-02-12 17:17 ` [PATCH 00/14] drm/i915/display: conversions " Ville Syrjälä
                   ` (4 subsequent siblings)
  18 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2025-02-12 16:36 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: jani.nikula

Going forward, struct intel_display is the main display device data
pointer. Convert i915_pipestat_enable_mask() to struct intel_display,
allowing further conversions elsewhere.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  | 19 ++++++++++---------
 .../gpu/drm/i915/display/intel_display_irq.h  |  5 +++--
 .../drm/i915/display/intel_fifo_underrun.c    |  4 ++--
 3 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index b8fcf74bd3ac..880eaed83cd5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -226,29 +226,30 @@ void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits)
 	ibx_display_interrupt_update(i915, bits, 0);
 }
 
-u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
+u32 i915_pipestat_enable_mask(struct intel_display *display,
 			      enum pipe pipe)
 {
-	u32 status_mask = dev_priv->display.irq.pipestat_irq_mask[pipe];
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
+	u32 status_mask = display->irq.pipestat_irq_mask[pipe];
 	u32 enable_mask = status_mask << 16;
 
 	lockdep_assert_held(&dev_priv->irq_lock);
 
-	if (DISPLAY_VER(dev_priv) < 5)
+	if (DISPLAY_VER(display) < 5)
 		goto out;
 
 	/*
 	 * On pipe A we don't support the PSR interrupt yet,
 	 * on pipe B and C the same bit MBZ.
 	 */
-	if (drm_WARN_ON_ONCE(&dev_priv->drm,
+	if (drm_WARN_ON_ONCE(display->drm,
 			     status_mask & PIPE_A_PSR_STATUS_VLV))
 		return 0;
 	/*
 	 * On pipe B and C we don't support the PSR interrupt yet, on pipe
 	 * A the same bit is for perf counters which we don't use either.
 	 */
-	if (drm_WARN_ON_ONCE(&dev_priv->drm,
+	if (drm_WARN_ON_ONCE(display->drm,
 			     status_mask & PIPE_B_PSR_STATUS_VLV))
 		return 0;
 
@@ -261,7 +262,7 @@ u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
 		enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 
 out:
-	drm_WARN_ONCE(&dev_priv->drm,
+	drm_WARN_ONCE(display->drm,
 		      enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
 		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
@@ -288,7 +289,7 @@ void i915_enable_pipestat(struct drm_i915_private *dev_priv,
 		return;
 
 	dev_priv->display.irq.pipestat_irq_mask[pipe] |= status_mask;
-	enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
+	enable_mask = i915_pipestat_enable_mask(display, pipe);
 
 	intel_de_write(display, reg, enable_mask | status_mask);
 	intel_de_posting_read(display, reg);
@@ -312,7 +313,7 @@ void i915_disable_pipestat(struct drm_i915_private *dev_priv,
 		return;
 
 	dev_priv->display.irq.pipestat_irq_mask[pipe] &= ~status_mask;
-	enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
+	enable_mask = i915_pipestat_enable_mask(display, pipe);
 
 	intel_de_write(display, reg, enable_mask | status_mask);
 	intel_de_posting_read(display, reg);
@@ -525,7 +526,7 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
 
 		reg = PIPESTAT(dev_priv, pipe);
 		pipe_stats[pipe] = intel_de_read(display, reg) & status_mask;
-		enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
+		enable_mask = i915_pipestat_enable_mask(display, pipe);
 
 		/*
 		 * Clear the PIPE*STAT regs before the IIR
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index b077712b7be1..75ab38a0908e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -11,8 +11,9 @@
 #include "intel_display_limits.h"
 
 enum pipe;
-struct drm_i915_private;
 struct drm_crtc;
+struct drm_i915_private;
+struct intel_display;
 
 void valleyview_enable_display_irqs(struct drm_i915_private *i915);
 void valleyview_disable_display_irqs(struct drm_i915_private *i915);
@@ -64,7 +65,7 @@ void gen8_de_irq_postinstall(struct drm_i915_private *i915);
 void gen11_de_irq_postinstall(struct drm_i915_private *i915);
 void dg1_de_irq_postinstall(struct drm_i915_private *i915);
 
-u32 i915_pipestat_enable_mask(struct drm_i915_private *i915, enum pipe pipe);
+u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
 void i915_enable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask);
 void i915_disable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask);
 void i915_enable_asle_pipestat(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index 14b00988a81f..7a8fbff39be0 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -103,7 +103,7 @@ static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
 	if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
 		return;
 
-	enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);
+	enable_mask = i915_pipestat_enable_mask(display, crtc->pipe);
 	intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
 	intel_de_posting_read(display, reg);
 
@@ -121,7 +121,7 @@ static void i9xx_set_fifo_underrun_reporting(struct intel_display *display,
 	lockdep_assert_held(&dev_priv->irq_lock);
 
 	if (enable) {
-		u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
+		u32 enable_mask = i915_pipestat_enable_mask(display, pipe);
 
 		intel_de_write(display, reg,
 			       enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
-- 
2.39.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* Re: [PATCH 00/14] drm/i915/display: conversions to struct intel_display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
                   ` (13 preceding siblings ...)
  2025-02-12 16:36 ` [PATCH 14/14] drm/i915/display: convert i915_pipestat_enable_mask() " Jani Nikula
@ 2025-02-12 17:17 ` Ville Syrjälä
  2025-02-13  8:27   ` Jani Nikula
  2025-02-12 21:19 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
                   ` (3 subsequent siblings)
  18 siblings, 1 reply; 35+ messages in thread
From: Ville Syrjälä @ 2025-02-12 17:17 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx, intel-xe

On Wed, Feb 12, 2025 at 06:36:29PM +0200, Jani Nikula wrote:
> Convert a bunch of files and functions to struct intel display.
> 
> The approach is to mostly convert a file, then see what the stragglers
> are, convert those too, and repeat.
> 
> The PCH checks are starting to become a big straggler for further
> conversions.

Aye. I wonder if we should in fact change all the HAS_PCH_FOO()
stuff to some kind of "south display type" thing. The current
situation is a bit of a mess due to:
- DG1/2 declare some kind of fake PCH type
- BXT/GLK don't declare one and yet we still use many
  PCH/south display registers

Anyways, series is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> 
> BR,
> Jani.
> 
> Jani Nikula (14):
>   drm/i915/dp: convert g4x_dp.[ch] to struct intel display
>   drm/i915/hdmi: convert g4x_hdmi.[ch] to struct intel_display
>   drm/i915/ips: convert hsw_ips.c to struct intel_display
>   drm/i915/display: convert assert_transcoder*() to struct intel_display
>   drm/i915/display: convert assert_port_valid() to struct intel_display
>   drm/i915/hpd: drop dev_priv parameter from intel_hpd_pin_default()
>   drm/i915/display: convert
>     intel_set_{cpu,pch}_fifo_underrun_reporting() to intel_display
>   drm/i915/sdvo: convert intel_sdvo.[ch] to struct intel_display
>   drm/i915/display: convert intel_cpu_transcoder_mode_valid() to
>     intel_display
>   drm/i915/display: convert intel_mode_valid_max_plane_size() to
>     intel_display
>   drm/i915/dsi: convert platform checks to display->platform.<platform>
>     style
>   drm/i915/combo-phy: convert intel_combo_phy.[ch] to struct
>     intel_display
>   drm/i915/display: convert intel_fifo_underrun.[ch] to struct
>     intel_display
>   drm/i915/display: convert i915_pipestat_enable_mask() to struct
>     intel_display
> 
>  drivers/gpu/drm/i915/display/g4x_dp.c         |  99 +++---
>  drivers/gpu/drm/i915/display/g4x_dp.h         |  14 +-
>  drivers/gpu/drm/i915/display/g4x_hdmi.c       | 154 +++++----
>  drivers/gpu/drm/i915/display/g4x_hdmi.h       |   6 +-
>  drivers/gpu/drm/i915/display/hsw_ips.c        |  26 +-
>  drivers/gpu/drm/i915/display/icl_dsi.c        |  21 +-
>  .../gpu/drm/i915/display/intel_combo_phy.c    | 180 ++++++-----
>  .../gpu/drm/i915/display/intel_combo_phy.h    |   8 +-
>  drivers/gpu/drm/i915/display/intel_crt.c      |  21 +-
>  drivers/gpu/drm/i915/display/intel_crtc.c     |   2 +-
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  11 +-
>  drivers/gpu/drm/i915/display/intel_display.c  | 155 ++++-----
>  drivers/gpu/drm/i915/display/intel_display.h  |  10 +-
>  .../gpu/drm/i915/display/intel_display_irq.c  |  37 +--
>  .../gpu/drm/i915/display/intel_display_irq.h  |   5 +-
>  .../drm/i915/display/intel_display_power.c    |   5 +-
>  .../i915/display/intel_display_power_well.c   |   3 +-
>  drivers/gpu/drm/i915/display/intel_dp.c       |   5 +-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   |   5 +-
>  drivers/gpu/drm/i915/display/intel_dpll.c     |  30 +-
>  drivers/gpu/drm/i915/display/intel_dsi.c      |   8 +-
>  drivers/gpu/drm/i915/display/intel_dvo.c      |   8 +-
>  drivers/gpu/drm/i915/display/intel_fdi.c      |   3 +-
>  .../drm/i915/display/intel_fifo_underrun.c    | 181 ++++++-----
>  .../drm/i915/display/intel_fifo_underrun.h    |  18 +-
>  drivers/gpu/drm/i915/display/intel_hdmi.c     |   5 +-
>  drivers/gpu/drm/i915/display/intel_hotplug.c  |   4 +-
>  drivers/gpu/drm/i915/display/intel_hotplug.h  |   3 +-
>  drivers/gpu/drm/i915/display/intel_lvds.c     |   6 +-
>  .../drm/i915/display/intel_modeset_setup.c    |   6 +-
>  .../gpu/drm/i915/display/intel_pch_display.c  |   4 +-
>  drivers/gpu/drm/i915/display/intel_pps.c      |  11 +-
>  drivers/gpu/drm/i915/display/intel_sdvo.c     | 293 +++++++++---------
>  drivers/gpu/drm/i915/display/intel_sdvo.h     |  10 +-
>  drivers/gpu/drm/i915/display/intel_tv.c       |   6 +-
>  drivers/gpu/drm/i915/display/vlv_dsi.c        |   8 +-
>  36 files changed, 671 insertions(+), 700 deletions(-)
> 
> -- 
> 2.39.5

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 00/14] drm/i915/display: conversions to struct intel_display
  2025-02-12 17:17 ` [PATCH 00/14] drm/i915/display: conversions " Ville Syrjälä
@ 2025-02-13  8:27   ` Jani Nikula
  0 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2025-02-13  8:27 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx, intel-xe

On Wed, 12 Feb 2025, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Feb 12, 2025 at 06:36:29PM +0200, Jani Nikula wrote:
>> Convert a bunch of files and functions to struct intel display.
>> 
>> The approach is to mostly convert a file, then see what the stragglers
>> are, convert those too, and repeat.
>> 
>> The PCH checks are starting to become a big straggler for further
>> conversions.
>
> Aye. I wonder if we should in fact change all the HAS_PCH_FOO()
> stuff to some kind of "south display type" thing. The current
> situation is a bit of a mess due to:
> - DG1/2 declare some kind of fake PCH type
> - BXT/GLK don't declare one and yet we still use many
>   PCH/south display registers

I'm also thinking most or all of the PCH checks outside of display
should be removed.

> Anyways, series is
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Thanks, pushed to din!

>
>> 
>> BR,
>> Jani.
>> 
>> Jani Nikula (14):
>>   drm/i915/dp: convert g4x_dp.[ch] to struct intel display
>>   drm/i915/hdmi: convert g4x_hdmi.[ch] to struct intel_display
>>   drm/i915/ips: convert hsw_ips.c to struct intel_display
>>   drm/i915/display: convert assert_transcoder*() to struct intel_display
>>   drm/i915/display: convert assert_port_valid() to struct intel_display
>>   drm/i915/hpd: drop dev_priv parameter from intel_hpd_pin_default()
>>   drm/i915/display: convert
>>     intel_set_{cpu,pch}_fifo_underrun_reporting() to intel_display
>>   drm/i915/sdvo: convert intel_sdvo.[ch] to struct intel_display
>>   drm/i915/display: convert intel_cpu_transcoder_mode_valid() to
>>     intel_display
>>   drm/i915/display: convert intel_mode_valid_max_plane_size() to
>>     intel_display
>>   drm/i915/dsi: convert platform checks to display->platform.<platform>
>>     style
>>   drm/i915/combo-phy: convert intel_combo_phy.[ch] to struct
>>     intel_display
>>   drm/i915/display: convert intel_fifo_underrun.[ch] to struct
>>     intel_display
>>   drm/i915/display: convert i915_pipestat_enable_mask() to struct
>>     intel_display
>> 
>>  drivers/gpu/drm/i915/display/g4x_dp.c         |  99 +++---
>>  drivers/gpu/drm/i915/display/g4x_dp.h         |  14 +-
>>  drivers/gpu/drm/i915/display/g4x_hdmi.c       | 154 +++++----
>>  drivers/gpu/drm/i915/display/g4x_hdmi.h       |   6 +-
>>  drivers/gpu/drm/i915/display/hsw_ips.c        |  26 +-
>>  drivers/gpu/drm/i915/display/icl_dsi.c        |  21 +-
>>  .../gpu/drm/i915/display/intel_combo_phy.c    | 180 ++++++-----
>>  .../gpu/drm/i915/display/intel_combo_phy.h    |   8 +-
>>  drivers/gpu/drm/i915/display/intel_crt.c      |  21 +-
>>  drivers/gpu/drm/i915/display/intel_crtc.c     |   2 +-
>>  drivers/gpu/drm/i915/display/intel_ddi.c      |  11 +-
>>  drivers/gpu/drm/i915/display/intel_display.c  | 155 ++++-----
>>  drivers/gpu/drm/i915/display/intel_display.h  |  10 +-
>>  .../gpu/drm/i915/display/intel_display_irq.c  |  37 +--
>>  .../gpu/drm/i915/display/intel_display_irq.h  |   5 +-
>>  .../drm/i915/display/intel_display_power.c    |   5 +-
>>  .../i915/display/intel_display_power_well.c   |   3 +-
>>  drivers/gpu/drm/i915/display/intel_dp.c       |   5 +-
>>  drivers/gpu/drm/i915/display/intel_dp_mst.c   |   5 +-
>>  drivers/gpu/drm/i915/display/intel_dpll.c     |  30 +-
>>  drivers/gpu/drm/i915/display/intel_dsi.c      |   8 +-
>>  drivers/gpu/drm/i915/display/intel_dvo.c      |   8 +-
>>  drivers/gpu/drm/i915/display/intel_fdi.c      |   3 +-
>>  .../drm/i915/display/intel_fifo_underrun.c    | 181 ++++++-----
>>  .../drm/i915/display/intel_fifo_underrun.h    |  18 +-
>>  drivers/gpu/drm/i915/display/intel_hdmi.c     |   5 +-
>>  drivers/gpu/drm/i915/display/intel_hotplug.c  |   4 +-
>>  drivers/gpu/drm/i915/display/intel_hotplug.h  |   3 +-
>>  drivers/gpu/drm/i915/display/intel_lvds.c     |   6 +-
>>  .../drm/i915/display/intel_modeset_setup.c    |   6 +-
>>  .../gpu/drm/i915/display/intel_pch_display.c  |   4 +-
>>  drivers/gpu/drm/i915/display/intel_pps.c      |  11 +-
>>  drivers/gpu/drm/i915/display/intel_sdvo.c     | 293 +++++++++---------
>>  drivers/gpu/drm/i915/display/intel_sdvo.h     |  10 +-
>>  drivers/gpu/drm/i915/display/intel_tv.c       |   6 +-
>>  drivers/gpu/drm/i915/display/vlv_dsi.c        |   8 +-
>>  36 files changed, 671 insertions(+), 700 deletions(-)
>> 
>> -- 
>> 2.39.5

-- 
Jani Nikula, Intel

^ permalink raw reply	[flat|nested] 35+ messages in thread

* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: conversions to struct intel_display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
                   ` (14 preceding siblings ...)
  2025-02-12 17:17 ` [PATCH 00/14] drm/i915/display: conversions " Ville Syrjälä
@ 2025-02-12 21:19 ` Patchwork
  2025-02-12 21:20 ` ✗ Fi.CI.SPARSE: " Patchwork
                   ` (2 subsequent siblings)
  18 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2025-02-12 21:19 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/display: conversions to struct intel_display
URL   : https://patchwork.freedesktop.org/series/144748/
State : warning

== Summary ==

Error: dim checkpatch failed
a146155ca1cd drm/i915/dp: convert g4x_dp.[ch] to struct intel display
-:349: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#349: FILE: drivers/gpu/drm/i915/display/g4x_dp.h:32:
 }
+static inline bool g4x_dp_port_enabled(struct intel_display *display,

-:356: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#356: FILE: drivers/gpu/drm/i915/display/g4x_dp.h:38:
 }
+static inline bool g4x_dp_init(struct intel_display *display,

total: 0 errors, 0 warnings, 2 checks, 431 lines checked
9549a0945a42 drm/i915/hdmi: convert g4x_hdmi.[ch] to struct intel_display
62ec4880efc5 drm/i915/ips: convert hsw_ips.c to struct intel_display
b62006beb265 drm/i915/display: convert assert_transcoder*() to struct intel_display
008508f7d91c drm/i915/display: convert assert_port_valid() to struct intel_display
d397e2b12f72 drm/i915/hpd: drop dev_priv parameter from intel_hpd_pin_default()
a2f2b5abd6c1 drm/i915/display: convert intel_set_{cpu, pch}_fifo_underrun_reporting() to intel_display
b00286055884 drm/i915/sdvo: convert intel_sdvo.[ch] to struct intel_display
-:960: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#960: FILE: drivers/gpu/drm/i915/display/intel_sdvo.c:3170:
+			drm_property_create_range(display->drm, 0, "right_margin", 0, data_value[0]);

-:1157: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#1157: FILE: drivers/gpu/drm/i915/display/intel_sdvo.h:28:
 }
+static inline bool intel_sdvo_init(struct intel_display *display,

total: 0 errors, 1 warnings, 1 checks, 1036 lines checked
f0a80538b060 drm/i915/display: convert intel_cpu_transcoder_mode_valid() to intel_display
443821a9d111 drm/i915/display: convert intel_mode_valid_max_plane_size() to intel_display
f037c1c020e8 drm/i915/dsi: convert platform checks to display->platform.<platform> style
4041ad28d05d drm/i915/combo-phy: convert intel_combo_phy.[ch] to struct intel_display
-:61: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects?
#61: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:13:
+#define for_each_combo_phy(__display, __phy) \
 	for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)	\
+		for_each_if(intel_phy_is_combo(__display, __phy))

-:67: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects?
#67: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:17:
+#define for_each_combo_phy_reverse(__display, __phy) \
 	for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
+		for_each_if(intel_phy_is_combo(__display, __phy))

total: 0 errors, 0 warnings, 2 checks, 531 lines checked
250b2e0262b0 drm/i915/display: convert intel_fifo_underrun.[ch] to struct intel_display
863ed0d1a293 drm/i915/display: convert i915_pipestat_enable_mask() to struct intel_display



^ permalink raw reply	[flat|nested] 35+ messages in thread

* ✗ Fi.CI.SPARSE: warning for drm/i915/display: conversions to struct intel_display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
                   ` (15 preceding siblings ...)
  2025-02-12 21:19 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2025-02-12 21:20 ` Patchwork
  2025-02-12 21:39 ` ✓ i915.CI.BAT: success " Patchwork
  2025-02-13  6:10 ` ✗ i915.CI.Full: failure " Patchwork
  18 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2025-02-12 21:20 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/display: conversions to struct intel_display
URL   : https://patchwork.freedesktop.org/series/144748/
State : warning

== Summary ==

Error: patch https://patchwork.freedesktop.org/api/1.0/series/144748/revisions/1/mbox/ not found



^ permalink raw reply	[flat|nested] 35+ messages in thread

* ✓ i915.CI.BAT: success for drm/i915/display: conversions to struct intel_display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
                   ` (16 preceding siblings ...)
  2025-02-12 21:20 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2025-02-12 21:39 ` Patchwork
  2025-02-13  6:10 ` ✗ i915.CI.Full: failure " Patchwork
  18 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2025-02-12 21:39 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 6157 bytes --]

== Series Details ==

Series: drm/i915/display: conversions to struct intel_display
URL   : https://patchwork.freedesktop.org/series/144748/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_16122 -> Patchwork_144748v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/index.html

Participating hosts (43 -> 43)
------------------------------

  Additional (1): fi-pnv-d510 
  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_144748v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - bat-adls-6:         [PASS][1] -> [FAIL][2] ([i915#13633])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/bat-adls-6/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/bat-adls-6/igt@i915_pm_rpm@module-reload.html
    - bat-dg1-7:          [PASS][3] -> [FAIL][4] ([i915#13633])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/bat-dg1-7/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/bat-dg1-7/igt@i915_pm_rpm@module-reload.html
    - bat-rpls-4:         [PASS][5] -> [FAIL][6] ([i915#13633])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/bat-rpls-4/igt@i915_pm_rpm@module-reload.html

  * igt@kms_flip@basic-flip-vs-dpms@a-dp1:
    - bat-apl-1:          [PASS][7] -> [DMESG-WARN][8] ([i915#13532]) +1 other test dmesg-warn
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/bat-apl-1/igt@kms_flip@basic-flip-vs-dpms@a-dp1.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/bat-apl-1/igt@kms_flip@basic-flip-vs-dpms@a-dp1.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         [PASS][9] -> [SKIP][10] ([i915#9197]) +3 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  * igt@kms_psr@psr-primary-mmap-gtt:
    - fi-pnv-d510:        NOTRUN -> [SKIP][11] +33 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/fi-pnv-d510/igt@kms_psr@psr-primary-mmap-gtt.html

  * igt@runner@aborted:
    - bat-twl-1:          NOTRUN -> [FAIL][12] ([i915#13655])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/bat-twl-1/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@dmabuf@all-tests:
    - bat-apl-1:          [INCOMPLETE][13] ([i915#12904]) -> [PASS][14] +1 other test pass
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/bat-apl-1/igt@dmabuf@all-tests.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/bat-apl-1/igt@dmabuf@all-tests.html

  * igt@i915_selftest@live:
    - bat-dg1-6:          [INCOMPLETE][15] -> [PASS][16] +1 other test pass
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/bat-dg1-6/igt@i915_selftest@live.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/bat-dg1-6/igt@i915_selftest@live.html
    - bat-twl-2:          [ABORT][17] ([i915#12919] / [i915#13503]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/bat-twl-2/igt@i915_selftest@live.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/bat-twl-2/igt@i915_selftest@live.html

  * igt@i915_selftest@live@gt_engines:
    - bat-twl-2:          [ABORT][19] ([i915#12919]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/bat-twl-2/igt@i915_selftest@live@gt_engines.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/bat-twl-2/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-3:         [DMESG-FAIL][21] ([i915#12061]) -> [PASS][22] +1 other test pass
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/bat-arlh-3/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-9:         [DMESG-FAIL][23] ([i915#12061]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
    - bat-arls-6:         [DMESG-FAIL][25] ([i915#12061]) -> [PASS][26] +1 other test pass
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/bat-arls-6/igt@i915_selftest@live@workarounds.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/bat-arls-6/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
  [i915#12919]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12919
  [i915#13503]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13503
  [i915#13532]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13532
  [i915#13633]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13633
  [i915#13655]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13655
  [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197


Build changes
-------------

  * Linux: CI_DRM_16122 -> Patchwork_144748v1

  CI-20190529: 20190529
  CI_DRM_16122: 1e935d0d289627796230e9e1ca1451647fe9a2ad @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8228: 8228
  Patchwork_144748v1: 1e935d0d289627796230e9e1ca1451647fe9a2ad @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/index.html

[-- Attachment #2: Type: text/html, Size: 7366 bytes --]

^ permalink raw reply	[flat|nested] 35+ messages in thread

* ✗ i915.CI.Full: failure for drm/i915/display: conversions to struct intel_display
  2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
                   ` (17 preceding siblings ...)
  2025-02-12 21:39 ` ✓ i915.CI.BAT: success " Patchwork
@ 2025-02-13  6:10 ` Patchwork
  18 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2025-02-13  6:10 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 100280 bytes --]

== Series Details ==

Series: drm/i915/display: conversions to struct intel_display
URL   : https://patchwork.freedesktop.org/series/144748/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16122_full -> Patchwork_144748v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_144748v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_144748v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_144748v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@reload-no-display:
    - shard-snb:          [PASS][1] -> [INCOMPLETE][2] +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-snb6/igt@i915_module_load@reload-no-display.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-snb1/igt@i915_module_load@reload-no-display.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-dg1:          [PASS][3] -> [SKIP][4] +83 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-18/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_cursor_crc@cursor-offscreen-256x85:
    - shard-dg1:          NOTRUN -> [SKIP][5] +26 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_cursor_crc@cursor-offscreen-256x85.html

  * igt@kms_flip@flip-vs-expired-vblank@a-dp4:
    - shard-dg2:          NOTRUN -> [FAIL][6]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-10/igt@kms_flip@flip-vs-expired-vblank@a-dp4.html

  * igt@perf_pmu@module-unload:
    - shard-mtlp:         [PASS][7] -> [INCOMPLETE][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-mtlp-2/igt@perf_pmu@module-unload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-4/igt@perf_pmu@module-unload.html
    - shard-dg2:          NOTRUN -> [INCOMPLETE][9]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-4/igt@perf_pmu@module-unload.html

  
#### Warnings ####

  * igt@kms_atomic_interruptible@universal-setplane-cursor:
    - shard-dg1:          [DMESG-WARN][10] ([i915#4423]) -> [SKIP][11] +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_atomic_interruptible@universal-setplane-cursor.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_atomic_interruptible@universal-setplane-cursor.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-dg1:          [SKIP][12] ([i915#4538] / [i915#5286]) -> [SKIP][13] +7 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-13/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-dg1:          [SKIP][14] ([i915#3638]) -> [SKIP][15] +2 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-18/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-dg1:          [SKIP][16] ([i915#4538]) -> [SKIP][17] +5 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-18/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-dg1:          [SKIP][18] ([i915#12805]) -> [SKIP][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-13/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - shard-dg1:          [SKIP][20] ([i915#12313]) -> [SKIP][21] +4 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-13/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg1:          [SKIP][22] ([i915#6095]) -> [SKIP][23] +14 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg1:          [SKIP][24] ([i915#7116] / [i915#9424]) -> [SKIP][25] +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-13/igt@kms_content_protection@atomic-dpms.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-dg1:          [SKIP][26] ([i915#3299]) -> [SKIP][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-17/igt@kms_content_protection@dp-mst-lic-type-0.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@srm:
    - shard-dg1:          [SKIP][28] ([i915#7116]) -> [SKIP][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_content_protection@srm.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-dg1:          [SKIP][30] ([i915#3555]) -> [SKIP][31] +6 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-18/igt@kms_cursor_crc@cursor-random-32x32.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-dg1:          [SKIP][32] ([i915#4103] / [i915#4213]) -> [SKIP][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-dg1:          [SKIP][34] ([i915#9723]) -> [SKIP][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-13/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-dg1:          [SKIP][36] ([i915#3840]) -> [SKIP][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-dg1:          [SKIP][38] ([i915#12713]) -> [SKIP][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_hdr@brightness-with-hdr.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-dg1:          [SKIP][40] ([i915#3555] / [i915#8228]) -> [SKIP][41] +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-18/igt@kms_hdr@invalid-metadata-sizes.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_rotation_crc@exhaust-fences:
    - shard-dg1:          [SKIP][42] ([i915#4884]) -> [SKIP][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_rotation_crc@exhaust-fences.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_rotation_crc@exhaust-fences.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg1:          [SKIP][44] ([i915#8623]) -> [SKIP][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@lobf:
    - shard-dg1:          [SKIP][46] ([i915#11920]) -> [SKIP][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-18/igt@kms_vrr@lobf.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_vrr@lobf.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-dg1:          [SKIP][48] ([i915#9906]) -> [SKIP][49] +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-13/igt@kms_vrr@seamless-rr-switch-drrs.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_vrr@seamless-rr-switch-drrs.html

  
New tests
---------

  New tests have been introduced between CI_DRM_16122_full and Patchwork_144748v1_full:

### New IGT tests (4) ###

  * igt@kms_cursor_edge_walk@128x128-left-edge@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [3.69] s

  * igt@kms_cursor_edge_walk@128x128-top-bottom@pipe-a-hdmi-a-2:
    - Statuses : 2 pass(s)
    - Exec time: [3.30, 3.68] s

  * igt@kms_cursor_edge_walk@128x128-top-bottom@pipe-d-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [3.22] s

  * igt@kms_cursor_edge_walk@64x64-top-edge@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [3.70] s

  

Known issues
------------

  Here are the changes found in Patchwork_144748v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@object-reloc-purge-cache:
    - shard-dg2-9:        NOTRUN -> [SKIP][50] ([i915#8411]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@api_intel_bb@object-reloc-purge-cache.html
    - shard-rkl:          NOTRUN -> [SKIP][51] ([i915#8411]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-5/igt@api_intel_bb@object-reloc-purge-cache.html

  * igt@device_reset@cold-reset-bound:
    - shard-dg2:          NOTRUN -> [SKIP][52] ([i915#11078])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-4/igt@device_reset@cold-reset-bound.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-tglu-1:       NOTRUN -> [SKIP][53] ([i915#11078])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@drm_fdinfo@isolation:
    - shard-dg2:          NOTRUN -> [SKIP][54] ([i915#8414]) +9 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@drm_fdinfo@isolation.html

  * igt@drm_fdinfo@most-busy-idle-check-all@bcs0:
    - shard-dg1:          NOTRUN -> [SKIP][55] ([i915#8414]) +6 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@drm_fdinfo@most-busy-idle-check-all@bcs0.html

  * igt@fbdev@eof:
    - shard-dg1:          [PASS][56] -> [SKIP][57] ([i915#2582]) +1 other test skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@fbdev@eof.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@fbdev@eof.html

  * igt@gem_busy@semaphore:
    - shard-dg2-9:        NOTRUN -> [SKIP][58] ([i915#3936])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@gem_busy@semaphore.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-tglu:         NOTRUN -> [SKIP][59] ([i915#3555] / [i915#9323])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-9/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@block-multicopy-inplace:
    - shard-rkl:          NOTRUN -> [SKIP][60] ([i915#3555] / [i915#9323]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@gem_ccs@block-multicopy-inplace.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-dg1:          NOTRUN -> [SKIP][61] ([i915#7697])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-dg2-9:        NOTRUN -> [SKIP][62] ([i915#7697])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_create@create-ext-cpu-access-sanity-check:
    - shard-tglu-1:       NOTRUN -> [SKIP][63] ([i915#6335])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@gem_create@create-ext-cpu-access-sanity-check.html

  * igt@gem_ctx_freq@sysfs:
    - shard-dg2:          NOTRUN -> [FAIL][64] ([i915#9561]) +1 other test fail
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-11/igt@gem_ctx_freq@sysfs.html

  * igt@gem_ctx_param@set-priority-not-supported:
    - shard-tglu-1:       NOTRUN -> [SKIP][65] +39 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@gem_ctx_param@set-priority-not-supported.html

  * igt@gem_ctx_persistence@heartbeat-stop:
    - shard-dg1:          NOTRUN -> [SKIP][66] ([i915#8555])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@gem_ctx_persistence@heartbeat-stop.html

  * igt@gem_eio@hibernate:
    - shard-tglu-1:       NOTRUN -> [ABORT][67] ([i915#7975])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@gem_eio@hibernate.html
    - shard-mtlp:         NOTRUN -> [ABORT][68] ([i915#7975])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@gem_eio@hibernate.html

  * igt@gem_exec_balancer@invalid-bonds:
    - shard-dg2-9:        NOTRUN -> [SKIP][69] ([i915#4036])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@gem_exec_balancer@invalid-bonds.html

  * igt@gem_exec_balancer@noheartbeat:
    - shard-dg2:          NOTRUN -> [SKIP][70] ([i915#8555])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@gem_exec_balancer@noheartbeat.html

  * igt@gem_exec_balancer@parallel-balancer:
    - shard-rkl:          NOTRUN -> [SKIP][71] ([i915#4525])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-5/igt@gem_exec_balancer@parallel-balancer.html
    - shard-tglu:         NOTRUN -> [SKIP][72] ([i915#4525])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-3/igt@gem_exec_balancer@parallel-balancer.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-tglu-1:       NOTRUN -> [SKIP][73] ([i915#4525])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_capture@capture-invisible:
    - shard-tglu-1:       NOTRUN -> [SKIP][74] ([i915#6334]) +1 other test skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@gem_exec_capture@capture-invisible.html

  * igt@gem_exec_fence@submit3:
    - shard-dg2:          NOTRUN -> [SKIP][75] ([i915#4812])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-4/igt@gem_exec_fence@submit3.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
    - shard-dg2-9:        NOTRUN -> [SKIP][76] ([i915#3539] / [i915#4852])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html

  * igt@gem_exec_flush@basic-uc-ro-default:
    - shard-dg2:          NOTRUN -> [SKIP][77] ([i915#3539] / [i915#4852]) +3 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-11/igt@gem_exec_flush@basic-uc-ro-default.html

  * igt@gem_exec_reloc@basic-active:
    - shard-rkl:          NOTRUN -> [SKIP][78] ([i915#3281]) +6 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-5/igt@gem_exec_reloc@basic-active.html

  * igt@gem_exec_reloc@basic-cpu-read:
    - shard-dg2:          NOTRUN -> [SKIP][79] ([i915#3281]) +5 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@gem_exec_reloc@basic-cpu-read.html

  * igt@gem_exec_reloc@basic-gtt-noreloc:
    - shard-mtlp:         NOTRUN -> [SKIP][80] ([i915#3281]) +2 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@gem_exec_reloc@basic-gtt-noreloc.html

  * igt@gem_exec_reloc@basic-gtt-read:
    - shard-dg1:          NOTRUN -> [SKIP][81] ([i915#3281])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@gem_exec_reloc@basic-gtt-read.html

  * igt@gem_exec_reloc@basic-write-gtt:
    - shard-dg2-9:        NOTRUN -> [SKIP][82] ([i915#3281]) +5 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@gem_exec_reloc@basic-write-gtt.html

  * igt@gem_exec_schedule@preempt-queue-chain:
    - shard-mtlp:         NOTRUN -> [SKIP][83] ([i915#4537] / [i915#4812])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@gem_exec_schedule@preempt-queue-chain.html

  * igt@gem_exec_schedule@preempt-queue-contexts:
    - shard-dg2-9:        NOTRUN -> [SKIP][84] ([i915#4537] / [i915#4812])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@gem_exec_schedule@preempt-queue-contexts.html

  * igt@gem_exec_schedule@semaphore-power:
    - shard-rkl:          NOTRUN -> [SKIP][85] ([i915#7276])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@gem_exec_schedule@semaphore-power.html

  * igt@gem_exec_suspend@basic-s4-devices:
    - shard-dg2:          NOTRUN -> [ABORT][86] ([i915#7975]) +1 other test abort
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@gem_exec_suspend@basic-s4-devices.html
    - shard-rkl:          NOTRUN -> [ABORT][87] ([i915#7975]) +1 other test abort
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@gem_fence_thrash@bo-write-verify-x:
    - shard-dg2:          NOTRUN -> [SKIP][88] ([i915#4860]) +1 other test skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-10/igt@gem_fence_thrash@bo-write-verify-x.html

  * igt@gem_fenced_exec_thrash@2-spare-fences:
    - shard-dg1:          NOTRUN -> [SKIP][89] ([i915#4860])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@gem_fenced_exec_thrash@2-spare-fences.html

  * igt@gem_lmem_swapping@massive-random:
    - shard-glk:          NOTRUN -> [SKIP][90] ([i915#4613])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-glk1/igt@gem_lmem_swapping@massive-random.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-mtlp:         NOTRUN -> [SKIP][91] ([i915#4613])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][92] ([i915#4613]) +1 other test skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg1:          [PASS][93] -> [TIMEOUT][94] ([i915#5493]) +1 other test timeout
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_lmem_swapping@verify-random:
    - shard-rkl:          NOTRUN -> [SKIP][95] ([i915#4613]) +1 other test skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-5/igt@gem_lmem_swapping@verify-random.html
    - shard-tglu:         NOTRUN -> [SKIP][96] ([i915#4613]) +2 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-3/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_madvise@dontneed-before-exec:
    - shard-mtlp:         NOTRUN -> [SKIP][97] ([i915#3282]) +1 other test skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@gem_madvise@dontneed-before-exec.html

  * igt@gem_madvise@dontneed-before-pwrite:
    - shard-dg2-9:        NOTRUN -> [SKIP][98] ([i915#3282])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@gem_madvise@dontneed-before-pwrite.html

  * igt@gem_media_vme:
    - shard-tglu-1:       NOTRUN -> [SKIP][99] ([i915#284])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@gem_media_vme.html

  * igt@gem_mmap@bad-offset:
    - shard-mtlp:         NOTRUN -> [SKIP][100] ([i915#4083]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@gem_mmap@bad-offset.html

  * igt@gem_mmap_gtt@basic-read-write-distinct:
    - shard-dg2-9:        NOTRUN -> [SKIP][101] ([i915#4077]) +2 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@gem_mmap_gtt@basic-read-write-distinct.html

  * igt@gem_mmap_gtt@fault-concurrent-x:
    - shard-dg2:          NOTRUN -> [SKIP][102] ([i915#4077]) +2 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-11/igt@gem_mmap_gtt@fault-concurrent-x.html

  * igt@gem_mmap_wc@copy:
    - shard-dg2:          NOTRUN -> [SKIP][103] ([i915#4083]) +3 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-10/igt@gem_mmap_wc@copy.html

  * igt@gem_mmap_wc@read:
    - shard-dg1:          NOTRUN -> [SKIP][104] ([i915#4083])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@gem_mmap_wc@read.html

  * igt@gem_mmap_wc@write-wc-read-gtt:
    - shard-dg2-9:        NOTRUN -> [SKIP][105] ([i915#4083]) +1 other test skip
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@gem_mmap_wc@write-wc-read-gtt.html

  * igt@gem_partial_pwrite_pread@writes-after-reads:
    - shard-rkl:          NOTRUN -> [SKIP][106] ([i915#3282]) +3 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@gem_partial_pwrite_pread@writes-after-reads.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-display:
    - shard-dg1:          NOTRUN -> [SKIP][107] ([i915#3282]) +1 other test skip
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@gem_partial_pwrite_pread@writes-after-reads-display.html

  * igt@gem_pread@exhaustion:
    - shard-tglu-1:       NOTRUN -> [WARN][108] ([i915#2658])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@gem_pread@exhaustion.html

  * igt@gem_pxp@create-regular-context-1:
    - shard-rkl:          NOTRUN -> [TIMEOUT][109] ([i915#12917] / [i915#12964]) +1 other test timeout
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-4/igt@gem_pxp@create-regular-context-1.html

  * igt@gem_pxp@display-protected-crc:
    - shard-dg2-9:        NOTRUN -> [SKIP][110] ([i915#4270])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@gem_pxp@display-protected-crc.html

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - shard-dg2:          NOTRUN -> [SKIP][111] ([i915#4270]) +2 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
    - shard-rkl:          NOTRUN -> [TIMEOUT][112] ([i915#12964])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html

  * igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
    - shard-rkl:          [PASS][113] -> [TIMEOUT][114] ([i915#12917] / [i915#12964])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-rkl-8/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-6/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html

  * igt@gem_readwrite@new-obj:
    - shard-dg2:          NOTRUN -> [SKIP][115] ([i915#3282]) +3 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-10/igt@gem_readwrite@new-obj.html

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][116] ([i915#8428]) +1 other test skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html

  * igt@gem_render_copy@y-tiled-to-vebox-x-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][117] ([i915#5190] / [i915#8428]) +1 other test skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-4/igt@gem_render_copy@y-tiled-to-vebox-x-tiled.html

  * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs:
    - shard-dg2-9:        NOTRUN -> [SKIP][118] ([i915#5190] / [i915#8428]) +2 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][119] ([i915#4079])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_tiled_partial_pwrite_pread@writes-after-reads:
    - shard-dg1:          NOTRUN -> [SKIP][120] ([i915#4077]) +4 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@gem_tiled_partial_pwrite_pread@writes-after-reads.html

  * igt@gem_tiled_pread_basic:
    - shard-dg2-9:        NOTRUN -> [SKIP][121] ([i915#4079])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@gem_tiled_pread_basic.html

  * igt@gem_userptr_blits@access-control:
    - shard-mtlp:         NOTRUN -> [SKIP][122] ([i915#3297])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@gem_userptr_blits@access-control.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-dg2:          NOTRUN -> [SKIP][123] ([i915#3297])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@gem_userptr_blits@create-destroy-unsync.html
    - shard-rkl:          NOTRUN -> [SKIP][124] ([i915#3297]) +2 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-dg2-9:        NOTRUN -> [SKIP][125] ([i915#3297] / [i915#4880])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@gem_userptr_blits@readonly-pwrite-unsync:
    - shard-tglu:         NOTRUN -> [SKIP][126] ([i915#3297]) +1 other test skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-3/igt@gem_userptr_blits@readonly-pwrite-unsync.html

  * igt@gem_userptr_blits@readonly-unsync:
    - shard-dg2-9:        NOTRUN -> [SKIP][127] ([i915#3297]) +1 other test skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@gem_userptr_blits@readonly-unsync.html

  * igt@gem_userptr_blits@relocations:
    - shard-rkl:          NOTRUN -> [SKIP][128] ([i915#3281] / [i915#3297])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@gem_userptr_blits@relocations.html

  * igt@gem_userptr_blits@unsync-unmap:
    - shard-tglu-1:       NOTRUN -> [SKIP][129] ([i915#3297]) +1 other test skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@gem_userptr_blits@unsync-unmap.html

  * igt@gen3_render_tiledx_blits:
    - shard-dg1:          NOTRUN -> [SKIP][130] +2 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@gen3_render_tiledx_blits.html

  * igt@gen7_exec_parse@bitmasks:
    - shard-dg2:          NOTRUN -> [SKIP][131] +6 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-11/igt@gen7_exec_parse@bitmasks.html

  * igt@gen9_exec_parse@bb-large:
    - shard-tglu-1:       NOTRUN -> [SKIP][132] ([i915#2527] / [i915#2856]) +1 other test skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@gen9_exec_parse@bb-large.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-rkl:          NOTRUN -> [SKIP][133] ([i915#2527]) +1 other test skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@gen9_exec_parse@bb-oversize.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-dg2-9:        NOTRUN -> [SKIP][134] ([i915#2856])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-tglu:         NOTRUN -> [SKIP][135] ([i915#2527] / [i915#2856]) +1 other test skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-10/igt@gen9_exec_parse@bb-start-far.html

  * igt@gen9_exec_parse@bb-start-param:
    - shard-dg2:          NOTRUN -> [SKIP][136] ([i915#2856]) +1 other test skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-10/igt@gen9_exec_parse@bb-start-param.html

  * igt@gen9_exec_parse@cmd-crossing-page:
    - shard-dg1:          NOTRUN -> [SKIP][137] ([i915#2527])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@gen9_exec_parse@cmd-crossing-page.html

  * igt@gen9_exec_parse@unaligned-jump:
    - shard-mtlp:         NOTRUN -> [SKIP][138] ([i915#2856])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@gen9_exec_parse@unaligned-jump.html

  * igt@i915_fb_tiling:
    - shard-dg2-9:        NOTRUN -> [SKIP][139] ([i915#4881])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@i915_fb_tiling.html

  * igt@i915_hangman@detector@vcs0:
    - shard-mtlp:         [PASS][140] -> [ABORT][141] ([i915#13193]) +2 other tests abort
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-mtlp-3/igt@i915_hangman@detector@vcs0.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-7/igt@i915_hangman@detector@vcs0.html

  * igt@i915_hangman@hangcheck-unterminated:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][142] ([i915#12964]) +15 other tests dmesg-warn
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@i915_hangman@hangcheck-unterminated.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-rkl:          [PASS][143] -> [ABORT][144] ([i915#9820])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-rkl-3/igt@i915_module_load@reload-with-fault-injection.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-8/igt@i915_module_load@reload-with-fault-injection.html
    - shard-tglu:         [PASS][145] -> [ABORT][146] ([i915#12817] / [i915#9820])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-tglu-9/igt@i915_module_load@reload-with-fault-injection.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-10/igt@i915_module_load@reload-with-fault-injection.html
    - shard-mtlp:         NOTRUN -> [ABORT][147] ([i915#10131] / [i915#10887] / [i915#13592])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@i915_module_load@reload-with-fault-injection.html
    - shard-dg2:          [PASS][148] -> [ABORT][149] ([i915#10887] / [i915#9820])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg2-7/igt@i915_module_load@reload-with-fault-injection.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-6/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_freq_api@freq-reset:
    - shard-tglu-1:       NOTRUN -> [SKIP][150] ([i915#8399]) +1 other test skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@i915_pm_freq_api@freq-reset.html

  * igt@i915_pm_freq_mult@media-freq@gt0:
    - shard-tglu:         NOTRUN -> [SKIP][151] ([i915#6590]) +1 other test skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-10/igt@i915_pm_freq_mult@media-freq@gt0.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-rkl:          NOTRUN -> [FAIL][152] ([i915#12942]) +1 other test fail
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-tglu:         NOTRUN -> [WARN][153] ([i915#2681]) +4 other tests warn
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-9/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_pm_rps@min-max-config-idle:
    - shard-dg2:          NOTRUN -> [SKIP][154] ([i915#11681] / [i915#6621])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-10/igt@i915_pm_rps@min-max-config-idle.html

  * igt@i915_pm_sseu@full-enable:
    - shard-dg2-9:        NOTRUN -> [SKIP][155] ([i915#4387])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@i915_pm_sseu@full-enable.html
    - shard-rkl:          NOTRUN -> [SKIP][156] ([i915#4387])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-5/igt@i915_pm_sseu@full-enable.html
    - shard-tglu:         NOTRUN -> [SKIP][157] ([i915#4387])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-3/igt@i915_pm_sseu@full-enable.html

  * igt@i915_query@hwconfig_table:
    - shard-tglu-1:       NOTRUN -> [SKIP][158] ([i915#6245])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@i915_query@hwconfig_table.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-rkl:          NOTRUN -> [SKIP][159] ([i915#5723])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-4/igt@i915_query@test-query-geometry-subslices.html
    - shard-tglu:         NOTRUN -> [SKIP][160] ([i915#5723])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-9/igt@i915_query@test-query-geometry-subslices.html

  * igt@i915_selftest@mock@memory_region:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][161] ([i915#9311]) +1 other test dmesg-warn
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@i915_selftest@mock@memory_region.html

  * igt@i915_suspend@sysfs-reader:
    - shard-glk:          [PASS][162] -> [INCOMPLETE][163] ([i915#13502] / [i915#4817])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-glk4/igt@i915_suspend@sysfs-reader.html
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-glk1/igt@i915_suspend@sysfs-reader.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
    - shard-dg2-9:        NOTRUN -> [SKIP][164] ([i915#4212])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-mtlp:         NOTRUN -> [SKIP][165] ([i915#5190])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
    - shard-dg2:          NOTRUN -> [SKIP][166] ([i915#4212])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-4/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-hdmi-a-4-y-rc-ccs-cc:
    - shard-dg1:          NOTRUN -> [SKIP][167] ([i915#8709]) +3 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-19/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-hdmi-a-4-y-rc-ccs-cc.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc:
    - shard-rkl:          NOTRUN -> [SKIP][168] ([i915#8709]) +1 other test skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-4/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][169] ([i915#8709]) +15 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-6/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-dg2:          NOTRUN -> [SKIP][170] ([i915#9531])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
    - shard-rkl:          NOTRUN -> [SKIP][171] ([i915#9531])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition:
    - shard-mtlp:         NOTRUN -> [SKIP][172] ([i915#1769] / [i915#3555])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_atomic_transition@plane-all-modeset-transition.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-dg2:          [PASS][173] -> [FAIL][174] ([i915#5956]) +1 other test fail
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg2-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing:
    - shard-dg1:          [PASS][175] -> [SKIP][176]
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing.html
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-rkl:          NOTRUN -> [SKIP][177] ([i915#5286]) +4 other tests skip
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-tglu:         NOTRUN -> [SKIP][178] ([i915#5286]) +3 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-9/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-tglu-1:       NOTRUN -> [SKIP][179] ([i915#5286]) +2 other tests skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-mtlp:         [PASS][180] -> [FAIL][181] ([i915#5138])
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][182] ([i915#3638])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-4/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-90:
    - shard-dg2-9:        NOTRUN -> [SKIP][183] ([i915#4538] / [i915#5190]) +1 other test skip
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_big_fb@y-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-dg2:          NOTRUN -> [SKIP][184] ([i915#5190]) +1 other test skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@y-tiled-addfb-size-overflow:
    - shard-dg2-9:        NOTRUN -> [SKIP][185] ([i915#5190]) +1 other test skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_big_fb@y-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][186] ([i915#4538] / [i915#5190]) +7 other tests skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-11/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-mtlp:         NOTRUN -> [SKIP][187] +5 other tests skip
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb:
    - shard-rkl:          [PASS][188] -> [DMESG-WARN][189] ([i915#12964]) +4 other tests dmesg-warn
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-rkl-8/igt@kms_busy@extended-pageflip-modeset-hang-oldfb.html
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-6/igt@kms_busy@extended-pageflip-modeset-hang-oldfb.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][190] ([i915#6095]) +127 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-14/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-dg2-9:        NOTRUN -> [SKIP][191] ([i915#12313])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][192] ([i915#6095]) +54 other tests skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-3/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][193] ([i915#12313])
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-4/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][194] ([i915#12313])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-a-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][195] ([i915#10307] / [i915#6095]) +185 other tests skip
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-11/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-a-dp-3.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][196] ([i915#12313])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-10/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][197] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-4/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][198] ([i915#6095]) +39 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][199] ([i915#6095]) +77 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-2:
    - shard-dg2-9:        NOTRUN -> [SKIP][200] ([i915#6095]) +4 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-a-hdmi-a-2:
    - shard-glk:          NOTRUN -> [INCOMPLETE][201] ([i915#12796]) +1 other test incomplete
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-glk1/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][202] ([i915#6095]) +20 other tests skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1:
    - shard-glk:          [PASS][203] -> [INCOMPLETE][204] ([i915#12796])
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-glk3/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-glk3/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-2:
    - shard-dg2-9:        NOTRUN -> [SKIP][205] ([i915#10307] / [i915#6095]) +19 other tests skip
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][206] ([i915#12313]) +1 other test skip
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][207] ([i915#6095]) +24 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][208] ([i915#12313]) +1 other test skip
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-10/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1:
    - shard-glk:          NOTRUN -> [SKIP][209] +41 other tests skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-glk1/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-tglu-1:       NOTRUN -> [SKIP][210] ([i915#3742])
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][211] ([i915#11616] / [i915#7213]) +3 other tests skip
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html

  * igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][212] ([i915#4087]) +3 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-6/igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3.html

  * igt@kms_chamelium_audio@dp-audio-edid:
    - shard-mtlp:         NOTRUN -> [SKIP][213] ([i915#11151] / [i915#7828]) +2 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_chamelium_audio@dp-audio-edid.html

  * igt@kms_chamelium_audio@hdmi-audio:
    - shard-dg2:          NOTRUN -> [SKIP][214] ([i915#11151] / [i915#7828]) +5 other tests skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-4/igt@kms_chamelium_audio@hdmi-audio.html

  * igt@kms_chamelium_frames@hdmi-crc-fast:
    - shard-dg2-9:        NOTRUN -> [SKIP][215] ([i915#11151] / [i915#7828]) +2 other tests skip
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_chamelium_frames@hdmi-crc-fast.html

  * igt@kms_chamelium_frames@hdmi-frame-dump:
    - shard-tglu:         NOTRUN -> [SKIP][216] ([i915#11151] / [i915#7828]) +4 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-10/igt@kms_chamelium_frames@hdmi-frame-dump.html

  * igt@kms_chamelium_hpd@dp-hpd:
    - shard-rkl:          NOTRUN -> [SKIP][217] ([i915#11151] / [i915#7828]) +6 other tests skip
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@kms_chamelium_hpd@dp-hpd.html

  * igt@kms_chamelium_hpd@dp-hpd-storm-disable:
    - shard-tglu-1:       NOTRUN -> [SKIP][218] ([i915#11151] / [i915#7828]) +3 other tests skip
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html

  * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
    - shard-dg1:          NOTRUN -> [SKIP][219] ([i915#11151] / [i915#7828]) +1 other test skip
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html

  * igt@kms_color@deep-color:
    - shard-dg2:          [PASS][220] -> [SKIP][221] ([i915#3555]) +1 other test skip
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg2-10/igt@kms_color@deep-color.html
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-7/igt@kms_color@deep-color.html
    - shard-tglu-1:       NOTRUN -> [SKIP][222] ([i915#3555] / [i915#9979])
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_color@deep-color.html

  * igt@kms_content_protection@atomic:
    - shard-dg2-9:        NOTRUN -> [SKIP][223] ([i915#7118] / [i915#9424])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-dg2:          NOTRUN -> [SKIP][224] ([i915#3299])
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-rkl:          NOTRUN -> [SKIP][225] ([i915#3116]) +1 other test skip
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@legacy:
    - shard-tglu-1:       NOTRUN -> [SKIP][226] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [FAIL][227] ([i915#7173]) +1 other test fail
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-10/igt@kms_content_protection@lic-type-0@pipe-a-dp-4.html

  * igt@kms_content_protection@mei-interface:
    - shard-tglu-1:       NOTRUN -> [SKIP][228] ([i915#6944] / [i915#9424])
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@srm:
    - shard-mtlp:         NOTRUN -> [SKIP][229] ([i915#6944])
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-offscreen-32x10:
    - shard-dg2-9:        NOTRUN -> [SKIP][230] ([i915#3555]) +1 other test skip
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_cursor_crc@cursor-offscreen-32x10.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-tglu:         NOTRUN -> [SKIP][231] ([i915#13049]) +3 other tests skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-3/igt@kms_cursor_crc@cursor-onscreen-512x512.html
    - shard-dg2-9:        NOTRUN -> [SKIP][232] ([i915#13049]) +1 other test skip
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_cursor_crc@cursor-onscreen-512x512.html
    - shard-rkl:          NOTRUN -> [SKIP][233] ([i915#13049]) +1 other test skip
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-5/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-tglu-1:       NOTRUN -> [SKIP][234] ([i915#13049])
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-dg2:          NOTRUN -> [SKIP][235] ([i915#3555])
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-4/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_crc@cursor-rapid-movement-max-size:
    - shard-tglu-1:       NOTRUN -> [SKIP][236] ([i915#3555]) +1 other test skip
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-mtlp:         NOTRUN -> [SKIP][237] ([i915#8814])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [DMESG-WARN][238] ([i915#4423])
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-17/igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-4.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-mtlp:         NOTRUN -> [SKIP][239] ([i915#9809])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][240] ([i915#13046] / [i915#5354]) +3 other tests skip
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-mtlp:         NOTRUN -> [SKIP][241] ([i915#4213])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-dg2-9:        NOTRUN -> [SKIP][242] ([i915#4103] / [i915#4213])
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
    - shard-dg2-9:        NOTRUN -> [SKIP][243] ([i915#13046] / [i915#5354]) +2 other tests skip
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html

  * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
    - shard-dg2:          NOTRUN -> [SKIP][244] ([i915#9067])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
    - shard-rkl:          NOTRUN -> [SKIP][245] ([i915#9067])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-rkl:          NOTRUN -> [SKIP][246] ([i915#4103])
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-tglu-1:       NOTRUN -> [SKIP][247] ([i915#4103])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_display_modes@mst-extended-mode-negative:
    - shard-dg2-9:        NOTRUN -> [SKIP][248] ([i915#8588])
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_display_modes@mst-extended-mode-negative.html
    - shard-rkl:          NOTRUN -> [SKIP][249] ([i915#8588])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-5/igt@kms_display_modes@mst-extended-mode-negative.html
    - shard-tglu:         NOTRUN -> [SKIP][250] ([i915#8588])
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-3/igt@kms_display_modes@mst-extended-mode-negative.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][251] ([i915#3804])
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_dp_aux_dev:
    - shard-dg2:          NOTRUN -> [SKIP][252] ([i915#1257])
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-4/igt@kms_dp_aux_dev.html

  * igt@kms_draw_crc@draw-method-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][253] ([i915#8812])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@kms_draw_crc@draw-method-mmap-gtt.html

  * igt@kms_dsc@dsc-basic:
    - shard-tglu-1:       NOTRUN -> [SKIP][254] ([i915#3555] / [i915#3840])
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-mtlp:         NOTRUN -> [SKIP][255] ([i915#3840])
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-rkl:          NOTRUN -> [SKIP][256] ([i915#3840] / [i915#9053])
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-dg1:          [PASS][257] -> [SKIP][258] ([i915#1849])
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_fbcon_fbt@fbc-suspend.html
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_feature_discovery@display-2x:
    - shard-dg2:          NOTRUN -> [SKIP][259] ([i915#1839])
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@kms_feature_discovery@display-2x.html
    - shard-rkl:          NOTRUN -> [SKIP][260] ([i915#1839])
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@kms_feature_discovery@display-2x.html

  * igt@kms_feature_discovery@display-4x:
    - shard-tglu-1:       NOTRUN -> [SKIP][261] ([i915#1839]) +1 other test skip
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-mtlp:         NOTRUN -> [SKIP][262] ([i915#9337])
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@psr1:
    - shard-tglu:         NOTRUN -> [SKIP][263] ([i915#658])
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-10/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
    - shard-mtlp:         NOTRUN -> [SKIP][264] ([i915#3637]) +1 other test skip
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
    - shard-dg1:          NOTRUN -> [SKIP][265] ([i915#9934]) +2 other tests skip
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][266] ([i915#9934]) +6 other tests skip
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-flip-vs-panning:
    - shard-dg2-9:        NOTRUN -> [SKIP][267] ([i915#9934]) +4 other tests skip
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_flip@2x-flip-vs-panning.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-tglu:         NOTRUN -> [SKIP][268] ([i915#3637]) +7 other tests skip
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-3/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset:
    - shard-dg2:          NOTRUN -> [SKIP][269] ([i915#9934]) +2 other tests skip
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-11/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html

  * igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
    - shard-tglu-1:       NOTRUN -> [SKIP][270] ([i915#3637]) +4 other tests skip
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
    - shard-tglu:         [PASS][271] -> [FAIL][272] ([i915#11989]) +1 other test fail
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-tglu-10/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-dg2:          [PASS][273] -> [FAIL][274] ([i915#13027])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg2-2/igt@kms_flip@flip-vs-expired-vblank.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-10/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@wf_vblank-ts-check-interruptible@b-dp4:
    - shard-dg2:          NOTRUN -> [FAIL][275] ([i915#11989]) +2 other tests fail
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-10/igt@kms_flip@wf_vblank-ts-check-interruptible@b-dp4.html

  * igt@kms_flip@wf_vblank-ts-check-interruptible@b-vga1:
    - shard-snb:          [PASS][276] -> [FAIL][277] ([i915#11989]) +2 other tests fail
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-snb4/igt@kms_flip@wf_vblank-ts-check-interruptible@b-vga1.html
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-snb4/igt@kms_flip@wf_vblank-ts-check-interruptible@b-vga1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][278] ([i915#2587] / [i915#2672]) +4 other tests skip
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-13/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][279] ([i915#2672]) +2 other tests skip
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-10/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-dg1:          [PASS][280] -> [SKIP][281] ([i915#3555]) +5 other tests skip
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][282] ([i915#2672] / [i915#8813])
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][283] ([i915#2672] / [i915#3555]) +1 other test skip
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
    - shard-tglu-1:       NOTRUN -> [SKIP][284] ([i915#2587] / [i915#2672]) +1 other test skip
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-rkl:          NOTRUN -> [SKIP][285] ([i915#2672] / [i915#3555]) +5 other tests skip
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
    - shard-tglu:         NOTRUN -> [SKIP][286] ([i915#2672] / [i915#3555])
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-9/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][287] ([i915#2672]) +5 other tests skip
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
    - shard-tglu:         NOTRUN -> [SKIP][288] ([i915#2587] / [i915#2672])
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-9/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling:
    - shard-dg1:          NOTRUN -> [SKIP][289] ([i915#3555]) +1 other test skip
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
    - shard-dg2:          NOTRUN -> [SKIP][290] ([i915#2672] / [i915#3555])
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-dg2-9:        NOTRUN -> [SKIP][291] ([i915#2672] / [i915#3555])
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-dg2-9:        NOTRUN -> [SKIP][292] ([i915#2672])
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][293] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-mtlp:         NOTRUN -> [SKIP][294] ([i915#2672] / [i915#3555] / [i915#8813]) +2 other tests skip
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
    - shard-dg1:          [PASS][295] -> [SKIP][296] ([i915#4342]) +6 other tests skip
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-snb:          [PASS][297] -> [SKIP][298] +4 other tests skip
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt:
    - shard-dg2:          NOTRUN -> [SKIP][299] ([i915#5354]) +13 other tests skip
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary:
    - shard-dg2:          [PASS][300] -> [FAIL][301] ([i915#6880]) +1 other test fail
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-dg2-9:        NOTRUN -> [SKIP][302] ([i915#10055])
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt:
    - shard-dg2-9:        NOTRUN -> [SKIP][303] ([i915#3458]) +6 other tests skip
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][304] +21 other tests skip
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt:
    - shard-dg2-9:        NOTRUN -> [SKIP][305] ([i915#5354]) +11 other tests skip
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
    - shard-dg1:          NOTRUN -> [SKIP][306] ([i915#4342]) +15 other tests skip
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-mtlp:         NOTRUN -> [SKIP][307] ([i915#1825]) +10 other tests skip
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt:
    - shard-rkl:          NOTRUN -> [SKIP][308] ([i915#1825]) +32 other tests skip
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][309] ([i915#8708]) +13 other tests skip
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-10/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][310] ([i915#10433] / [i915#3458])
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][311] ([i915#3458]) +8 other tests skip
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][312] ([i915#8708]) +5 other tests skip
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
    - shard-rkl:          NOTRUN -> [SKIP][313] ([i915#3023]) +20 other tests skip
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-dg2-9:        NOTRUN -> [SKIP][314] ([i915#8708]) +6 other tests skip
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-tglu:         NOTRUN -> [SKIP][315] +65 other tests skip
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-10/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-dg2:          [PASS][316] -> [SKIP][317] ([i915#3555] / [i915#8228])
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg2-10/igt@kms_hdr@bpc-switch-suspend.html
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-3/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-tglu-1:       NOTRUN -> [SKIP][318] ([i915#12713])
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@invalid-hdr:
    - shard-tglu-1:       NOTRUN -> [SKIP][319] ([i915#3555] / [i915#8228])
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@static-toggle:
    - shard-tglu:         NOTRUN -> [SKIP][320] ([i915#3555] / [i915#8228])
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-10/igt@kms_hdr@static-toggle.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][321] ([i915#12394])
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-10/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][322] ([i915#12339])
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@kms_joiner@basic-ultra-joiner.html
    - shard-dg2:          NOTRUN -> [SKIP][323] ([i915#12339])
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][324] ([i915#12388])
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-dg2-9:        NOTRUN -> [SKIP][325] ([i915#12339])
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          NOTRUN -> [SKIP][326] ([i915#4816])
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
    - shard-tglu:         NOTRUN -> [SKIP][327] ([i915#1839])
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-9/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-tglu-1:       NOTRUN -> [SKIP][328] ([i915#6301])
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c:
    - shard-dg2-9:        NOTRUN -> [SKIP][329] +4 other tests skip
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1:
    - shard-glk:          [PASS][330] -> [INCOMPLETE][331] ([i915#12756])
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-glk7/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-glk9/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html

  * igt@kms_plane@pixel-format-source-clamping:
    - shard-dg1:          [PASS][332] -> [SKIP][333] ([i915#8825]) +1 other test skip
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-18/igt@kms_plane@pixel-format-source-clamping.html
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_plane@pixel-format-source-clamping.html

  * igt@kms_plane_alpha_blend@alpha-transparent-fb:
    - shard-dg1:          [PASS][334] -> [SKIP][335] ([i915#7294]) +1 other test skip
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-13/igt@kms_plane_alpha_blend@alpha-transparent-fb.html
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_plane_alpha_blend@alpha-transparent-fb.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-rkl:          NOTRUN -> [SKIP][336] ([i915#3555]) +6 other tests skip
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-dg2:          NOTRUN -> [SKIP][337] ([i915#3555] / [i915#8806])
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-4/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-d:
    - shard-dg1:          NOTRUN -> [SKIP][338] ([i915#12247] / [i915#8152]) +2 other tests skip
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-d.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b:
    - shard-mtlp:         NOTRUN -> [SKIP][339] ([i915#12247]) +4 other tests skip
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation:
    - shard-tglu-1:       NOTRUN -> [SKIP][340] ([i915#12247]) +4 other tests skip
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a:
    - shard-rkl:          NOTRUN -> [SKIP][341] ([i915#12247]) +7 other tests skip
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-4/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-b:
    - shard-tglu:         NOTRUN -> [SKIP][342] ([i915#12247]) +13 other tests skip
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-9/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-b.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5:
    - shard-dg1:          [PASS][343] -> [SKIP][344] ([i915#12247] / [i915#6953] / [i915#8152])
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-13/igt@kms_plane_scaling@planes-downscale-factor-0-5.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_plane_scaling@planes-downscale-factor-0-5.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling:
    - shard-dg1:          [PASS][345] -> [SKIP][346] ([i915#12247] / [i915#3558] / [i915#8152])
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling.html
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling@pipe-d:
    - shard-dg1:          [PASS][347] -> [SKIP][348] ([i915#12247] / [i915#8152]) +2 other tests skip
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling@pipe-d.html
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling@pipe-d.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25:
    - shard-dg2-9:        NOTRUN -> [SKIP][349] ([i915#12247] / [i915#6953] / [i915#9423])
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html
    - shard-rkl:          NOTRUN -> [SKIP][350] ([i915#12247] / [i915#6953])
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-5/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html
    - shard-tglu:         NOTRUN -> [SKIP][351] ([i915#12247] / [i915#6953])
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-3/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c:
    - shard-dg2-9:        NOTRUN -> [SKIP][352] ([i915#12247]) +3 other tests skip
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5:
    - shard-dg1:          [PASS][353] -> [SKIP][354] ([i915#12247] / [i915#3555] / [i915#6953] / [i915#8152])
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-17/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b:
    - shard-dg1:          [PASS][355] -> [SKIP][356] ([i915#12247]) +14 other tests skip
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-17/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b.html
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75:
    - shard-dg1:          NOTRUN -> [SKIP][357] ([i915#12247] / [i915#6953] / [i915#8152])
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b:
    - shard-dg1:          NOTRUN -> [SKIP][358] ([i915#12247]) +5 other tests skip
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25:
    - shard-dg1:          [PASS][359] -> [SKIP][360] ([i915#3555] / [i915#6953] / [i915#8152]) +1 other test skip
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_plane_scaling@planes-upscale-factor-0-25.html
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_plane_scaling@planes-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-d:
    - shard-dg1:          [PASS][361] -> [SKIP][362] ([i915#8152]) +2 other tests skip
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-d.html
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-d.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-tglu-1:       NOTRUN -> [SKIP][363] ([i915#9812])
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][364] ([i915#5354])
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc5-dpms-negative:
    - shard-dg1:          [PASS][365] -> [SKIP][366] ([i915#13441])
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-18/igt@kms_pm_dc@dc5-dpms-negative.html
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_pm_dc@dc5-dpms-negative.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-rkl:          NOTRUN -> [SKIP][367] ([i915#9685])
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-4/igt@kms_pm_dc@dc5-psr.html
    - shard-tglu:         NOTRUN -> [SKIP][368] ([i915#9685])
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-9/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-dg2:          NOTRUN -> [SKIP][369] ([i915#3828])
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-11/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][370] ([i915#5978])
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-10/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-dg1:          NOTRUN -> [FAIL][371] ([i915#12561] / [i915#7330])
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-rkl:          NOTRUN -> [SKIP][372] ([i915#3828])
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          [PASS][373] -> [SKIP][374] ([i915#9519])
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-2/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-dg1:          [PASS][375] -> [SKIP][376] ([i915#9519])
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-13/igt@kms_pm_rpm@dpms-non-lpsp.html
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@fences:
    - shard-mtlp:         NOTRUN -> [SKIP][377] ([i915#4077])
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_pm_rpm@fences.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-dg2-9:        NOTRUN -> [SKIP][378] ([i915#9519])
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-dg2:          NOTRUN -> [SKIP][379] ([i915#9519]) +1 other test skip
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@kms_pm_rpm@modeset-non-lpsp.html
    - shard-rkl:          NOTRUN -> [SKIP][380] ([i915#9519])
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-tglu:         NOTRUN -> [SKIP][381] ([i915#9519])
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-10/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@system-suspend-modeset:
    - shard-dg1:          [PASS][382] -> [SKIP][383] ([i915#3547] / [i915#9519])
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-19/igt@kms_pm_rpm@system-suspend-modeset.html
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_pm_rpm@system-suspend-modeset.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-dg2-9:        NOTRUN -> [SKIP][384] ([i915#6524] / [i915#6805])
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
    - shard-glk:          NOTRUN -> [SKIP][385] ([i915#11520])
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-glk1/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
    - shard-dg1:          NOTRUN -> [SKIP][386] ([i915#11520]) +1 other test skip
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][387] ([i915#9808])
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-b-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][388] ([i915#12316]) +1 other test skip
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-b-edp-1.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-dg2-9:        NOTRUN -> [SKIP][389] ([i915#11520]) +1 other test skip
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html
    - shard-rkl:          NOTRUN -> [SKIP][390] ([i915#11520]) +7 other tests skip
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-5/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html
    - shard-tglu:         NOTRUN -> [SKIP][391] ([i915#11520]) +4 other tests skip
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-3/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
    - shard-tglu-1:       NOTRUN -> [SKIP][392] ([i915#11520]) +4 other tests skip
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-dg2:          NOTRUN -> [SKIP][393] ([i915#11520]) +5 other tests skip
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-4/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-dg2-9:        NOTRUN -> [SKIP][394] ([i915#9683])
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-dg1:          NOTRUN -> [SKIP][395] ([i915#9683])
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-pr-sprite-render:
    - shard-dg1:          NOTRUN -> [SKIP][396] ([i915#1072] / [i915#9732]) +4 other tests skip
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg1-15/igt@kms_psr@fbc-pr-sprite-render.html

  * igt@kms_psr@fbc-psr-sprite-mmap-cpu:
    - shard-dg2-9:        NOTRUN -> [SKIP][397] ([i915#1072] / [i915#9732]) +8 other tests skip
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_psr@fbc-psr-sprite-mmap-cpu.html

  * igt@kms_psr@fbc-psr2-cursor-mmap-cpu:
    - shard-mtlp:         NOTRUN -> [SKIP][398] ([i915#9688]) +4 other tests skip
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_psr@fbc-psr2-cursor-mmap-cpu.html

  * igt@kms_psr@pr-dpms:
    - shard-tglu:         NOTRUN -> [SKIP][399] ([i915#9732]) +15 other tests skip
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-10/igt@kms_psr@pr-dpms.html

  * igt@kms_psr@psr-cursor-render:
    - shard-dg2:          NOTRUN -> [SKIP][400] ([i915#1072] / [i915#9732]) +14 other tests skip
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-4/igt@kms_psr@psr-cursor-render.html

  * igt@kms_psr@psr2-sprite-mmap-cpu:
    - shard-tglu-1:       NOTRUN -> [SKIP][401] ([i915#9732]) +9 other tests skip
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_psr@psr2-sprite-mmap-cpu.html

  * igt@kms_psr@psr2-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][402] ([i915#1072] / [i915#9732]) +17 other tests skip
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-7/igt@kms_psr@psr2-suspend.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2:          NOTRUN -> [SKIP][403] ([i915#12755])
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-8/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@exhaust-fences:
    - shard-mtlp:         NOTRUN -> [SKIP][404] ([i915#4235])
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_rotation_crc@exhaust-fences.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-tglu-1:       NOTRUN -> [SKIP][405] ([i915#5289])
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-1/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-mtlp:         NOTRUN -> [SKIP][406] ([i915#12755])
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-mtlp-8/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-rkl:          NOTRUN -> [SKIP][407] ([i915#5289]) +2 other tests skip
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-rkl-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
    - shard-tglu:         NOTRUN -> [SKIP][408] ([i915#5289]) +1 other test skip
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-tglu-9/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-dg2-9:        NOTRUN -> [SKIP][409] ([i915#12755] / [i915#5190])
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free:
    - shard-dg2-9:        NOTRUN -> [ABORT][410] ([i915#13179]) +1 other test abort
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-9/igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free.html

  * igt@kms_sysfs_edid_timing:
    - shard-dg2:          NOTRUN -> [FAIL][411] ([IGT#160])
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/shard-dg2-4/igt@kms_sysfs_edid_timing.html
    - shard-dg1:          [PASS][412] -> [FAIL][413] ([IGT#160] / [i915#6493])
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16122/shard-dg1-15/

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144748v1/index.html

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^ permalink raw reply	[flat|nested] 35+ messages in thread

end of thread, other threads:[~2025-02-13 11:16 UTC | newest]

Thread overview: 35+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-02-12 16:36 [PATCH 00/14] drm/i915/display: conversions to struct intel_display Jani Nikula
2025-02-12 16:36 ` [PATCH 01/14] drm/i915/dp: convert g4x_dp.[ch] to struct intel display Jani Nikula
2025-02-13  8:48   ` Kandpal, Suraj
2025-02-13  9:13     ` Jani Nikula
2025-02-13  9:19       ` Kandpal, Suraj
2025-02-12 16:36 ` [PATCH 02/14] drm/i915/hdmi: convert g4x_hdmi.[ch] to struct intel_display Jani Nikula
2025-02-13  8:55   ` Kandpal, Suraj
2025-02-13  9:15     ` Jani Nikula
2025-02-12 16:36 ` [PATCH 03/14] drm/i915/ips: convert hsw_ips.c " Jani Nikula
2025-02-13  8:56   ` Kandpal, Suraj
2025-02-12 16:36 ` [PATCH 04/14] drm/i915/display: convert assert_transcoder*() " Jani Nikula
2025-02-13  8:58   ` Kandpal, Suraj
2025-02-12 16:36 ` [PATCH 05/14] drm/i915/display: convert assert_port_valid() " Jani Nikula
2025-02-13  8:59   ` Kandpal, Suraj
2025-02-12 16:36 ` [PATCH 06/14] drm/i915/hpd: drop dev_priv parameter from intel_hpd_pin_default() Jani Nikula
2025-02-13  9:01   ` Kandpal, Suraj
2025-02-12 16:36 ` [PATCH 07/14] drm/i915/display: convert intel_set_{cpu, pch}_fifo_underrun_reporting() to intel_display Jani Nikula
2025-02-13  9:03   ` Kandpal, Suraj
2025-02-12 16:36 ` [PATCH 08/14] drm/i915/sdvo: convert intel_sdvo.[ch] to struct intel_display Jani Nikula
2025-02-13  9:13   ` Kandpal, Suraj
2025-02-13 11:16     ` Jani Nikula
2025-02-12 16:36 ` [PATCH 09/14] drm/i915/display: convert intel_cpu_transcoder_mode_valid() to intel_display Jani Nikula
2025-02-13  9:15   ` Kandpal, Suraj
2025-02-12 16:36 ` [PATCH 10/14] drm/i915/display: convert intel_mode_valid_max_plane_size() " Jani Nikula
2025-02-13  9:16   ` Kandpal, Suraj
2025-02-12 16:36 ` [PATCH 11/14] drm/i915/dsi: convert platform checks to display->platform.<platform> style Jani Nikula
2025-02-12 16:36 ` [PATCH 12/14] drm/i915/combo-phy: convert intel_combo_phy.[ch] to struct intel_display Jani Nikula
2025-02-12 16:36 ` [PATCH 13/14] drm/i915/display: convert intel_fifo_underrun.[ch] " Jani Nikula
2025-02-12 16:36 ` [PATCH 14/14] drm/i915/display: convert i915_pipestat_enable_mask() " Jani Nikula
2025-02-12 17:17 ` [PATCH 00/14] drm/i915/display: conversions " Ville Syrjälä
2025-02-13  8:27   ` Jani Nikula
2025-02-12 21:19 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2025-02-12 21:20 ` ✗ Fi.CI.SPARSE: " Patchwork
2025-02-12 21:39 ` ✓ i915.CI.BAT: success " Patchwork
2025-02-13  6:10 ` ✗ i915.CI.Full: failure " Patchwork

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