From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 06/10] drm/i915/dvo: Rename the "active data order" bits
Date: Tue, 22 Nov 2022 14:33:48 +0200 [thread overview]
Message-ID: <87pmdfxj6b.fsf@intel.com> (raw)
In-Reply-To: <20221122120825.26338-7-ville.syrjala@linux.intel.com>
On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We have two sets of bits for DVO "data order" stuff. Rename
> one set to ACT_DATA_ORDER to make it clear they are separate
> bitfields.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dvo.c | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index 255deb55b932..b36c3a620250 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -288,10 +288,10 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
> enum pipe pipe = crtc->pipe;
> u32 dvo_val;
>
> - /* Save the data order, since I don't know what it should be set to. */
> + /* Save the active data order, since I don't know what it should be set to. */
> dvo_val = intel_de_read(i915, DVO(port)) &
> (DVO_DEDICATED_INT_ENABLE |
> - DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
> + DVO_PRESERVE_MASK | DVO_ACT_DATA_ORDER_GBRG);
> dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
> DVO_BLANK_ACTIVE_HIGH;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 89c834d8fff8..464be86d6125 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2600,10 +2600,10 @@
> #define DVO_VSYNC_TRISTATE (1 << 9)
> #define DVO_HSYNC_TRISTATE (1 << 8)
> #define DVO_BORDER_ENABLE (1 << 7)
> -#define DVO_DATA_ORDER_GBRG (1 << 6)
> -#define DVO_DATA_ORDER_RGGB (0 << 6)
> -#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
> -#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
> +#define DVO_ACT_DATA_ORDER_GBRG (1 << 6)
> +#define DVO_ACT_DATA_ORDER_RGGB (0 << 6)
> +#define DVO_ACT_DATA_ORDER_GBRG_ERRATA (0 << 6)
> +#define DVO_ACT_DATA_ORDER_RGGB_ERRATA (1 << 6)
> #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
> #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
> #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2022-11-22 12:34 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-22 12:08 [Intel-gfx] [PATCH 00/10] drm/i915/dvo: Further DVO fixes/cleanups Ville Syrjala
2022-11-22 12:08 ` [Intel-gfx] [PATCH 01/10] drm/i915/dvo/ch7xxx: Fix suspend/resume Ville Syrjala
2022-11-22 12:31 ` Jani Nikula
2022-11-23 14:52 ` Ville Syrjälä
2022-11-22 12:08 ` [Intel-gfx] [PATCH 02/10] drm/i915/dvo/sil164: Nuke pointless return statements Ville Syrjala
2022-11-22 12:32 ` Jani Nikula
2022-11-22 12:08 ` [Intel-gfx] [PATCH 03/10] drm/i915/dvo/sil164: Fix suspend/resume Ville Syrjala
2022-11-22 12:32 ` Jani Nikula
2022-11-22 12:08 ` [Intel-gfx] [PATCH 04/10] drm/i915/dvo: Parametrize DVO/DVO_SRCDIM registers Ville Syrjala
2022-11-22 12:33 ` Jani Nikula
2022-11-22 12:08 ` [Intel-gfx] [PATCH 05/10] drm/i915/dvo: Define a few more DVO register bits Ville Syrjala
2022-11-22 12:33 ` Jani Nikula
2022-11-22 12:08 ` [Intel-gfx] [PATCH 06/10] drm/i915/dvo: Rename the "active data order" bits Ville Syrjala
2022-11-22 12:33 ` Jani Nikula [this message]
2022-11-22 12:08 ` [Intel-gfx] [PATCH 07/10] drm/i915/dvo: Use REG_BIT() & co. for DVO registers Ville Syrjala
2022-11-22 12:35 ` Jani Nikula
2022-11-22 12:36 ` Jani Nikula
2022-11-22 12:08 ` [Intel-gfx] [PATCH 08/10] drm/i915/dvo: Use intel_de_rmw() for DVO enable/disable Ville Syrjala
2022-11-22 12:38 ` Jani Nikula
2022-11-22 12:08 ` [Intel-gfx] [PATCH 09/10] drm/i915/dvo: Extract intel_dvo_regs.h Ville Syrjala
2022-11-22 12:39 ` Jani Nikula
2022-11-22 12:08 ` [Intel-gfx] [PATCH 10/10] drm/i915/dvo: Log about what was detected on which DVO port Ville Syrjala
2022-11-22 12:39 ` Jani Nikula
2022-11-22 15:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dvo: Further DVO fixes/cleanups Patchwork
2022-11-22 15:55 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2022-11-22 16:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-11-23 0:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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