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* [Intel-gfx] [PATCH 1/2] drm/i915/pps: added get_pps_idx() hook as part of pps_get_register() cleanup
@ 2022-09-06  7:14 Animesh Manna
  2022-09-06  7:14 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enabled 2nd pps for dual EDP scenario Animesh Manna
                   ` (5 more replies)
  0 siblings, 6 replies; 9+ messages in thread
From: Animesh Manna @ 2022-09-06  7:14 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Simplified pps_get_register() which use get_pps_idx() hook to derive the
pps instance and get_pps_idx() will be initialized at pps_init().

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
 drivers/gpu/drm/i915/display/intel_pps.c           | 12 ++++++------
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0da9b208d56e..b78b29951241 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1693,6 +1693,7 @@ struct intel_dp {
 	u8 (*preemph_max)(struct intel_dp *intel_dp);
 	u8 (*voltage_max)(struct intel_dp *intel_dp,
 			  const struct intel_crtc_state *crtc_state);
+	int (*get_pps_idx)(struct intel_dp *intel_dp);
 
 	/* Displayport compliance testing */
 	struct intel_dp_compliance compliance;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 21944f5bf3a8..4e770218e29f 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -362,15 +362,10 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
 				    struct pps_registers *regs)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	int pps_idx = 0;
+	int pps_idx = intel_dp->get_pps_idx(intel_dp);
 
 	memset(regs, 0, sizeof(*regs));
 
-	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
-		pps_idx = bxt_power_sequencer_idx(intel_dp);
-	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-		pps_idx = vlv_power_sequencer_pipe(intel_dp);
-
 	regs->pp_ctrl = PP_CONTROL(pps_idx);
 	regs->pp_stat = PP_STATUS(pps_idx);
 	regs->pp_on = PP_ON_DELAYS(pps_idx);
@@ -1432,6 +1427,11 @@ void intel_pps_init(struct intel_dp *intel_dp)
 	intel_dp->pps.initializing = true;
 	INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
 
+	if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+		intel_dp->get_pps_idx = bxt_power_sequencer_idx;
+	else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+		intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
+
 	pps_init_timestamps(intel_dp);
 
 	with_intel_pps_lock(intel_dp, wakeref) {
-- 
2.29.0


^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/pps: added get_pps_idx() hook as part of pps_get_register() cleanup
@ 2022-09-06  6:45 Animesh Manna
  2022-09-06  6:45 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enabled 2nd pps for dual EDP scenario Animesh Manna
  0 siblings, 1 reply; 9+ messages in thread
From: Animesh Manna @ 2022-09-06  6:45 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Simplified pps_get_register() which use get_pps_idx() hook to derive the
pps instance and get_pps_idx() will be initialized at pps_init().

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h |  2 ++
 drivers/gpu/drm/i915/display/intel_pps.c           | 12 ++++++------
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0da9b208d56e..95f71a572b07 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1723,6 +1723,8 @@ struct intel_dp {
 
 	/* When we last wrote the OUI for eDP */
 	unsigned long last_oui_write;
+
+	int (*get_pps_idx)(struct intel_dp *intel_dp);
 };
 
 enum lspcon_vendor {
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 21944f5bf3a8..4e770218e29f 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -362,15 +362,10 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
 				    struct pps_registers *regs)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	int pps_idx = 0;
+	int pps_idx = intel_dp->get_pps_idx(intel_dp);
 
 	memset(regs, 0, sizeof(*regs));
 
-	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
-		pps_idx = bxt_power_sequencer_idx(intel_dp);
-	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-		pps_idx = vlv_power_sequencer_pipe(intel_dp);
-
 	regs->pp_ctrl = PP_CONTROL(pps_idx);
 	regs->pp_stat = PP_STATUS(pps_idx);
 	regs->pp_on = PP_ON_DELAYS(pps_idx);
@@ -1432,6 +1427,11 @@ void intel_pps_init(struct intel_dp *intel_dp)
 	intel_dp->pps.initializing = true;
 	INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
 
+	if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+		intel_dp->get_pps_idx = bxt_power_sequencer_idx;
+	else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+		intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
+
 	pps_init_timestamps(intel_dp);
 
 	with_intel_pps_lock(intel_dp, wakeref) {
-- 
2.29.0


^ permalink raw reply related	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-09-21  8:03 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-09-06  7:14 [Intel-gfx] [PATCH 1/2] drm/i915/pps: added get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna
2022-09-06  7:14 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enabled 2nd pps for dual EDP scenario Animesh Manna
2022-09-06 17:17   ` Jani Nikula
2022-09-06  7:39 ` [Intel-gfx] [PATCH 1/2] drm/i915/pps: added get_pps_idx() hook as part of pps_get_register() cleanup Jani Nikula
2022-09-06  7:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] " Patchwork
2022-09-06  7:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-09-06  7:54 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-09-21  8:02 ` [Intel-gfx] [drm/i915/pps] 9049e35416: BUG:kernel_NULL_pointer_dereference, address kernel test robot
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2022-09-06  6:45 [Intel-gfx] [PATCH 1/2] drm/i915/pps: added get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna
2022-09-06  6:45 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enabled 2nd pps for dual EDP scenario Animesh Manna

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