* [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Exercise intel_timeline_read_hwsp()
2020-10-21 22:04 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use the local HWSP offset during submission Chris Wilson
@ 2020-10-21 22:04 ` Chris Wilson
2020-10-23 11:26 ` Mika Kuoppala
2020-10-21 22:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/gt: Use the local HWSP offset during submission Patchwork
` (9 subsequent siblings)
10 siblings, 1 reply; 14+ messages in thread
From: Chris Wilson @ 2020-10-21 22:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
intel_timeline_read_hwsp() is used to support semaphore waits between
engines, that may themselves be deferred for arbitrary periods -- that
is the read of the target request's HWSP is at an indeterminant point in
the future. To support this, we need to prevent overwriting a HWSP that
is being watched across a seqno wrap (otherwise the next request will
write its value into the old HWSP preventing the watcher from making
progress, ad infinitum.) To simulate the observer across a wrap, let's
create a request that reads from the HWSP and dispatch it at different
points around a wrap to see if the value is lost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 378 +++++++++++++++++++-
1 file changed, 376 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index 19c2cb166e7c..2edf2b15885f 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -17,8 +17,9 @@
#include "../selftests/i915_random.h"
#include "../i915_selftest.h"
-#include "../selftests/igt_flush_test.h"
-#include "../selftests/mock_gem_device.h"
+#include "selftests/igt_flush_test.h"
+#include "selftests/lib_sw_fence.h"
+#include "selftests/mock_gem_device.h"
#include "selftests/mock_timeline.h"
static struct page *hwsp_page(struct intel_timeline *tl)
@@ -755,6 +756,378 @@ static int live_hwsp_wrap(void *arg)
return err;
}
+static int emit_read_hwsp(struct i915_request *rq,
+ u32 seqno, u32 hwsp,
+ u32 *addr)
+{
+ const u32 gpr = i915_mmio_reg_offset(GEN8_RING_CS_GPR(rq->engine->mmio_base, 0));
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 12);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
+ *cs++ = *addr;
+ *cs++ = 0;
+ *cs++ = seqno;
+ *addr += 4;
+
+ *cs++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = gpr;
+ *cs++ = hwsp;
+ *cs++ = 0;
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = gpr;
+ *cs++ = *addr;
+ *cs++ = 0;
+ *addr += 4;
+
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
+struct hwsp_watcher {
+ struct i915_vma *vma;
+ struct i915_request *rq;
+ u32 addr;
+ u32 *map;
+};
+
+static bool cmp_lt(u32 a, u32 b)
+{
+ return a < b;
+}
+
+static bool cmp_gte(u32 a, u32 b)
+{
+ return a >= b;
+}
+
+static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+
+ obj = i915_gem_object_create_internal(gt->i915, SZ_2M);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ w->map = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(w->map)) {
+ i915_gem_object_put(obj);
+ return PTR_ERR(w->map);
+ }
+
+ vma = i915_gem_object_ggtt_pin_ww(obj, NULL, NULL, 0, 0, 0);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return PTR_ERR(vma);
+ }
+
+ w->vma = vma;
+ w->addr = i915_ggtt_offset(vma);
+ return 0;
+}
+
+static int create_watcher(struct hwsp_watcher *w,
+ struct intel_engine_cs *engine,
+ int ringsz)
+{
+ struct intel_context *ce;
+ struct intel_timeline *tl;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ ce->ring = __intel_context_ring_size(ringsz);
+ w->rq = intel_context_create_request(ce);
+ intel_context_put(ce);
+ if (IS_ERR(w->rq))
+ return PTR_ERR(w->rq);
+
+ w->addr = i915_ggtt_offset(w->vma);
+ tl = w->rq->context->timeline;
+
+ /* some light mutex juggling required; think co-routines */
+ lockdep_unpin_lock(&tl->mutex, w->rq->cookie);
+ mutex_unlock(&tl->mutex);
+
+ return 0;
+}
+
+static int check_watcher(struct hwsp_watcher *w, const char *name,
+ bool (*op)(u32 hwsp, u32 seqno))
+{
+ struct i915_request *rq = fetch_and_zero(&w->rq);
+ struct intel_timeline *tl = rq->context->timeline;
+ u32 offset, end;
+ int err;
+
+ GEM_BUG_ON(w->addr - i915_ggtt_offset(w->vma) > w->vma->size);
+
+ i915_request_get(rq);
+ mutex_lock(&tl->mutex);
+ rq->cookie = lockdep_pin_lock(&tl->mutex);
+ i915_request_add(rq);
+
+ if (i915_request_wait(rq, 0, HZ) < 0) {
+ err = -ETIME;
+ goto out;
+ }
+
+ err = 0;
+ offset = 0;
+ end = (w->addr - i915_ggtt_offset(w->vma)) / sizeof(*w->map);
+ while (offset < end) {
+ if (!op(w->map[offset + 1], w->map[offset])) {
+ pr_err("Watcher '%s' found HWSP value %x for seqno %x\n",
+ name, w->map[offset + 1], w->map[offset]);
+ err = -EINVAL;
+ }
+
+ offset += 2;
+ }
+
+out:
+ i915_request_put(rq);
+ return err;
+}
+
+static void cleanup_watcher(struct hwsp_watcher *w)
+{
+ if (w->rq) {
+ struct intel_timeline *tl = w->rq->context->timeline;
+
+ mutex_lock(&tl->mutex);
+ w->rq->cookie = lockdep_pin_lock(&tl->mutex);
+
+ i915_request_add(w->rq);
+ }
+
+ i915_vma_unpin_and_release(&w->vma, I915_VMA_RELEASE_MAP);
+}
+
+static bool retire_requests(struct intel_timeline *tl)
+{
+ struct i915_request *rq, *rn;
+
+ mutex_lock(&tl->mutex);
+ list_for_each_entry_safe(rq, rn, &tl->requests, link)
+ if (!i915_request_retire(rq))
+ break;
+ mutex_unlock(&tl->mutex);
+
+ return !i915_active_fence_isset(&tl->last_request);
+}
+
+static struct i915_request *wrap_timeline(struct i915_request *rq)
+{
+ struct intel_context *ce = rq->context;
+ struct intel_timeline *tl = ce->timeline;
+ u32 seqno = rq->fence.seqno;
+
+ while (tl->seqno >= seqno) { /* Cause a wrap */
+ i915_request_put(rq);
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ return rq;
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ }
+
+ i915_request_put(rq);
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ return rq;
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ return rq;
+}
+
+static int live_hwsp_read(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct hwsp_watcher watcher[2] = {};
+ struct intel_engine_cs *engine;
+ struct intel_timeline *tl;
+ enum intel_engine_id id;
+ int err = 0;
+ int i;
+
+ /*
+ * If we take a reference to the HWSP for reading on the GPU, that
+ * read may be arbitrarily delayed (either by foreign fence or
+ * priority saturation) and a wrap can happen within 30 minutes.
+ * When the GPU read is finally submitted it should be correct,
+ * even across multiple wraps.
+ */
+
+ if (INTEL_GEN(gt->i915) < 8) /* CS convenience [SRM/LRM] */
+ return 0;
+
+ tl = intel_timeline_create(gt);
+ if (IS_ERR(tl))
+ return PTR_ERR(tl);
+
+ if (!tl->hwsp_cacheline)
+ goto out_free;
+
+ for (i = 0; i < ARRAY_SIZE(watcher); i++) {
+ err = setup_watcher(&watcher[i], gt);
+ if (err)
+ goto out;
+ }
+
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce;
+ unsigned long count = 0;
+ IGT_TIMEOUT(end_time);
+
+ /* Create a request we can use for remote reading of the HWSP */
+ err = create_watcher(&watcher[1], engine, SZ_512K);
+ if (err)
+ goto out;
+
+ do {
+ struct i915_sw_fence *submit;
+ struct i915_request *rq;
+ u32 hwsp;
+
+ submit = heap_fence_create(GFP_KERNEL);
+ if (!submit) {
+ err = -ENOMEM;
+ goto out;
+ }
+
+ err = create_watcher(&watcher[0], engine, SZ_4K);
+ if (err)
+ goto out;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ goto out;
+ }
+
+ /* Skip to the end, saving 30 minutes of nops */
+ tl->seqno = -10u + 2 * (count & 3);
+ WRITE_ONCE(*(u32 *)tl->hwsp_seqno, tl->seqno);
+ ce->timeline = intel_timeline_get(tl);
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ intel_context_put(ce);
+ goto out;
+ }
+
+ err = i915_sw_fence_await_dma_fence(&rq->submit,
+ &watcher[0].rq->fence, 0,
+ GFP_KERNEL);
+ if (err < 0) {
+ i915_request_add(rq);
+ intel_context_put(ce);
+ goto out;
+ }
+
+ mutex_lock(&watcher[0].rq->context->timeline->mutex);
+ err = intel_timeline_read_hwsp(rq, watcher[0].rq, &hwsp);
+ if (err == 0)
+ err = emit_read_hwsp(watcher[0].rq, /* before */
+ rq->fence.seqno, hwsp,
+ &watcher[0].addr);
+ mutex_unlock(&watcher[0].rq->context->timeline->mutex);
+ if (err) {
+ i915_request_add(rq);
+ intel_context_put(ce);
+ goto out;
+ }
+
+ mutex_lock(&watcher[1].rq->context->timeline->mutex);
+ err = intel_timeline_read_hwsp(rq, watcher[1].rq, &hwsp);
+ if (err == 0)
+ err = emit_read_hwsp(watcher[1].rq, /* after */
+ rq->fence.seqno, hwsp,
+ &watcher[1].addr);
+ mutex_unlock(&watcher[1].rq->context->timeline->mutex);
+ if (err) {
+ i915_request_add(rq);
+ intel_context_put(ce);
+ goto out;
+ }
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ rq = wrap_timeline(rq);
+ intel_context_put(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out;
+ }
+
+ err = i915_sw_fence_await_dma_fence(&watcher[1].rq->submit,
+ &rq->fence, 0,
+ GFP_KERNEL);
+ if (err < 0) {
+ i915_request_put(rq);
+ goto out;
+ }
+
+ err = check_watcher(&watcher[0], "before", cmp_lt);
+ i915_sw_fence_commit(submit);
+ heap_fence_put(submit);
+ if (err) {
+ i915_request_put(rq);
+ goto out;
+ }
+ count++;
+
+ if (8 * watcher[1].rq->ring->emit >
+ 3 * watcher[1].rq->ring->size) {
+ i915_request_put(rq);
+ break;
+ }
+
+ /* Flush the timeline before manually wrapping again */
+ if (i915_request_wait(rq,
+ I915_WAIT_INTERRUPTIBLE,
+ HZ) < 0) {
+ err = -ETIME;
+ i915_request_put(rq);
+ goto out;
+ }
+
+ retire_requests(tl);
+ i915_request_put(rq);
+ } while (!__igt_timeout(end_time, NULL));
+ WRITE_ONCE(*(u32 *)tl->hwsp_seqno, 0xdeadbeef);
+
+ pr_info("%s: simulated %lu wraps\n", engine->name, count);
+ err = check_watcher(&watcher[1], "after", cmp_gte);
+ if (err)
+ goto out;
+ }
+
+out:
+ for (i = 0; i < ARRAY_SIZE(watcher); i++)
+ cleanup_watcher(&watcher[i]);
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+
+out_free:
+ intel_timeline_put(tl);
+ return err;
+}
+
static int live_hwsp_rollover_kernel(void *arg)
{
struct intel_gt *gt = arg;
@@ -998,6 +1371,7 @@ int intel_timeline_live_selftests(struct drm_i915_private *i915)
SUBTEST(live_hwsp_engine),
SUBTEST(live_hwsp_alternate),
SUBTEST(live_hwsp_wrap),
+ SUBTEST(live_hwsp_read),
SUBTEST(live_hwsp_rollover_kernel),
SUBTEST(live_hwsp_rollover_user),
};
--
2.20.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Exercise intel_timeline_read_hwsp()
2020-10-21 22:04 ` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Exercise intel_timeline_read_hwsp() Chris Wilson
@ 2020-10-23 11:26 ` Mika Kuoppala
0 siblings, 0 replies; 14+ messages in thread
From: Mika Kuoppala @ 2020-10-23 11:26 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> intel_timeline_read_hwsp() is used to support semaphore waits between
> engines, that may themselves be deferred for arbitrary periods -- that
> is the read of the target request's HWSP is at an indeterminant point in
> the future. To support this, we need to prevent overwriting a HWSP that
> is being watched across a seqno wrap (otherwise the next request will
> write its value into the old HWSP preventing the watcher from making
> progress, ad infinitum.) To simulate the observer across a wrap, let's
> create a request that reads from the HWSP and dispatch it at different
> points around a wrap to see if the value is lost.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/selftest_timeline.c | 378 +++++++++++++++++++-
> 1 file changed, 376 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> index 19c2cb166e7c..2edf2b15885f 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> @@ -17,8 +17,9 @@
> #include "../selftests/i915_random.h"
> #include "../i915_selftest.h"
>
> -#include "../selftests/igt_flush_test.h"
> -#include "../selftests/mock_gem_device.h"
> +#include "selftests/igt_flush_test.h"
> +#include "selftests/lib_sw_fence.h"
> +#include "selftests/mock_gem_device.h"
> #include "selftests/mock_timeline.h"
>
> static struct page *hwsp_page(struct intel_timeline *tl)
> @@ -755,6 +756,378 @@ static int live_hwsp_wrap(void *arg)
> return err;
> }
>
> +static int emit_read_hwsp(struct i915_request *rq,
> + u32 seqno, u32 hwsp,
> + u32 *addr)
> +{
> + const u32 gpr = i915_mmio_reg_offset(GEN8_RING_CS_GPR(rq->engine->mmio_base, 0));
> + u32 *cs;
> +
> + cs = intel_ring_begin(rq, 12);
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> +
> + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> + *cs++ = *addr;
> + *cs++ = 0;
> + *cs++ = seqno;
> + *addr += 4;
> +
> + *cs++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_USE_GGTT;
> + *cs++ = gpr;
> + *cs++ = hwsp;
> + *cs++ = 0;
> +
> + *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
> + *cs++ = gpr;
> + *cs++ = *addr;
> + *cs++ = 0;
> + *addr += 4;
> +
> + intel_ring_advance(rq, cs);
> +
> + return 0;
> +}
> +
> +struct hwsp_watcher {
> + struct i915_vma *vma;
> + struct i915_request *rq;
> + u32 addr;
> + u32 *map;
> +};
> +
> +static bool cmp_lt(u32 a, u32 b)
> +{
> + return a < b;
> +}
> +
> +static bool cmp_gte(u32 a, u32 b)
> +{
> + return a >= b;
> +}
> +
> +static int setup_watcher(struct hwsp_watcher *w, struct intel_gt *gt)
> +{
> + struct drm_i915_gem_object *obj;
> + struct i915_vma *vma;
> +
> + obj = i915_gem_object_create_internal(gt->i915, SZ_2M);
> + if (IS_ERR(obj))
> + return PTR_ERR(obj);
> +
> + w->map = i915_gem_object_pin_map(obj, I915_MAP_WB);
> + if (IS_ERR(w->map)) {
> + i915_gem_object_put(obj);
> + return PTR_ERR(w->map);
> + }
> +
> + vma = i915_gem_object_ggtt_pin_ww(obj, NULL, NULL, 0, 0, 0);
> + if (IS_ERR(vma)) {
> + i915_gem_object_put(obj);
> + return PTR_ERR(vma);
> + }
> +
> + w->vma = vma;
> + w->addr = i915_ggtt_offset(vma);
> + return 0;
> +}
> +
> +static int create_watcher(struct hwsp_watcher *w,
> + struct intel_engine_cs *engine,
> + int ringsz)
> +{
> + struct intel_context *ce;
> + struct intel_timeline *tl;
> +
> + ce = intel_context_create(engine);
> + if (IS_ERR(ce))
> + return PTR_ERR(ce);
> +
> + ce->ring = __intel_context_ring_size(ringsz);
> + w->rq = intel_context_create_request(ce);
> + intel_context_put(ce);
> + if (IS_ERR(w->rq))
> + return PTR_ERR(w->rq);
> +
> + w->addr = i915_ggtt_offset(w->vma);
> + tl = w->rq->context->timeline;
> +
> + /* some light mutex juggling required; think co-routines */
> + lockdep_unpin_lock(&tl->mutex, w->rq->cookie);
> + mutex_unlock(&tl->mutex);
> +
> + return 0;
> +}
> +
> +static int check_watcher(struct hwsp_watcher *w, const char *name,
> + bool (*op)(u32 hwsp, u32 seqno))
> +{
> + struct i915_request *rq = fetch_and_zero(&w->rq);
> + struct intel_timeline *tl = rq->context->timeline;
> + u32 offset, end;
> + int err;
> +
> + GEM_BUG_ON(w->addr - i915_ggtt_offset(w->vma) > w->vma->size);
> +
> + i915_request_get(rq);
> + mutex_lock(&tl->mutex);
> + rq->cookie = lockdep_pin_lock(&tl->mutex);
> + i915_request_add(rq);
> +
> + if (i915_request_wait(rq, 0, HZ) < 0) {
> + err = -ETIME;
> + goto out;
> + }
> +
> + err = 0;
> + offset = 0;
> + end = (w->addr - i915_ggtt_offset(w->vma)) / sizeof(*w->map);
> + while (offset < end) {
> + if (!op(w->map[offset + 1], w->map[offset])) {
> + pr_err("Watcher '%s' found HWSP value %x for seqno %x\n",
> + name, w->map[offset + 1], w->map[offset]);
> + err = -EINVAL;
> + }
> +
> + offset += 2;
> + }
> +
> +out:
> + i915_request_put(rq);
> + return err;
> +}
> +
> +static void cleanup_watcher(struct hwsp_watcher *w)
> +{
> + if (w->rq) {
> + struct intel_timeline *tl = w->rq->context->timeline;
> +
> + mutex_lock(&tl->mutex);
> + w->rq->cookie = lockdep_pin_lock(&tl->mutex);
> +
> + i915_request_add(w->rq);
> + }
> +
> + i915_vma_unpin_and_release(&w->vma, I915_VMA_RELEASE_MAP);
> +}
> +
> +static bool retire_requests(struct intel_timeline *tl)
> +{
> + struct i915_request *rq, *rn;
> +
> + mutex_lock(&tl->mutex);
> + list_for_each_entry_safe(rq, rn, &tl->requests, link)
> + if (!i915_request_retire(rq))
> + break;
> + mutex_unlock(&tl->mutex);
> +
> + return !i915_active_fence_isset(&tl->last_request);
> +}
> +
> +static struct i915_request *wrap_timeline(struct i915_request *rq)
> +{
> + struct intel_context *ce = rq->context;
> + struct intel_timeline *tl = ce->timeline;
> + u32 seqno = rq->fence.seqno;
> +
> + while (tl->seqno >= seqno) { /* Cause a wrap */
> + i915_request_put(rq);
> + rq = intel_context_create_request(ce);
> + if (IS_ERR(rq))
> + return rq;
> +
> + i915_request_get(rq);
> + i915_request_add(rq);
> + }
> +
> + i915_request_put(rq);
> + rq = intel_context_create_request(ce);
> + if (IS_ERR(rq))
> + return rq;
> +
> + i915_request_get(rq);
> + i915_request_add(rq);
> +
> + return rq;
> +}
> +
> +static int live_hwsp_read(void *arg)
> +{
> + struct intel_gt *gt = arg;
> + struct hwsp_watcher watcher[2] = {};
> + struct intel_engine_cs *engine;
> + struct intel_timeline *tl;
> + enum intel_engine_id id;
> + int err = 0;
> + int i;
> +
> + /*
> + * If we take a reference to the HWSP for reading on the GPU, that
> + * read may be arbitrarily delayed (either by foreign fence or
> + * priority saturation) and a wrap can happen within 30 minutes.
> + * When the GPU read is finally submitted it should be correct,
> + * even across multiple wraps.
> + */
> +
> + if (INTEL_GEN(gt->i915) < 8) /* CS convenience [SRM/LRM] */
> + return 0;
> +
> + tl = intel_timeline_create(gt);
> + if (IS_ERR(tl))
> + return PTR_ERR(tl);
> +
> + if (!tl->hwsp_cacheline)
> + goto out_free;
> +
> + for (i = 0; i < ARRAY_SIZE(watcher); i++) {
> + err = setup_watcher(&watcher[i], gt);
> + if (err)
> + goto out;
> + }
> +
> + for_each_engine(engine, gt, id) {
> + struct intel_context *ce;
> + unsigned long count = 0;
> + IGT_TIMEOUT(end_time);
> +
> + /* Create a request we can use for remote reading of the HWSP */
> + err = create_watcher(&watcher[1], engine, SZ_512K);
> + if (err)
> + goto out;
> +
> + do {
> + struct i915_sw_fence *submit;
> + struct i915_request *rq;
> + u32 hwsp;
> +
> + submit = heap_fence_create(GFP_KERNEL);
> + if (!submit) {
> + err = -ENOMEM;
> + goto out;
> + }
> +
> + err = create_watcher(&watcher[0], engine, SZ_4K);
> + if (err)
> + goto out;
> +
> + ce = intel_context_create(engine);
> + if (IS_ERR(ce)) {
> + err = PTR_ERR(ce);
> + goto out;
> + }
> +
> + /* Skip to the end, saving 30 minutes of nops */
> + tl->seqno = -10u + 2 * (count & 3);
> + WRITE_ONCE(*(u32 *)tl->hwsp_seqno, tl->seqno);
> + ce->timeline = intel_timeline_get(tl);
> +
> + rq = intel_context_create_request(ce);
> + if (IS_ERR(rq)) {
> + err = PTR_ERR(rq);
> + intel_context_put(ce);
> + goto out;
> + }
> +
> + err = i915_sw_fence_await_dma_fence(&rq->submit,
> + &watcher[0].rq->fence, 0,
> + GFP_KERNEL);
> + if (err < 0) {
> + i915_request_add(rq);
> + intel_context_put(ce);
> + goto out;
> + }
> +
> + mutex_lock(&watcher[0].rq->context->timeline->mutex);
> + err = intel_timeline_read_hwsp(rq, watcher[0].rq, &hwsp);
> + if (err == 0)
> + err = emit_read_hwsp(watcher[0].rq, /* before */
> + rq->fence.seqno, hwsp,
> + &watcher[0].addr);
> + mutex_unlock(&watcher[0].rq->context->timeline->mutex);
> + if (err) {
> + i915_request_add(rq);
> + intel_context_put(ce);
> + goto out;
> + }
> +
> + mutex_lock(&watcher[1].rq->context->timeline->mutex);
> + err = intel_timeline_read_hwsp(rq, watcher[1].rq, &hwsp);
> + if (err == 0)
> + err = emit_read_hwsp(watcher[1].rq, /* after */
> + rq->fence.seqno, hwsp,
> + &watcher[1].addr);
> + mutex_unlock(&watcher[1].rq->context->timeline->mutex);
> + if (err) {
> + i915_request_add(rq);
> + intel_context_put(ce);
> + goto out;
> + }
> +
> + i915_request_get(rq);
> + i915_request_add(rq);
> +
> + rq = wrap_timeline(rq);
> + intel_context_put(ce);
> + if (IS_ERR(rq)) {
> + err = PTR_ERR(rq);
> + goto out;
> + }
> +
> + err = i915_sw_fence_await_dma_fence(&watcher[1].rq->submit,
> + &rq->fence, 0,
> + GFP_KERNEL);
> + if (err < 0) {
> + i915_request_put(rq);
> + goto out;
> + }
> +
> + err = check_watcher(&watcher[0], "before", cmp_lt);
> + i915_sw_fence_commit(submit);
> + heap_fence_put(submit);
> + if (err) {
> + i915_request_put(rq);
> + goto out;
> + }
> + count++;
> +
> + if (8 * watcher[1].rq->ring->emit >
> + 3 * watcher[1].rq->ring->size) {
> + i915_request_put(rq);
> + break;
> + }
> +
> + /* Flush the timeline before manually wrapping again */
> + if (i915_request_wait(rq,
> + I915_WAIT_INTERRUPTIBLE,
> + HZ) < 0) {
> + err = -ETIME;
> + i915_request_put(rq);
> + goto out;
> + }
> +
> + retire_requests(tl);
> + i915_request_put(rq);
> + } while (!__igt_timeout(end_time, NULL));
> + WRITE_ONCE(*(u32 *)tl->hwsp_seqno, 0xdeadbeef);
> +
> + pr_info("%s: simulated %lu wraps\n", engine->name, count);
> + err = check_watcher(&watcher[1], "after", cmp_gte);
> + if (err)
> + goto out;
> + }
> +
> +out:
> + for (i = 0; i < ARRAY_SIZE(watcher); i++)
> + cleanup_watcher(&watcher[i]);
> +
> + if (igt_flush_test(gt->i915))
> + err = -EIO;
> +
> +out_free:
> + intel_timeline_put(tl);
> + return err;
> +}
> +
> static int live_hwsp_rollover_kernel(void *arg)
> {
> struct intel_gt *gt = arg;
> @@ -998,6 +1371,7 @@ int intel_timeline_live_selftests(struct drm_i915_private *i915)
> SUBTEST(live_hwsp_engine),
> SUBTEST(live_hwsp_alternate),
> SUBTEST(live_hwsp_wrap),
> + SUBTEST(live_hwsp_read),
> SUBTEST(live_hwsp_rollover_kernel),
> SUBTEST(live_hwsp_rollover_user),
> };
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/gt: Use the local HWSP offset during submission
2020-10-21 22:04 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use the local HWSP offset during submission Chris Wilson
2020-10-21 22:04 ` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Exercise intel_timeline_read_hwsp() Chris Wilson
@ 2020-10-21 22:30 ` Patchwork
2020-10-21 22:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (8 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-10-21 22:30 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Use the local HWSP offset during submission
URL : https://patchwork.freedesktop.org/series/82935/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c352f2f98f6d drm/i915/gt: Use the local HWSP offset during submission
eb87d384627b drm/i915/selftests: Exercise intel_timeline_read_hwsp()
-:270: WARNING:LINE_SPACING: Missing a blank line after declarations
#270: FILE: drivers/gpu/drm/i915/gt/selftest_timeline.c:991:
+ unsigned long count = 0;
+ IGT_TIMEOUT(end_time);
total: 0 errors, 1 warnings, 0 checks, 396 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/gt: Use the local HWSP offset during submission
2020-10-21 22:04 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use the local HWSP offset during submission Chris Wilson
2020-10-21 22:04 ` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Exercise intel_timeline_read_hwsp() Chris Wilson
2020-10-21 22:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/gt: Use the local HWSP offset during submission Patchwork
@ 2020-10-21 22:31 ` Patchwork
2020-10-21 22:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (7 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-10-21 22:31 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Use the local HWSP offset during submission
URL : https://patchwork.freedesktop.org/series/82935/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_lrc.c:3603:26: warning: dereference of noderef expression
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Use the local HWSP offset during submission
2020-10-21 22:04 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use the local HWSP offset during submission Chris Wilson
` (2 preceding siblings ...)
2020-10-21 22:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-10-21 22:55 ` Patchwork
2020-10-22 1:16 ` [Intel-gfx] [PATCH 1/2] " kernel test robot
` (6 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-10-21 22:55 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4250 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Use the local HWSP offset during submission
URL : https://patchwork.freedesktop.org/series/82935/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9179 -> Patchwork_18760
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/index.html
Known issues
------------
Here are the changes found in Patchwork_18760 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@execlists:
- fi-icl-y: [PASS][3] -> [INCOMPLETE][4] ([i915#2276])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/fi-icl-y/igt@i915_selftest@live@execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/fi-icl-y/igt@i915_selftest@live@execlists.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
#### Possible fixes ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-7500u: [DMESG-FAIL][11] ([i915#165]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2276]: https://gitlab.freedesktop.org/drm/intel/issues/2276
Participating hosts (45 -> 38)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9179 -> Patchwork_18760
CI-20190529: 20190529
CI_DRM_9179: 0246759e4ea7f02d823d195387dd6e35d95bb843 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5822: b4bcf05cb9839037128905deda7146434155cc41 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18760: eb87d384627be113d0ab77026ba0fd26ac7b077f @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
eb87d384627b drm/i915/selftests: Exercise intel_timeline_read_hwsp()
c352f2f98f6d drm/i915/gt: Use the local HWSP offset during submission
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/index.html
[-- Attachment #1.2: Type: text/html, Size: 5300 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use the local HWSP offset during submission
2020-10-21 22:04 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use the local HWSP offset during submission Chris Wilson
` (3 preceding siblings ...)
2020-10-21 22:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-10-22 1:16 ` kernel test robot
2020-10-22 3:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork
` (5 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: kernel test robot @ 2020-10-22 1:16 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: kbuild-all, stable, Chris Wilson
[-- Attachment #1: Type: text/plain, Size: 1908 bytes --]
Hi Chris,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip linus/master v5.9 next-20201021]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-gt-Use-the-local-HWSP-offset-during-submission/20201022-060619
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-s002-20201021 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.3-dirty
# https://github.com/0day-ci/linux/commit/034e13871db55a3eed93d3157408443584dddd1f
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Chris-Wilson/drm-i915-gt-Use-the-local-HWSP-offset-during-submission/20201022-060619
git checkout 034e13871db55a3eed93d3157408443584dddd1f
# save the attached .config to linux build tree
make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
"sparse warnings: (new ones prefixed by >>)"
>> drivers/gpu/drm/i915/gt/intel_lrc.c:3553:26: sparse: sparse: dereference of noderef expression
vim +3553 drivers/gpu/drm/i915/gt/intel_lrc.c
3549
3550 static u32 hwsp_offset(struct i915_request *rq)
3551 {
3552 if (rq->hwsp_cacheline)
> 3553 return rq->hwsp_cacheline->ggtt_offset;
3554 else
3555 return i915_request_active_timeline(rq)->hwsp_offset;
3556 }
3557
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/gt: Use the local HWSP offset during submission
2020-10-21 22:04 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use the local HWSP offset during submission Chris Wilson
` (4 preceding siblings ...)
2020-10-22 1:16 ` [Intel-gfx] [PATCH 1/2] " kernel test robot
@ 2020-10-22 3:36 ` Patchwork
2020-10-22 6:41 ` [Intel-gfx] [PATCH] " Chris Wilson
` (4 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-10-22 3:36 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
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== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Use the local HWSP offset during submission
URL : https://patchwork.freedesktop.org/series/82935/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9179_full -> Patchwork_18760_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18760_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18760_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18760_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_fence@syncobj-timeline-invalid-flags:
- shard-snb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-snb2/igt@gem_exec_fence@syncobj-timeline-invalid-flags.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-snb7/igt@gem_exec_fence@syncobj-timeline-invalid-flags.html
Known issues
------------
Here are the changes found in Patchwork_18760_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#658])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-iclb2/igt@feature_discovery@psr2.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-iclb7/igt@feature_discovery@psr2.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-hsw: [PASS][5] -> [FAIL][6] ([i915#2389])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-hsw8/igt@gem_exec_reloc@basic-many-active@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-hsw5/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@gem_exec_reloc@basic-many-active@vcs0:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2389]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-glk2/igt@gem_exec_reloc@basic-many-active@vcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-glk5/igt@gem_exec_reloc@basic-many-active@vcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][9] -> [SKIP][10] ([i915#2190])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-tglb3/igt@gem_huc_copy@huc-copy.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: [PASS][11] -> [FAIL][12] ([i915#454])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-skl7/igt@i915_pm_dc@dc6-psr.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-skl3/igt@i915_pm_dc@dc6-psr.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [PASS][13] -> [INCOMPLETE][14] ([i915#300])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge:
- shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-glk5/igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-glk4/igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-tglb: [PASS][17] -> [FAIL][18] ([i915#2346])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-tglb6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-tglb6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled:
- shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#1635] / [i915#1982]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-apl7/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-apl2/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
- shard-snb: [PASS][21] -> [FAIL][22] ([i915#54])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-snb2/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-snb2/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][23] -> [FAIL][24] ([i915#2122])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
- shard-tglb: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-skl: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) +4 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][29] -> [FAIL][30] ([i915#1188])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][33] -> [FAIL][34] ([i915#1635] / [i915#31])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-apl8/igt@kms_setmode@basic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-apl8/igt@kms_setmode@basic.html
* igt@kms_universal_plane@universal-plane-gen9-features-pipe-a:
- shard-iclb: [PASS][35] -> [DMESG-WARN][36] ([i915#1982])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-iclb5/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-iclb8/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- shard-skl: [DMESG-WARN][37] ([i915#1982]) -> [PASS][38] +4 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-skl9/igt@core_hotunplug@unbind-rebind.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-skl8/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_whisper@basic-forked-all:
- shard-glk: [DMESG-WARN][39] ([i915#118] / [i915#95]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-glk5/igt@gem_exec_whisper@basic-forked-all.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-glk4/igt@gem_exec_whisper@basic-forked-all.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [INCOMPLETE][41] ([i915#198]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-skl7/igt@gem_softpin@noreloc-s3.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-skl9/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-skl: [TIMEOUT][43] ([i915#2424]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-skl6/igt@gem_userptr_blits@sync-unmap-cycles.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-skl8/igt@gem_userptr_blits@sync-unmap-cycles.html
* {igt@kms_async_flips@alternate-sync-async-flip}:
- shard-kbl: [FAIL][45] ([i915#2521]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-kbl1/igt@kms_async_flips@alternate-sync-async-flip.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-kbl4/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_cursor_crc@pipe-c-cursor-128x128-onscreen:
- shard-skl: [FAIL][47] ([i915#54]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-128x128-onscreen.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-128x128-onscreen.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [FAIL][49] ([i915#2122]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-apl: [INCOMPLETE][51] ([i915#1635] / [i915#2377]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-apl4/igt@kms_flip@flip-vs-suspend@c-dp1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-apl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-tglb: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +6 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][55] ([fdo#108145] / [i915#265]) -> [PASS][56] +4 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_cursor@pipe-a-primary-size-256:
- shard-glk: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-glk6/igt@kms_plane_cursor@pipe-a-primary-size-256.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-glk7/igt@kms_plane_cursor@pipe-a-primary-size-256.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-iclb8/igt@kms_psr@psr2_suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-iclb2/igt@kms_psr@psr2_suspend.html
* igt@kms_universal_plane@universal-plane-gen9-features-pipe-a:
- shard-kbl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-kbl2/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-kbl2/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][63] ([i915#180]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][65] ([i915#658]) -> [SKIP][66] ([i915#588])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][67] ([i915#1515]) -> [FAIL][68] ([i915#1515])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
- shard-skl: [INCOMPLETE][69] ([i915#198] / [i915#1982]) -> [DMESG-WARN][70] ([i915#1982])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-skl9/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-skl3/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-tglb: [DMESG-WARN][71] ([i915#2411]) -> [DMESG-WARN][72] ([i915#1982] / [i915#2411])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_setmode@basic:
- shard-skl: [DMESG-WARN][73] ([i915#1982]) -> [FAIL][74] ([i915#31])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9179/shard-skl9/igt@kms_setmode@basic.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/shard-skl8/igt@kms_setmode@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2377]: https://gitlab.freedesktop.org/drm/intel/issues/2377
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 12)
------------------------------
Additional (1): pig-snb-2600
Build changes
-------------
* Linux: CI_DRM_9179 -> Patchwork_18760
CI-20190529: 20190529
CI_DRM_9179: 0246759e4ea7f02d823d195387dd6e35d95bb843 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5822: b4bcf05cb9839037128905deda7146434155cc41 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18760: eb87d384627be113d0ab77026ba0fd26ac7b077f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18760/index.html
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^ permalink raw reply [flat|nested] 14+ messages in thread* [Intel-gfx] [PATCH] drm/i915/gt: Use the local HWSP offset during submission
2020-10-21 22:04 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use the local HWSP offset during submission Chris Wilson
` (5 preceding siblings ...)
2020-10-22 3:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork
@ 2020-10-22 6:41 ` Chris Wilson
2020-10-23 11:25 ` Mika Kuoppala
2020-10-22 7:01 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with drm/i915/gt: Use the local HWSP offset during submission (rev2) Patchwork
` (3 subsequent siblings)
10 siblings, 1 reply; 14+ messages in thread
From: Chris Wilson @ 2020-10-22 6:41 UTC (permalink / raw)
To: intel-gfx; +Cc: stable, Chris Wilson
We wrap the timeline on construction of the next request, but there may
still be requests in flight that have not yet finalized the breadcrumb.
(The breadcrumb is delayed as we need engine-local offsets, and for the
virtual engine that is not known until execution.) As such, by the time
we write to the timeline's HWSP offset it may have changed, and we
should use the value we preserved in the request instead.
Though the window is small and infrequent (at full flow we can expect a
timeline's seqno to wrap once every 30 minutes), the impact of writing
the old seqno into the new HWSP is severe: the old requests are never
completed, and the new requests are completed before they are even
submitted.
Fixes: ebece7539242 ("drm/i915: Keep timeline HWSP allocated until idle across the system")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: <stable@vger.kernel.org> # v5.2+
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 27 +++++++++++++------
drivers/gpu/drm/i915/gt/intel_timeline.c | 18 +++++++------
.../gpu/drm/i915/gt/intel_timeline_types.h | 2 ++
3 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index c22d47cc6701..d0be98b67138 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3597,6 +3597,19 @@ static const struct intel_context_ops execlists_context_ops = {
.destroy = execlists_context_destroy,
};
+static u32 hwsp_offset(const struct i915_request *rq)
+{
+ const struct intel_timeline_cacheline *cl;
+
+ /* Before the request is executed, the timeline/cachline is fixed */
+
+ cl = rcu_dereference_protected(rq->hwsp_cacheline, 1);
+ if (cl)
+ return cl->ggtt_offset;
+
+ return rcu_dereference_protected(rq->timeline, 1)->hwsp_offset;
+}
+
static int gen8_emit_init_breadcrumb(struct i915_request *rq)
{
u32 *cs;
@@ -3619,7 +3632,7 @@ static int gen8_emit_init_breadcrumb(struct i915_request *rq)
*cs++ = MI_NOOP;
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
- *cs++ = i915_request_timeline(rq)->hwsp_offset;
+ *cs++ = hwsp_offset(rq);
*cs++ = 0;
*cs++ = rq->fence.seqno - 1;
@@ -4939,11 +4952,9 @@ gen8_emit_fini_breadcrumb_tail(struct i915_request *request, u32 *cs)
return gen8_emit_wa_tail(request, cs);
}
-static u32 *emit_xcs_breadcrumb(struct i915_request *request, u32 *cs)
+static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs)
{
- u32 addr = i915_request_active_timeline(request)->hwsp_offset;
-
- return gen8_emit_ggtt_write(cs, request->fence.seqno, addr, 0);
+ return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0);
}
static u32 *gen8_emit_fini_breadcrumb(struct i915_request *rq, u32 *cs)
@@ -4962,7 +4973,7 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
/* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
cs = gen8_emit_ggtt_write_rcs(cs,
request->fence.seqno,
- i915_request_active_timeline(request)->hwsp_offset,
+ hwsp_offset(request),
PIPE_CONTROL_FLUSH_ENABLE |
PIPE_CONTROL_CS_STALL);
@@ -4974,7 +4985,7 @@ gen11_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
{
cs = gen8_emit_ggtt_write_rcs(cs,
request->fence.seqno,
- i915_request_active_timeline(request)->hwsp_offset,
+ hwsp_offset(request),
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_TILE_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
@@ -5044,7 +5055,7 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
{
cs = gen12_emit_ggtt_write_rcs(cs,
request->fence.seqno,
- i915_request_active_timeline(request)->hwsp_offset,
+ hwsp_offset(request),
PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_TILE_CACHE_FLUSH |
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
index a2f74cefe4c3..7ea94d201fe6 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -188,10 +188,14 @@ cacheline_alloc(struct intel_timeline_hwsp *hwsp, unsigned int cacheline)
return cl;
}
-static void cacheline_acquire(struct intel_timeline_cacheline *cl)
+static void cacheline_acquire(struct intel_timeline_cacheline *cl,
+ u32 ggtt_offset)
{
- if (cl)
- i915_active_acquire(&cl->active);
+ if (!cl)
+ return;
+
+ cl->ggtt_offset = ggtt_offset;
+ i915_active_acquire(&cl->active);
}
static void cacheline_release(struct intel_timeline_cacheline *cl)
@@ -340,7 +344,7 @@ int intel_timeline_pin(struct intel_timeline *tl, struct i915_gem_ww_ctx *ww)
GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
tl->fence_context, tl->hwsp_offset);
- cacheline_acquire(tl->hwsp_cacheline);
+ cacheline_acquire(tl->hwsp_cacheline, tl->hwsp_offset);
if (atomic_fetch_inc(&tl->pin_count)) {
cacheline_release(tl->hwsp_cacheline);
__i915_vma_unpin(tl->hwsp_ggtt);
@@ -515,7 +519,7 @@ __intel_timeline_get_seqno(struct intel_timeline *tl,
GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
tl->fence_context, tl->hwsp_offset);
- cacheline_acquire(cl);
+ cacheline_acquire(cl, tl->hwsp_offset);
tl->hwsp_cacheline = cl;
*seqno = timeline_advance(tl);
@@ -573,9 +577,7 @@ int intel_timeline_read_hwsp(struct i915_request *from,
if (err)
goto out;
- *hwsp = i915_ggtt_offset(cl->hwsp->vma) +
- ptr_unmask_bits(cl->vaddr, CACHELINE_BITS) * CACHELINE_BYTES;
-
+ *hwsp = cl->ggtt_offset;
out:
i915_active_release(&cl->active);
return err;
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
index 02181c5020db..4474f487f589 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
@@ -94,6 +94,8 @@ struct intel_timeline_cacheline {
struct intel_timeline_hwsp *hwsp;
void *vaddr;
+ u32 ggtt_offset;
+
struct rcu_head rcu;
};
--
2.20.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915/gt: Use the local HWSP offset during submission
2020-10-22 6:41 ` [Intel-gfx] [PATCH] " Chris Wilson
@ 2020-10-23 11:25 ` Mika Kuoppala
0 siblings, 0 replies; 14+ messages in thread
From: Mika Kuoppala @ 2020-10-23 11:25 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: stable, Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> We wrap the timeline on construction of the next request, but there may
> still be requests in flight that have not yet finalized the breadcrumb.
> (The breadcrumb is delayed as we need engine-local offsets, and for the
> virtual engine that is not known until execution.) As such, by the time
> we write to the timeline's HWSP offset it may have changed, and we
> should use the value we preserved in the request instead.
>
> Though the window is small and infrequent (at full flow we can expect a
> timeline's seqno to wrap once every 30 minutes), the impact of writing
> the old seqno into the new HWSP is severe: the old requests are never
> completed, and the new requests are completed before they are even
> submitted.
>
> Fixes: ebece7539242 ("drm/i915: Keep timeline HWSP allocated until idle across the system")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: <stable@vger.kernel.org> # v5.2+
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 27 +++++++++++++------
> drivers/gpu/drm/i915/gt/intel_timeline.c | 18 +++++++------
> .../gpu/drm/i915/gt/intel_timeline_types.h | 2 ++
> 3 files changed, 31 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index c22d47cc6701..d0be98b67138 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -3597,6 +3597,19 @@ static const struct intel_context_ops execlists_context_ops = {
> .destroy = execlists_context_destroy,
> };
>
> +static u32 hwsp_offset(const struct i915_request *rq)
> +{
> + const struct intel_timeline_cacheline *cl;
> +
> + /* Before the request is executed, the timeline/cachline is fixed */
s/cachline/cacheline
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> +
> + cl = rcu_dereference_protected(rq->hwsp_cacheline, 1);
> + if (cl)
> + return cl->ggtt_offset;
> +
> + return rcu_dereference_protected(rq->timeline, 1)->hwsp_offset;
> +}
> +
> static int gen8_emit_init_breadcrumb(struct i915_request *rq)
> {
> u32 *cs;
> @@ -3619,7 +3632,7 @@ static int gen8_emit_init_breadcrumb(struct i915_request *rq)
> *cs++ = MI_NOOP;
>
> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> - *cs++ = i915_request_timeline(rq)->hwsp_offset;
> + *cs++ = hwsp_offset(rq);
> *cs++ = 0;
> *cs++ = rq->fence.seqno - 1;
>
> @@ -4939,11 +4952,9 @@ gen8_emit_fini_breadcrumb_tail(struct i915_request *request, u32 *cs)
> return gen8_emit_wa_tail(request, cs);
> }
>
> -static u32 *emit_xcs_breadcrumb(struct i915_request *request, u32 *cs)
> +static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs)
> {
> - u32 addr = i915_request_active_timeline(request)->hwsp_offset;
> -
> - return gen8_emit_ggtt_write(cs, request->fence.seqno, addr, 0);
> + return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0);
> }
>
> static u32 *gen8_emit_fini_breadcrumb(struct i915_request *rq, u32 *cs)
> @@ -4962,7 +4973,7 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
> /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
> cs = gen8_emit_ggtt_write_rcs(cs,
> request->fence.seqno,
> - i915_request_active_timeline(request)->hwsp_offset,
> + hwsp_offset(request),
> PIPE_CONTROL_FLUSH_ENABLE |
> PIPE_CONTROL_CS_STALL);
>
> @@ -4974,7 +4985,7 @@ gen11_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
> {
> cs = gen8_emit_ggtt_write_rcs(cs,
> request->fence.seqno,
> - i915_request_active_timeline(request)->hwsp_offset,
> + hwsp_offset(request),
> PIPE_CONTROL_CS_STALL |
> PIPE_CONTROL_TILE_CACHE_FLUSH |
> PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
> @@ -5044,7 +5055,7 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
> {
> cs = gen12_emit_ggtt_write_rcs(cs,
> request->fence.seqno,
> - i915_request_active_timeline(request)->hwsp_offset,
> + hwsp_offset(request),
> PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
> PIPE_CONTROL_CS_STALL |
> PIPE_CONTROL_TILE_CACHE_FLUSH |
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
> index a2f74cefe4c3..7ea94d201fe6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
> @@ -188,10 +188,14 @@ cacheline_alloc(struct intel_timeline_hwsp *hwsp, unsigned int cacheline)
> return cl;
> }
>
> -static void cacheline_acquire(struct intel_timeline_cacheline *cl)
> +static void cacheline_acquire(struct intel_timeline_cacheline *cl,
> + u32 ggtt_offset)
> {
> - if (cl)
> - i915_active_acquire(&cl->active);
> + if (!cl)
> + return;
> +
> + cl->ggtt_offset = ggtt_offset;
> + i915_active_acquire(&cl->active);
> }
>
> static void cacheline_release(struct intel_timeline_cacheline *cl)
> @@ -340,7 +344,7 @@ int intel_timeline_pin(struct intel_timeline *tl, struct i915_gem_ww_ctx *ww)
> GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
> tl->fence_context, tl->hwsp_offset);
>
> - cacheline_acquire(tl->hwsp_cacheline);
> + cacheline_acquire(tl->hwsp_cacheline, tl->hwsp_offset);
> if (atomic_fetch_inc(&tl->pin_count)) {
> cacheline_release(tl->hwsp_cacheline);
> __i915_vma_unpin(tl->hwsp_ggtt);
> @@ -515,7 +519,7 @@ __intel_timeline_get_seqno(struct intel_timeline *tl,
> GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
> tl->fence_context, tl->hwsp_offset);
>
> - cacheline_acquire(cl);
> + cacheline_acquire(cl, tl->hwsp_offset);
> tl->hwsp_cacheline = cl;
>
> *seqno = timeline_advance(tl);
> @@ -573,9 +577,7 @@ int intel_timeline_read_hwsp(struct i915_request *from,
> if (err)
> goto out;
>
> - *hwsp = i915_ggtt_offset(cl->hwsp->vma) +
> - ptr_unmask_bits(cl->vaddr, CACHELINE_BITS) * CACHELINE_BYTES;
> -
> + *hwsp = cl->ggtt_offset;
> out:
> i915_active_release(&cl->active);
> return err;
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> index 02181c5020db..4474f487f589 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> @@ -94,6 +94,8 @@ struct intel_timeline_cacheline {
> struct intel_timeline_hwsp *hwsp;
> void *vaddr;
>
> + u32 ggtt_offset;
> +
> struct rcu_head rcu;
> };
>
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with drm/i915/gt: Use the local HWSP offset during submission (rev2)
2020-10-21 22:04 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use the local HWSP offset during submission Chris Wilson
` (6 preceding siblings ...)
2020-10-22 6:41 ` [Intel-gfx] [PATCH] " Chris Wilson
@ 2020-10-22 7:01 ` Patchwork
2020-10-22 7:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-10-22 7:01 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with drm/i915/gt: Use the local HWSP offset during submission (rev2)
URL : https://patchwork.freedesktop.org/series/82935/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a0a057614518 drm/i915/gt: Use the local HWSP offset during submission
9004d18b0348 drm/i915/selftests: Exercise intel_timeline_read_hwsp()
-:270: WARNING:LINE_SPACING: Missing a blank line after declarations
#270: FILE: drivers/gpu/drm/i915/gt/selftest_timeline.c:991:
+ unsigned long count = 0;
+ IGT_TIMEOUT(end_time);
total: 0 errors, 1 warnings, 0 checks, 396 lines checked
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^ permalink raw reply [flat|nested] 14+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with drm/i915/gt: Use the local HWSP offset during submission (rev2)
2020-10-21 22:04 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use the local HWSP offset during submission Chris Wilson
` (7 preceding siblings ...)
2020-10-22 7:01 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with drm/i915/gt: Use the local HWSP offset during submission (rev2) Patchwork
@ 2020-10-22 7:02 ` Patchwork
2020-10-22 7:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-22 9:50 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
10 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-10-22 7:02 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with drm/i915/gt: Use the local HWSP offset during submission (rev2)
URL : https://patchwork.freedesktop.org/series/82935/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with drm/i915/gt: Use the local HWSP offset during submission (rev2)
2020-10-21 22:04 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use the local HWSP offset during submission Chris Wilson
` (8 preceding siblings ...)
2020-10-22 7:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-10-22 7:26 ` Patchwork
2020-10-22 9:50 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
10 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-10-22 7:26 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4435 bytes --]
== Series Details ==
Series: series starting with drm/i915/gt: Use the local HWSP offset during submission (rev2)
URL : https://patchwork.freedesktop.org/series/82935/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9180 -> Patchwork_18762
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/index.html
Known issues
------------
Here are the changes found in Patchwork_18762 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982] / [k.org#205379])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-tgl-u2/igt@i915_module_load@reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/fi-tgl-u2/igt@i915_module_load@reload.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([i915#1161] / [i915#262])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-r: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-kbl-r/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/fi-kbl-r/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Possible fixes ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [DMESG-WARN][9] ([i915#2203]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
- fi-icl-u2: [FAIL][11] ([i915#1161]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-kbl-7560u}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (45 -> 38)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9180 -> Patchwork_18762
CI-20190529: 20190529
CI_DRM_9180: b174cec7fd714a954d4a65088ca53e32ae9cd45e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5822: b4bcf05cb9839037128905deda7146434155cc41 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18762: 9004d18b0348b7f3c79e6f9753339b042f6c028d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9004d18b0348 drm/i915/selftests: Exercise intel_timeline_read_hwsp()
a0a057614518 drm/i915/gt: Use the local HWSP offset during submission
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/index.html
[-- Attachment #1.2: Type: text/html, Size: 5480 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with drm/i915/gt: Use the local HWSP offset during submission (rev2)
2020-10-21 22:04 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use the local HWSP offset during submission Chris Wilson
` (9 preceding siblings ...)
2020-10-22 7:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-10-22 9:50 ` Patchwork
10 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-10-22 9:50 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 15245 bytes --]
== Series Details ==
Series: series starting with drm/i915/gt: Use the local HWSP offset during submission (rev2)
URL : https://patchwork.freedesktop.org/series/82935/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9180_full -> Patchwork_18762_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18762_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18762_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18762_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@2x-dpms-vs-vblank-race@bc-vga1-hdmi-a1:
- shard-hsw: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-hsw7/igt@kms_flip@2x-dpms-vs-vblank-race@bc-vga1-hdmi-a1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-hsw5/igt@kms_flip@2x-dpms-vs-vblank-race@bc-vga1-hdmi-a1.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@core_hotunplug@hotrebind}:
- shard-hsw: NOTRUN -> [WARN][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-hsw5/igt@core_hotunplug@hotrebind.html
Known issues
------------
Here are the changes found in Patchwork_18762_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_reloc@basic-many-active@vecs0:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2389]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-glk9/igt@gem_exec_reloc@basic-many-active@vecs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-glk6/igt@gem_exec_reloc@basic-many-active@vecs0.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [PASS][6] -> [INCOMPLETE][7] ([i915#155])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-kbl1/igt@i915_suspend@debugfs-reader.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-kbl6/igt@i915_suspend@debugfs-reader.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-kbl: [PASS][8] -> [DMESG-WARN][9] ([i915#1982])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-kbl1/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-kbl6/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
- shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#1635] / [i915#1982])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-apl4/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-apl3/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy:
- shard-hsw: [PASS][12] -> [DMESG-WARN][13] ([IGT#6])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-hsw2/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-hsw1/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
* igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
- shard-snb: [PASS][14] -> [FAIL][15] ([i915#54])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-snb5/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-snb2/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][16] -> [FAIL][17] ([i915#79])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-glk: [PASS][18] -> [DMESG-WARN][19] ([i915#1982]) +2 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-glk7/igt@kms_frontbuffer_tracking@fbc-stridechange.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-glk3/igt@kms_frontbuffer_tracking@fbc-stridechange.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt:
- shard-tglb: [PASS][20] -> [DMESG-WARN][21] ([i915#1982]) +5 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][22] -> [FAIL][23] ([fdo#108145] / [i915#265])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][24] -> [SKIP][25] ([fdo#109441]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-iclb5/igt@kms_psr@psr2_cursor_render.html
* igt@perf@short-reads:
- shard-skl: [PASS][26] -> [DMESG-WARN][27] ([i915#1982]) +6 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-skl9/igt@perf@short-reads.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-skl2/igt@perf@short-reads.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- shard-skl: [DMESG-WARN][28] ([i915#1982]) -> [PASS][29] +6 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-skl10/igt@core_hotunplug@unbind-rebind.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-skl2/igt@core_hotunplug@unbind-rebind.html
- shard-iclb: [DMESG-WARN][30] ([i915#1982]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-iclb4/igt@core_hotunplug@unbind-rebind.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-iclb6/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_schedule@pi-common@bcs0:
- shard-apl: [INCOMPLETE][32] ([i915#1635]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-apl7/igt@gem_exec_schedule@pi-common@bcs0.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-apl4/igt@gem_exec_schedule@pi-common@bcs0.html
* igt@gem_exec_whisper@basic-contexts-priority-all:
- shard-iclb: [INCOMPLETE][34] -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-iclb2/igt@gem_exec_whisper@basic-contexts-priority-all.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-iclb7/igt@gem_exec_whisper@basic-contexts-priority-all.html
* igt@gem_exec_whisper@basic-forked-all:
- shard-glk: [DMESG-WARN][36] ([i915#118] / [i915#95]) -> [PASS][37] +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-glk1/igt@gem_exec_whisper@basic-forked-all.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-glk7/igt@gem_exec_whisper@basic-forked-all.html
* igt@gem_exec_whisper@basic-queues-priority-all:
- shard-skl: [FAIL][38] -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-skl6/igt@gem_exec_whisper@basic-queues-priority-all.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-skl8/igt@gem_exec_whisper@basic-queues-priority-all.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-skl: [TIMEOUT][40] ([i915#2424]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-skl3/igt@gem_userptr_blits@unsync-unmap-cycles.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-skl6/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][42] ([i915#1436] / [i915#716]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-skl3/igt@gen9_exec_parse@allowed-single.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-skl1/igt@gen9_exec_parse@allowed-single.html
* igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled:
- shard-snb: [SKIP][44] ([fdo#109271]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-snb5/igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-snb2/igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
- shard-glk: [FAIL][46] ([i915#79]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-glk2/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-glk6/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-modesetfrombusy:
- shard-glk: [FAIL][48] ([i915#49]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-glk7/igt@kms_frontbuffer_tracking@fbc-modesetfrombusy.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-glk4/igt@kms_frontbuffer_tracking@fbc-modesetfrombusy.html
- shard-snb: [FAIL][50] ([i915#2546]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-snb5/igt@kms_frontbuffer_tracking@fbc-modesetfrombusy.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-snb2/igt@kms_frontbuffer_tracking@fbc-modesetfrombusy.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
- shard-tglb: [DMESG-WARN][52] ([i915#1982]) -> [PASS][53] +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][54] ([fdo#108145] / [i915#265]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][56] ([fdo#109642] / [fdo#111068]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-iclb8/igt@kms_psr2_su@frontbuffer.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [SKIP][58] ([fdo#109441]) -> [PASS][59] +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-iclb4/igt@kms_psr@psr2_cursor_plane_onoff.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
#### Warnings ####
* igt@i915_pm_dc@dc6-psr:
- shard-skl: [INCOMPLETE][60] ([i915#198]) -> [FAIL][61] ([i915#454])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-skl1/igt@i915_pm_dc@dc6-psr.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-skl7/igt@i915_pm_dc@dc6-psr.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-tglb: [DMESG-WARN][62] ([i915#1982] / [i915#2411]) -> [DMESG-WARN][63] ([i915#2411])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9180 -> Patchwork_18762
CI-20190529: 20190529
CI_DRM_9180: b174cec7fd714a954d4a65088ca53e32ae9cd45e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5822: b4bcf05cb9839037128905deda7146434155cc41 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18762: 9004d18b0348b7f3c79e6f9753339b042f6c028d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/index.html
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