* [PATCH 5/9] drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks
2025-02-10 12:39 Suraj Kandpal
@ 2025-02-10 12:39 ` Suraj Kandpal
0 siblings, 0 replies; 29+ messages in thread
From: Suraj Kandpal @ 2025-02-10 12:39 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, jani.nikula, Suraj Kandpal
We use intel_display for function hooks of shared_dpll_mgr and
any function that gets called when we use for_each_shared_dpll.
This also contains some opportunistic display->platform.xx changes
all to reductate the use of drm_i915_private.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 130 +--
.../i915/display/intel_display_power_well.c | 3 +-
drivers/gpu/drm/i915/display/intel_dkl_phy.c | 54 +-
drivers/gpu/drm/i915/display/intel_dkl_phy.h | 9 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 789 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 10 +-
.../drm/i915/display/intel_modeset_setup.c | 4 +-
.../gpu/drm/i915/display/intel_pch_display.c | 43 +-
8 files changed, 528 insertions(+), 514 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index db3c2d85c57b..5f072ce1e0ad 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -358,10 +358,10 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
}
}
-static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
+static int icl_calc_tbt_pll_link(struct intel_display *display,
enum port port)
{
- u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
+ u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
switch (val) {
case DDI_CLK_SEL_NONE:
@@ -1366,7 +1366,7 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum tc_port tc_port = intel_encoder_to_tc(encoder);
const struct intel_ddi_buf_trans *trans;
int n_entries, ln;
@@ -1375,17 +1375,17 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
return;
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
- if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
+ if (drm_WARN_ON_ONCE(display->drm, !trans))
return;
for (ln = 0; ln < 2; ln++) {
int level;
- intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
+ intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
- intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
+ intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln),
DKL_TX_PRESHOOT_COEFF_MASK |
DKL_TX_DE_EMPAHSIS_COEFF_MASK |
DKL_TX_VSWING_CONTROL_MASK,
@@ -1395,7 +1395,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
- intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
+ intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln),
DKL_TX_PRESHOOT_COEFF_MASK |
DKL_TX_DE_EMPAHSIS_COEFF_MASK |
DKL_TX_VSWING_CONTROL_MASK,
@@ -1403,10 +1403,10 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
- intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
+ intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
DKL_TX_DP20BITMODE, 0);
- if (IS_ALDERLAKE_P(dev_priv)) {
+ if (display->platform.alderlake_p) {
u32 val;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
@@ -1422,7 +1422,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
}
- intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
+ intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
val);
@@ -1550,14 +1550,14 @@ static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t
}
static struct intel_shared_dpll *
-_icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
+_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
u32 clk_sel_mask, u32 clk_sel_shift)
{
enum intel_dpll_id id;
- id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
+ id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
- return intel_get_shared_dpll_by_id(i915, id);
+ return intel_get_shared_dpll_by_id(display, id);
}
static void adls_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1596,10 +1596,10 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
- return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
+ return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy),
ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
}
@@ -1640,10 +1640,10 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
- return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
+ return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
}
@@ -1693,12 +1693,12 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
enum intel_dpll_id id;
u32 val;
- val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
+ val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy));
val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
id = val;
@@ -1711,7 +1711,7 @@ static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
if (phy >= PHY_C)
id += DPLL_ID_DG1_DPLL2;
- return intel_get_shared_dpll_by_id(i915, id);
+ return intel_get_shared_dpll_by_id(display, id);
}
static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
@@ -1750,10 +1750,10 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
- return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
+ return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
}
@@ -1858,13 +1858,13 @@ static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum tc_port tc_port = intel_encoder_to_tc(encoder);
enum port port = encoder->port;
enum intel_dpll_id id;
u32 tmp;
- tmp = intel_de_read(i915, DDI_CLK_SEL(port));
+ tmp = intel_de_read(display, DDI_CLK_SEL(port));
switch (tmp & DDI_CLK_SEL_MASK) {
case DDI_CLK_SEL_TBT_162:
@@ -1883,12 +1883,12 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode
return NULL;
}
- return intel_get_shared_dpll_by_id(i915, id);
+ return intel_get_shared_dpll_by_id(display, id);
}
static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder->base.dev);
enum intel_dpll_id id;
switch (encoder->port) {
@@ -1906,7 +1906,7 @@ static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
return NULL;
}
- return intel_get_shared_dpll_by_id(i915, id);
+ return intel_get_shared_dpll_by_id(display, id);
}
static void skl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1957,12 +1957,12 @@ static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum intel_dpll_id id;
u32 tmp;
- tmp = intel_de_read(i915, DPLL_CTRL2);
+ tmp = intel_de_read(display, DPLL_CTRL2);
/*
* FIXME Not sure if the override affects both
@@ -1974,7 +1974,7 @@ static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
- return intel_get_shared_dpll_by_id(i915, id);
+ return intel_get_shared_dpll_by_id(display, id);
}
void hsw_ddi_enable_clock(struct intel_encoder *encoder,
@@ -2008,12 +2008,12 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum intel_dpll_id id;
u32 tmp;
- tmp = intel_de_read(i915, PORT_CLK_SEL(port));
+ tmp = intel_de_read(display, PORT_CLK_SEL(port));
switch (tmp & PORT_CLK_SEL_MASK) {
case PORT_CLK_SEL_WRPLL1:
@@ -2041,7 +2041,7 @@ static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
return NULL;
}
- return intel_get_shared_dpll_by_id(i915, id);
+ return intel_get_shared_dpll_by_id(display, id);
}
void intel_ddi_enable_clock(struct intel_encoder *encoder,
@@ -2121,13 +2121,13 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
}
static void
-tgl_dkl_phy_check_and_rewrite(struct drm_i915_private *dev_priv,
+tgl_dkl_phy_check_and_rewrite(struct intel_display *display,
enum tc_port tc_port, u32 ln0, u32 ln1)
{
- if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
- intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
- if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
- intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+ if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)))
+ intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);
+ if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)))
+ intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);
}
static void
@@ -2135,24 +2135,23 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
u32 ln0, ln1, pin_assignment;
u8 width;
- if (DISPLAY_VER(dev_priv) >= 14)
+ if (DISPLAY_VER(display) >= 14)
return;
if (!intel_encoder_is_tc(&dig_port->base) ||
intel_tc_port_in_tbt_alt_mode(dig_port))
return;
- if (DISPLAY_VER(dev_priv) >= 12) {
- ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0));
- ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1));
+ if (DISPLAY_VER(display) >= 12) {
+ ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0));
+ ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1));
} else {
- ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
- ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
+ ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port));
+ ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port));
}
ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
@@ -2164,7 +2163,7 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
switch (pin_assignment) {
case 0x0:
- drm_WARN_ON(&dev_priv->drm,
+ drm_WARN_ON(display->drm,
!intel_tc_port_in_legacy_mode(dig_port));
if (width == 1) {
ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
@@ -2209,16 +2208,16 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
MISSING_CASE(pin_assignment);
}
- if (DISPLAY_VER(dev_priv) >= 12) {
- intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
- intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+ if (DISPLAY_VER(display) >= 12) {
+ intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);
+ intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);
/* WA_14018221282 */
if (IS_DISPLAY_VER(display, 12, 13))
- tgl_dkl_phy_check_and_rewrite(dev_priv, tc_port, ln0, ln1);
+ tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1);
} else {
- intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
- intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
+ intel_de_write(display, MG_DP_MODE(0, tc_port), ln0);
+ intel_de_write(display, MG_DP_MODE(1, tc_port), ln1);
}
}
@@ -3725,12 +3724,13 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum tc_port tc_port = intel_encoder_to_tc(encoder);
int ln;
for (ln = 0; ln < 2; ln++)
- intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0);
+ intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln),
+ DKL_PCS_DW5_CORE_SOFTRESET, 0);
}
static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
@@ -4248,21 +4248,21 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct intel_shared_dpll *pll)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
bool pll_active;
- if (drm_WARN_ON(&i915->drm, !pll))
+ if (drm_WARN_ON(display->drm, !pll))
return;
port_dpll->pll = pll;
- pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
- drm_WARN_ON(&i915->drm, !pll_active);
+ pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
+ drm_WARN_ON(display->drm, !pll_active);
icl_set_active_port_dpll(crtc_state, port_dpll_id);
- crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
+ crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
&crtc_state->dpll_hw_state);
}
@@ -4351,12 +4351,12 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct intel_shared_dpll *pll)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum icl_port_dpll_id port_dpll_id;
struct icl_port_dpll *port_dpll;
bool pll_active;
- if (drm_WARN_ON(&i915->drm, !pll))
+ if (drm_WARN_ON(display->drm, !pll))
return;
if (icl_ddi_tc_pll_is_tbt(pll))
@@ -4367,15 +4367,15 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
port_dpll->pll = pll;
- pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
- drm_WARN_ON(&i915->drm, !pll_active);
+ pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
+ drm_WARN_ON(display->drm, !pll_active);
icl_set_active_port_dpll(crtc_state, port_dpll_id);
if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
- crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
+ crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
else
- crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
+ crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
&crtc_state->dpll_hw_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index f45a4f9ba23c..a31d1678dfc0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -507,7 +507,6 @@ static void
icl_tc_phy_aux_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
@@ -539,7 +538,7 @@ icl_tc_phy_aux_power_well_enable(struct intel_display *display,
tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx);
- if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) &
+ if (wait_for(intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)) &
DKL_CMN_UC_DW27_UC_HEALTH, 1))
drm_warn(display->drm,
"Timeout waiting TC uC health\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c b/drivers/gpu/drm/i915/display/intel_dkl_phy.c
index b146b4c46943..0920f78f182e 100644
--- a/drivers/gpu/drm/i915/display/intel_dkl_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c
@@ -20,20 +20,20 @@ void intel_dkl_phy_init(struct drm_i915_private *i915)
}
static void
-dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
+dkl_phy_set_hip_idx(struct intel_display *display, struct intel_dkl_phy_reg reg)
{
enum tc_port tc_port = DKL_REG_TC_PORT(reg);
- drm_WARN_ON(&i915->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS);
+ drm_WARN_ON(display->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS);
- intel_de_write(i915,
+ intel_de_write(display,
HIP_INDEX_REG(tc_port),
HIP_INDEX_VAL(tc_port, reg.bank_idx));
}
/**
* intel_dkl_phy_read - read a Dekel PHY register
- * @i915: i915 device instance
+ * @display: intel_display device instance
* @reg: Dekel PHY register
*
* Read the @reg Dekel PHY register.
@@ -41,42 +41,42 @@ dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
* Returns the read value.
*/
u32
-intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
+intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
{
u32 val;
- spin_lock(&i915->display.dkl.phy_lock);
+ spin_lock(&display->dkl.phy_lock);
- dkl_phy_set_hip_idx(i915, reg);
- val = intel_de_read(i915, DKL_REG_MMIO(reg));
+ dkl_phy_set_hip_idx(display, reg);
+ val = intel_de_read(display, DKL_REG_MMIO(reg));
- spin_unlock(&i915->display.dkl.phy_lock);
+ spin_unlock(&display->dkl.phy_lock);
return val;
}
/**
* intel_dkl_phy_write - write a Dekel PHY register
- * @i915: i915 device instance
+ * @display: intel_display device instance
* @reg: Dekel PHY register
* @val: value to write
*
* Write @val to the @reg Dekel PHY register.
*/
void
-intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val)
+intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val)
{
- spin_lock(&i915->display.dkl.phy_lock);
+ spin_lock(&display->dkl.phy_lock);
- dkl_phy_set_hip_idx(i915, reg);
- intel_de_write(i915, DKL_REG_MMIO(reg), val);
+ dkl_phy_set_hip_idx(display, reg);
+ intel_de_write(display, DKL_REG_MMIO(reg), val);
- spin_unlock(&i915->display.dkl.phy_lock);
+ spin_unlock(&display->dkl.phy_lock);
}
/**
* intel_dkl_phy_rmw - read-modify-write a Dekel PHY register
- * @i915: i915 device instance
+ * @display: display device instance
* @reg: Dekel PHY register
* @clear: mask to clear
* @set: mask to set
@@ -85,30 +85,30 @@ intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg,
* this value back to the register if the value differs from the read one.
*/
void
-intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set)
+intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set)
{
- spin_lock(&i915->display.dkl.phy_lock);
+ spin_lock(&display->dkl.phy_lock);
- dkl_phy_set_hip_idx(i915, reg);
- intel_de_rmw(i915, DKL_REG_MMIO(reg), clear, set);
+ dkl_phy_set_hip_idx(display, reg);
+ intel_de_rmw(display, DKL_REG_MMIO(reg), clear, set);
- spin_unlock(&i915->display.dkl.phy_lock);
+ spin_unlock(&display->dkl.phy_lock);
}
/**
* intel_dkl_phy_posting_read - do a posting read from a Dekel PHY register
- * @i915: i915 device instance
+ * @display: display device instance
* @reg: Dekel PHY register
*
* Read the @reg Dekel PHY register without returning the read value.
*/
void
-intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
+intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
{
- spin_lock(&i915->display.dkl.phy_lock);
+ spin_lock(&display->dkl.phy_lock);
- dkl_phy_set_hip_idx(i915, reg);
- intel_de_posting_read(i915, DKL_REG_MMIO(reg));
+ dkl_phy_set_hip_idx(display, reg);
+ intel_de_posting_read(display, DKL_REG_MMIO(reg));
- spin_unlock(&i915->display.dkl.phy_lock);
+ spin_unlock(&display->dkl.phy_lock);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.h b/drivers/gpu/drm/i915/display/intel_dkl_phy.h
index 5956ec3e940b..1d96e6be657c 100644
--- a/drivers/gpu/drm/i915/display/intel_dkl_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.h
@@ -11,15 +11,16 @@
#include "intel_dkl_phy_regs.h"
struct drm_i915_private;
+struct intel_display;
void intel_dkl_phy_init(struct drm_i915_private *i915);
u32
-intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg);
+intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
void
-intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val);
+intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val);
void
-intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set);
+intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set);
void
-intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg);
+intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
#endif /* __INTEL_DKL_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ec46adb13af7..8655522458d6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -65,7 +65,7 @@ struct intel_shared_dpll_funcs {
* Hook for enabling the pll, called from intel_enable_shared_dpll() if
* the pll is not already enabled.
*/
- void (*enable)(struct drm_i915_private *i915,
+ void (*enable)(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
@@ -74,7 +74,7 @@ struct intel_shared_dpll_funcs {
* only when it is safe to disable the pll, i.e., there are no more
* tracked users for it.
*/
- void (*disable)(struct drm_i915_private *i915,
+ void (*disable)(struct intel_display *display,
struct intel_shared_dpll *pll);
/*
@@ -82,7 +82,7 @@ struct intel_shared_dpll_funcs {
* registers. This is used for initial hw state readout and state
* verification after a mode set.
*/
- bool (*get_hw_state)(struct drm_i915_private *i915,
+ bool (*get_hw_state)(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state);
@@ -90,7 +90,7 @@ struct intel_shared_dpll_funcs {
* Hook for calculating the pll's output frequency based on its passed
* in state.
*/
- int (*get_freq)(struct drm_i915_private *i915,
+ int (*get_freq)(struct intel_display *i915,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
};
@@ -148,17 +148,16 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
/**
* intel_get_shared_dpll_by_id - get a DPLL given its id
- * @i915: i915 device instance
+ * @display: intel_display device instance
* @id: pll id
*
* Returns:
* A pointer to the DPLL with @id
*/
struct intel_shared_dpll *
-intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
+intel_get_shared_dpll_by_id(struct intel_display *display,
enum intel_dpll_id id)
{
- struct intel_display *display = to_intel_display(&i915->drm);
struct intel_shared_dpll *pll;
int i;
@@ -184,7 +183,7 @@ void assert_shared_dpll(struct drm_i915_private *i915,
"asserting DPLL %s with no DPLL\n", str_on_off(state)))
return;
- cur_state = intel_dpll_get_hw_state(i915, pll, &hw_state);
+ cur_state = intel_dpll_get_hw_state(display, pll, &hw_state);
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
"%s assertion failure (expected %s, current %s)\n",
pll->info->name, str_on_off(state),
@@ -202,12 +201,12 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
}
static i915_reg_t
-intel_combo_pll_enable_reg(struct drm_i915_private *i915,
+intel_combo_pll_enable_reg(struct intel_display *display,
struct intel_shared_dpll *pll)
{
- if (IS_DG1(i915))
+ if (display->platform.dg1)
return DG1_DPLL_ENABLE(pll->info->id);
- else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
+ else if ((display->platform.jasperlake || display->platform.elkhartlake) &&
(pll->info->id == DPLL_ID_EHL_DPLL4))
return MG_PLL_ENABLE(0);
@@ -215,36 +214,40 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
}
static i915_reg_t
-intel_tc_pll_enable_reg(struct drm_i915_private *i915,
+intel_tc_pll_enable_reg(struct intel_display *display,
struct intel_shared_dpll *pll)
{
const enum intel_dpll_id id = pll->info->id;
enum tc_port tc_port = icl_pll_id_to_tc_port(id);
- if (IS_ALDERLAKE_P(i915))
+ if (display->platform.alderlake_p)
return ADLP_PORTTC_PLL_ENABLE(tc_port);
return MG_PLL_ENABLE(tc_port);
}
-static void _intel_enable_shared_dpll(struct drm_i915_private *i915,
+static void _intel_enable_shared_dpll(struct intel_display *display,
struct intel_shared_dpll *pll)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
if (pll->info->power_domain)
pll->wakeref = intel_display_power_get(i915, pll->info->power_domain);
- pll->info->funcs->enable(i915, pll, &pll->state.hw_state);
+ pll->info->funcs->enable(display, pll, &pll->state.hw_state);
pll->on = true;
}
-static void _intel_disable_shared_dpll(struct drm_i915_private *i915,
+static void _intel_disable_shared_dpll(struct intel_display *display,
struct intel_shared_dpll *pll)
{
- pll->info->funcs->disable(i915, pll);
+ pll->info->funcs->disable(display, pll);
pll->on = false;
if (pll->info->power_domain)
- intel_display_power_put(i915, pll->info->power_domain, pll->wakeref);
+ intel_display_power_put(to_i915(display->drm),
+ pll->info->power_domain,
+ pll->wakeref);
}
/**
@@ -255,42 +258,43 @@ static void _intel_disable_shared_dpll(struct drm_i915_private *i915,
*/
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
unsigned int pipe_mask = BIT(crtc->pipe);
unsigned int old_mask;
- if (drm_WARN_ON(&i915->drm, pll == NULL))
+ if (drm_WARN_ON(display->drm, !pll))
return;
- mutex_lock(&i915->display.dpll.lock);
+ mutex_lock(&display->dpll.lock);
old_mask = pll->active_mask;
- if (drm_WARN_ON(&i915->drm, !(pll->state.pipe_mask & pipe_mask)) ||
- drm_WARN_ON(&i915->drm, pll->active_mask & pipe_mask))
+ if (drm_WARN_ON(display->drm, !(pll->state.pipe_mask & pipe_mask)) ||
+ drm_WARN_ON(display->drm, pll->active_mask & pipe_mask))
goto out;
pll->active_mask |= pipe_mask;
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"enable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
pll->info->name, pll->active_mask, pll->on,
crtc->base.base.id, crtc->base.name);
if (old_mask) {
- drm_WARN_ON(&i915->drm, !pll->on);
+ drm_WARN_ON(display->drm, !pll->on);
assert_shared_dpll_enabled(i915, pll);
goto out;
}
- drm_WARN_ON(&i915->drm, pll->on);
+ drm_WARN_ON(display->drm, pll->on);
- drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name);
+ drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name);
- _intel_enable_shared_dpll(i915, pll);
+ _intel_enable_shared_dpll(display, pll);
out:
- mutex_unlock(&i915->display.dpll.lock);
+ mutex_unlock(&display->dpll.lock);
}
/**
@@ -301,48 +305,48 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
*/
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
unsigned int pipe_mask = BIT(crtc->pipe);
/* PCH only available on ILK+ */
- if (DISPLAY_VER(i915) < 5)
+ if (DISPLAY_VER(display) < 5)
return;
if (pll == NULL)
return;
- mutex_lock(&i915->display.dpll.lock);
- if (drm_WARN(&i915->drm, !(pll->active_mask & pipe_mask),
+ mutex_lock(&display->dpll.lock);
+ if (drm_WARN(display->drm, !(pll->active_mask & pipe_mask),
"%s not used by [CRTC:%d:%s]\n", pll->info->name,
crtc->base.base.id, crtc->base.name))
goto out;
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"disable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
pll->info->name, pll->active_mask, pll->on,
crtc->base.base.id, crtc->base.name);
assert_shared_dpll_enabled(i915, pll);
- drm_WARN_ON(&i915->drm, !pll->on);
+ drm_WARN_ON(display->drm, !pll->on);
pll->active_mask &= ~pipe_mask;
if (pll->active_mask)
goto out;
- drm_dbg_kms(&i915->drm, "disabling %s\n", pll->info->name);
+ drm_dbg_kms(display->drm, "disabling %s\n", pll->info->name);
- _intel_disable_shared_dpll(i915, pll);
+ _intel_disable_shared_dpll(display, pll);
out:
- mutex_unlock(&i915->display.dpll.lock);
+ mutex_unlock(&display->dpll.lock);
}
static unsigned long
-intel_dpll_mask_all(struct drm_i915_private *i915)
+intel_dpll_mask_all(struct intel_display *display)
{
- struct intel_display *display = to_intel_display(&i915->drm);
struct intel_shared_dpll *pll;
unsigned long dpll_mask = 0;
int i;
@@ -362,20 +366,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
const struct intel_dpll_hw_state *dpll_hw_state,
unsigned long dpll_mask)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- unsigned long dpll_mask_all = intel_dpll_mask_all(i915);
+ struct intel_display *display = to_intel_display(crtc);
+ unsigned long dpll_mask_all = intel_dpll_mask_all(display);
struct intel_shared_dpll_state *shared_dpll;
struct intel_shared_dpll *unused_pll = NULL;
enum intel_dpll_id id;
shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
- drm_WARN_ON(&i915->drm, dpll_mask & ~dpll_mask_all);
+ drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
struct intel_shared_dpll *pll;
- pll = intel_get_shared_dpll_by_id(i915, id);
+ pll = intel_get_shared_dpll_by_id(display, id);
if (!pll)
continue;
@@ -389,7 +393,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
if (memcmp(dpll_hw_state,
&shared_dpll[pll->index].hw_state,
sizeof(*dpll_hw_state)) == 0) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n",
crtc->base.base.id, crtc->base.name,
pll->info->name,
@@ -401,7 +405,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
/* Ok no matching timings, maybe there's a free one? */
if (unused_pll) {
- drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] allocated %s\n",
+ drm_dbg_kms(display->drm, "[CRTC:%d:%s] allocated %s\n",
crtc->base.base.id, crtc->base.name,
unused_pll->info->name);
return unused_pll;
@@ -524,10 +528,11 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
swap(pll->state, shared_dpll[pll->index]);
}
-static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915,
+static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
@@ -538,10 +543,10 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915,
if (!wakeref)
return false;
- val = intel_de_read(i915, PCH_DPLL(id));
+ val = intel_de_read(display, PCH_DPLL(id));
hw_state->dpll = val;
- hw_state->fp0 = intel_de_read(i915, PCH_FP0(id));
- hw_state->fp1 = intel_de_read(i915, PCH_FP1(id));
+ hw_state->fp0 = intel_de_read(display, PCH_FP0(id));
+ hw_state->fp1 = intel_de_read(display, PCH_FP1(id));
intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
@@ -561,23 +566,24 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915)
"PCH refclk assertion failure, should be active but is disabled\n");
}
-static void ibx_pch_dpll_enable(struct drm_i915_private *i915,
+static void ibx_pch_dpll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
const enum intel_dpll_id id = pll->info->id;
/* PCH refclock must be enabled first */
ibx_assert_pch_refclk_enabled(i915);
- intel_de_write(i915, PCH_FP0(id), hw_state->fp0);
- intel_de_write(i915, PCH_FP1(id), hw_state->fp1);
+ intel_de_write(display, PCH_FP0(id), hw_state->fp0);
+ intel_de_write(display, PCH_FP1(id), hw_state->fp1);
- intel_de_write(i915, PCH_DPLL(id), hw_state->dpll);
+ intel_de_write(display, PCH_DPLL(id), hw_state->dpll);
/* Wait for the clocks to stabilize. */
- intel_de_posting_read(i915, PCH_DPLL(id));
+ intel_de_posting_read(display, PCH_DPLL(id));
udelay(150);
/* The pixel multiplier can only be updated once the
@@ -585,18 +591,18 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *i915,
*
* So write it again.
*/
- intel_de_write(i915, PCH_DPLL(id), hw_state->dpll);
- intel_de_posting_read(i915, PCH_DPLL(id));
+ intel_de_write(display, PCH_DPLL(id), hw_state->dpll);
+ intel_de_posting_read(display, PCH_DPLL(id));
udelay(200);
}
-static void ibx_pch_dpll_disable(struct drm_i915_private *i915,
+static void ibx_pch_dpll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
const enum intel_dpll_id id = pll->info->id;
- intel_de_write(i915, PCH_DPLL(id), 0);
- intel_de_posting_read(i915, PCH_DPLL(id));
+ intel_de_write(display, PCH_DPLL(id), 0);
+ intel_de_posting_read(display, PCH_DPLL(id));
udelay(200);
}
@@ -611,18 +617,19 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(state);
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll;
enum intel_dpll_id id;
if (HAS_PCH_IBX(i915)) {
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
id = (enum intel_dpll_id) crtc->pipe;
- pll = intel_get_shared_dpll_by_id(i915, id);
+ pll = intel_get_shared_dpll_by_id(display, id);
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"[CRTC:%d:%s] using pre-allocated %s\n",
crtc->base.base.id, crtc->base.name,
pll->info->name);
@@ -691,65 +698,66 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
.compare_hw_state = ibx_compare_hw_state,
};
-static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915,
+static void hsw_ddi_wrpll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
const enum intel_dpll_id id = pll->info->id;
- intel_de_write(i915, WRPLL_CTL(id), hw_state->wrpll);
- intel_de_posting_read(i915, WRPLL_CTL(id));
+ intel_de_write(display, WRPLL_CTL(id), hw_state->wrpll);
+ intel_de_posting_read(display, WRPLL_CTL(id));
udelay(20);
}
-static void hsw_ddi_spll_enable(struct drm_i915_private *i915,
+static void hsw_ddi_spll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
- intel_de_write(i915, SPLL_CTL, hw_state->spll);
- intel_de_posting_read(i915, SPLL_CTL);
+ intel_de_write(display, SPLL_CTL, hw_state->spll);
+ intel_de_posting_read(display, SPLL_CTL);
udelay(20);
}
-static void hsw_ddi_wrpll_disable(struct drm_i915_private *i915,
+static void hsw_ddi_wrpll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
const enum intel_dpll_id id = pll->info->id;
- intel_de_rmw(i915, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0);
- intel_de_posting_read(i915, WRPLL_CTL(id));
+ intel_de_rmw(display, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0);
+ intel_de_posting_read(display, WRPLL_CTL(id));
/*
* Try to set up the PCH reference clock once all DPLLs
* that depend on it have been shut down.
*/
- if (i915->display.dpll.pch_ssc_use & BIT(id))
- intel_init_pch_refclk(i915);
+ if (display->dpll.pch_ssc_use & BIT(id))
+ intel_init_pch_refclk(to_i915(display->drm));
}
-static void hsw_ddi_spll_disable(struct drm_i915_private *i915,
+static void hsw_ddi_spll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
enum intel_dpll_id id = pll->info->id;
- intel_de_rmw(i915, SPLL_CTL, SPLL_PLL_ENABLE, 0);
- intel_de_posting_read(i915, SPLL_CTL);
+ intel_de_rmw(display, SPLL_CTL, SPLL_PLL_ENABLE, 0);
+ intel_de_posting_read(display, SPLL_CTL);
/*
* Try to set up the PCH reference clock once all DPLLs
* that depend on it have been shut down.
*/
- if (i915->display.dpll.pch_ssc_use & BIT(id))
- intel_init_pch_refclk(i915);
+ if (display->dpll.pch_ssc_use & BIT(id))
+ intel_init_pch_refclk(to_i915(display->drm));
}
-static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915,
+static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
@@ -760,7 +768,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915,
if (!wakeref)
return false;
- val = intel_de_read(i915, WRPLL_CTL(id));
+ val = intel_de_read(display, WRPLL_CTL(id));
hw_state->wrpll = val;
intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
@@ -768,10 +776,11 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915,
return val & WRPLL_PLL_ENABLE;
}
-static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915,
+static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
intel_wakeref_t wakeref;
u32 val;
@@ -781,7 +790,7 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915,
if (!wakeref)
return false;
- val = intel_de_read(i915, SPLL_CTL);
+ val = intel_de_read(display, SPLL_CTL);
hw_state->spll = val;
intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
@@ -995,7 +1004,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
*r2_out = best.r2;
}
-static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915,
+static int hsw_ddi_wrpll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -1007,8 +1016,8 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915,
switch (wrpll & WRPLL_REF_MASK) {
case WRPLL_REF_SPECIAL_HSW:
/* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
- if (IS_HASWELL(i915) && !IS_HASWELL_ULT(i915)) {
- refclk = i915->display.dpll.ref_clks.nssc;
+ if (display->platform.haswell && !display->platform.haswell_ult) {
+ refclk = display->dpll.ref_clks.nssc;
break;
}
fallthrough;
@@ -1018,7 +1027,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915,
* code only cares about 5% accuracy, and spread is a max of
* 0.5% downspread.
*/
- refclk = i915->display.dpll.ref_clks.ssc;
+ refclk = display->dpll.ref_clks.ssc;
break;
case WRPLL_REF_LCPLL:
refclk = 2700000;
@@ -1040,7 +1049,7 @@ static int
hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
@@ -1053,7 +1062,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
WRPLL_DIVIDER_POST(p);
- crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL,
+ crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL,
&crtc_state->dpll_hw_state);
return 0;
@@ -1093,7 +1102,7 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
static struct intel_shared_dpll *
hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_shared_dpll *pll;
enum intel_dpll_id pll_id;
int clock = crtc_state->port_clock;
@@ -1113,7 +1122,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
return NULL;
}
- pll = intel_get_shared_dpll_by_id(i915, pll_id);
+ pll = intel_get_shared_dpll_by_id(display, pll_id);
if (!pll)
return NULL;
@@ -1121,7 +1130,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
return pll;
}
-static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
+static int hsw_ddi_lcpll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -1138,7 +1147,7 @@ static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
link_clock = 270000;
break;
default:
- drm_WARN(&i915->drm, 1, "bad port clock sel\n");
+ drm_WARN(display->drm, 1, "bad port clock sel\n");
break;
}
@@ -1173,7 +1182,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
BIT(DPLL_ID_SPLL));
}
-static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
+static int hsw_ddi_spll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -1191,7 +1200,7 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
link_clock = 270000;
break;
default:
- drm_WARN(&i915->drm, 1, "bad spll freq\n");
+ drm_WARN(display->drm, 1, "bad spll freq\n");
break;
}
@@ -1284,18 +1293,18 @@ static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
.get_freq = hsw_ddi_spll_get_freq,
};
-static void hsw_ddi_lcpll_enable(struct drm_i915_private *i915,
+static void hsw_ddi_lcpll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *hw_state)
{
}
-static void hsw_ddi_lcpll_disable(struct drm_i915_private *i915,
+static void hsw_ddi_lcpll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
}
-static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *i915,
+static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -1363,21 +1372,21 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
},
};
-static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915,
+static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct skl_dpll_hw_state *hw_state)
{
const enum intel_dpll_id id = pll->info->id;
- intel_de_rmw(i915, DPLL_CTRL1,
+ intel_de_rmw(display, DPLL_CTRL1,
DPLL_CTRL1_HDMI_MODE(id) |
DPLL_CTRL1_SSC(id) |
DPLL_CTRL1_LINK_RATE_MASK(id),
hw_state->ctrl1 << (id * 6));
- intel_de_posting_read(i915, DPLL_CTRL1);
+ intel_de_posting_read(display, DPLL_CTRL1);
}
-static void skl_ddi_pll_enable(struct drm_i915_private *i915,
+static void skl_ddi_pll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -1385,49 +1394,50 @@ static void skl_ddi_pll_enable(struct drm_i915_private *i915,
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
- skl_ddi_pll_write_ctrl1(i915, pll, hw_state);
+ skl_ddi_pll_write_ctrl1(display, pll, hw_state);
- intel_de_write(i915, regs[id].cfgcr1, hw_state->cfgcr1);
- intel_de_write(i915, regs[id].cfgcr2, hw_state->cfgcr2);
- intel_de_posting_read(i915, regs[id].cfgcr1);
- intel_de_posting_read(i915, regs[id].cfgcr2);
+ intel_de_write(display, regs[id].cfgcr1, hw_state->cfgcr1);
+ intel_de_write(display, regs[id].cfgcr2, hw_state->cfgcr2);
+ intel_de_posting_read(display, regs[id].cfgcr1);
+ intel_de_posting_read(display, regs[id].cfgcr2);
/* the enable bit is always bit 31 */
- intel_de_rmw(i915, regs[id].ctl, 0, LCPLL_PLL_ENABLE);
+ intel_de_rmw(display, regs[id].ctl, 0, LCPLL_PLL_ENABLE);
- if (intel_de_wait_for_set(i915, DPLL_STATUS, DPLL_LOCK(id), 5))
- drm_err(&i915->drm, "DPLL %d not locked\n", id);
+ if (intel_de_wait_for_set(display, DPLL_STATUS, DPLL_LOCK(id), 5))
+ drm_err(display->drm, "DPLL %d not locked\n", id);
}
-static void skl_ddi_dpll0_enable(struct drm_i915_private *i915,
+static void skl_ddi_dpll0_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
- skl_ddi_pll_write_ctrl1(i915, pll, hw_state);
+ skl_ddi_pll_write_ctrl1(display, pll, hw_state);
}
-static void skl_ddi_pll_disable(struct drm_i915_private *i915,
+static void skl_ddi_pll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
/* the enable bit is always bit 31 */
- intel_de_rmw(i915, regs[id].ctl, LCPLL_PLL_ENABLE, 0);
- intel_de_posting_read(i915, regs[id].ctl);
+ intel_de_rmw(display, regs[id].ctl, LCPLL_PLL_ENABLE, 0);
+ intel_de_posting_read(display, regs[id].ctl);
}
-static void skl_ddi_dpll0_disable(struct drm_i915_private *i915,
+static void skl_ddi_dpll0_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
}
-static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915,
+static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
@@ -1442,17 +1452,17 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915,
ret = false;
- val = intel_de_read(i915, regs[id].ctl);
+ val = intel_de_read(display, regs[id].ctl);
if (!(val & LCPLL_PLL_ENABLE))
goto out;
- val = intel_de_read(i915, DPLL_CTRL1);
+ val = intel_de_read(display, DPLL_CTRL1);
hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
/* avoid reading back stale values if HDMI mode is not enabled */
if (val & DPLL_CTRL1_HDMI_MODE(id)) {
- hw_state->cfgcr1 = intel_de_read(i915, regs[id].cfgcr1);
- hw_state->cfgcr2 = intel_de_read(i915, regs[id].cfgcr2);
+ hw_state->cfgcr1 = intel_de_read(display, regs[id].cfgcr1);
+ hw_state->cfgcr2 = intel_de_read(display, regs[id].cfgcr2);
}
ret = true;
@@ -1462,10 +1472,11 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915,
return ret;
}
-static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915,
+static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
@@ -1481,11 +1492,11 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915,
ret = false;
/* DPLL0 is always enabled since it drives CDCLK */
- val = intel_de_read(i915, regs[id].ctl);
+ val = intel_de_read(display, regs[id].ctl);
if (drm_WARN_ON(&i915->drm, !(val & LCPLL_PLL_ENABLE)))
goto out;
- val = intel_de_read(i915, DPLL_CTRL1);
+ val = intel_de_read(display, DPLL_CTRL1);
hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
ret = true;
@@ -1735,12 +1746,12 @@ skl_ddi_calculate_wrpll(int clock,
return 0;
}
-static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
+static int skl_ddi_wrpll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
- int ref_clock = i915->display.dpll.ref_clks.nssc;
+ int ref_clock = display->dpll.ref_clks.nssc;
u32 p0, p1, p2, dco_freq;
p0 = hw_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
@@ -1767,7 +1778,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
* Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0,
* handling it the same way as PDIV_7.
*/
- drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
+ drm_dbg_kms(display->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
fallthrough;
case DPLL_CFGCR2_PDIV_7:
p0 = 7;
@@ -1801,7 +1812,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
dco_freq += ((hw_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) *
ref_clock / 0x8000;
- if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
+ if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0))
return 0;
return dco_freq / (p0 * p1 * p2 * 5);
@@ -1809,13 +1820,13 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
struct skl_wrpll_params wrpll_params = {};
int ret;
ret = skl_ddi_calculate_wrpll(crtc_state->port_clock,
- i915->display.dpll.ref_clks.nssc, &wrpll_params);
+ display->dpll.ref_clks.nssc, &wrpll_params);
if (ret)
return ret;
@@ -1839,7 +1850,7 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
wrpll_params.central_freq;
- crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL,
+ crtc_state->port_clock = skl_ddi_wrpll_get_freq(display, NULL,
&crtc_state->dpll_hw_state);
return 0;
@@ -1883,7 +1894,7 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
return 0;
}
-static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
+static int skl_ddi_lcpll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -1911,7 +1922,7 @@ static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
link_clock = 270000;
break;
default:
- drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
+ drm_WARN(display->drm, 1, "Unsupported link rate\n");
break;
}
@@ -1962,7 +1973,7 @@ static int skl_get_dpll(struct intel_atomic_state *state,
return 0;
}
-static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
+static int skl_ddi_pll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -1973,9 +1984,9 @@ static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
* the internal shift for each field
*/
if (hw_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
- return skl_ddi_wrpll_get_freq(i915, pll, dpll_hw_state);
+ return skl_ddi_wrpll_get_freq(display, pll, dpll_hw_state);
else
- return skl_ddi_lcpll_get_freq(i915, pll, dpll_hw_state);
+ return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);
}
static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
@@ -2037,11 +2048,10 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
.compare_hw_state = skl_compare_hw_state,
};
-static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
+static void bxt_ddi_pll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
- struct intel_display *display = &i915->display;
const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
enum dpio_phy phy;
@@ -2051,120 +2061,120 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
bxt_port_to_phy_channel(display, port, &phy, &ch);
/* Non-SSC reference */
- intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
+ intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
- if (IS_GEMINILAKE(i915)) {
- intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port),
+ if (display->platform.geminilake) {
+ intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
0, PORT_PLL_POWER_ENABLE);
- if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) &
+ if (wait_for_us((intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) &
PORT_PLL_POWER_STATE), 200))
- drm_err(&i915->drm,
+ drm_err(display->drm,
"Power state not set for PLL:%d\n", port);
}
/* Disable 10 bit clock */
- intel_de_rmw(i915, BXT_PORT_PLL_EBB_4(phy, ch),
+ intel_de_rmw(display, BXT_PORT_PLL_EBB_4(phy, ch),
PORT_PLL_10BIT_CLK_ENABLE, 0);
/* Write P1 & P2 */
- intel_de_rmw(i915, BXT_PORT_PLL_EBB_0(phy, ch),
+ intel_de_rmw(display, BXT_PORT_PLL_EBB_0(phy, ch),
PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, hw_state->ebb0);
/* Write M2 integer */
- intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 0),
+ intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 0),
PORT_PLL_M2_INT_MASK, hw_state->pll0);
/* Write N */
- intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 1),
+ intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 1),
PORT_PLL_N_MASK, hw_state->pll1);
/* Write M2 fraction */
- intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 2),
+ intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 2),
PORT_PLL_M2_FRAC_MASK, hw_state->pll2);
/* Write M2 fraction enable */
- intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 3),
+ intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 3),
PORT_PLL_M2_FRAC_ENABLE, hw_state->pll3);
/* Write coeff */
- temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6));
+ temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));
temp &= ~PORT_PLL_PROP_COEFF_MASK;
temp &= ~PORT_PLL_INT_COEFF_MASK;
temp &= ~PORT_PLL_GAIN_CTL_MASK;
temp |= hw_state->pll6;
- intel_de_write(i915, BXT_PORT_PLL(phy, ch, 6), temp);
+ intel_de_write(display, BXT_PORT_PLL(phy, ch, 6), temp);
/* Write calibration val */
- intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 8),
+ intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 8),
PORT_PLL_TARGET_CNT_MASK, hw_state->pll8);
- intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 9),
+ intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 9),
PORT_PLL_LOCK_THRESHOLD_MASK, hw_state->pll9);
- temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10));
+ temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));
temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
temp &= ~PORT_PLL_DCO_AMP_MASK;
temp |= hw_state->pll10;
- intel_de_write(i915, BXT_PORT_PLL(phy, ch, 10), temp);
+ intel_de_write(display, BXT_PORT_PLL(phy, ch, 10), temp);
/* Recalibrate with new settings */
- temp = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch));
+ temp = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));
temp |= PORT_PLL_RECALIBRATE;
- intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp);
+ intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp);
temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
temp |= hw_state->ebb4;
- intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp);
+ intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp);
/* Enable PLL */
- intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
- intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port));
+ intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
+ intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
- if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
+ if (wait_for_us((intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
200))
- drm_err(&i915->drm, "PLL %d not locked\n", port);
+ drm_err(display->drm, "PLL %d not locked\n", port);
- if (IS_GEMINILAKE(i915)) {
- temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN(phy, ch, 0));
+ if (display->platform.geminilake) {
+ temp = intel_de_read(display, BXT_PORT_TX_DW5_LN(phy, ch, 0));
temp |= DCC_DELAY_RANGE_2;
- intel_de_write(i915, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
+ intel_de_write(display, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
}
/*
* While we write to the group register to program all lanes at once we
* can read only lane registers and we pick lanes 0/1 for that.
*/
- temp = intel_de_read(i915, BXT_PORT_PCS_DW12_LN01(phy, ch));
+ temp = intel_de_read(display, BXT_PORT_PCS_DW12_LN01(phy, ch));
temp &= ~LANE_STAGGER_MASK;
temp &= ~LANESTAGGER_STRAP_OVRD;
temp |= hw_state->pcsdw12;
- intel_de_write(i915, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
+ intel_de_write(display, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
}
-static void bxt_ddi_pll_disable(struct drm_i915_private *i915,
+static void bxt_ddi_pll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
- intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);
- intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port));
+ intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);
+ intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
- if (IS_GEMINILAKE(i915)) {
- intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port),
+ if (display->platform.geminilake) {
+ intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
PORT_PLL_POWER_ENABLE, 0);
- if (wait_for_us(!(intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) &
+ if (wait_for_us(!(intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) &
PORT_PLL_POWER_STATE), 200))
- drm_err(&i915->drm,
+ drm_err(display->drm,
"Power state not reset for PLL:%d\n", port);
}
}
-static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
+static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
intel_wakeref_t wakeref;
@@ -2182,40 +2192,40 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
ret = false;
- val = intel_de_read(i915, BXT_PORT_PLL_ENABLE(port));
+ val = intel_de_read(display, BXT_PORT_PLL_ENABLE(port));
if (!(val & PORT_PLL_ENABLE))
goto out;
- hw_state->ebb0 = intel_de_read(i915, BXT_PORT_PLL_EBB_0(phy, ch));
+ hw_state->ebb0 = intel_de_read(display, BXT_PORT_PLL_EBB_0(phy, ch));
hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
- hw_state->ebb4 = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch));
+ hw_state->ebb4 = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));
hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
- hw_state->pll0 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 0));
+ hw_state->pll0 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 0));
hw_state->pll0 &= PORT_PLL_M2_INT_MASK;
- hw_state->pll1 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 1));
+ hw_state->pll1 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 1));
hw_state->pll1 &= PORT_PLL_N_MASK;
- hw_state->pll2 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 2));
+ hw_state->pll2 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 2));
hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
- hw_state->pll3 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 3));
+ hw_state->pll3 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 3));
hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
- hw_state->pll6 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6));
+ hw_state->pll6 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));
hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
PORT_PLL_INT_COEFF_MASK |
PORT_PLL_GAIN_CTL_MASK;
- hw_state->pll8 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 8));
+ hw_state->pll8 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 8));
hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
- hw_state->pll9 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 9));
+ hw_state->pll9 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 9));
hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
- hw_state->pll10 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10));
+ hw_state->pll10 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));
hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
PORT_PLL_DCO_AMP_MASK;
@@ -2224,13 +2234,13 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
* can read only lane registers. We configure all lanes the same way, so
* here just read out lanes 0/1 and output a note if lanes 2/3 differ.
*/
- hw_state->pcsdw12 = intel_de_read(i915,
+ hw_state->pcsdw12 = intel_de_read(display,
BXT_PORT_PCS_DW12_LN01(phy, ch));
- if (intel_de_read(i915, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
- drm_dbg(&i915->drm,
+ if (intel_de_read(display, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
+ drm_dbg(display->drm,
"lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
hw_state->pcsdw12,
- intel_de_read(i915,
+ intel_de_read(display,
BXT_PORT_PCS_DW12_LN23(phy, ch)));
hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
@@ -2361,7 +2371,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
return 0;
}
-static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
+static int bxt_ddi_pll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -2377,7 +2387,7 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, hw_state->ebb0);
clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, hw_state->ebb0);
- return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock);
+ return chv_calc_dpll_params(display->dpll.ref_clks.nssc, &clock);
}
static int
@@ -2393,7 +2403,7 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
static int
bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
struct dpll clk_div = {};
int ret;
@@ -2403,7 +2413,7 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
if (ret)
return ret;
- crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL,
+ crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL,
&crtc_state->dpll_hw_state);
return 0;
@@ -2428,17 +2438,17 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll;
enum intel_dpll_id id;
/* 1:1 mapping between ports and PLLs */
id = (enum intel_dpll_id) encoder->port;
- pll = intel_get_shared_dpll_by_id(i915, id);
+ pll = intel_get_shared_dpll_by_id(display, id);
- drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
+ drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
crtc->base.base.id, crtc->base.name, pll->info->name);
intel_reference_shared_dpll(state, crtc,
@@ -2604,12 +2614,14 @@ static void icl_wrpll_params_populate(struct skl_wrpll_params *params,
* Program half of the nominal DCO divider fraction value.
*/
static bool
-ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
+ehl_combo_pll_div_frac_wa_needed(struct intel_display *display)
{
- return ((IS_ELKHARTLAKE(i915) &&
- IS_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
- IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
- i915->display.dpll.ref_clks.nssc == 38400;
+ return ((display->platform.elkhartlake &&
+ IS_DISPLAY_STEP(display, STEP_B0, STEP_FOREVER)) ||
+ display->platform.tigerlake ||
+ display->platform.alderlake_s ||
+ display->platform.alderlake_p) &&
+ display->dpll.ref_clks.nssc == 38400;
}
struct icl_combo_pll_params {
@@ -2756,7 +2768,7 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
return 0;
}
-static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
+static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -2764,14 +2776,14 @@ static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
* The PLL outputs multiple frequencies at the same time, selection is
* made at DDI clock mux level.
*/
- drm_WARN_ON(&i915->drm, 1);
+ drm_WARN_ON(display->drm, 1);
return 0;
}
-static int icl_wrpll_ref_clock(struct drm_i915_private *i915)
+static int icl_wrpll_ref_clock(struct intel_display *display)
{
- int ref_clock = i915->display.dpll.ref_clks.nssc;
+ int ref_clock = display->dpll.ref_clks.nssc;
/*
* For ICL+, the spec states: if reference frequency is 38.4,
@@ -2787,8 +2799,8 @@ static int
icl_calc_wrpll(struct intel_crtc_state *crtc_state,
struct skl_wrpll_params *wrpll_params)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- int ref_clock = icl_wrpll_ref_clock(i915);
+ struct intel_display *display = to_intel_display(crtc_state);
+ int ref_clock = icl_wrpll_ref_clock(display);
u32 afe_clock = crtc_state->port_clock * 5;
u32 dco_min = 7998000;
u32 dco_max = 10000000;
@@ -2827,12 +2839,12 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
return 0;
}
-static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
+static int icl_ddi_combo_pll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
- int ref_clock = icl_wrpll_ref_clock(i915);
+ int ref_clock = icl_wrpll_ref_clock(display);
u32 dco_fraction;
u32 p0, p1, p2, dco_freq;
@@ -2878,25 +2890,25 @@ static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
dco_fraction = (hw_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
DPLL_CFGCR0_DCO_FRACTION_SHIFT;
- if (ehl_combo_pll_div_frac_wa_needed(i915))
+ if (ehl_combo_pll_div_frac_wa_needed(display))
dco_fraction *= 2;
dco_freq += (dco_fraction * ref_clock) / 0x8000;
- if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
+ if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0))
return 0;
return dco_freq / (p0 * p1 * p2 * 5);
}
-static void icl_calc_dpll_state(struct drm_i915_private *i915,
+static void icl_calc_dpll_state(struct intel_display *display,
const struct skl_wrpll_params *pll_params,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
u32 dco_fraction = pll_params->dco_fraction;
- if (ehl_combo_pll_div_frac_wa_needed(i915))
+ if (ehl_combo_pll_div_frac_wa_needed(display))
dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
hw_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
@@ -2907,13 +2919,13 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
DPLL_CFGCR1_KDIV(pll_params->kdiv) |
DPLL_CFGCR1_PDIV(pll_params->pdiv);
- if (DISPLAY_VER(i915) >= 12)
+ if (DISPLAY_VER(display) >= 12)
hw_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
else
hw_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
- if (i915->display.vbt.override_afc_startup)
- hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val);
+ if (display->vbt.override_afc_startup)
+ hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(display->vbt.override_afc_startup_val);
}
static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
@@ -3200,7 +3212,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
return 0;
}
-static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915,
+static int icl_ddi_mg_pll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -3208,9 +3220,9 @@ static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915,
u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
u64 tmp;
- ref_clock = i915->display.dpll.ref_clks.nssc;
+ ref_clock = display->dpll.ref_clks.nssc;
- if (DISPLAY_VER(i915) >= 12) {
+ if (DISPLAY_VER(display) >= 12) {
m1 = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
m2_int = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
@@ -3315,7 +3327,7 @@ static void icl_update_active_dpll(struct intel_atomic_state *state,
static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct icl_port_dpll *port_dpll =
@@ -3332,12 +3344,12 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
if (ret)
return ret;
- icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state);
+ icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state);
/* this is mainly for the fastset check */
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
- crtc_state->port_clock = icl_ddi_combo_pll_get_freq(i915, NULL,
+ crtc_state->port_clock = icl_ddi_combo_pll_get_freq(display, NULL,
&port_dpll->hw_state);
return 0;
@@ -3407,7 +3419,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_crtc_state *old_crtc_state =
@@ -3422,7 +3434,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
if (ret)
return ret;
- icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state);
+ icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state);
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
@@ -3436,7 +3448,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
else
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
- crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL,
+ crtc_state->port_clock = icl_ddi_mg_pll_get_freq(display, NULL,
&port_dpll->hw_state);
return 0;
@@ -3540,10 +3552,11 @@ static void icl_put_dplls(struct intel_atomic_state *state,
}
}
-static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
+static bool mg_pll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
const enum intel_dpll_id id = pll->info->id;
enum tc_port tc_port = icl_pll_id_to_tc_port(id);
@@ -3551,18 +3564,18 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
bool ret = false;
u32 val;
- i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
+ i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
wakeref = intel_display_power_get_if_enabled(i915,
POWER_DOMAIN_DISPLAY_CORE);
if (!wakeref)
return false;
- val = intel_de_read(i915, enable_reg);
+ val = intel_de_read(display, enable_reg);
if (!(val & PLL_ENABLE))
goto out;
- hw_state->mg_refclkin_ctl = intel_de_read(i915,
+ hw_state->mg_refclkin_ctl = intel_de_read(display,
MG_REFCLKIN_CTL(tc_port));
hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
@@ -3572,23 +3585,23 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
hw_state->mg_clktop2_hsclkctl =
- intel_de_read(i915, MG_CLKTOP2_HSCLKCTL(tc_port));
+ intel_de_read(display, MG_CLKTOP2_HSCLKCTL(tc_port));
hw_state->mg_clktop2_hsclkctl &=
MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
- hw_state->mg_pll_div0 = intel_de_read(i915, MG_PLL_DIV0(tc_port));
- hw_state->mg_pll_div1 = intel_de_read(i915, MG_PLL_DIV1(tc_port));
- hw_state->mg_pll_lf = intel_de_read(i915, MG_PLL_LF(tc_port));
- hw_state->mg_pll_frac_lock = intel_de_read(i915,
+ hw_state->mg_pll_div0 = intel_de_read(display, MG_PLL_DIV0(tc_port));
+ hw_state->mg_pll_div1 = intel_de_read(display, MG_PLL_DIV1(tc_port));
+ hw_state->mg_pll_lf = intel_de_read(display, MG_PLL_LF(tc_port));
+ hw_state->mg_pll_frac_lock = intel_de_read(display,
MG_PLL_FRAC_LOCK(tc_port));
- hw_state->mg_pll_ssc = intel_de_read(i915, MG_PLL_SSC(tc_port));
+ hw_state->mg_pll_ssc = intel_de_read(display, MG_PLL_SSC(tc_port));
- hw_state->mg_pll_bias = intel_de_read(i915, MG_PLL_BIAS(tc_port));
+ hw_state->mg_pll_bias = intel_de_read(display, MG_PLL_BIAS(tc_port));
hw_state->mg_pll_tdc_coldst_bias =
- intel_de_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port));
+ intel_de_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));
if (i915->display.dpll.ref_clks.nssc == 38400) {
hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
@@ -3607,10 +3620,11 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
return ret;
}
-static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
+static bool dkl_pll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
const enum intel_dpll_id id = pll->info->id;
enum tc_port tc_port = icl_pll_id_to_tc_port(id);
@@ -3623,7 +3637,7 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
if (!wakeref)
return false;
- val = intel_de_read(i915, intel_tc_pll_enable_reg(i915, pll));
+ val = intel_de_read(display, intel_tc_pll_enable_reg(display, pll));
if (!(val & PLL_ENABLE))
goto out;
@@ -3631,12 +3645,12 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
* All registers read here have the same HIP_INDEX_REG even though
* they are on different building blocks
*/
- hw_state->mg_refclkin_ctl = intel_dkl_phy_read(i915,
+ hw_state->mg_refclkin_ctl = intel_dkl_phy_read(display,
DKL_REFCLKIN_CTL(tc_port));
hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
hw_state->mg_clktop2_hsclkctl =
- intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port));
+ intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));
hw_state->mg_clktop2_hsclkctl &=
MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
@@ -3644,32 +3658,32 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
hw_state->mg_clktop2_coreclkctl1 =
- intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port));
+ intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));
hw_state->mg_clktop2_coreclkctl1 &=
MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
- hw_state->mg_pll_div0 = intel_dkl_phy_read(i915, DKL_PLL_DIV0(tc_port));
+ hw_state->mg_pll_div0 = intel_dkl_phy_read(display, DKL_PLL_DIV0(tc_port));
val = DKL_PLL_DIV0_MASK;
- if (i915->display.vbt.override_afc_startup)
+ if (display->vbt.override_afc_startup)
val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
hw_state->mg_pll_div0 &= val;
- hw_state->mg_pll_div1 = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port));
+ hw_state->mg_pll_div1 = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));
hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK |
DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
- hw_state->mg_pll_ssc = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port));
+ hw_state->mg_pll_ssc = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));
hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
DKL_PLL_SSC_STEP_LEN_MASK |
DKL_PLL_SSC_STEP_NUM_MASK |
DKL_PLL_SSC_EN);
- hw_state->mg_pll_bias = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port));
+ hw_state->mg_pll_bias = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));
hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H |
DKL_PLL_BIAS_FBDIV_FRAC_MASK);
hw_state->mg_pll_tdc_coldst_bias =
- intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
+ intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
@@ -3679,11 +3693,12 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
return ret;
}
-static bool icl_pll_get_hw_state(struct drm_i915_private *i915,
+static bool icl_pll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state,
i915_reg_t enable_reg)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
@@ -3695,41 +3710,41 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *i915,
if (!wakeref)
return false;
- val = intel_de_read(i915, enable_reg);
+ val = intel_de_read(display, enable_reg);
if (!(val & PLL_ENABLE))
goto out;
- if (IS_ALDERLAKE_S(i915)) {
- hw_state->cfgcr0 = intel_de_read(i915, ADLS_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = intel_de_read(i915, ADLS_DPLL_CFGCR1(id));
- } else if (IS_DG1(i915)) {
- hw_state->cfgcr0 = intel_de_read(i915, DG1_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = intel_de_read(i915, DG1_DPLL_CFGCR1(id));
- } else if (IS_ROCKETLAKE(i915)) {
- hw_state->cfgcr0 = intel_de_read(i915,
+ if (display->platform.alderlake_s) {
+ hw_state->cfgcr0 = intel_de_read(display, ADLS_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = intel_de_read(display, ADLS_DPLL_CFGCR1(id));
+ } else if (display->platform.dg1) {
+ hw_state->cfgcr0 = intel_de_read(display, DG1_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = intel_de_read(display, DG1_DPLL_CFGCR1(id));
+ } else if (display->platform.rocketlake) {
+ hw_state->cfgcr0 = intel_de_read(display,
RKL_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = intel_de_read(i915,
+ hw_state->cfgcr1 = intel_de_read(display,
RKL_DPLL_CFGCR1(id));
- } else if (DISPLAY_VER(i915) >= 12) {
- hw_state->cfgcr0 = intel_de_read(i915,
+ } else if (DISPLAY_VER(display) >= 12) {
+ hw_state->cfgcr0 = intel_de_read(display,
TGL_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = intel_de_read(i915,
+ hw_state->cfgcr1 = intel_de_read(display,
TGL_DPLL_CFGCR1(id));
if (i915->display.vbt.override_afc_startup) {
- hw_state->div0 = intel_de_read(i915, TGL_DPLL0_DIV0(id));
+ hw_state->div0 = intel_de_read(display, TGL_DPLL0_DIV0(id));
hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
}
} else {
- if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
+ if ((display->platform.jasperlake || display->platform.elkhartlake) &&
id == DPLL_ID_EHL_DPLL4) {
- hw_state->cfgcr0 = intel_de_read(i915,
+ hw_state->cfgcr0 = intel_de_read(display,
ICL_DPLL_CFGCR0(4));
- hw_state->cfgcr1 = intel_de_read(i915,
+ hw_state->cfgcr1 = intel_de_read(display,
ICL_DPLL_CFGCR1(4));
} else {
- hw_state->cfgcr0 = intel_de_read(i915,
+ hw_state->cfgcr0 = intel_de_read(display,
ICL_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = intel_de_read(i915,
+ hw_state->cfgcr1 = intel_de_read(display,
ICL_DPLL_CFGCR1(id));
}
}
@@ -3740,44 +3755,44 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *i915,
return ret;
}
-static bool combo_pll_get_hw_state(struct drm_i915_private *i915,
+static bool combo_pll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
+ i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
- return icl_pll_get_hw_state(i915, pll, dpll_hw_state, enable_reg);
+ return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);
}
-static bool tbt_pll_get_hw_state(struct drm_i915_private *i915,
+static bool tbt_pll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- return icl_pll_get_hw_state(i915, pll, dpll_hw_state, TBT_PLL_ENABLE);
+ return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
}
-static void icl_dpll_write(struct drm_i915_private *i915,
+static void icl_dpll_write(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct icl_dpll_hw_state *hw_state)
{
const enum intel_dpll_id id = pll->info->id;
i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG;
- if (IS_ALDERLAKE_S(i915)) {
+ if (display->platform.alderlake_s) {
cfgcr0_reg = ADLS_DPLL_CFGCR0(id);
cfgcr1_reg = ADLS_DPLL_CFGCR1(id);
- } else if (IS_DG1(i915)) {
+ } else if (display->platform.dg1) {
cfgcr0_reg = DG1_DPLL_CFGCR0(id);
cfgcr1_reg = DG1_DPLL_CFGCR1(id);
- } else if (IS_ROCKETLAKE(i915)) {
+ } else if (display->platform.rocketlake) {
cfgcr0_reg = RKL_DPLL_CFGCR0(id);
cfgcr1_reg = RKL_DPLL_CFGCR1(id);
- } else if (DISPLAY_VER(i915) >= 12) {
+ } else if (DISPLAY_VER(display) >= 12) {
cfgcr0_reg = TGL_DPLL_CFGCR0(id);
cfgcr1_reg = TGL_DPLL_CFGCR1(id);
div0_reg = TGL_DPLL0_DIV0(id);
} else {
- if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
+ if ((display->platform.jasperlake || display->platform.elkhartlake) &&
id == DPLL_ID_EHL_DPLL4) {
cfgcr0_reg = ICL_DPLL_CFGCR0(4);
cfgcr1_reg = ICL_DPLL_CFGCR1(4);
@@ -3787,18 +3802,18 @@ static void icl_dpll_write(struct drm_i915_private *i915,
}
}
- intel_de_write(i915, cfgcr0_reg, hw_state->cfgcr0);
- intel_de_write(i915, cfgcr1_reg, hw_state->cfgcr1);
- drm_WARN_ON_ONCE(&i915->drm, i915->display.vbt.override_afc_startup &&
+ intel_de_write(display, cfgcr0_reg, hw_state->cfgcr0);
+ intel_de_write(display, cfgcr1_reg, hw_state->cfgcr1);
+ drm_WARN_ON_ONCE(display->drm, display->vbt.override_afc_startup &&
!i915_mmio_reg_valid(div0_reg));
- if (i915->display.vbt.override_afc_startup &&
+ if (display->vbt.override_afc_startup &&
i915_mmio_reg_valid(div0_reg))
- intel_de_rmw(i915, div0_reg,
+ intel_de_rmw(display, div0_reg,
TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0);
- intel_de_posting_read(i915, cfgcr1_reg);
+ intel_de_posting_read(display, cfgcr1_reg);
}
-static void icl_mg_pll_write(struct drm_i915_private *i915,
+static void icl_mg_pll_write(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct icl_dpll_hw_state *hw_state)
{
@@ -3810,38 +3825,38 @@ static void icl_mg_pll_write(struct drm_i915_private *i915,
* during the calc/readout phase if the mask depends on some other HW
* state like refclk, see icl_calc_mg_pll_state().
*/
- intel_de_rmw(i915, MG_REFCLKIN_CTL(tc_port),
+ intel_de_rmw(display, MG_REFCLKIN_CTL(tc_port),
MG_REFCLKIN_CTL_OD_2_MUX_MASK, hw_state->mg_refclkin_ctl);
- intel_de_rmw(i915, MG_CLKTOP2_CORECLKCTL1(tc_port),
+ intel_de_rmw(display, MG_CLKTOP2_CORECLKCTL1(tc_port),
MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK,
hw_state->mg_clktop2_coreclkctl1);
- intel_de_rmw(i915, MG_CLKTOP2_HSCLKCTL(tc_port),
+ intel_de_rmw(display, MG_CLKTOP2_HSCLKCTL(tc_port),
MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK,
hw_state->mg_clktop2_hsclkctl);
- intel_de_write(i915, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
- intel_de_write(i915, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
- intel_de_write(i915, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
- intel_de_write(i915, MG_PLL_FRAC_LOCK(tc_port),
+ intel_de_write(display, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
+ intel_de_write(display, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
+ intel_de_write(display, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
+ intel_de_write(display, MG_PLL_FRAC_LOCK(tc_port),
hw_state->mg_pll_frac_lock);
- intel_de_write(i915, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
+ intel_de_write(display, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
- intel_de_rmw(i915, MG_PLL_BIAS(tc_port),
+ intel_de_rmw(display, MG_PLL_BIAS(tc_port),
hw_state->mg_pll_bias_mask, hw_state->mg_pll_bias);
- intel_de_rmw(i915, MG_PLL_TDC_COLDST_BIAS(tc_port),
+ intel_de_rmw(display, MG_PLL_TDC_COLDST_BIAS(tc_port),
hw_state->mg_pll_tdc_coldst_bias_mask,
hw_state->mg_pll_tdc_coldst_bias);
- intel_de_posting_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port));
+ intel_de_posting_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));
}
-static void dkl_pll_write(struct drm_i915_private *i915,
+static void dkl_pll_write(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct icl_dpll_hw_state *hw_state)
{
@@ -3853,90 +3868,90 @@ static void dkl_pll_write(struct drm_i915_private *i915,
* though on different building block
*/
/* All the registers are RMW */
- val = intel_dkl_phy_read(i915, DKL_REFCLKIN_CTL(tc_port));
+ val = intel_dkl_phy_read(display, DKL_REFCLKIN_CTL(tc_port));
val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
val |= hw_state->mg_refclkin_ctl;
- intel_dkl_phy_write(i915, DKL_REFCLKIN_CTL(tc_port), val);
+ intel_dkl_phy_write(display, DKL_REFCLKIN_CTL(tc_port), val);
- val = intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port));
+ val = intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));
val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
val |= hw_state->mg_clktop2_coreclkctl1;
- intel_dkl_phy_write(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
+ intel_dkl_phy_write(display, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
- val = intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port));
+ val = intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));
val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
val |= hw_state->mg_clktop2_hsclkctl;
- intel_dkl_phy_write(i915, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
+ intel_dkl_phy_write(display, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
val = DKL_PLL_DIV0_MASK;
- if (i915->display.vbt.override_afc_startup)
+ if (display->vbt.override_afc_startup)
val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
- intel_dkl_phy_rmw(i915, DKL_PLL_DIV0(tc_port), val,
+ intel_dkl_phy_rmw(display, DKL_PLL_DIV0(tc_port), val,
hw_state->mg_pll_div0);
- val = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port));
+ val = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));
val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK |
DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
val |= hw_state->mg_pll_div1;
- intel_dkl_phy_write(i915, DKL_PLL_DIV1(tc_port), val);
+ intel_dkl_phy_write(display, DKL_PLL_DIV1(tc_port), val);
- val = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port));
+ val = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));
val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
DKL_PLL_SSC_STEP_LEN_MASK |
DKL_PLL_SSC_STEP_NUM_MASK |
DKL_PLL_SSC_EN);
val |= hw_state->mg_pll_ssc;
- intel_dkl_phy_write(i915, DKL_PLL_SSC(tc_port), val);
+ intel_dkl_phy_write(display, DKL_PLL_SSC(tc_port), val);
- val = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port));
+ val = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));
val &= ~(DKL_PLL_BIAS_FRAC_EN_H |
DKL_PLL_BIAS_FBDIV_FRAC_MASK);
val |= hw_state->mg_pll_bias;
- intel_dkl_phy_write(i915, DKL_PLL_BIAS(tc_port), val);
+ intel_dkl_phy_write(display, DKL_PLL_BIAS(tc_port), val);
- val = intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
+ val = intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
val |= hw_state->mg_pll_tdc_coldst_bias;
- intel_dkl_phy_write(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
+ intel_dkl_phy_write(display, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
- intel_dkl_phy_posting_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
+ intel_dkl_phy_posting_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
}
-static void icl_pll_power_enable(struct drm_i915_private *i915,
+static void icl_pll_power_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
i915_reg_t enable_reg)
{
- intel_de_rmw(i915, enable_reg, 0, PLL_POWER_ENABLE);
+ intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);
/*
* The spec says we need to "wait" but it also says it should be
* immediate.
*/
- if (intel_de_wait_for_set(i915, enable_reg, PLL_POWER_STATE, 1))
- drm_err(&i915->drm, "PLL %d Power not enabled\n",
+ if (intel_de_wait_for_set(display, enable_reg, PLL_POWER_STATE, 1))
+ drm_err(display->drm, "PLL %d Power not enabled\n",
pll->info->id);
}
-static void icl_pll_enable(struct drm_i915_private *i915,
+static void icl_pll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
i915_reg_t enable_reg)
{
- intel_de_rmw(i915, enable_reg, 0, PLL_ENABLE);
+ intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
/* Timeout is actually 600us. */
- if (intel_de_wait_for_set(i915, enable_reg, PLL_LOCK, 1))
- drm_err(&i915->drm, "PLL %d not locked\n", pll->info->id);
+ if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 1))
+ drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
}
-static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll)
+static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_shared_dpll *pll)
{
u32 val;
- if (!(IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) ||
+ if (!(display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) ||
pll->info->id != DPLL_ID_ICL_DPLL0)
return;
/*
@@ -3950,22 +3965,22 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte
* Instead of the usual place for workarounds we apply this one here,
* since TRANS_CMTG_CHICKEN is only accessible while DPLL0 is enabled.
*/
- val = intel_de_read(i915, TRANS_CMTG_CHICKEN);
- val = intel_de_rmw(i915, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING);
- if (drm_WARN_ON(&i915->drm, val & ~DISABLE_DPT_CLK_GATING))
- drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
+ val = intel_de_read(display, TRANS_CMTG_CHICKEN);
+ val = intel_de_rmw(display, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING);
+ if (drm_WARN_ON(display->drm, val & ~DISABLE_DPT_CLK_GATING))
+ drm_dbg_kms(display->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
}
-static void combo_pll_enable(struct drm_i915_private *i915,
+static void combo_pll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
- i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
+ i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
- icl_pll_power_enable(i915, pll, enable_reg);
+ icl_pll_power_enable(display, pll, enable_reg);
- icl_dpll_write(i915, pll, hw_state);
+ icl_dpll_write(display, pll, hw_state);
/*
* DVFS pre sequence would be here, but in our driver the cdclk code
@@ -3973,22 +3988,22 @@ static void combo_pll_enable(struct drm_i915_private *i915,
* nothing here.
*/
- icl_pll_enable(i915, pll, enable_reg);
+ icl_pll_enable(display, pll, enable_reg);
- adlp_cmtg_clock_gating_wa(i915, pll);
+ adlp_cmtg_clock_gating_wa(display, pll);
/* DVFS post sequence would be here. See the comment above. */
}
-static void tbt_pll_enable(struct drm_i915_private *i915,
+static void tbt_pll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
- icl_pll_power_enable(i915, pll, TBT_PLL_ENABLE);
+ icl_pll_power_enable(display, pll, TBT_PLL_ENABLE);
- icl_dpll_write(i915, pll, hw_state);
+ icl_dpll_write(display, pll, hw_state);
/*
* DVFS pre sequence would be here, but in our driver the cdclk code
@@ -3996,24 +4011,24 @@ static void tbt_pll_enable(struct drm_i915_private *i915,
* nothing here.
*/
- icl_pll_enable(i915, pll, TBT_PLL_ENABLE);
+ icl_pll_enable(display, pll, TBT_PLL_ENABLE);
/* DVFS post sequence would be here. See the comment above. */
}
-static void mg_pll_enable(struct drm_i915_private *i915,
+static void mg_pll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
- i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
+ i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
- icl_pll_power_enable(i915, pll, enable_reg);
+ icl_pll_power_enable(display, pll, enable_reg);
- if (DISPLAY_VER(i915) >= 12)
- dkl_pll_write(i915, pll, hw_state);
+ if (DISPLAY_VER(display) >= 12)
+ dkl_pll_write(display, pll, hw_state);
else
- icl_mg_pll_write(i915, pll, hw_state);
+ icl_mg_pll_write(display, pll, hw_state);
/*
* DVFS pre sequence would be here, but in our driver the cdclk code
@@ -4021,12 +4036,12 @@ static void mg_pll_enable(struct drm_i915_private *i915,
* nothing here.
*/
- icl_pll_enable(i915, pll, enable_reg);
+ icl_pll_enable(display, pll, enable_reg);
/* DVFS post sequence would be here. See the comment above. */
}
-static void icl_pll_disable(struct drm_i915_private *i915,
+static void icl_pll_disable(struct intel_display *display,
struct intel_shared_dpll *pll,
i915_reg_t enable_reg)
{
@@ -4038,45 +4053,45 @@ static void icl_pll_disable(struct drm_i915_private *i915,
* nothing here.
*/
- intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0);
+ intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);
/* Timeout is actually 1us. */
- if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 1))
- drm_err(&i915->drm, "PLL %d locked\n", pll->info->id);
+ if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 1))
+ drm_err(display->drm, "PLL %d locked\n", pll->info->id);
/* DVFS post sequence would be here. See the comment above. */
- intel_de_rmw(i915, enable_reg, PLL_POWER_ENABLE, 0);
+ intel_de_rmw(display, enable_reg, PLL_POWER_ENABLE, 0);
/*
* The spec says we need to "wait" but it also says it should be
* immediate.
*/
- if (intel_de_wait_for_clear(i915, enable_reg, PLL_POWER_STATE, 1))
- drm_err(&i915->drm, "PLL %d Power not disabled\n",
+ if (intel_de_wait_for_clear(display, enable_reg, PLL_POWER_STATE, 1))
+ drm_err(display->drm, "PLL %d Power not disabled\n",
pll->info->id);
}
-static void combo_pll_disable(struct drm_i915_private *i915,
+static void combo_pll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
+ i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
- icl_pll_disable(i915, pll, enable_reg);
+ icl_pll_disable(display, pll, enable_reg);
}
-static void tbt_pll_disable(struct drm_i915_private *i915,
+static void tbt_pll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
- icl_pll_disable(i915, pll, TBT_PLL_ENABLE);
+ icl_pll_disable(display, pll, TBT_PLL_ENABLE);
}
-static void mg_pll_disable(struct drm_i915_private *i915,
+static void mg_pll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
+ i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
- icl_pll_disable(i915, pll, enable_reg);
+ icl_pll_disable(display, pll, enable_reg);
}
static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
@@ -4477,49 +4492,50 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
/**
* intel_dpll_get_freq - calculate the DPLL's output frequency
- * @i915: i915 device
+ * @display: intel_display device
* @pll: DPLL for which to calculate the output frequency
* @dpll_hw_state: DPLL state from which to calculate the output frequency
*
* Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
*/
-int intel_dpll_get_freq(struct drm_i915_private *i915,
+int intel_dpll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
- if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
+ if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
return 0;
- return pll->info->funcs->get_freq(i915, pll, dpll_hw_state);
+ return pll->info->funcs->get_freq(display, pll, dpll_hw_state);
}
/**
* intel_dpll_get_hw_state - readout the DPLL's hardware state
- * @i915: i915 device
+ * @display: intel_display device instance
* @pll: DPLL for which to calculate the output frequency
* @dpll_hw_state: DPLL's hardware state
*
* Read out @pll's hardware state into @dpll_hw_state.
*/
-bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
+bool intel_dpll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- return pll->info->funcs->get_hw_state(i915, pll, dpll_hw_state);
+ return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
}
-static void readout_dpll_hw_state(struct drm_i915_private *i915,
+static void readout_dpll_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_crtc *crtc;
- pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state);
+ pll->on = intel_dpll_get_hw_state(display, pll, &pll->state.hw_state);
if (pll->on && pll->info->power_domain)
pll->wakeref = intel_display_power_get(i915, pll->info->power_domain);
pll->state.pipe_mask = 0;
- for_each_intel_crtc(&i915->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
@@ -4528,7 +4544,7 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915,
}
pll->active_mask = pll->state.pipe_mask;
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"%s hw state readout: pipe_mask 0x%x, on %i\n",
pll->info->name, pll->state.pipe_mask, pll->on);
}
@@ -4539,42 +4555,40 @@ void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
i915->display.dpll.mgr->update_ref_clks(i915);
}
-void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
+void intel_dpll_readout_hw_state(struct intel_display *display)
{
- struct intel_display *display = to_intel_display(&i915->drm);
struct intel_shared_dpll *pll;
int i;
for_each_shared_dpll(display, pll, i)
- readout_dpll_hw_state(i915, pll);
+ readout_dpll_hw_state(display, pll);
}
-static void sanitize_dpll_state(struct drm_i915_private *i915,
+static void sanitize_dpll_state(struct intel_display *display,
struct intel_shared_dpll *pll)
{
if (!pll->on)
return;
- adlp_cmtg_clock_gating_wa(i915, pll);
+ adlp_cmtg_clock_gating_wa(display, pll);
if (pll->active_mask)
return;
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"%s enabled but not in use, disabling\n",
pll->info->name);
- _intel_disable_shared_dpll(i915, pll);
+ _intel_disable_shared_dpll(display, pll);
}
-void intel_dpll_sanitize_state(struct drm_i915_private *i915)
+void intel_dpll_sanitize_state(struct intel_display *display)
{
- struct intel_display *display = to_intel_display(&i915->drm);
struct intel_shared_dpll *pll;
int i;
for_each_shared_dpll(display, pll, i)
- sanitize_dpll_state(i915, pll);
+ sanitize_dpll_state(display, pll);
}
/**
@@ -4624,17 +4638,16 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
}
static void
-verify_single_dpll_state(struct drm_i915_private *i915,
+verify_single_dpll_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_crtc *crtc,
const struct intel_crtc_state *new_crtc_state)
{
- struct intel_display *display = &i915->display;
struct intel_dpll_hw_state dpll_hw_state = {};
u8 pipe_mask;
bool active;
- active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state);
+ active = intel_dpll_get_hw_state(display, pll, &dpll_hw_state);
if (!pll->info->always_on) {
INTEL_DISPLAY_STATE_WARN(display, !pll->on && pll->active_mask,
@@ -4690,14 +4703,13 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
if (new_crtc_state->shared_dpll)
- verify_single_dpll_state(i915, new_crtc_state->shared_dpll,
+ verify_single_dpll_state(display, new_crtc_state->shared_dpll,
crtc, new_crtc_state);
if (old_crtc_state->shared_dpll &&
@@ -4721,10 +4733,9 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_shared_dpll *pll;
int i;
for_each_shared_dpll(display, pll, i)
- verify_single_dpll_state(i915, pll, NULL, NULL);
+ verify_single_dpll_state(display, pll, NULL, NULL);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 42379494f347..ebd0ed79d2b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -390,7 +390,7 @@ struct intel_shared_dpll {
/* shared dpll functions */
struct intel_shared_dpll *
-intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
+intel_get_shared_dpll_by_id(struct intel_display *display,
enum intel_dpll_id id);
void assert_shared_dpll(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
@@ -413,10 +413,10 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
void intel_update_active_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
-int intel_dpll_get_freq(struct drm_i915_private *i915,
+int intel_dpll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
-bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
+bool intel_dpll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state);
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
@@ -424,8 +424,8 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
void intel_shared_dpll_init(struct drm_i915_private *i915);
void intel_dpll_update_ref_clks(struct drm_i915_private *i915);
-void intel_dpll_readout_hw_state(struct drm_i915_private *i915);
-void intel_dpll_sanitize_state(struct drm_i915_private *i915);
+void intel_dpll_readout_hw_state(struct intel_display *display);
+void intel_dpll_sanitize_state(struct intel_display *display);
void intel_dpll_dump_hw_state(struct intel_display *display,
struct drm_printer *p,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 10cdfdad82e4..4a6dd0d99e3e 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -795,7 +795,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
pipe_name(pipe));
}
- intel_dpll_readout_hw_state(i915);
+ intel_dpll_readout_hw_state(display);
drm_connector_list_iter_begin(&i915->drm, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
@@ -1014,7 +1014,7 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
intel_sanitize_all_crtcs(i915, ctx);
- intel_dpll_sanitize_state(i915);
+ intel_dpll_sanitize_state(display);
intel_wm_get_hw_state(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 8fa5a6334d10..e874a577b7d1 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -249,6 +249,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct intel_display *display = to_intel_display(crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
i915_reg_t reg;
@@ -263,7 +264,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
if (HAS_PCH_CPT(dev_priv)) {
reg = TRANS_CHICKEN2(pipe);
- val = intel_de_read(dev_priv, reg);
+ val = intel_de_read(display, reg);
/*
* Workaround: Set the timing override bit
* before enabling the pch transcoder.
@@ -272,12 +273,12 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
/* Configure frame start delay to match the CPU */
val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
- intel_de_write(dev_priv, reg, val);
+ intel_de_write(display, reg, val);
}
reg = PCH_TRANSCONF(pipe);
- val = intel_de_read(dev_priv, reg);
- pipeconf_val = intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe));
+ val = intel_de_read(display, reg);
+ pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe));
if (HAS_PCH_IBX(dev_priv)) {
/* Configure frame start delay to match the CPU */
@@ -307,9 +308,9 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
val |= TRANS_INTERLACE_PROGRESSIVE;
}
- intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
- if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
- drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
+ intel_de_write(display, reg, val | TRANS_ENABLE);
+ if (intel_de_wait_for_set(display, reg, TRANS_STATE_ENABLE, 100))
+ drm_err(display->drm, "failed to enable transcoder %c\n",
pipe_name(pipe));
}
@@ -383,15 +384,15 @@ void ilk_pch_enable(struct intel_atomic_state *state,
if (HAS_PCH_CPT(dev_priv)) {
u32 sel;
- temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
+ temp = intel_de_read(display, PCH_DPLL_SEL);
temp |= TRANS_DPLL_ENABLE(pipe);
sel = TRANS_DPLLB_SEL(pipe);
if (crtc_state->shared_dpll ==
- intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
+ intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
temp |= sel;
else
temp &= ~sel;
- intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
+ intel_de_write(display, PCH_DPLL_SEL, temp);
}
/*
@@ -420,11 +421,12 @@ void ilk_pch_enable(struct intel_atomic_state *state,
intel_crtc_has_dp_encoder(crtc_state)) {
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
- u32 bpc = (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) >> 5;
+ u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))
+ & TRANSCONF_BPC_MASK) >> 5;
i915_reg_t reg = TRANS_DP_CTL(pipe);
enum port port;
- temp = intel_de_read(dev_priv, reg);
+ temp = intel_de_read(display, reg);
temp &= ~(TRANS_DP_PORT_SEL_MASK |
TRANS_DP_VSYNC_ACTIVE_HIGH |
TRANS_DP_HSYNC_ACTIVE_HIGH |
@@ -438,10 +440,10 @@ void ilk_pch_enable(struct intel_atomic_state *state,
temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
port = intel_get_crtc_new_encoder(state, crtc_state)->port;
- drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D);
+ drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D);
temp |= TRANS_DP_PORT_SEL(port);
- intel_de_write(dev_priv, reg, temp);
+ intel_de_write(display, reg, temp);
}
ilk_enable_pch_transcoder(crtc_state);
@@ -496,6 +498,7 @@ static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct intel_display *display = to_intel_display(crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll;
enum pipe pipe = crtc->pipe;
@@ -503,12 +506,12 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
bool pll_active;
u32 tmp;
- if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
+ if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
return;
crtc_state->has_pch_encoder = true;
- tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
+ tmp = intel_de_read(display, FDI_RX_CTL(pipe));
crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
FDI_DP_PORT_WIDTH_SHIFT) + 1;
@@ -522,19 +525,19 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
*/
pll_id = (enum intel_dpll_id) pipe;
} else {
- tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
+ tmp = intel_de_read(display, PCH_DPLL_SEL);
if (tmp & TRANS_DPLLB_SEL(pipe))
pll_id = DPLL_ID_PCH_PLL_B;
else
pll_id = DPLL_ID_PCH_PLL_A;
}
- crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
+ crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id);
pll = crtc_state->shared_dpll;
- pll_active = intel_dpll_get_hw_state(dev_priv, pll,
+ pll_active = intel_dpll_get_hw_state(display, pll,
&crtc_state->dpll_hw_state);
- drm_WARN_ON(&dev_priv->drm, !pll_active);
+ drm_WARN_ON(display->drm, !pll_active);
tmp = crtc_state->dpll_hw_state.i9xx.dpll;
crtc_state->pixel_multiplier =
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 0/9] drm_i915_private to intel_display cleanup
@ 2025-02-11 10:48 Suraj Kandpal
2025-02-11 10:48 ` [PATCH 1/9] drm/i915/display_debug_fs: Use intel_display wherever possible Suraj Kandpal
` (13 more replies)
0 siblings, 14 replies; 29+ messages in thread
From: Suraj Kandpal @ 2025-02-11 10:48 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, jani.nikula, Suraj Kandpal
This series started as a cleanup to convert as many drm_i915_private
to intel_display in intel_display_debug_fs but overflowed and ended up
cleaning intel_dpll_mgr.c part of the code too and some other places
calling these functions. This series also replaces IS_PLATFORM()
with display->platform.xx to reduce drm_i915_private usage.
Some stuff that kept me from removing i915_private altogether were
PCH checks.
--v2
-Rebase
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Suraj Kandpal (9):
drm/i915/display_debug_fs: Use intel_display wherever possible
drm/i915/display_debug_fs: Prefer using display->platform
drm/i915/dpll: Change param to intel_display in for_each_shared_dpll
drm/i915/dpll: Use intel_display for dpll dump and compare hw state
drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks
drm/i915/dpll: Use intel_display for asserting pll
drm/i915/dpll: Use intel_display for update_refclk hook
drm/i915/dpll: Accept intel_display as argument for shared_dpll_init
drm/i915/dpll: Replace all other leftover drm_i915_private
.../drm/i915/display/intel_crtc_state_dump.c | 3 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 130 +--
drivers/gpu/drm/i915/display/intel_display.c | 30 +-
.../drm/i915/display/intel_display_debugfs.c | 173 +--
.../drm/i915/display/intel_display_driver.c | 4 +-
.../i915/display/intel_display_power_well.c | 13 +-
drivers/gpu/drm/i915/display/intel_dkl_phy.c | 54 +-
drivers/gpu/drm/i915/display/intel_dkl_phy.h | 9 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 11 +-
drivers/gpu/drm/i915/display/intel_dpll.h | 5 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1011 ++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 27 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 16 +-
drivers/gpu/drm/i915/display/intel_fdi.h | 7 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 7 +-
.../drm/i915/display/intel_modeset_setup.c | 4 +-
.../gpu/drm/i915/display/intel_pch_display.c | 45 +-
.../gpu/drm/i915/display/intel_pch_refclk.c | 36 +-
drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 12 +-
drivers/gpu/drm/i915/display/vlv_dsi_pll.h | 10 +-
20 files changed, 799 insertions(+), 808 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 1/9] drm/i915/display_debug_fs: Use intel_display wherever possible
2025-02-11 10:48 [PATCH 0/9] drm_i915_private to intel_display cleanup Suraj Kandpal
@ 2025-02-11 10:48 ` Suraj Kandpal
2025-02-11 12:51 ` Jani Nikula
2025-02-11 12:52 ` Jani Nikula
2025-02-11 10:48 ` [PATCH 2/9] drm/i915/display_debug_fs: Prefer using display->platform Suraj Kandpal
` (12 subsequent siblings)
13 siblings, 2 replies; 29+ messages in thread
From: Suraj Kandpal @ 2025-02-11 10:48 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, jani.nikula, Suraj Kandpal
Use struct intel_display wherever possible in intel_display_debug_fs.c
to reduce the use of drm_i915_private.
--v2
-Rebase
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 158 +++++++++---------
1 file changed, 81 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 89e5eea90be8..d85924caa26e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -68,17 +68,17 @@ static int intel_display_caps(struct seq_file *m, void *data)
static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_display *display = node_to_intel_display(m->private);
- spin_lock(&dev_priv->display.fb_tracking.lock);
+ spin_lock(&display->fb_tracking.lock);
seq_printf(m, "FB tracking busy bits: 0x%08x\n",
- dev_priv->display.fb_tracking.busy_bits);
+ display->fb_tracking.busy_bits);
seq_printf(m, "FB tracking flip bits: 0x%08x\n",
- dev_priv->display.fb_tracking.flip_bits);
+ display->fb_tracking.flip_bits);
- spin_unlock(&dev_priv->display.fb_tracking.lock);
+ spin_unlock(&display->fb_tracking.lock);
return 0;
}
@@ -86,25 +86,25 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
static int i915_sr_status(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct intel_display *display = &dev_priv->display;
+ struct intel_display *display = node_to_intel_display(m->private);
intel_wakeref_t wakeref;
bool sr_enabled = false;
wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);
- if (DISPLAY_VER(dev_priv) >= 9)
+ if (DISPLAY_VER(display) >= 9)
/* no global SR status; inspect per-plane WM */;
else if (HAS_PCH_SPLIT(dev_priv))
- sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM_LP_ENABLE;
+ sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;
else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
IS_I945G(dev_priv) || IS_I945GM(dev_priv))
- sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
+ sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
else if (IS_I915GM(dev_priv))
- sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN;
+ sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;
else if (IS_PINEVIEW(dev_priv))
- sr_enabled = intel_de_read(dev_priv, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
+ sr_enabled = intel_de_read(display, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
+ sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
@@ -115,12 +115,12 @@ static int i915_sr_status(struct seq_file *m, void *unused)
static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_display *display = node_to_intel_display(m->private);
struct intel_framebuffer *fbdev_fb = NULL;
struct drm_framebuffer *drm_fb;
#ifdef CONFIG_DRM_FBDEV_EMULATION
- fbdev_fb = intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev);
+ fbdev_fb = intel_fbdev_framebuffer(display->fbdev.fbdev);
if (fbdev_fb) {
seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
fbdev_fb->base.width,
@@ -134,8 +134,8 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
}
#endif
- mutex_lock(&dev_priv->drm.mode_config.fb_lock);
- drm_for_each_fb(drm_fb, &dev_priv->drm) {
+ mutex_lock(&display->drm->mode_config.fb_lock);
+ drm_for_each_fb(drm_fb, display->drm) {
struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
if (fb == fbdev_fb)
continue;
@@ -150,7 +150,7 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
intel_bo_describe(m, intel_fb_bo(&fb->base));
seq_putc(m, '\n');
}
- mutex_unlock(&dev_priv->drm.mode_config.fb_lock);
+ mutex_unlock(&display->drm->mode_config.fb_lock);
return 0;
}
@@ -179,14 +179,14 @@ static void intel_encoder_info(struct seq_file *m,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_display *display = node_to_intel_display(m->private);
struct drm_connector_list_iter conn_iter;
struct drm_connector *connector;
seq_printf(m, "\t[ENCODER:%d:%s]: connectors:\n",
encoder->base.base.id, encoder->base.name);
- drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
+ drm_connector_list_iter_begin(display->drm, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter) {
const struct drm_connector_state *conn_state =
connector->state;
@@ -391,10 +391,10 @@ static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane)
static void intel_plane_info(struct seq_file *m, struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_display *display = node_to_intel_display(m->private);
struct intel_plane *plane;
- for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+ for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
seq_printf(m, "\t[PLANE:%d:%s]: type=%s\n",
plane->base.base.id, plane->base.name,
plane_type(plane->base.type));
@@ -537,7 +537,7 @@ static void crtc_updates_add(struct intel_crtc *crtc)
static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_display *display = node_to_intel_display(m->private);
struct drm_printer p = drm_seq_file_printer(m);
const struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
@@ -571,7 +571,7 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
intel_vdsc_state_dump(&p, 1, crtc_state);
- for_each_intel_encoder_mask(&dev_priv->drm, encoder,
+ for_each_intel_encoder_mask(display->drm, encoder,
crtc_state->uapi.encoder_mask)
intel_encoder_info(m, crtc, encoder);
@@ -586,6 +586,7 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
static int i915_display_info(struct seq_file *m, void *unused)
{
+ struct intel_display *display = node_to_intel_display(m->private);
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_crtc *crtc;
struct drm_connector *connector;
@@ -594,22 +595,22 @@ static int i915_display_info(struct seq_file *m, void *unused)
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
- drm_modeset_lock_all(&dev_priv->drm);
+ drm_modeset_lock_all(display->drm);
seq_printf(m, "CRTC info\n");
seq_printf(m, "---------\n");
- for_each_intel_crtc(&dev_priv->drm, crtc)
+ for_each_intel_crtc(display->drm, crtc)
intel_crtc_info(m, crtc);
seq_printf(m, "\n");
seq_printf(m, "Connector info\n");
seq_printf(m, "--------------\n");
- drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
+ drm_connector_list_iter_begin(display->drm, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter)
intel_connector_info(m, connector);
drm_connector_list_iter_end(&conn_iter);
- drm_modeset_unlock_all(&dev_priv->drm);
+ drm_modeset_unlock_all(display->drm);
intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
@@ -618,11 +619,11 @@ static int i915_display_info(struct seq_file *m, void *unused)
static int i915_display_capabilities(struct seq_file *m, void *unused)
{
- struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_display *display = node_to_intel_display(m->private);
struct drm_printer p = drm_seq_file_printer(m);
- intel_display_device_info_print(DISPLAY_INFO(i915),
- DISPLAY_RUNTIME_INFO(i915), &p);
+ intel_display_device_info_print(DISPLAY_INFO(display),
+ DISPLAY_RUNTIME_INFO(display), &p);
return 0;
}
@@ -630,15 +631,16 @@ static int i915_display_capabilities(struct seq_file *m, void *unused)
static int i915_shared_dplls_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_display *display = node_to_intel_display(m->private);
struct drm_printer p = drm_seq_file_printer(m);
struct intel_shared_dpll *pll;
int i;
- drm_modeset_lock_all(&dev_priv->drm);
+ drm_modeset_lock_all(display->drm);
drm_printf(&p, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n",
- dev_priv->display.dpll.ref_clks.nssc,
- dev_priv->display.dpll.ref_clks.ssc);
+ display->dpll.ref_clks.nssc,
+ display->dpll.ref_clks.ssc);
for_each_shared_dpll(dev_priv, pll, i) {
drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,
@@ -649,25 +651,25 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
drm_printf(&p, " tracked hardware state:\n");
intel_dpll_dump_hw_state(dev_priv, &p, &pll->state.hw_state);
}
- drm_modeset_unlock_all(&dev_priv->drm);
+ drm_modeset_unlock_all(display->drm);
return 0;
}
static int i915_ddb_info(struct seq_file *m, void *unused)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_display *display = node_to_intel_display(m->private);
struct skl_ddb_entry *entry;
struct intel_crtc *crtc;
- if (DISPLAY_VER(dev_priv) < 9)
+ if (DISPLAY_VER(display) < 9)
return -ENODEV;
- drm_modeset_lock_all(&dev_priv->drm);
+ drm_modeset_lock_all(display->drm);
seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
enum pipe pipe = crtc->pipe;
@@ -687,16 +689,16 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
entry->end, skl_ddb_entry_size(entry));
}
- drm_modeset_unlock_all(&dev_priv->drm);
+ drm_modeset_unlock_all(display->drm);
return 0;
}
static bool
-intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
+intel_lpsp_power_well_enabled(struct intel_display *display,
enum i915_power_well_id power_well_id)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
intel_wakeref_t wakeref;
bool is_enabled;
@@ -710,15 +712,16 @@ intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
static int i915_lpsp_status(struct seq_file *m, void *unused)
{
+ struct intel_display *display = node_to_intel_display(m->private);
struct drm_i915_private *i915 = node_to_i915(m->private);
bool lpsp_enabled = false;
- if (DISPLAY_VER(i915) >= 13 || IS_DISPLAY_VER(i915, 9, 10)) {
- lpsp_enabled = !intel_lpsp_power_well_enabled(i915, SKL_DISP_PW_2);
- } else if (IS_DISPLAY_VER(i915, 11, 12)) {
- lpsp_enabled = !intel_lpsp_power_well_enabled(i915, ICL_DISP_PW_3);
+ if (DISPLAY_VER(display) >= 13 || IS_DISPLAY_VER(display, 9, 10)) {
+ lpsp_enabled = !intel_lpsp_power_well_enabled(display, SKL_DISP_PW_2);
+ } else if (IS_DISPLAY_VER(display, 11, 12)) {
+ lpsp_enabled = !intel_lpsp_power_well_enabled(display, ICL_DISP_PW_3);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
- lpsp_enabled = !intel_lpsp_power_well_enabled(i915, HSW_DISP_PW_GLOBAL);
+ lpsp_enabled = !intel_lpsp_power_well_enabled(display, HSW_DISP_PW_GLOBAL);
} else {
seq_puts(m, "LPSP: not supported\n");
return 0;
@@ -731,13 +734,13 @@ static int i915_lpsp_status(struct seq_file *m, void *unused)
static int i915_dp_mst_info(struct seq_file *m, void *unused)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_display *display = node_to_intel_display(m->private);
struct intel_encoder *intel_encoder;
struct intel_digital_port *dig_port;
struct drm_connector *connector;
struct drm_connector_list_iter conn_iter;
- drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
+ drm_connector_list_iter_begin(display->drm, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter) {
if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
continue;
@@ -765,7 +768,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
const char __user *ubuf,
size_t cnt, loff_t *ppos)
{
- struct drm_i915_private *dev_priv = filp->private_data;
+ struct intel_display *display = filp->private_data;
struct intel_crtc *crtc;
int ret;
bool reset;
@@ -777,7 +780,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
if (!reset)
return cnt;
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
struct drm_crtc_commit *commit;
struct intel_crtc_state *crtc_state;
@@ -794,7 +797,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
}
if (!ret && crtc_state->hw.active) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Re-arming FIFO underruns on pipe %c\n",
pipe_name(crtc->pipe));
@@ -807,7 +810,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
return ret;
}
- intel_fbc_reset_underrun(&dev_priv->display);
+ intel_fbc_reset_underrun(display);
return cnt;
}
@@ -839,7 +842,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
struct drm_minor *minor = i915->drm.primary;
debugfs_create_file("i915_fifo_underrun_reset", 0644, minor->debugfs_root,
- to_i915(minor->dev), &i915_fifo_underrun_reset_ops);
+ to_intel_display(minor->dev), &i915_fifo_underrun_reset_ops);
drm_debugfs_create_files(intel_display_debugfs_list,
ARRAY_SIZE(intel_display_debugfs_list),
@@ -860,8 +863,9 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
static int i915_lpsp_capability_show(struct seq_file *m, void *data)
{
struct intel_connector *connector = m->private;
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct intel_encoder *encoder = intel_attached_encoder(connector);
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
int connector_type = connector->base.connector_type;
bool lpsp_capable = false;
@@ -871,19 +875,19 @@ static int i915_lpsp_capability_show(struct seq_file *m, void *data)
if (connector->base.status != connector_status_connected)
return -ENODEV;
- if (DISPLAY_VER(i915) >= 13)
+ if (DISPLAY_VER(display) >= 13)
lpsp_capable = encoder->port <= PORT_B;
- else if (DISPLAY_VER(i915) >= 12)
+ else if (DISPLAY_VER(display) >= 12)
/*
* Actually TGL can drive LPSP on port till DDI_C
* but there is no physical connected DDI_C on TGL sku's,
* even driver is not initializing DDI_C port for gen12.
*/
lpsp_capable = encoder->port <= PORT_B;
- else if (DISPLAY_VER(i915) == 11)
+ else if (DISPLAY_VER(display) == 11)
lpsp_capable = (connector_type == DRM_MODE_CONNECTOR_DSI ||
connector_type == DRM_MODE_CONNECTOR_eDP);
- else if (IS_DISPLAY_VER(i915, 9, 10))
+ else if (IS_DISPLAY_VER(display, 9, 10))
lpsp_capable = (encoder->port == PORT_A &&
(connector_type == DRM_MODE_CONNECTOR_DSI ||
connector_type == DRM_MODE_CONNECTOR_eDP ||
@@ -900,7 +904,7 @@ DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability);
static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
{
struct intel_connector *connector = m->private;
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct drm_crtc *crtc;
struct intel_dp *intel_dp;
struct drm_modeset_acquire_ctx ctx;
@@ -912,7 +916,7 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
do {
try_again = false;
- ret = drm_modeset_lock(&i915->drm.mode_config.connection_mutex,
+ ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,
&ctx);
if (ret) {
if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) {
@@ -973,7 +977,7 @@ static ssize_t i915_dsc_fec_support_write(struct file *file,
{
struct seq_file *m = file->private_data;
struct intel_connector *connector = m->private;
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct intel_encoder *encoder = intel_attached_encoder(connector);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
bool dsc_enable = false;
@@ -982,14 +986,14 @@ static ssize_t i915_dsc_fec_support_write(struct file *file,
if (len == 0)
return 0;
- drm_dbg(&i915->drm,
+ drm_dbg(display->drm,
"Copied %zu bytes from user to force DSC\n", len);
ret = kstrtobool_from_user(ubuf, len, &dsc_enable);
if (ret < 0)
return ret;
- drm_dbg(&i915->drm, "Got %s for DSC Enable\n",
+ drm_dbg(display->drm, "Got %s for DSC Enable\n",
(dsc_enable) ? "true" : "false");
intel_dp->force_dsc_en = dsc_enable;
@@ -1016,7 +1020,7 @@ static const struct file_operations i915_dsc_fec_support_fops = {
static int i915_dsc_bpc_show(struct seq_file *m, void *data)
{
struct intel_connector *connector = m->private;
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct intel_encoder *encoder = intel_attached_encoder(connector);
struct drm_crtc *crtc;
struct intel_crtc_state *crtc_state;
@@ -1025,7 +1029,7 @@ static int i915_dsc_bpc_show(struct seq_file *m, void *data)
if (!encoder)
return -ENODEV;
- ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
+ ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
if (ret)
return ret;
@@ -1038,7 +1042,7 @@ static int i915_dsc_bpc_show(struct seq_file *m, void *data)
crtc_state = to_intel_crtc_state(crtc->state);
seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component);
-out: drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
+out: drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
return ret;
}
@@ -1082,7 +1086,7 @@ static const struct file_operations i915_dsc_bpc_fops = {
static int i915_dsc_output_format_show(struct seq_file *m, void *data)
{
struct intel_connector *connector = m->private;
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct intel_encoder *encoder = intel_attached_encoder(connector);
struct drm_crtc *crtc;
struct intel_crtc_state *crtc_state;
@@ -1091,7 +1095,7 @@ static int i915_dsc_output_format_show(struct seq_file *m, void *data)
if (!encoder)
return -ENODEV;
- ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
+ ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
if (ret)
return ret;
@@ -1105,7 +1109,7 @@ static int i915_dsc_output_format_show(struct seq_file *m, void *data)
seq_printf(m, "DSC_Output_Format: %s\n",
intel_output_format_name(crtc_state->output_format));
-out: drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
+out: drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
return ret;
}
@@ -1149,7 +1153,7 @@ static const struct file_operations i915_dsc_output_format_fops = {
static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
{
struct intel_connector *connector = m->private;
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct intel_encoder *encoder = intel_attached_encoder(connector);
struct drm_crtc *crtc;
struct intel_dp *intel_dp;
@@ -1158,7 +1162,7 @@ static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
if (!encoder)
return -ENODEV;
- ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
+ ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
if (ret)
return ret;
@@ -1173,7 +1177,7 @@ static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
out:
- drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
+ drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
return ret;
}
@@ -1184,8 +1188,8 @@ static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
{
struct seq_file *m = file->private_data;
struct intel_connector *connector = m->private;
+ struct intel_display *display = to_intel_display(connector);
struct intel_encoder *encoder = intel_attached_encoder(connector);
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
bool dsc_fractional_bpp_enable = false;
int ret;
@@ -1193,14 +1197,14 @@ static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
if (len == 0)
return 0;
- drm_dbg(&i915->drm,
+ drm_dbg(display->drm,
"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
if (ret < 0)
return ret;
- drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
+ drm_dbg(display->drm, "Got %s for DSC Fractional BPP Enable\n",
(dsc_fractional_bpp_enable) ? "true" : "false");
intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
@@ -1329,7 +1333,7 @@ static const struct file_operations i915_joiner_fops = {
*/
void intel_connector_debugfs_add(struct intel_connector *connector)
{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct dentry *root = connector->base.debugfs_entry;
int connector_type = connector->base.connector_type;
@@ -1344,7 +1348,7 @@ void intel_connector_debugfs_add(struct intel_connector *connector)
intel_alpm_lobf_debugfs_add(connector);
intel_dp_link_training_debugfs_add(connector);
- if (DISPLAY_VER(i915) >= 11 &&
+ if (DISPLAY_VER(display) >= 11 &&
((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !connector->mst_port) ||
connector_type == DRM_MODE_CONNECTOR_eDP)) {
debugfs_create_file("i915_dsc_fec_support", 0644, root,
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 2/9] drm/i915/display_debug_fs: Prefer using display->platform
2025-02-11 10:48 [PATCH 0/9] drm_i915_private to intel_display cleanup Suraj Kandpal
2025-02-11 10:48 ` [PATCH 1/9] drm/i915/display_debug_fs: Use intel_display wherever possible Suraj Kandpal
@ 2025-02-11 10:48 ` Suraj Kandpal
2025-02-11 12:53 ` Jani Nikula
2025-02-11 10:48 ` [PATCH 3/9] drm/i915/dpll: Change param to intel_display in for_each_shared_dpll Suraj Kandpal
` (11 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Suraj Kandpal @ 2025-02-11 10:48 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, jani.nikula, Suraj Kandpal
Prefer using display->platform.xx instead of IS_PLATFORM() checks
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index d85924caa26e..991c1726f522 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -96,14 +96,14 @@ static int i915_sr_status(struct seq_file *m, void *unused)
/* no global SR status; inspect per-plane WM */;
else if (HAS_PCH_SPLIT(dev_priv))
sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;
- else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
- IS_I945G(dev_priv) || IS_I945GM(dev_priv))
+ else if (display->platform.i965gm || display->platform.g4x ||
+ display->platform.i945g || display->platform.i945gm)
sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
- else if (IS_I915GM(dev_priv))
+ else if (display->platform.i915gm)
sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;
- else if (IS_PINEVIEW(dev_priv))
+ else if (display->platform.pineview)
sr_enabled = intel_de_read(display, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
- else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ else if (display->platform.valleyview || display->platform.cherryview)
sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 3/9] drm/i915/dpll: Change param to intel_display in for_each_shared_dpll
2025-02-11 10:48 [PATCH 0/9] drm_i915_private to intel_display cleanup Suraj Kandpal
2025-02-11 10:48 ` [PATCH 1/9] drm/i915/display_debug_fs: Use intel_display wherever possible Suraj Kandpal
2025-02-11 10:48 ` [PATCH 2/9] drm/i915/display_debug_fs: Prefer using display->platform Suraj Kandpal
@ 2025-02-11 10:48 ` Suraj Kandpal
2025-02-11 12:56 ` Jani Nikula
2025-02-11 10:48 ` [PATCH 4/9] drm/i915/dpll: Use intel_display for dpll dump and compare hw state Suraj Kandpal
` (10 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Suraj Kandpal @ 2025-02-11 10:48 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, jani.nikula, Suraj Kandpal
Change the argument of for_each_shared_dpll to take intel_display which
helps move as an ongoing effort to get rid off the dependency on
drm_i915_private. Some opportunistic changes in intel_pch_refclk done
too.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 ++++++++-----
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 6 ++--
.../gpu/drm/i915/display/intel_pch_refclk.c | 36 +++++++++----------
4 files changed, 37 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 991c1726f522..87e6f4000101 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -642,7 +642,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
display->dpll.ref_clks.nssc,
display->dpll.ref_clks.ssc);
- for_each_shared_dpll(dev_priv, pll, i) {
+ for_each_shared_dpll(display, pll, i) {
drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,
pll->info->name, pll->info->id);
drm_printf(&p, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index cb2ef317d219..171d16e91c61 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -121,10 +121,11 @@ intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915,
struct intel_shared_dpll_state *shared_dpll)
{
struct intel_shared_dpll *pll;
+ struct intel_display *display = to_intel_display(&i915->drm);
int i;
/* Copy shared dpll state */
- for_each_shared_dpll(i915, pll, i)
+ for_each_shared_dpll(display, pll, i)
shared_dpll[pll->index] = pll->state;
}
@@ -157,10 +158,11 @@ struct intel_shared_dpll *
intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
enum intel_dpll_id id)
{
+ struct intel_display *display = to_intel_display(&i915->drm);
struct intel_shared_dpll *pll;
int i;
- for_each_shared_dpll(i915, pll, i) {
+ for_each_shared_dpll(display, pll, i) {
if (pll->info->id == id)
return pll;
}
@@ -344,12 +346,13 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
static unsigned long
intel_dpll_mask_all(struct drm_i915_private *i915)
{
+ struct intel_display *display = to_intel_display(&i915->drm);
struct intel_shared_dpll *pll;
unsigned long dpll_mask = 0;
int i;
- for_each_shared_dpll(i915, pll, i) {
- drm_WARN_ON(&i915->drm, dpll_mask & BIT(pll->info->id));
+ for_each_shared_dpll(display, pll, i) {
+ drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id));
dpll_mask |= BIT(pll->info->id);
}
@@ -513,7 +516,7 @@ static void intel_put_dpll(struct intel_atomic_state *state,
*/
void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
struct intel_shared_dpll *pll;
int i;
@@ -521,7 +524,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
if (!state->dpll_set)
return;
- for_each_shared_dpll(i915, pll, i)
+ for_each_shared_dpll(display, pll, i)
swap(pll->state, shared_dpll[pll->index]);
}
@@ -4551,10 +4554,11 @@ void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
{
+ struct intel_display *display = to_intel_display(&i915->drm);
struct intel_shared_dpll *pll;
int i;
- for_each_shared_dpll(i915, pll, i)
+ for_each_shared_dpll(display, pll, i)
readout_dpll_hw_state(i915, pll);
}
@@ -4578,10 +4582,11 @@ static void sanitize_dpll_state(struct drm_i915_private *i915,
void intel_dpll_sanitize_state(struct drm_i915_private *i915)
{
+ struct intel_display *display = to_intel_display(&i915->drm);
struct intel_shared_dpll *pll;
int i;
- for_each_shared_dpll(i915, pll, i)
+ for_each_shared_dpll(display, pll, i)
sanitize_dpll_state(i915, pll);
}
@@ -4728,10 +4733,11 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_shared_dpll *pll;
int i;
- for_each_shared_dpll(i915, pll, i)
+ for_each_shared_dpll(display, pll, i)
verify_single_dpll_state(i915, pll, NULL, NULL);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 3eee76874304..382bdf8f0b65 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -30,9 +30,9 @@
#include "intel_display_power.h"
#include "intel_wakeref.h"
-#define for_each_shared_dpll(__i915, __pll, __i) \
- for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \
- ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++)
+#define for_each_shared_dpll(__display, __pll, __i) \
+ for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
+ ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
enum tc_port;
struct drm_i915_private;
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 71471c1d7dc9..68e953d2b124 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -492,7 +492,7 @@ static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
{
- struct intel_display *display = &dev_priv->display;
+ struct intel_display *display = to_intel_display(&dev_priv->drm);
struct intel_encoder *encoder;
struct intel_shared_dpll *pll;
int i;
@@ -505,7 +505,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
bool using_ssc_source = false;
/* We need to take the global config into account */
- for_each_intel_encoder(&dev_priv->drm, encoder) {
+ for_each_intel_encoder(display->drm, encoder) {
switch (encoder->type) {
case INTEL_OUTPUT_LVDS:
has_panel = true;
@@ -522,7 +522,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
}
if (HAS_PCH_IBX(dev_priv)) {
- has_ck505 = dev_priv->display.vbt.display_clock_mode;
+ has_ck505 = display->vbt.display_clock_mode;
can_ssc = has_ck505;
} else {
has_ck505 = false;
@@ -530,10 +530,10 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
}
/* Check if any DPLLs are using the SSC source */
- for_each_shared_dpll(dev_priv, pll, i) {
+ for_each_shared_dpll(display, pll, i) {
u32 temp;
- temp = intel_de_read(dev_priv, PCH_DPLL(pll->info->id));
+ temp = intel_de_read(display, PCH_DPLL(pll->info->id));
if (!(temp & DPLL_VCO_ENABLE))
continue;
@@ -545,7 +545,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
}
}
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
has_panel, has_lvds, has_ck505, using_ssc_source);
@@ -554,7 +554,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
* PCH B stepping, previous chipset stepping should be
* ignoring this setting.
*/
- val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
+ val = intel_de_read(display, PCH_DREF_CONTROL);
/* As we must carefully and slowly disable/enable each source in turn,
* compute the final state we want first and check if we need to
@@ -614,8 +614,8 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
}
/* Get SSC going before enabling the outputs */
- intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
- intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
+ intel_de_write(display, PCH_DREF_CONTROL, val);
+ intel_de_posting_read(display, PCH_DREF_CONTROL);
udelay(200);
val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
@@ -633,23 +633,23 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
}
- intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
- intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
+ intel_de_write(display, PCH_DREF_CONTROL, val);
+ intel_de_posting_read(display, PCH_DREF_CONTROL);
udelay(200);
} else {
- drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
+ drm_dbg_kms(display->drm, "Disabling CPU source output\n");
val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
/* Turn off CPU output */
val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
- intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
- intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
+ intel_de_write(display, PCH_DREF_CONTROL, val);
+ intel_de_posting_read(display, PCH_DREF_CONTROL);
udelay(200);
if (!using_ssc_source) {
- drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
+ drm_dbg_kms(display->drm, "Disabling SSC source\n");
/* Turn off the SSC source */
val &= ~DREF_SSC_SOURCE_MASK;
@@ -658,13 +658,13 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
/* Turn off SSC1 */
val &= ~DREF_SSC1_ENABLE;
- intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
- intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
+ intel_de_write(display, PCH_DREF_CONTROL, val);
+ intel_de_posting_read(display, PCH_DREF_CONTROL);
udelay(200);
}
}
- drm_WARN_ON(&dev_priv->drm, val != final);
+ drm_WARN_ON(display->drm, val != final);
}
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 4/9] drm/i915/dpll: Use intel_display for dpll dump and compare hw state
2025-02-11 10:48 [PATCH 0/9] drm_i915_private to intel_display cleanup Suraj Kandpal
` (2 preceding siblings ...)
2025-02-11 10:48 ` [PATCH 3/9] drm/i915/dpll: Change param to intel_display in for_each_shared_dpll Suraj Kandpal
@ 2025-02-11 10:48 ` Suraj Kandpal
2025-02-11 12:59 ` Jani Nikula
2025-02-11 10:48 ` [PATCH 5/9] drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks Suraj Kandpal
` (9 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Suraj Kandpal @ 2025-02-11 10:48 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, jani.nikula, Suraj Kandpal
Lets use intel_display for dpll dump and compare hw state. This also
helps elimanate drm_i915_private dependency from i915_shared_dplls_info
in display_debug_fs.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../gpu/drm/i915/display/intel_crtc_state_dump.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display.c | 8 ++++----
.../gpu/drm/i915/display/intel_display_debugfs.c | 3 +--
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 ++++++++--------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++--
5 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index ecd0d9853c60..599ddce96371 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -176,6 +176,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state,
const char *context)
{
+ struct intel_display *display = to_intel_display(pipe_config);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
const struct intel_plane_state *plane_state;
@@ -340,7 +341,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
pipe_config->ips_enabled, pipe_config->double_wide,
pipe_config->has_drrs);
- intel_dpll_dump_hw_state(i915, &p, &pipe_config->dpll_hw_state);
+ intel_dpll_dump_hw_state(display, &p, &pipe_config->dpll_hw_state);
if (IS_CHERRYVIEW(i915))
drm_printf(&p, "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9f8a8c94cf4c..5f4b1d8eed3e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5348,14 +5348,14 @@ pipe_config_pll_mismatch(struct drm_printer *p, bool fastset,
const struct intel_dpll_hw_state *a,
const struct intel_dpll_hw_state *b)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */
drm_printf(p, "expected:\n");
- intel_dpll_dump_hw_state(i915, p, a);
+ intel_dpll_dump_hw_state(display, p, a);
drm_printf(p, "found:\n");
- intel_dpll_dump_hw_state(i915, p, b);
+ intel_dpll_dump_hw_state(display, p, b);
}
static void
@@ -5495,7 +5495,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
} while (0)
#define PIPE_CONF_CHECK_PLL(name) do { \
- if (!intel_dpll_compare_hw_state(dev_priv, ¤t_config->name, \
+ if (!intel_dpll_compare_hw_state(display, ¤t_config->name, \
&pipe_config->name)) { \
pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \
¤t_config->name, \
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 87e6f4000101..970b8078db8b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -630,7 +630,6 @@ static int i915_display_capabilities(struct seq_file *m, void *unused)
static int i915_shared_dplls_info(struct seq_file *m, void *unused)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_display *display = node_to_intel_display(m->private);
struct drm_printer p = drm_seq_file_printer(m);
struct intel_shared_dpll *pll;
@@ -649,7 +648,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
pll->state.pipe_mask, pll->active_mask,
str_yes_no(pll->on));
drm_printf(&p, " tracked hardware state:\n");
- intel_dpll_dump_hw_state(dev_priv, &p, &pll->state.hw_state);
+ intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state);
}
drm_modeset_unlock_all(display->drm);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 171d16e91c61..ee4e263ce999 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4592,18 +4592,18 @@ void intel_dpll_sanitize_state(struct drm_i915_private *i915)
/**
* intel_dpll_dump_hw_state - dump hw_state
- * @i915: i915 drm device
+ * @display: intel_display structure
* @p: where to print the state to
* @dpll_hw_state: hw state to be dumped
*
* Dumo out the relevant values in @dpll_hw_state.
*/
-void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
+void intel_dpll_dump_hw_state(struct intel_display *display,
struct drm_printer *p,
const struct intel_dpll_hw_state *dpll_hw_state)
{
- if (i915->display.dpll.mgr) {
- i915->display.dpll.mgr->dump_hw_state(p, dpll_hw_state);
+ if (display->dpll.mgr) {
+ display->dpll.mgr->dump_hw_state(p, dpll_hw_state);
} else {
/* fallback for platforms that don't use the shared dpll
* infrastructure
@@ -4614,7 +4614,7 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
/**
* intel_dpll_compare_hw_state - compare the two states
- * @i915: i915 drm device
+ * @display: intel_display structure
* @a: first DPLL hw state
* @b: second DPLL hw state
*
@@ -4622,12 +4622,12 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
*
* Returns: true if the states are equal, false if the differ
*/
-bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,
+bool intel_dpll_compare_hw_state(struct intel_display *display,
const struct intel_dpll_hw_state *a,
const struct intel_dpll_hw_state *b)
{
- if (i915->display.dpll.mgr) {
- return i915->display.dpll.mgr->compare_hw_state(a, b);
+ if (display->dpll.mgr) {
+ return display->dpll.mgr->compare_hw_state(a, b);
} else {
/* fallback for platforms that don't use the shared dpll
* infrastructure
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 382bdf8f0b65..42379494f347 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -427,10 +427,10 @@ void intel_dpll_update_ref_clks(struct drm_i915_private *i915);
void intel_dpll_readout_hw_state(struct drm_i915_private *i915);
void intel_dpll_sanitize_state(struct drm_i915_private *i915);
-void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
+void intel_dpll_dump_hw_state(struct intel_display *display,
struct drm_printer *p,
const struct intel_dpll_hw_state *dpll_hw_state);
-bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,
+bool intel_dpll_compare_hw_state(struct intel_display *display,
const struct intel_dpll_hw_state *a,
const struct intel_dpll_hw_state *b);
enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 5/9] drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks
2025-02-11 10:48 [PATCH 0/9] drm_i915_private to intel_display cleanup Suraj Kandpal
` (3 preceding siblings ...)
2025-02-11 10:48 ` [PATCH 4/9] drm/i915/dpll: Use intel_display for dpll dump and compare hw state Suraj Kandpal
@ 2025-02-11 10:48 ` Suraj Kandpal
2025-02-11 13:10 ` Jani Nikula
2025-02-11 10:48 ` [PATCH 6/9] drm/i915/dpll: Use intel_display for asserting pll Suraj Kandpal
` (8 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Suraj Kandpal @ 2025-02-11 10:48 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, jani.nikula, Suraj Kandpal
We use intel_display for function hooks of shared_dpll_mgr and
any function that gets called when we use for_each_shared_dpll.
This also contains some opportunistic display->platform.xx changes
all to reductate the use of drm_i915_private.
--v2
-rebase
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 130 +--
.../i915/display/intel_display_power_well.c | 3 +-
drivers/gpu/drm/i915/display/intel_dkl_phy.c | 54 +-
drivers/gpu/drm/i915/display/intel_dkl_phy.h | 9 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 794 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 10 +-
.../drm/i915/display/intel_modeset_setup.c | 4 +-
.../gpu/drm/i915/display/intel_pch_display.c | 43 +-
8 files changed, 517 insertions(+), 530 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6e09dfcbaa7d..bb7abcb9e633 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -358,10 +358,10 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
}
}
-static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
+static int icl_calc_tbt_pll_link(struct intel_display *display,
enum port port)
{
- u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
+ u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
switch (val) {
case DDI_CLK_SEL_NONE:
@@ -1367,7 +1367,7 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum tc_port tc_port = intel_encoder_to_tc(encoder);
const struct intel_ddi_buf_trans *trans;
int n_entries, ln;
@@ -1376,17 +1376,17 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
return;
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
- if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
+ if (drm_WARN_ON_ONCE(display->drm, !trans))
return;
for (ln = 0; ln < 2; ln++) {
int level;
- intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
+ intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
- intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
+ intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln),
DKL_TX_PRESHOOT_COEFF_MASK |
DKL_TX_DE_EMPAHSIS_COEFF_MASK |
DKL_TX_VSWING_CONTROL_MASK,
@@ -1396,7 +1396,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
- intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
+ intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln),
DKL_TX_PRESHOOT_COEFF_MASK |
DKL_TX_DE_EMPAHSIS_COEFF_MASK |
DKL_TX_VSWING_CONTROL_MASK,
@@ -1404,10 +1404,10 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
- intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
+ intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
DKL_TX_DP20BITMODE, 0);
- if (IS_ALDERLAKE_P(dev_priv)) {
+ if (display->platform.alderlake_p) {
u32 val;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
@@ -1423,7 +1423,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
}
- intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
+ intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
val);
@@ -1551,14 +1551,14 @@ static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t
}
static struct intel_shared_dpll *
-_icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
+_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
u32 clk_sel_mask, u32 clk_sel_shift)
{
enum intel_dpll_id id;
- id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
+ id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
- return intel_get_shared_dpll_by_id(i915, id);
+ return intel_get_shared_dpll_by_id(display, id);
}
static void adls_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1597,10 +1597,10 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
- return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
+ return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy),
ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
}
@@ -1641,10 +1641,10 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
- return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
+ return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
}
@@ -1694,12 +1694,12 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
enum intel_dpll_id id;
u32 val;
- val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
+ val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy));
val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
id = val;
@@ -1712,7 +1712,7 @@ static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
if (phy >= PHY_C)
id += DPLL_ID_DG1_DPLL2;
- return intel_get_shared_dpll_by_id(i915, id);
+ return intel_get_shared_dpll_by_id(display, id);
}
static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
@@ -1751,10 +1751,10 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
- return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
+ return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
}
@@ -1859,13 +1859,13 @@ static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum tc_port tc_port = intel_encoder_to_tc(encoder);
enum port port = encoder->port;
enum intel_dpll_id id;
u32 tmp;
- tmp = intel_de_read(i915, DDI_CLK_SEL(port));
+ tmp = intel_de_read(display, DDI_CLK_SEL(port));
switch (tmp & DDI_CLK_SEL_MASK) {
case DDI_CLK_SEL_TBT_162:
@@ -1884,12 +1884,12 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode
return NULL;
}
- return intel_get_shared_dpll_by_id(i915, id);
+ return intel_get_shared_dpll_by_id(display, id);
}
static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder->base.dev);
enum intel_dpll_id id;
switch (encoder->port) {
@@ -1907,7 +1907,7 @@ static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
return NULL;
}
- return intel_get_shared_dpll_by_id(i915, id);
+ return intel_get_shared_dpll_by_id(display, id);
}
static void skl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1958,12 +1958,12 @@ static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum intel_dpll_id id;
u32 tmp;
- tmp = intel_de_read(i915, DPLL_CTRL2);
+ tmp = intel_de_read(display, DPLL_CTRL2);
/*
* FIXME Not sure if the override affects both
@@ -1975,7 +1975,7 @@ static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
- return intel_get_shared_dpll_by_id(i915, id);
+ return intel_get_shared_dpll_by_id(display, id);
}
void hsw_ddi_enable_clock(struct intel_encoder *encoder,
@@ -2009,12 +2009,12 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum intel_dpll_id id;
u32 tmp;
- tmp = intel_de_read(i915, PORT_CLK_SEL(port));
+ tmp = intel_de_read(display, PORT_CLK_SEL(port));
switch (tmp & PORT_CLK_SEL_MASK) {
case PORT_CLK_SEL_WRPLL1:
@@ -2042,7 +2042,7 @@ static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
return NULL;
}
- return intel_get_shared_dpll_by_id(i915, id);
+ return intel_get_shared_dpll_by_id(display, id);
}
void intel_ddi_enable_clock(struct intel_encoder *encoder,
@@ -2122,13 +2122,13 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
}
static void
-tgl_dkl_phy_check_and_rewrite(struct drm_i915_private *dev_priv,
+tgl_dkl_phy_check_and_rewrite(struct intel_display *display,
enum tc_port tc_port, u32 ln0, u32 ln1)
{
- if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
- intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
- if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
- intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+ if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)))
+ intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);
+ if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)))
+ intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);
}
static void
@@ -2136,24 +2136,23 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
u32 ln0, ln1, pin_assignment;
u8 width;
- if (DISPLAY_VER(dev_priv) >= 14)
+ if (DISPLAY_VER(display) >= 14)
return;
if (!intel_encoder_is_tc(&dig_port->base) ||
intel_tc_port_in_tbt_alt_mode(dig_port))
return;
- if (DISPLAY_VER(dev_priv) >= 12) {
- ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0));
- ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1));
+ if (DISPLAY_VER(display) >= 12) {
+ ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0));
+ ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1));
} else {
- ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
- ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
+ ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port));
+ ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port));
}
ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
@@ -2165,7 +2164,7 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
switch (pin_assignment) {
case 0x0:
- drm_WARN_ON(&dev_priv->drm,
+ drm_WARN_ON(display->drm,
!intel_tc_port_in_legacy_mode(dig_port));
if (width == 1) {
ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
@@ -2210,16 +2209,16 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
MISSING_CASE(pin_assignment);
}
- if (DISPLAY_VER(dev_priv) >= 12) {
- intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
- intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+ if (DISPLAY_VER(display) >= 12) {
+ intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);
+ intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);
/* WA_14018221282 */
if (IS_DISPLAY_VER(display, 12, 13))
- tgl_dkl_phy_check_and_rewrite(dev_priv, tc_port, ln0, ln1);
+ tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1);
} else {
- intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
- intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
+ intel_de_write(display, MG_DP_MODE(0, tc_port), ln0);
+ intel_de_write(display, MG_DP_MODE(1, tc_port), ln1);
}
}
@@ -3731,12 +3730,13 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum tc_port tc_port = intel_encoder_to_tc(encoder);
int ln;
for (ln = 0; ln < 2; ln++)
- intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0);
+ intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln),
+ DKL_PCS_DW5_CORE_SOFTRESET, 0);
}
static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
@@ -4257,21 +4257,21 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct intel_shared_dpll *pll)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
bool pll_active;
- if (drm_WARN_ON(&i915->drm, !pll))
+ if (drm_WARN_ON(display->drm, !pll))
return;
port_dpll->pll = pll;
- pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
- drm_WARN_ON(&i915->drm, !pll_active);
+ pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
+ drm_WARN_ON(display->drm, !pll_active);
icl_set_active_port_dpll(crtc_state, port_dpll_id);
- crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
+ crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
&crtc_state->dpll_hw_state);
}
@@ -4360,12 +4360,12 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct intel_shared_dpll *pll)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum icl_port_dpll_id port_dpll_id;
struct icl_port_dpll *port_dpll;
bool pll_active;
- if (drm_WARN_ON(&i915->drm, !pll))
+ if (drm_WARN_ON(display->drm, !pll))
return;
if (icl_ddi_tc_pll_is_tbt(pll))
@@ -4376,15 +4376,15 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
port_dpll->pll = pll;
- pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
- drm_WARN_ON(&i915->drm, !pll_active);
+ pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
+ drm_WARN_ON(display->drm, !pll_active);
icl_set_active_port_dpll(crtc_state, port_dpll_id);
if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
- crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
+ crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
else
- crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
+ crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
&crtc_state->dpll_hw_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index f45a4f9ba23c..a31d1678dfc0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -507,7 +507,6 @@ static void
icl_tc_phy_aux_power_well_enable(struct intel_display *display,
struct i915_power_well *power_well)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
@@ -539,7 +538,7 @@ icl_tc_phy_aux_power_well_enable(struct intel_display *display,
tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx);
- if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) &
+ if (wait_for(intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)) &
DKL_CMN_UC_DW27_UC_HEALTH, 1))
drm_warn(display->drm,
"Timeout waiting TC uC health\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c b/drivers/gpu/drm/i915/display/intel_dkl_phy.c
index b146b4c46943..0920f78f182e 100644
--- a/drivers/gpu/drm/i915/display/intel_dkl_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c
@@ -20,20 +20,20 @@ void intel_dkl_phy_init(struct drm_i915_private *i915)
}
static void
-dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
+dkl_phy_set_hip_idx(struct intel_display *display, struct intel_dkl_phy_reg reg)
{
enum tc_port tc_port = DKL_REG_TC_PORT(reg);
- drm_WARN_ON(&i915->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS);
+ drm_WARN_ON(display->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS);
- intel_de_write(i915,
+ intel_de_write(display,
HIP_INDEX_REG(tc_port),
HIP_INDEX_VAL(tc_port, reg.bank_idx));
}
/**
* intel_dkl_phy_read - read a Dekel PHY register
- * @i915: i915 device instance
+ * @display: intel_display device instance
* @reg: Dekel PHY register
*
* Read the @reg Dekel PHY register.
@@ -41,42 +41,42 @@ dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
* Returns the read value.
*/
u32
-intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
+intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
{
u32 val;
- spin_lock(&i915->display.dkl.phy_lock);
+ spin_lock(&display->dkl.phy_lock);
- dkl_phy_set_hip_idx(i915, reg);
- val = intel_de_read(i915, DKL_REG_MMIO(reg));
+ dkl_phy_set_hip_idx(display, reg);
+ val = intel_de_read(display, DKL_REG_MMIO(reg));
- spin_unlock(&i915->display.dkl.phy_lock);
+ spin_unlock(&display->dkl.phy_lock);
return val;
}
/**
* intel_dkl_phy_write - write a Dekel PHY register
- * @i915: i915 device instance
+ * @display: intel_display device instance
* @reg: Dekel PHY register
* @val: value to write
*
* Write @val to the @reg Dekel PHY register.
*/
void
-intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val)
+intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val)
{
- spin_lock(&i915->display.dkl.phy_lock);
+ spin_lock(&display->dkl.phy_lock);
- dkl_phy_set_hip_idx(i915, reg);
- intel_de_write(i915, DKL_REG_MMIO(reg), val);
+ dkl_phy_set_hip_idx(display, reg);
+ intel_de_write(display, DKL_REG_MMIO(reg), val);
- spin_unlock(&i915->display.dkl.phy_lock);
+ spin_unlock(&display->dkl.phy_lock);
}
/**
* intel_dkl_phy_rmw - read-modify-write a Dekel PHY register
- * @i915: i915 device instance
+ * @display: display device instance
* @reg: Dekel PHY register
* @clear: mask to clear
* @set: mask to set
@@ -85,30 +85,30 @@ intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg,
* this value back to the register if the value differs from the read one.
*/
void
-intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set)
+intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set)
{
- spin_lock(&i915->display.dkl.phy_lock);
+ spin_lock(&display->dkl.phy_lock);
- dkl_phy_set_hip_idx(i915, reg);
- intel_de_rmw(i915, DKL_REG_MMIO(reg), clear, set);
+ dkl_phy_set_hip_idx(display, reg);
+ intel_de_rmw(display, DKL_REG_MMIO(reg), clear, set);
- spin_unlock(&i915->display.dkl.phy_lock);
+ spin_unlock(&display->dkl.phy_lock);
}
/**
* intel_dkl_phy_posting_read - do a posting read from a Dekel PHY register
- * @i915: i915 device instance
+ * @display: display device instance
* @reg: Dekel PHY register
*
* Read the @reg Dekel PHY register without returning the read value.
*/
void
-intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
+intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
{
- spin_lock(&i915->display.dkl.phy_lock);
+ spin_lock(&display->dkl.phy_lock);
- dkl_phy_set_hip_idx(i915, reg);
- intel_de_posting_read(i915, DKL_REG_MMIO(reg));
+ dkl_phy_set_hip_idx(display, reg);
+ intel_de_posting_read(display, DKL_REG_MMIO(reg));
- spin_unlock(&i915->display.dkl.phy_lock);
+ spin_unlock(&display->dkl.phy_lock);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.h b/drivers/gpu/drm/i915/display/intel_dkl_phy.h
index 5956ec3e940b..1d96e6be657c 100644
--- a/drivers/gpu/drm/i915/display/intel_dkl_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.h
@@ -11,15 +11,16 @@
#include "intel_dkl_phy_regs.h"
struct drm_i915_private;
+struct intel_display;
void intel_dkl_phy_init(struct drm_i915_private *i915);
u32
-intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg);
+intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
void
-intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val);
+intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val);
void
-intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set);
+intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set);
void
-intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg);
+intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
#endif /* __INTEL_DKL_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ee4e263ce999..9976ac6322d1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -65,7 +65,7 @@ struct intel_shared_dpll_funcs {
* Hook for enabling the pll, called from intel_enable_shared_dpll() if
* the pll is not already enabled.
*/
- void (*enable)(struct drm_i915_private *i915,
+ void (*enable)(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
@@ -74,7 +74,7 @@ struct intel_shared_dpll_funcs {
* only when it is safe to disable the pll, i.e., there are no more
* tracked users for it.
*/
- void (*disable)(struct drm_i915_private *i915,
+ void (*disable)(struct intel_display *display,
struct intel_shared_dpll *pll);
/*
@@ -82,7 +82,7 @@ struct intel_shared_dpll_funcs {
* registers. This is used for initial hw state readout and state
* verification after a mode set.
*/
- bool (*get_hw_state)(struct drm_i915_private *i915,
+ bool (*get_hw_state)(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state);
@@ -90,7 +90,7 @@ struct intel_shared_dpll_funcs {
* Hook for calculating the pll's output frequency based on its passed
* in state.
*/
- int (*get_freq)(struct drm_i915_private *i915,
+ int (*get_freq)(struct intel_display *i915,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
};
@@ -148,17 +148,16 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
/**
* intel_get_shared_dpll_by_id - get a DPLL given its id
- * @i915: i915 device instance
+ * @display: intel_display device instance
* @id: pll id
*
* Returns:
* A pointer to the DPLL with @id
*/
struct intel_shared_dpll *
-intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
+intel_get_shared_dpll_by_id(struct intel_display *display,
enum intel_dpll_id id)
{
- struct intel_display *display = to_intel_display(&i915->drm);
struct intel_shared_dpll *pll;
int i;
@@ -184,7 +183,7 @@ void assert_shared_dpll(struct drm_i915_private *i915,
"asserting DPLL %s with no DPLL\n", str_on_off(state)))
return;
- cur_state = intel_dpll_get_hw_state(i915, pll, &hw_state);
+ cur_state = intel_dpll_get_hw_state(display, pll, &hw_state);
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
"%s assertion failure (expected %s, current %s)\n",
pll->info->name, str_on_off(state),
@@ -202,12 +201,12 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
}
static i915_reg_t
-intel_combo_pll_enable_reg(struct drm_i915_private *i915,
+intel_combo_pll_enable_reg(struct intel_display *display,
struct intel_shared_dpll *pll)
{
- if (IS_DG1(i915))
+ if (display->platform.dg1)
return DG1_DPLL_ENABLE(pll->info->id);
- else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
+ else if ((display->platform.jasperlake || display->platform.elkhartlake) &&
(pll->info->id == DPLL_ID_EHL_DPLL4))
return MG_PLL_ENABLE(0);
@@ -215,36 +214,32 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
}
static i915_reg_t
-intel_tc_pll_enable_reg(struct drm_i915_private *i915,
+intel_tc_pll_enable_reg(struct intel_display *display,
struct intel_shared_dpll *pll)
{
const enum intel_dpll_id id = pll->info->id;
enum tc_port tc_port = icl_pll_id_to_tc_port(id);
- if (IS_ALDERLAKE_P(i915))
+ if (display->platform.alderlake_p)
return ADLP_PORTTC_PLL_ENABLE(tc_port);
return MG_PLL_ENABLE(tc_port);
}
-static void _intel_enable_shared_dpll(struct drm_i915_private *i915,
+static void _intel_enable_shared_dpll(struct intel_display *display,
struct intel_shared_dpll *pll)
{
- struct intel_display *display = &i915->display;
-
if (pll->info->power_domain)
pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
- pll->info->funcs->enable(i915, pll, &pll->state.hw_state);
+ pll->info->funcs->enable(display, pll, &pll->state.hw_state);
pll->on = true;
}
-static void _intel_disable_shared_dpll(struct drm_i915_private *i915,
+static void _intel_disable_shared_dpll(struct intel_display *display,
struct intel_shared_dpll *pll)
{
- struct intel_display *display = &i915->display;
-
- pll->info->funcs->disable(i915, pll);
+ pll->info->funcs->disable(display, pll);
pll->on = false;
if (pll->info->power_domain)
@@ -259,42 +254,43 @@ static void _intel_disable_shared_dpll(struct drm_i915_private *i915,
*/
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
unsigned int pipe_mask = BIT(crtc->pipe);
unsigned int old_mask;
- if (drm_WARN_ON(&i915->drm, pll == NULL))
+ if (drm_WARN_ON(display->drm, !pll))
return;
- mutex_lock(&i915->display.dpll.lock);
+ mutex_lock(&display->dpll.lock);
old_mask = pll->active_mask;
- if (drm_WARN_ON(&i915->drm, !(pll->state.pipe_mask & pipe_mask)) ||
- drm_WARN_ON(&i915->drm, pll->active_mask & pipe_mask))
+ if (drm_WARN_ON(display->drm, !(pll->state.pipe_mask & pipe_mask)) ||
+ drm_WARN_ON(display->drm, pll->active_mask & pipe_mask))
goto out;
pll->active_mask |= pipe_mask;
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"enable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
pll->info->name, pll->active_mask, pll->on,
crtc->base.base.id, crtc->base.name);
if (old_mask) {
- drm_WARN_ON(&i915->drm, !pll->on);
+ drm_WARN_ON(display->drm, !pll->on);
assert_shared_dpll_enabled(i915, pll);
goto out;
}
- drm_WARN_ON(&i915->drm, pll->on);
+ drm_WARN_ON(display->drm, pll->on);
- drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name);
+ drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name);
- _intel_enable_shared_dpll(i915, pll);
+ _intel_enable_shared_dpll(display, pll);
out:
- mutex_unlock(&i915->display.dpll.lock);
+ mutex_unlock(&display->dpll.lock);
}
/**
@@ -305,48 +301,48 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
*/
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
unsigned int pipe_mask = BIT(crtc->pipe);
/* PCH only available on ILK+ */
- if (DISPLAY_VER(i915) < 5)
+ if (DISPLAY_VER(display) < 5)
return;
if (pll == NULL)
return;
- mutex_lock(&i915->display.dpll.lock);
- if (drm_WARN(&i915->drm, !(pll->active_mask & pipe_mask),
+ mutex_lock(&display->dpll.lock);
+ if (drm_WARN(display->drm, !(pll->active_mask & pipe_mask),
"%s not used by [CRTC:%d:%s]\n", pll->info->name,
crtc->base.base.id, crtc->base.name))
goto out;
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"disable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
pll->info->name, pll->active_mask, pll->on,
crtc->base.base.id, crtc->base.name);
assert_shared_dpll_enabled(i915, pll);
- drm_WARN_ON(&i915->drm, !pll->on);
+ drm_WARN_ON(display->drm, !pll->on);
pll->active_mask &= ~pipe_mask;
if (pll->active_mask)
goto out;
- drm_dbg_kms(&i915->drm, "disabling %s\n", pll->info->name);
+ drm_dbg_kms(display->drm, "disabling %s\n", pll->info->name);
- _intel_disable_shared_dpll(i915, pll);
+ _intel_disable_shared_dpll(display, pll);
out:
- mutex_unlock(&i915->display.dpll.lock);
+ mutex_unlock(&display->dpll.lock);
}
static unsigned long
-intel_dpll_mask_all(struct drm_i915_private *i915)
+intel_dpll_mask_all(struct intel_display *display)
{
- struct intel_display *display = to_intel_display(&i915->drm);
struct intel_shared_dpll *pll;
unsigned long dpll_mask = 0;
int i;
@@ -366,20 +362,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
const struct intel_dpll_hw_state *dpll_hw_state,
unsigned long dpll_mask)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- unsigned long dpll_mask_all = intel_dpll_mask_all(i915);
+ struct intel_display *display = to_intel_display(crtc);
+ unsigned long dpll_mask_all = intel_dpll_mask_all(display);
struct intel_shared_dpll_state *shared_dpll;
struct intel_shared_dpll *unused_pll = NULL;
enum intel_dpll_id id;
shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
- drm_WARN_ON(&i915->drm, dpll_mask & ~dpll_mask_all);
+ drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
struct intel_shared_dpll *pll;
- pll = intel_get_shared_dpll_by_id(i915, id);
+ pll = intel_get_shared_dpll_by_id(display, id);
if (!pll)
continue;
@@ -393,7 +389,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
if (memcmp(dpll_hw_state,
&shared_dpll[pll->index].hw_state,
sizeof(*dpll_hw_state)) == 0) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n",
crtc->base.base.id, crtc->base.name,
pll->info->name,
@@ -405,7 +401,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
/* Ok no matching timings, maybe there's a free one? */
if (unused_pll) {
- drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] allocated %s\n",
+ drm_dbg_kms(display->drm, "[CRTC:%d:%s] allocated %s\n",
crtc->base.base.id, crtc->base.name,
unused_pll->info->name);
return unused_pll;
@@ -528,11 +524,10 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
swap(pll->state, shared_dpll[pll->index]);
}
-static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915,
+static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- struct intel_display *display = &i915->display;
struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
@@ -543,10 +538,10 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915,
if (!wakeref)
return false;
- val = intel_de_read(i915, PCH_DPLL(id));
+ val = intel_de_read(display, PCH_DPLL(id));
hw_state->dpll = val;
- hw_state->fp0 = intel_de_read(i915, PCH_FP0(id));
- hw_state->fp1 = intel_de_read(i915, PCH_FP1(id));
+ hw_state->fp0 = intel_de_read(display, PCH_FP0(id));
+ hw_state->fp1 = intel_de_read(display, PCH_FP1(id));
intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
@@ -566,23 +561,24 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915)
"PCH refclk assertion failure, should be active but is disabled\n");
}
-static void ibx_pch_dpll_enable(struct drm_i915_private *i915,
+static void ibx_pch_dpll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
const enum intel_dpll_id id = pll->info->id;
/* PCH refclock must be enabled first */
ibx_assert_pch_refclk_enabled(i915);
- intel_de_write(i915, PCH_FP0(id), hw_state->fp0);
- intel_de_write(i915, PCH_FP1(id), hw_state->fp1);
+ intel_de_write(display, PCH_FP0(id), hw_state->fp0);
+ intel_de_write(display, PCH_FP1(id), hw_state->fp1);
- intel_de_write(i915, PCH_DPLL(id), hw_state->dpll);
+ intel_de_write(display, PCH_DPLL(id), hw_state->dpll);
/* Wait for the clocks to stabilize. */
- intel_de_posting_read(i915, PCH_DPLL(id));
+ intel_de_posting_read(display, PCH_DPLL(id));
udelay(150);
/* The pixel multiplier can only be updated once the
@@ -590,18 +586,18 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *i915,
*
* So write it again.
*/
- intel_de_write(i915, PCH_DPLL(id), hw_state->dpll);
- intel_de_posting_read(i915, PCH_DPLL(id));
+ intel_de_write(display, PCH_DPLL(id), hw_state->dpll);
+ intel_de_posting_read(display, PCH_DPLL(id));
udelay(200);
}
-static void ibx_pch_dpll_disable(struct drm_i915_private *i915,
+static void ibx_pch_dpll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
const enum intel_dpll_id id = pll->info->id;
- intel_de_write(i915, PCH_DPLL(id), 0);
- intel_de_posting_read(i915, PCH_DPLL(id));
+ intel_de_write(display, PCH_DPLL(id), 0);
+ intel_de_posting_read(display, PCH_DPLL(id));
udelay(200);
}
@@ -616,18 +612,19 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(state);
+ struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll;
enum intel_dpll_id id;
if (HAS_PCH_IBX(i915)) {
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
id = (enum intel_dpll_id) crtc->pipe;
- pll = intel_get_shared_dpll_by_id(i915, id);
+ pll = intel_get_shared_dpll_by_id(display, id);
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"[CRTC:%d:%s] using pre-allocated %s\n",
crtc->base.base.id, crtc->base.name,
pll->info->name);
@@ -696,66 +693,65 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
.compare_hw_state = ibx_compare_hw_state,
};
-static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915,
+static void hsw_ddi_wrpll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
const enum intel_dpll_id id = pll->info->id;
- intel_de_write(i915, WRPLL_CTL(id), hw_state->wrpll);
- intel_de_posting_read(i915, WRPLL_CTL(id));
+ intel_de_write(display, WRPLL_CTL(id), hw_state->wrpll);
+ intel_de_posting_read(display, WRPLL_CTL(id));
udelay(20);
}
-static void hsw_ddi_spll_enable(struct drm_i915_private *i915,
+static void hsw_ddi_spll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
- intel_de_write(i915, SPLL_CTL, hw_state->spll);
- intel_de_posting_read(i915, SPLL_CTL);
+ intel_de_write(display, SPLL_CTL, hw_state->spll);
+ intel_de_posting_read(display, SPLL_CTL);
udelay(20);
}
-static void hsw_ddi_wrpll_disable(struct drm_i915_private *i915,
+static void hsw_ddi_wrpll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
const enum intel_dpll_id id = pll->info->id;
- intel_de_rmw(i915, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0);
- intel_de_posting_read(i915, WRPLL_CTL(id));
+ intel_de_rmw(display, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0);
+ intel_de_posting_read(display, WRPLL_CTL(id));
/*
* Try to set up the PCH reference clock once all DPLLs
* that depend on it have been shut down.
*/
- if (i915->display.dpll.pch_ssc_use & BIT(id))
- intel_init_pch_refclk(i915);
+ if (display->dpll.pch_ssc_use & BIT(id))
+ intel_init_pch_refclk(to_i915(display->drm));
}
-static void hsw_ddi_spll_disable(struct drm_i915_private *i915,
+static void hsw_ddi_spll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
enum intel_dpll_id id = pll->info->id;
- intel_de_rmw(i915, SPLL_CTL, SPLL_PLL_ENABLE, 0);
- intel_de_posting_read(i915, SPLL_CTL);
+ intel_de_rmw(display, SPLL_CTL, SPLL_PLL_ENABLE, 0);
+ intel_de_posting_read(display, SPLL_CTL);
/*
* Try to set up the PCH reference clock once all DPLLs
* that depend on it have been shut down.
*/
- if (i915->display.dpll.pch_ssc_use & BIT(id))
- intel_init_pch_refclk(i915);
+ if (display->dpll.pch_ssc_use & BIT(id))
+ intel_init_pch_refclk(to_i915(display->drm));
}
-static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915,
+static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- struct intel_display *display = &i915->display;
struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
@@ -766,7 +762,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915,
if (!wakeref)
return false;
- val = intel_de_read(i915, WRPLL_CTL(id));
+ val = intel_de_read(display, WRPLL_CTL(id));
hw_state->wrpll = val;
intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
@@ -774,11 +770,10 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915,
return val & WRPLL_PLL_ENABLE;
}
-static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915,
+static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- struct intel_display *display = &i915->display;
struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
intel_wakeref_t wakeref;
u32 val;
@@ -788,7 +783,7 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915,
if (!wakeref)
return false;
- val = intel_de_read(i915, SPLL_CTL);
+ val = intel_de_read(display, SPLL_CTL);
hw_state->spll = val;
intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
@@ -1002,7 +997,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
*r2_out = best.r2;
}
-static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915,
+static int hsw_ddi_wrpll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -1014,8 +1009,8 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915,
switch (wrpll & WRPLL_REF_MASK) {
case WRPLL_REF_SPECIAL_HSW:
/* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
- if (IS_HASWELL(i915) && !IS_HASWELL_ULT(i915)) {
- refclk = i915->display.dpll.ref_clks.nssc;
+ if (display->platform.haswell && !display->platform.haswell_ult) {
+ refclk = display->dpll.ref_clks.nssc;
break;
}
fallthrough;
@@ -1025,7 +1020,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915,
* code only cares about 5% accuracy, and spread is a max of
* 0.5% downspread.
*/
- refclk = i915->display.dpll.ref_clks.ssc;
+ refclk = display->dpll.ref_clks.ssc;
break;
case WRPLL_REF_LCPLL:
refclk = 2700000;
@@ -1047,7 +1042,7 @@ static int
hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
@@ -1060,7 +1055,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
WRPLL_DIVIDER_POST(p);
- crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL,
+ crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL,
&crtc_state->dpll_hw_state);
return 0;
@@ -1100,7 +1095,7 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
static struct intel_shared_dpll *
hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_shared_dpll *pll;
enum intel_dpll_id pll_id;
int clock = crtc_state->port_clock;
@@ -1120,7 +1115,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
return NULL;
}
- pll = intel_get_shared_dpll_by_id(i915, pll_id);
+ pll = intel_get_shared_dpll_by_id(display, pll_id);
if (!pll)
return NULL;
@@ -1128,7 +1123,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
return pll;
}
-static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
+static int hsw_ddi_lcpll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -1145,7 +1140,7 @@ static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
link_clock = 270000;
break;
default:
- drm_WARN(&i915->drm, 1, "bad port clock sel\n");
+ drm_WARN(display->drm, 1, "bad port clock sel\n");
break;
}
@@ -1180,7 +1175,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
BIT(DPLL_ID_SPLL));
}
-static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
+static int hsw_ddi_spll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -1198,7 +1193,7 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
link_clock = 270000;
break;
default:
- drm_WARN(&i915->drm, 1, "bad spll freq\n");
+ drm_WARN(display->drm, 1, "bad spll freq\n");
break;
}
@@ -1291,18 +1286,18 @@ static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
.get_freq = hsw_ddi_spll_get_freq,
};
-static void hsw_ddi_lcpll_enable(struct drm_i915_private *i915,
+static void hsw_ddi_lcpll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *hw_state)
{
}
-static void hsw_ddi_lcpll_disable(struct drm_i915_private *i915,
+static void hsw_ddi_lcpll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
}
-static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *i915,
+static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -1370,21 +1365,21 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
},
};
-static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915,
+static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct skl_dpll_hw_state *hw_state)
{
const enum intel_dpll_id id = pll->info->id;
- intel_de_rmw(i915, DPLL_CTRL1,
+ intel_de_rmw(display, DPLL_CTRL1,
DPLL_CTRL1_HDMI_MODE(id) |
DPLL_CTRL1_SSC(id) |
DPLL_CTRL1_LINK_RATE_MASK(id),
hw_state->ctrl1 << (id * 6));
- intel_de_posting_read(i915, DPLL_CTRL1);
+ intel_de_posting_read(display, DPLL_CTRL1);
}
-static void skl_ddi_pll_enable(struct drm_i915_private *i915,
+static void skl_ddi_pll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -1392,50 +1387,49 @@ static void skl_ddi_pll_enable(struct drm_i915_private *i915,
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
- skl_ddi_pll_write_ctrl1(i915, pll, hw_state);
+ skl_ddi_pll_write_ctrl1(display, pll, hw_state);
- intel_de_write(i915, regs[id].cfgcr1, hw_state->cfgcr1);
- intel_de_write(i915, regs[id].cfgcr2, hw_state->cfgcr2);
- intel_de_posting_read(i915, regs[id].cfgcr1);
- intel_de_posting_read(i915, regs[id].cfgcr2);
+ intel_de_write(display, regs[id].cfgcr1, hw_state->cfgcr1);
+ intel_de_write(display, regs[id].cfgcr2, hw_state->cfgcr2);
+ intel_de_posting_read(display, regs[id].cfgcr1);
+ intel_de_posting_read(display, regs[id].cfgcr2);
/* the enable bit is always bit 31 */
- intel_de_rmw(i915, regs[id].ctl, 0, LCPLL_PLL_ENABLE);
+ intel_de_rmw(display, regs[id].ctl, 0, LCPLL_PLL_ENABLE);
- if (intel_de_wait_for_set(i915, DPLL_STATUS, DPLL_LOCK(id), 5))
- drm_err(&i915->drm, "DPLL %d not locked\n", id);
+ if (intel_de_wait_for_set(display, DPLL_STATUS, DPLL_LOCK(id), 5))
+ drm_err(display->drm, "DPLL %d not locked\n", id);
}
-static void skl_ddi_dpll0_enable(struct drm_i915_private *i915,
+static void skl_ddi_dpll0_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
- skl_ddi_pll_write_ctrl1(i915, pll, hw_state);
+ skl_ddi_pll_write_ctrl1(display, pll, hw_state);
}
-static void skl_ddi_pll_disable(struct drm_i915_private *i915,
+static void skl_ddi_pll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
/* the enable bit is always bit 31 */
- intel_de_rmw(i915, regs[id].ctl, LCPLL_PLL_ENABLE, 0);
- intel_de_posting_read(i915, regs[id].ctl);
+ intel_de_rmw(display, regs[id].ctl, LCPLL_PLL_ENABLE, 0);
+ intel_de_posting_read(display, regs[id].ctl);
}
-static void skl_ddi_dpll0_disable(struct drm_i915_private *i915,
+static void skl_ddi_dpll0_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
}
-static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915,
+static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- struct intel_display *display = &i915->display;
struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
@@ -1450,17 +1444,17 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915,
ret = false;
- val = intel_de_read(i915, regs[id].ctl);
+ val = intel_de_read(display, regs[id].ctl);
if (!(val & LCPLL_PLL_ENABLE))
goto out;
- val = intel_de_read(i915, DPLL_CTRL1);
+ val = intel_de_read(display, DPLL_CTRL1);
hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
/* avoid reading back stale values if HDMI mode is not enabled */
if (val & DPLL_CTRL1_HDMI_MODE(id)) {
- hw_state->cfgcr1 = intel_de_read(i915, regs[id].cfgcr1);
- hw_state->cfgcr2 = intel_de_read(i915, regs[id].cfgcr2);
+ hw_state->cfgcr1 = intel_de_read(display, regs[id].cfgcr1);
+ hw_state->cfgcr2 = intel_de_read(display, regs[id].cfgcr2);
}
ret = true;
@@ -1470,11 +1464,10 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915,
return ret;
}
-static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915,
+static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- struct intel_display *display = &i915->display;
struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
@@ -1490,11 +1483,11 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915,
ret = false;
/* DPLL0 is always enabled since it drives CDCLK */
- val = intel_de_read(i915, regs[id].ctl);
- if (drm_WARN_ON(&i915->drm, !(val & LCPLL_PLL_ENABLE)))
+ val = intel_de_read(display, regs[id].ctl);
+ if (drm_WARN_ON(display->drm, !(val & LCPLL_PLL_ENABLE)))
goto out;
- val = intel_de_read(i915, DPLL_CTRL1);
+ val = intel_de_read(display, DPLL_CTRL1);
hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
ret = true;
@@ -1744,12 +1737,12 @@ skl_ddi_calculate_wrpll(int clock,
return 0;
}
-static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
+static int skl_ddi_wrpll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
- int ref_clock = i915->display.dpll.ref_clks.nssc;
+ int ref_clock = display->dpll.ref_clks.nssc;
u32 p0, p1, p2, dco_freq;
p0 = hw_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
@@ -1776,7 +1769,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
* Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0,
* handling it the same way as PDIV_7.
*/
- drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
+ drm_dbg_kms(display->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
fallthrough;
case DPLL_CFGCR2_PDIV_7:
p0 = 7;
@@ -1810,7 +1803,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
dco_freq += ((hw_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) *
ref_clock / 0x8000;
- if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
+ if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0))
return 0;
return dco_freq / (p0 * p1 * p2 * 5);
@@ -1818,13 +1811,13 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
struct skl_wrpll_params wrpll_params = {};
int ret;
ret = skl_ddi_calculate_wrpll(crtc_state->port_clock,
- i915->display.dpll.ref_clks.nssc, &wrpll_params);
+ display->dpll.ref_clks.nssc, &wrpll_params);
if (ret)
return ret;
@@ -1848,7 +1841,7 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
wrpll_params.central_freq;
- crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL,
+ crtc_state->port_clock = skl_ddi_wrpll_get_freq(display, NULL,
&crtc_state->dpll_hw_state);
return 0;
@@ -1892,7 +1885,7 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
return 0;
}
-static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
+static int skl_ddi_lcpll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -1920,7 +1913,7 @@ static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
link_clock = 270000;
break;
default:
- drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
+ drm_WARN(display->drm, 1, "Unsupported link rate\n");
break;
}
@@ -1971,7 +1964,7 @@ static int skl_get_dpll(struct intel_atomic_state *state,
return 0;
}
-static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
+static int skl_ddi_pll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -1982,9 +1975,9 @@ static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
* the internal shift for each field
*/
if (hw_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
- return skl_ddi_wrpll_get_freq(i915, pll, dpll_hw_state);
+ return skl_ddi_wrpll_get_freq(display, pll, dpll_hw_state);
else
- return skl_ddi_lcpll_get_freq(i915, pll, dpll_hw_state);
+ return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);
}
static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
@@ -2046,11 +2039,10 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
.compare_hw_state = skl_compare_hw_state,
};
-static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
+static void bxt_ddi_pll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
- struct intel_display *display = &i915->display;
const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
enum dpio_phy phy;
@@ -2060,120 +2052,119 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
bxt_port_to_phy_channel(display, port, &phy, &ch);
/* Non-SSC reference */
- intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
+ intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
- if (IS_GEMINILAKE(i915)) {
- intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port),
+ if (display->platform.geminilake) {
+ intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
0, PORT_PLL_POWER_ENABLE);
- if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) &
+ if (wait_for_us((intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) &
PORT_PLL_POWER_STATE), 200))
- drm_err(&i915->drm,
+ drm_err(display->drm,
"Power state not set for PLL:%d\n", port);
}
/* Disable 10 bit clock */
- intel_de_rmw(i915, BXT_PORT_PLL_EBB_4(phy, ch),
+ intel_de_rmw(display, BXT_PORT_PLL_EBB_4(phy, ch),
PORT_PLL_10BIT_CLK_ENABLE, 0);
/* Write P1 & P2 */
- intel_de_rmw(i915, BXT_PORT_PLL_EBB_0(phy, ch),
+ intel_de_rmw(display, BXT_PORT_PLL_EBB_0(phy, ch),
PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, hw_state->ebb0);
/* Write M2 integer */
- intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 0),
+ intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 0),
PORT_PLL_M2_INT_MASK, hw_state->pll0);
/* Write N */
- intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 1),
+ intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 1),
PORT_PLL_N_MASK, hw_state->pll1);
/* Write M2 fraction */
- intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 2),
+ intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 2),
PORT_PLL_M2_FRAC_MASK, hw_state->pll2);
/* Write M2 fraction enable */
- intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 3),
+ intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 3),
PORT_PLL_M2_FRAC_ENABLE, hw_state->pll3);
/* Write coeff */
- temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6));
+ temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));
temp &= ~PORT_PLL_PROP_COEFF_MASK;
temp &= ~PORT_PLL_INT_COEFF_MASK;
temp &= ~PORT_PLL_GAIN_CTL_MASK;
temp |= hw_state->pll6;
- intel_de_write(i915, BXT_PORT_PLL(phy, ch, 6), temp);
+ intel_de_write(display, BXT_PORT_PLL(phy, ch, 6), temp);
/* Write calibration val */
- intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 8),
+ intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 8),
PORT_PLL_TARGET_CNT_MASK, hw_state->pll8);
- intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 9),
+ intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 9),
PORT_PLL_LOCK_THRESHOLD_MASK, hw_state->pll9);
- temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10));
+ temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));
temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
temp &= ~PORT_PLL_DCO_AMP_MASK;
temp |= hw_state->pll10;
- intel_de_write(i915, BXT_PORT_PLL(phy, ch, 10), temp);
+ intel_de_write(display, BXT_PORT_PLL(phy, ch, 10), temp);
/* Recalibrate with new settings */
- temp = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch));
+ temp = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));
temp |= PORT_PLL_RECALIBRATE;
- intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp);
+ intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp);
temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
temp |= hw_state->ebb4;
- intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp);
+ intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp);
/* Enable PLL */
- intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
- intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port));
+ intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
+ intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
- if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
+ if (wait_for_us((intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
200))
- drm_err(&i915->drm, "PLL %d not locked\n", port);
+ drm_err(display->drm, "PLL %d not locked\n", port);
- if (IS_GEMINILAKE(i915)) {
- temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN(phy, ch, 0));
+ if (display->platform.geminilake) {
+ temp = intel_de_read(display, BXT_PORT_TX_DW5_LN(phy, ch, 0));
temp |= DCC_DELAY_RANGE_2;
- intel_de_write(i915, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
+ intel_de_write(display, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
}
/*
* While we write to the group register to program all lanes at once we
* can read only lane registers and we pick lanes 0/1 for that.
*/
- temp = intel_de_read(i915, BXT_PORT_PCS_DW12_LN01(phy, ch));
+ temp = intel_de_read(display, BXT_PORT_PCS_DW12_LN01(phy, ch));
temp &= ~LANE_STAGGER_MASK;
temp &= ~LANESTAGGER_STRAP_OVRD;
temp |= hw_state->pcsdw12;
- intel_de_write(i915, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
+ intel_de_write(display, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
}
-static void bxt_ddi_pll_disable(struct drm_i915_private *i915,
+static void bxt_ddi_pll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
- intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);
- intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port));
+ intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);
+ intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
- if (IS_GEMINILAKE(i915)) {
- intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port),
+ if (display->platform.geminilake) {
+ intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
PORT_PLL_POWER_ENABLE, 0);
- if (wait_for_us(!(intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) &
+ if (wait_for_us(!(intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) &
PORT_PLL_POWER_STATE), 200))
- drm_err(&i915->drm,
+ drm_err(display->drm,
"Power state not reset for PLL:%d\n", port);
}
}
-static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
+static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- struct intel_display *display = &i915->display;
struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
intel_wakeref_t wakeref;
@@ -2191,40 +2182,40 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
ret = false;
- val = intel_de_read(i915, BXT_PORT_PLL_ENABLE(port));
+ val = intel_de_read(display, BXT_PORT_PLL_ENABLE(port));
if (!(val & PORT_PLL_ENABLE))
goto out;
- hw_state->ebb0 = intel_de_read(i915, BXT_PORT_PLL_EBB_0(phy, ch));
+ hw_state->ebb0 = intel_de_read(display, BXT_PORT_PLL_EBB_0(phy, ch));
hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
- hw_state->ebb4 = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch));
+ hw_state->ebb4 = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));
hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
- hw_state->pll0 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 0));
+ hw_state->pll0 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 0));
hw_state->pll0 &= PORT_PLL_M2_INT_MASK;
- hw_state->pll1 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 1));
+ hw_state->pll1 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 1));
hw_state->pll1 &= PORT_PLL_N_MASK;
- hw_state->pll2 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 2));
+ hw_state->pll2 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 2));
hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
- hw_state->pll3 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 3));
+ hw_state->pll3 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 3));
hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
- hw_state->pll6 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6));
+ hw_state->pll6 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));
hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
PORT_PLL_INT_COEFF_MASK |
PORT_PLL_GAIN_CTL_MASK;
- hw_state->pll8 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 8));
+ hw_state->pll8 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 8));
hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
- hw_state->pll9 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 9));
+ hw_state->pll9 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 9));
hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
- hw_state->pll10 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10));
+ hw_state->pll10 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));
hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
PORT_PLL_DCO_AMP_MASK;
@@ -2233,13 +2224,13 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
* can read only lane registers. We configure all lanes the same way, so
* here just read out lanes 0/1 and output a note if lanes 2/3 differ.
*/
- hw_state->pcsdw12 = intel_de_read(i915,
+ hw_state->pcsdw12 = intel_de_read(display,
BXT_PORT_PCS_DW12_LN01(phy, ch));
- if (intel_de_read(i915, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
- drm_dbg(&i915->drm,
+ if (intel_de_read(display, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
+ drm_dbg(display->drm,
"lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
hw_state->pcsdw12,
- intel_de_read(i915,
+ intel_de_read(display,
BXT_PORT_PCS_DW12_LN23(phy, ch)));
hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
@@ -2370,7 +2361,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
return 0;
}
-static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
+static int bxt_ddi_pll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -2386,7 +2377,7 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, hw_state->ebb0);
clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, hw_state->ebb0);
- return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock);
+ return chv_calc_dpll_params(display->dpll.ref_clks.nssc, &clock);
}
static int
@@ -2402,7 +2393,7 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
static int
bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
struct dpll clk_div = {};
int ret;
@@ -2412,7 +2403,7 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
if (ret)
return ret;
- crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL,
+ crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL,
&crtc_state->dpll_hw_state);
return 0;
@@ -2437,17 +2428,17 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll;
enum intel_dpll_id id;
/* 1:1 mapping between ports and PLLs */
id = (enum intel_dpll_id) encoder->port;
- pll = intel_get_shared_dpll_by_id(i915, id);
+ pll = intel_get_shared_dpll_by_id(display, id);
- drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
+ drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
crtc->base.base.id, crtc->base.name, pll->info->name);
intel_reference_shared_dpll(state, crtc,
@@ -2613,12 +2604,14 @@ static void icl_wrpll_params_populate(struct skl_wrpll_params *params,
* Program half of the nominal DCO divider fraction value.
*/
static bool
-ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
+ehl_combo_pll_div_frac_wa_needed(struct intel_display *display)
{
- return ((IS_ELKHARTLAKE(i915) &&
- IS_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
- IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
- i915->display.dpll.ref_clks.nssc == 38400;
+ return ((display->platform.elkhartlake &&
+ IS_DISPLAY_STEP(display, STEP_B0, STEP_FOREVER)) ||
+ display->platform.tigerlake ||
+ display->platform.alderlake_s ||
+ display->platform.alderlake_p) &&
+ display->dpll.ref_clks.nssc == 38400;
}
struct icl_combo_pll_params {
@@ -2765,7 +2758,7 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
return 0;
}
-static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
+static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -2773,14 +2766,14 @@ static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
* The PLL outputs multiple frequencies at the same time, selection is
* made at DDI clock mux level.
*/
- drm_WARN_ON(&i915->drm, 1);
+ drm_WARN_ON(display->drm, 1);
return 0;
}
-static int icl_wrpll_ref_clock(struct drm_i915_private *i915)
+static int icl_wrpll_ref_clock(struct intel_display *display)
{
- int ref_clock = i915->display.dpll.ref_clks.nssc;
+ int ref_clock = display->dpll.ref_clks.nssc;
/*
* For ICL+, the spec states: if reference frequency is 38.4,
@@ -2796,8 +2789,8 @@ static int
icl_calc_wrpll(struct intel_crtc_state *crtc_state,
struct skl_wrpll_params *wrpll_params)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- int ref_clock = icl_wrpll_ref_clock(i915);
+ struct intel_display *display = to_intel_display(crtc_state);
+ int ref_clock = icl_wrpll_ref_clock(display);
u32 afe_clock = crtc_state->port_clock * 5;
u32 dco_min = 7998000;
u32 dco_max = 10000000;
@@ -2836,12 +2829,12 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
return 0;
}
-static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
+static int icl_ddi_combo_pll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
- int ref_clock = icl_wrpll_ref_clock(i915);
+ int ref_clock = icl_wrpll_ref_clock(display);
u32 dco_fraction;
u32 p0, p1, p2, dco_freq;
@@ -2887,25 +2880,25 @@ static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
dco_fraction = (hw_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
DPLL_CFGCR0_DCO_FRACTION_SHIFT;
- if (ehl_combo_pll_div_frac_wa_needed(i915))
+ if (ehl_combo_pll_div_frac_wa_needed(display))
dco_fraction *= 2;
dco_freq += (dco_fraction * ref_clock) / 0x8000;
- if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
+ if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0))
return 0;
return dco_freq / (p0 * p1 * p2 * 5);
}
-static void icl_calc_dpll_state(struct drm_i915_private *i915,
+static void icl_calc_dpll_state(struct intel_display *display,
const struct skl_wrpll_params *pll_params,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
u32 dco_fraction = pll_params->dco_fraction;
- if (ehl_combo_pll_div_frac_wa_needed(i915))
+ if (ehl_combo_pll_div_frac_wa_needed(display))
dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
hw_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
@@ -2916,13 +2909,13 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
DPLL_CFGCR1_KDIV(pll_params->kdiv) |
DPLL_CFGCR1_PDIV(pll_params->pdiv);
- if (DISPLAY_VER(i915) >= 12)
+ if (DISPLAY_VER(display) >= 12)
hw_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
else
hw_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
- if (i915->display.vbt.override_afc_startup)
- hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val);
+ if (display->vbt.override_afc_startup)
+ hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(display->vbt.override_afc_startup_val);
}
static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
@@ -3209,7 +3202,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
return 0;
}
-static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915,
+static int icl_ddi_mg_pll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
@@ -3217,9 +3210,9 @@ static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915,
u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
u64 tmp;
- ref_clock = i915->display.dpll.ref_clks.nssc;
+ ref_clock = display->dpll.ref_clks.nssc;
- if (DISPLAY_VER(i915) >= 12) {
+ if (DISPLAY_VER(display) >= 12) {
m1 = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
m2_int = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
@@ -3324,7 +3317,7 @@ static void icl_update_active_dpll(struct intel_atomic_state *state,
static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct icl_port_dpll *port_dpll =
@@ -3341,12 +3334,12 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
if (ret)
return ret;
- icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state);
+ icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state);
/* this is mainly for the fastset check */
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
- crtc_state->port_clock = icl_ddi_combo_pll_get_freq(i915, NULL,
+ crtc_state->port_clock = icl_ddi_combo_pll_get_freq(display, NULL,
&port_dpll->hw_state);
return 0;
@@ -3416,7 +3409,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_crtc_state *old_crtc_state =
@@ -3431,7 +3424,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
if (ret)
return ret;
- icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state);
+ icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state);
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
@@ -3445,7 +3438,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
else
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
- crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL,
+ crtc_state->port_clock = icl_ddi_mg_pll_get_freq(display, NULL,
&port_dpll->hw_state);
return 0;
@@ -3549,11 +3542,10 @@ static void icl_put_dplls(struct intel_atomic_state *state,
}
}
-static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
+static bool mg_pll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- struct intel_display *display = &i915->display;
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
const enum intel_dpll_id id = pll->info->id;
enum tc_port tc_port = icl_pll_id_to_tc_port(id);
@@ -3561,46 +3553,46 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
bool ret = false;
u32 val;
- i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
+ i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
wakeref = intel_display_power_get_if_enabled(display,
POWER_DOMAIN_DISPLAY_CORE);
if (!wakeref)
return false;
- val = intel_de_read(i915, enable_reg);
+ val = intel_de_read(display, enable_reg);
if (!(val & PLL_ENABLE))
goto out;
- hw_state->mg_refclkin_ctl = intel_de_read(i915,
+ hw_state->mg_refclkin_ctl = intel_de_read(display,
MG_REFCLKIN_CTL(tc_port));
hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
hw_state->mg_clktop2_coreclkctl1 =
- intel_de_read(i915, MG_CLKTOP2_CORECLKCTL1(tc_port));
+ intel_de_read(display, MG_CLKTOP2_CORECLKCTL1(tc_port));
hw_state->mg_clktop2_coreclkctl1 &=
MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
hw_state->mg_clktop2_hsclkctl =
- intel_de_read(i915, MG_CLKTOP2_HSCLKCTL(tc_port));
+ intel_de_read(display, MG_CLKTOP2_HSCLKCTL(tc_port));
hw_state->mg_clktop2_hsclkctl &=
MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
- hw_state->mg_pll_div0 = intel_de_read(i915, MG_PLL_DIV0(tc_port));
- hw_state->mg_pll_div1 = intel_de_read(i915, MG_PLL_DIV1(tc_port));
- hw_state->mg_pll_lf = intel_de_read(i915, MG_PLL_LF(tc_port));
- hw_state->mg_pll_frac_lock = intel_de_read(i915,
+ hw_state->mg_pll_div0 = intel_de_read(display, MG_PLL_DIV0(tc_port));
+ hw_state->mg_pll_div1 = intel_de_read(display, MG_PLL_DIV1(tc_port));
+ hw_state->mg_pll_lf = intel_de_read(display, MG_PLL_LF(tc_port));
+ hw_state->mg_pll_frac_lock = intel_de_read(display,
MG_PLL_FRAC_LOCK(tc_port));
- hw_state->mg_pll_ssc = intel_de_read(i915, MG_PLL_SSC(tc_port));
+ hw_state->mg_pll_ssc = intel_de_read(display, MG_PLL_SSC(tc_port));
- hw_state->mg_pll_bias = intel_de_read(i915, MG_PLL_BIAS(tc_port));
+ hw_state->mg_pll_bias = intel_de_read(display, MG_PLL_BIAS(tc_port));
hw_state->mg_pll_tdc_coldst_bias =
- intel_de_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port));
+ intel_de_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));
- if (i915->display.dpll.ref_clks.nssc == 38400) {
+ if (display->dpll.ref_clks.nssc == 38400) {
hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
hw_state->mg_pll_bias_mask = 0;
} else {
@@ -3617,11 +3609,10 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
return ret;
}
-static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
+static bool dkl_pll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- struct intel_display *display = &i915->display;
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
const enum intel_dpll_id id = pll->info->id;
enum tc_port tc_port = icl_pll_id_to_tc_port(id);
@@ -3634,7 +3625,7 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
if (!wakeref)
return false;
- val = intel_de_read(i915, intel_tc_pll_enable_reg(i915, pll));
+ val = intel_de_read(display, intel_tc_pll_enable_reg(display, pll));
if (!(val & PLL_ENABLE))
goto out;
@@ -3642,12 +3633,12 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
* All registers read here have the same HIP_INDEX_REG even though
* they are on different building blocks
*/
- hw_state->mg_refclkin_ctl = intel_dkl_phy_read(i915,
+ hw_state->mg_refclkin_ctl = intel_dkl_phy_read(display,
DKL_REFCLKIN_CTL(tc_port));
hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
hw_state->mg_clktop2_hsclkctl =
- intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port));
+ intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));
hw_state->mg_clktop2_hsclkctl &=
MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
@@ -3655,32 +3646,32 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
hw_state->mg_clktop2_coreclkctl1 =
- intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port));
+ intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));
hw_state->mg_clktop2_coreclkctl1 &=
MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
- hw_state->mg_pll_div0 = intel_dkl_phy_read(i915, DKL_PLL_DIV0(tc_port));
+ hw_state->mg_pll_div0 = intel_dkl_phy_read(display, DKL_PLL_DIV0(tc_port));
val = DKL_PLL_DIV0_MASK;
- if (i915->display.vbt.override_afc_startup)
+ if (display->vbt.override_afc_startup)
val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
hw_state->mg_pll_div0 &= val;
- hw_state->mg_pll_div1 = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port));
+ hw_state->mg_pll_div1 = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));
hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK |
DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
- hw_state->mg_pll_ssc = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port));
+ hw_state->mg_pll_ssc = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));
hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
DKL_PLL_SSC_STEP_LEN_MASK |
DKL_PLL_SSC_STEP_NUM_MASK |
DKL_PLL_SSC_EN);
- hw_state->mg_pll_bias = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port));
+ hw_state->mg_pll_bias = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));
hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H |
DKL_PLL_BIAS_FBDIV_FRAC_MASK);
hw_state->mg_pll_tdc_coldst_bias =
- intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
+ intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
@@ -3690,12 +3681,11 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
return ret;
}
-static bool icl_pll_get_hw_state(struct drm_i915_private *i915,
+static bool icl_pll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state,
i915_reg_t enable_reg)
{
- struct intel_display *display = &i915->display;
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
@@ -3707,41 +3697,41 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *i915,
if (!wakeref)
return false;
- val = intel_de_read(i915, enable_reg);
+ val = intel_de_read(display, enable_reg);
if (!(val & PLL_ENABLE))
goto out;
- if (IS_ALDERLAKE_S(i915)) {
- hw_state->cfgcr0 = intel_de_read(i915, ADLS_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = intel_de_read(i915, ADLS_DPLL_CFGCR1(id));
- } else if (IS_DG1(i915)) {
- hw_state->cfgcr0 = intel_de_read(i915, DG1_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = intel_de_read(i915, DG1_DPLL_CFGCR1(id));
- } else if (IS_ROCKETLAKE(i915)) {
- hw_state->cfgcr0 = intel_de_read(i915,
+ if (display->platform.alderlake_s) {
+ hw_state->cfgcr0 = intel_de_read(display, ADLS_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = intel_de_read(display, ADLS_DPLL_CFGCR1(id));
+ } else if (display->platform.dg1) {
+ hw_state->cfgcr0 = intel_de_read(display, DG1_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = intel_de_read(display, DG1_DPLL_CFGCR1(id));
+ } else if (display->platform.rocketlake) {
+ hw_state->cfgcr0 = intel_de_read(display,
RKL_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = intel_de_read(i915,
+ hw_state->cfgcr1 = intel_de_read(display,
RKL_DPLL_CFGCR1(id));
- } else if (DISPLAY_VER(i915) >= 12) {
- hw_state->cfgcr0 = intel_de_read(i915,
+ } else if (DISPLAY_VER(display) >= 12) {
+ hw_state->cfgcr0 = intel_de_read(display,
TGL_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = intel_de_read(i915,
+ hw_state->cfgcr1 = intel_de_read(display,
TGL_DPLL_CFGCR1(id));
- if (i915->display.vbt.override_afc_startup) {
- hw_state->div0 = intel_de_read(i915, TGL_DPLL0_DIV0(id));
+ if (display->vbt.override_afc_startup) {
+ hw_state->div0 = intel_de_read(display, TGL_DPLL0_DIV0(id));
hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
}
} else {
- if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
+ if ((display->platform.jasperlake || display->platform.elkhartlake) &&
id == DPLL_ID_EHL_DPLL4) {
- hw_state->cfgcr0 = intel_de_read(i915,
+ hw_state->cfgcr0 = intel_de_read(display,
ICL_DPLL_CFGCR0(4));
- hw_state->cfgcr1 = intel_de_read(i915,
+ hw_state->cfgcr1 = intel_de_read(display,
ICL_DPLL_CFGCR1(4));
} else {
- hw_state->cfgcr0 = intel_de_read(i915,
+ hw_state->cfgcr0 = intel_de_read(display,
ICL_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = intel_de_read(i915,
+ hw_state->cfgcr1 = intel_de_read(display,
ICL_DPLL_CFGCR1(id));
}
}
@@ -3752,44 +3742,44 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *i915,
return ret;
}
-static bool combo_pll_get_hw_state(struct drm_i915_private *i915,
+static bool combo_pll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
+ i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
- return icl_pll_get_hw_state(i915, pll, dpll_hw_state, enable_reg);
+ return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);
}
-static bool tbt_pll_get_hw_state(struct drm_i915_private *i915,
+static bool tbt_pll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- return icl_pll_get_hw_state(i915, pll, dpll_hw_state, TBT_PLL_ENABLE);
+ return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
}
-static void icl_dpll_write(struct drm_i915_private *i915,
+static void icl_dpll_write(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct icl_dpll_hw_state *hw_state)
{
const enum intel_dpll_id id = pll->info->id;
i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG;
- if (IS_ALDERLAKE_S(i915)) {
+ if (display->platform.alderlake_s) {
cfgcr0_reg = ADLS_DPLL_CFGCR0(id);
cfgcr1_reg = ADLS_DPLL_CFGCR1(id);
- } else if (IS_DG1(i915)) {
+ } else if (display->platform.dg1) {
cfgcr0_reg = DG1_DPLL_CFGCR0(id);
cfgcr1_reg = DG1_DPLL_CFGCR1(id);
- } else if (IS_ROCKETLAKE(i915)) {
+ } else if (display->platform.rocketlake) {
cfgcr0_reg = RKL_DPLL_CFGCR0(id);
cfgcr1_reg = RKL_DPLL_CFGCR1(id);
- } else if (DISPLAY_VER(i915) >= 12) {
+ } else if (DISPLAY_VER(display) >= 12) {
cfgcr0_reg = TGL_DPLL_CFGCR0(id);
cfgcr1_reg = TGL_DPLL_CFGCR1(id);
div0_reg = TGL_DPLL0_DIV0(id);
} else {
- if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
+ if ((display->platform.jasperlake || display->platform.elkhartlake) &&
id == DPLL_ID_EHL_DPLL4) {
cfgcr0_reg = ICL_DPLL_CFGCR0(4);
cfgcr1_reg = ICL_DPLL_CFGCR1(4);
@@ -3799,18 +3789,18 @@ static void icl_dpll_write(struct drm_i915_private *i915,
}
}
- intel_de_write(i915, cfgcr0_reg, hw_state->cfgcr0);
- intel_de_write(i915, cfgcr1_reg, hw_state->cfgcr1);
- drm_WARN_ON_ONCE(&i915->drm, i915->display.vbt.override_afc_startup &&
+ intel_de_write(display, cfgcr0_reg, hw_state->cfgcr0);
+ intel_de_write(display, cfgcr1_reg, hw_state->cfgcr1);
+ drm_WARN_ON_ONCE(display->drm, display->vbt.override_afc_startup &&
!i915_mmio_reg_valid(div0_reg));
- if (i915->display.vbt.override_afc_startup &&
+ if (display->vbt.override_afc_startup &&
i915_mmio_reg_valid(div0_reg))
- intel_de_rmw(i915, div0_reg,
+ intel_de_rmw(display, div0_reg,
TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0);
- intel_de_posting_read(i915, cfgcr1_reg);
+ intel_de_posting_read(display, cfgcr1_reg);
}
-static void icl_mg_pll_write(struct drm_i915_private *i915,
+static void icl_mg_pll_write(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct icl_dpll_hw_state *hw_state)
{
@@ -3822,38 +3812,38 @@ static void icl_mg_pll_write(struct drm_i915_private *i915,
* during the calc/readout phase if the mask depends on some other HW
* state like refclk, see icl_calc_mg_pll_state().
*/
- intel_de_rmw(i915, MG_REFCLKIN_CTL(tc_port),
+ intel_de_rmw(display, MG_REFCLKIN_CTL(tc_port),
MG_REFCLKIN_CTL_OD_2_MUX_MASK, hw_state->mg_refclkin_ctl);
- intel_de_rmw(i915, MG_CLKTOP2_CORECLKCTL1(tc_port),
+ intel_de_rmw(display, MG_CLKTOP2_CORECLKCTL1(tc_port),
MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK,
hw_state->mg_clktop2_coreclkctl1);
- intel_de_rmw(i915, MG_CLKTOP2_HSCLKCTL(tc_port),
+ intel_de_rmw(display, MG_CLKTOP2_HSCLKCTL(tc_port),
MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK,
hw_state->mg_clktop2_hsclkctl);
- intel_de_write(i915, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
- intel_de_write(i915, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
- intel_de_write(i915, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
- intel_de_write(i915, MG_PLL_FRAC_LOCK(tc_port),
+ intel_de_write(display, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
+ intel_de_write(display, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
+ intel_de_write(display, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
+ intel_de_write(display, MG_PLL_FRAC_LOCK(tc_port),
hw_state->mg_pll_frac_lock);
- intel_de_write(i915, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
+ intel_de_write(display, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
- intel_de_rmw(i915, MG_PLL_BIAS(tc_port),
+ intel_de_rmw(display, MG_PLL_BIAS(tc_port),
hw_state->mg_pll_bias_mask, hw_state->mg_pll_bias);
- intel_de_rmw(i915, MG_PLL_TDC_COLDST_BIAS(tc_port),
+ intel_de_rmw(display, MG_PLL_TDC_COLDST_BIAS(tc_port),
hw_state->mg_pll_tdc_coldst_bias_mask,
hw_state->mg_pll_tdc_coldst_bias);
- intel_de_posting_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port));
+ intel_de_posting_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));
}
-static void dkl_pll_write(struct drm_i915_private *i915,
+static void dkl_pll_write(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct icl_dpll_hw_state *hw_state)
{
@@ -3865,90 +3855,90 @@ static void dkl_pll_write(struct drm_i915_private *i915,
* though on different building block
*/
/* All the registers are RMW */
- val = intel_dkl_phy_read(i915, DKL_REFCLKIN_CTL(tc_port));
+ val = intel_dkl_phy_read(display, DKL_REFCLKIN_CTL(tc_port));
val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
val |= hw_state->mg_refclkin_ctl;
- intel_dkl_phy_write(i915, DKL_REFCLKIN_CTL(tc_port), val);
+ intel_dkl_phy_write(display, DKL_REFCLKIN_CTL(tc_port), val);
- val = intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port));
+ val = intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));
val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
val |= hw_state->mg_clktop2_coreclkctl1;
- intel_dkl_phy_write(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
+ intel_dkl_phy_write(display, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
- val = intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port));
+ val = intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));
val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
val |= hw_state->mg_clktop2_hsclkctl;
- intel_dkl_phy_write(i915, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
+ intel_dkl_phy_write(display, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
val = DKL_PLL_DIV0_MASK;
- if (i915->display.vbt.override_afc_startup)
+ if (display->vbt.override_afc_startup)
val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
- intel_dkl_phy_rmw(i915, DKL_PLL_DIV0(tc_port), val,
+ intel_dkl_phy_rmw(display, DKL_PLL_DIV0(tc_port), val,
hw_state->mg_pll_div0);
- val = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port));
+ val = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));
val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK |
DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
val |= hw_state->mg_pll_div1;
- intel_dkl_phy_write(i915, DKL_PLL_DIV1(tc_port), val);
+ intel_dkl_phy_write(display, DKL_PLL_DIV1(tc_port), val);
- val = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port));
+ val = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));
val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
DKL_PLL_SSC_STEP_LEN_MASK |
DKL_PLL_SSC_STEP_NUM_MASK |
DKL_PLL_SSC_EN);
val |= hw_state->mg_pll_ssc;
- intel_dkl_phy_write(i915, DKL_PLL_SSC(tc_port), val);
+ intel_dkl_phy_write(display, DKL_PLL_SSC(tc_port), val);
- val = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port));
+ val = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));
val &= ~(DKL_PLL_BIAS_FRAC_EN_H |
DKL_PLL_BIAS_FBDIV_FRAC_MASK);
val |= hw_state->mg_pll_bias;
- intel_dkl_phy_write(i915, DKL_PLL_BIAS(tc_port), val);
+ intel_dkl_phy_write(display, DKL_PLL_BIAS(tc_port), val);
- val = intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
+ val = intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
val |= hw_state->mg_pll_tdc_coldst_bias;
- intel_dkl_phy_write(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
+ intel_dkl_phy_write(display, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
- intel_dkl_phy_posting_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
+ intel_dkl_phy_posting_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
}
-static void icl_pll_power_enable(struct drm_i915_private *i915,
+static void icl_pll_power_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
i915_reg_t enable_reg)
{
- intel_de_rmw(i915, enable_reg, 0, PLL_POWER_ENABLE);
+ intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);
/*
* The spec says we need to "wait" but it also says it should be
* immediate.
*/
- if (intel_de_wait_for_set(i915, enable_reg, PLL_POWER_STATE, 1))
- drm_err(&i915->drm, "PLL %d Power not enabled\n",
+ if (intel_de_wait_for_set(display, enable_reg, PLL_POWER_STATE, 1))
+ drm_err(display->drm, "PLL %d Power not enabled\n",
pll->info->id);
}
-static void icl_pll_enable(struct drm_i915_private *i915,
+static void icl_pll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
i915_reg_t enable_reg)
{
- intel_de_rmw(i915, enable_reg, 0, PLL_ENABLE);
+ intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
/* Timeout is actually 600us. */
- if (intel_de_wait_for_set(i915, enable_reg, PLL_LOCK, 1))
- drm_err(&i915->drm, "PLL %d not locked\n", pll->info->id);
+ if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 1))
+ drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
}
-static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll)
+static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_shared_dpll *pll)
{
u32 val;
- if (!(IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) ||
+ if (!(display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) ||
pll->info->id != DPLL_ID_ICL_DPLL0)
return;
/*
@@ -3962,22 +3952,22 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte
* Instead of the usual place for workarounds we apply this one here,
* since TRANS_CMTG_CHICKEN is only accessible while DPLL0 is enabled.
*/
- val = intel_de_read(i915, TRANS_CMTG_CHICKEN);
- val = intel_de_rmw(i915, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING);
- if (drm_WARN_ON(&i915->drm, val & ~DISABLE_DPT_CLK_GATING))
- drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
+ val = intel_de_read(display, TRANS_CMTG_CHICKEN);
+ val = intel_de_rmw(display, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING);
+ if (drm_WARN_ON(display->drm, val & ~DISABLE_DPT_CLK_GATING))
+ drm_dbg_kms(display->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
}
-static void combo_pll_enable(struct drm_i915_private *i915,
+static void combo_pll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
- i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
+ i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
- icl_pll_power_enable(i915, pll, enable_reg);
+ icl_pll_power_enable(display, pll, enable_reg);
- icl_dpll_write(i915, pll, hw_state);
+ icl_dpll_write(display, pll, hw_state);
/*
* DVFS pre sequence would be here, but in our driver the cdclk code
@@ -3985,22 +3975,22 @@ static void combo_pll_enable(struct drm_i915_private *i915,
* nothing here.
*/
- icl_pll_enable(i915, pll, enable_reg);
+ icl_pll_enable(display, pll, enable_reg);
- adlp_cmtg_clock_gating_wa(i915, pll);
+ adlp_cmtg_clock_gating_wa(display, pll);
/* DVFS post sequence would be here. See the comment above. */
}
-static void tbt_pll_enable(struct drm_i915_private *i915,
+static void tbt_pll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
- icl_pll_power_enable(i915, pll, TBT_PLL_ENABLE);
+ icl_pll_power_enable(display, pll, TBT_PLL_ENABLE);
- icl_dpll_write(i915, pll, hw_state);
+ icl_dpll_write(display, pll, hw_state);
/*
* DVFS pre sequence would be here, but in our driver the cdclk code
@@ -4008,24 +3998,24 @@ static void tbt_pll_enable(struct drm_i915_private *i915,
* nothing here.
*/
- icl_pll_enable(i915, pll, TBT_PLL_ENABLE);
+ icl_pll_enable(display, pll, TBT_PLL_ENABLE);
/* DVFS post sequence would be here. See the comment above. */
}
-static void mg_pll_enable(struct drm_i915_private *i915,
+static void mg_pll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
- i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
+ i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
- icl_pll_power_enable(i915, pll, enable_reg);
+ icl_pll_power_enable(display, pll, enable_reg);
- if (DISPLAY_VER(i915) >= 12)
- dkl_pll_write(i915, pll, hw_state);
+ if (DISPLAY_VER(display) >= 12)
+ dkl_pll_write(display, pll, hw_state);
else
- icl_mg_pll_write(i915, pll, hw_state);
+ icl_mg_pll_write(display, pll, hw_state);
/*
* DVFS pre sequence would be here, but in our driver the cdclk code
@@ -4033,12 +4023,12 @@ static void mg_pll_enable(struct drm_i915_private *i915,
* nothing here.
*/
- icl_pll_enable(i915, pll, enable_reg);
+ icl_pll_enable(display, pll, enable_reg);
/* DVFS post sequence would be here. See the comment above. */
}
-static void icl_pll_disable(struct drm_i915_private *i915,
+static void icl_pll_disable(struct intel_display *display,
struct intel_shared_dpll *pll,
i915_reg_t enable_reg)
{
@@ -4050,45 +4040,45 @@ static void icl_pll_disable(struct drm_i915_private *i915,
* nothing here.
*/
- intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0);
+ intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);
/* Timeout is actually 1us. */
- if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 1))
- drm_err(&i915->drm, "PLL %d locked\n", pll->info->id);
+ if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 1))
+ drm_err(display->drm, "PLL %d locked\n", pll->info->id);
/* DVFS post sequence would be here. See the comment above. */
- intel_de_rmw(i915, enable_reg, PLL_POWER_ENABLE, 0);
+ intel_de_rmw(display, enable_reg, PLL_POWER_ENABLE, 0);
/*
* The spec says we need to "wait" but it also says it should be
* immediate.
*/
- if (intel_de_wait_for_clear(i915, enable_reg, PLL_POWER_STATE, 1))
- drm_err(&i915->drm, "PLL %d Power not disabled\n",
+ if (intel_de_wait_for_clear(display, enable_reg, PLL_POWER_STATE, 1))
+ drm_err(display->drm, "PLL %d Power not disabled\n",
pll->info->id);
}
-static void combo_pll_disable(struct drm_i915_private *i915,
+static void combo_pll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
+ i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
- icl_pll_disable(i915, pll, enable_reg);
+ icl_pll_disable(display, pll, enable_reg);
}
-static void tbt_pll_disable(struct drm_i915_private *i915,
+static void tbt_pll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
- icl_pll_disable(i915, pll, TBT_PLL_ENABLE);
+ icl_pll_disable(display, pll, TBT_PLL_ENABLE);
}
-static void mg_pll_disable(struct drm_i915_private *i915,
+static void mg_pll_disable(struct intel_display *display,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
+ i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
- icl_pll_disable(i915, pll, enable_reg);
+ icl_pll_disable(display, pll, enable_reg);
}
static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
@@ -4489,50 +4479,49 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
/**
* intel_dpll_get_freq - calculate the DPLL's output frequency
- * @i915: i915 device
+ * @display: intel_display device
* @pll: DPLL for which to calculate the output frequency
* @dpll_hw_state: DPLL state from which to calculate the output frequency
*
* Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
*/
-int intel_dpll_get_freq(struct drm_i915_private *i915,
+int intel_dpll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
- if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
+ if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
return 0;
- return pll->info->funcs->get_freq(i915, pll, dpll_hw_state);
+ return pll->info->funcs->get_freq(display, pll, dpll_hw_state);
}
/**
* intel_dpll_get_hw_state - readout the DPLL's hardware state
- * @i915: i915 device
+ * @display: intel_display device instance
* @pll: DPLL for which to calculate the output frequency
* @dpll_hw_state: DPLL's hardware state
*
* Read out @pll's hardware state into @dpll_hw_state.
*/
-bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
+bool intel_dpll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- return pll->info->funcs->get_hw_state(i915, pll, dpll_hw_state);
+ return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
}
-static void readout_dpll_hw_state(struct drm_i915_private *i915,
+static void readout_dpll_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll)
{
- struct intel_display *display = &i915->display;
struct intel_crtc *crtc;
- pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state);
+ pll->on = intel_dpll_get_hw_state(display, pll, &pll->state.hw_state);
if (pll->on && pll->info->power_domain)
pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
pll->state.pipe_mask = 0;
- for_each_intel_crtc(&i915->drm, crtc) {
+ for_each_intel_crtc(display->drm, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
@@ -4541,7 +4530,7 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915,
}
pll->active_mask = pll->state.pipe_mask;
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"%s hw state readout: pipe_mask 0x%x, on %i\n",
pll->info->name, pll->state.pipe_mask, pll->on);
}
@@ -4552,42 +4541,40 @@ void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
i915->display.dpll.mgr->update_ref_clks(i915);
}
-void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
+void intel_dpll_readout_hw_state(struct intel_display *display)
{
- struct intel_display *display = to_intel_display(&i915->drm);
struct intel_shared_dpll *pll;
int i;
for_each_shared_dpll(display, pll, i)
- readout_dpll_hw_state(i915, pll);
+ readout_dpll_hw_state(display, pll);
}
-static void sanitize_dpll_state(struct drm_i915_private *i915,
+static void sanitize_dpll_state(struct intel_display *display,
struct intel_shared_dpll *pll)
{
if (!pll->on)
return;
- adlp_cmtg_clock_gating_wa(i915, pll);
+ adlp_cmtg_clock_gating_wa(display, pll);
if (pll->active_mask)
return;
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"%s enabled but not in use, disabling\n",
pll->info->name);
- _intel_disable_shared_dpll(i915, pll);
+ _intel_disable_shared_dpll(display, pll);
}
-void intel_dpll_sanitize_state(struct drm_i915_private *i915)
+void intel_dpll_sanitize_state(struct intel_display *display)
{
- struct intel_display *display = to_intel_display(&i915->drm);
struct intel_shared_dpll *pll;
int i;
for_each_shared_dpll(display, pll, i)
- sanitize_dpll_state(i915, pll);
+ sanitize_dpll_state(display, pll);
}
/**
@@ -4637,17 +4624,16 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
}
static void
-verify_single_dpll_state(struct drm_i915_private *i915,
+verify_single_dpll_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_crtc *crtc,
const struct intel_crtc_state *new_crtc_state)
{
- struct intel_display *display = &i915->display;
struct intel_dpll_hw_state dpll_hw_state = {};
u8 pipe_mask;
bool active;
- active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state);
+ active = intel_dpll_get_hw_state(display, pll, &dpll_hw_state);
if (!pll->info->always_on) {
INTEL_DISPLAY_STATE_WARN(display, !pll->on && pll->active_mask,
@@ -4703,14 +4689,13 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
if (new_crtc_state->shared_dpll)
- verify_single_dpll_state(i915, new_crtc_state->shared_dpll,
+ verify_single_dpll_state(display, new_crtc_state->shared_dpll,
crtc, new_crtc_state);
if (old_crtc_state->shared_dpll &&
@@ -4734,10 +4719,9 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_shared_dpll *pll;
int i;
for_each_shared_dpll(display, pll, i)
- verify_single_dpll_state(i915, pll, NULL, NULL);
+ verify_single_dpll_state(display, pll, NULL, NULL);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 42379494f347..ebd0ed79d2b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -390,7 +390,7 @@ struct intel_shared_dpll {
/* shared dpll functions */
struct intel_shared_dpll *
-intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
+intel_get_shared_dpll_by_id(struct intel_display *display,
enum intel_dpll_id id);
void assert_shared_dpll(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
@@ -413,10 +413,10 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
void intel_update_active_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
-int intel_dpll_get_freq(struct drm_i915_private *i915,
+int intel_dpll_get_freq(struct intel_display *display,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
-bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
+bool intel_dpll_get_hw_state(struct intel_display *display,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state);
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
@@ -424,8 +424,8 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
void intel_shared_dpll_init(struct drm_i915_private *i915);
void intel_dpll_update_ref_clks(struct drm_i915_private *i915);
-void intel_dpll_readout_hw_state(struct drm_i915_private *i915);
-void intel_dpll_sanitize_state(struct drm_i915_private *i915);
+void intel_dpll_readout_hw_state(struct intel_display *display);
+void intel_dpll_sanitize_state(struct intel_display *display);
void intel_dpll_dump_hw_state(struct intel_display *display,
struct drm_printer *p,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 69373031c557..b4d1a18e9fd4 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -795,7 +795,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
pipe_name(pipe));
}
- intel_dpll_readout_hw_state(i915);
+ intel_dpll_readout_hw_state(display);
drm_connector_list_iter_begin(&i915->drm, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
@@ -1014,7 +1014,7 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
intel_sanitize_all_crtcs(i915, ctx);
- intel_dpll_sanitize_state(i915);
+ intel_dpll_sanitize_state(display);
intel_wm_get_hw_state(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 8fa5a6334d10..e874a577b7d1 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -249,6 +249,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct intel_display *display = to_intel_display(crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
i915_reg_t reg;
@@ -263,7 +264,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
if (HAS_PCH_CPT(dev_priv)) {
reg = TRANS_CHICKEN2(pipe);
- val = intel_de_read(dev_priv, reg);
+ val = intel_de_read(display, reg);
/*
* Workaround: Set the timing override bit
* before enabling the pch transcoder.
@@ -272,12 +273,12 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
/* Configure frame start delay to match the CPU */
val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
- intel_de_write(dev_priv, reg, val);
+ intel_de_write(display, reg, val);
}
reg = PCH_TRANSCONF(pipe);
- val = intel_de_read(dev_priv, reg);
- pipeconf_val = intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe));
+ val = intel_de_read(display, reg);
+ pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe));
if (HAS_PCH_IBX(dev_priv)) {
/* Configure frame start delay to match the CPU */
@@ -307,9 +308,9 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
val |= TRANS_INTERLACE_PROGRESSIVE;
}
- intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
- if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
- drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
+ intel_de_write(display, reg, val | TRANS_ENABLE);
+ if (intel_de_wait_for_set(display, reg, TRANS_STATE_ENABLE, 100))
+ drm_err(display->drm, "failed to enable transcoder %c\n",
pipe_name(pipe));
}
@@ -383,15 +384,15 @@ void ilk_pch_enable(struct intel_atomic_state *state,
if (HAS_PCH_CPT(dev_priv)) {
u32 sel;
- temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
+ temp = intel_de_read(display, PCH_DPLL_SEL);
temp |= TRANS_DPLL_ENABLE(pipe);
sel = TRANS_DPLLB_SEL(pipe);
if (crtc_state->shared_dpll ==
- intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
+ intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
temp |= sel;
else
temp &= ~sel;
- intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
+ intel_de_write(display, PCH_DPLL_SEL, temp);
}
/*
@@ -420,11 +421,12 @@ void ilk_pch_enable(struct intel_atomic_state *state,
intel_crtc_has_dp_encoder(crtc_state)) {
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
- u32 bpc = (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) >> 5;
+ u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))
+ & TRANSCONF_BPC_MASK) >> 5;
i915_reg_t reg = TRANS_DP_CTL(pipe);
enum port port;
- temp = intel_de_read(dev_priv, reg);
+ temp = intel_de_read(display, reg);
temp &= ~(TRANS_DP_PORT_SEL_MASK |
TRANS_DP_VSYNC_ACTIVE_HIGH |
TRANS_DP_HSYNC_ACTIVE_HIGH |
@@ -438,10 +440,10 @@ void ilk_pch_enable(struct intel_atomic_state *state,
temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
port = intel_get_crtc_new_encoder(state, crtc_state)->port;
- drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D);
+ drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D);
temp |= TRANS_DP_PORT_SEL(port);
- intel_de_write(dev_priv, reg, temp);
+ intel_de_write(display, reg, temp);
}
ilk_enable_pch_transcoder(crtc_state);
@@ -496,6 +498,7 @@ static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct intel_display *display = to_intel_display(crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll;
enum pipe pipe = crtc->pipe;
@@ -503,12 +506,12 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
bool pll_active;
u32 tmp;
- if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
+ if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
return;
crtc_state->has_pch_encoder = true;
- tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
+ tmp = intel_de_read(display, FDI_RX_CTL(pipe));
crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
FDI_DP_PORT_WIDTH_SHIFT) + 1;
@@ -522,19 +525,19 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
*/
pll_id = (enum intel_dpll_id) pipe;
} else {
- tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
+ tmp = intel_de_read(display, PCH_DPLL_SEL);
if (tmp & TRANS_DPLLB_SEL(pipe))
pll_id = DPLL_ID_PCH_PLL_B;
else
pll_id = DPLL_ID_PCH_PLL_A;
}
- crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
+ crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id);
pll = crtc_state->shared_dpll;
- pll_active = intel_dpll_get_hw_state(dev_priv, pll,
+ pll_active = intel_dpll_get_hw_state(display, pll,
&crtc_state->dpll_hw_state);
- drm_WARN_ON(&dev_priv->drm, !pll_active);
+ drm_WARN_ON(display->drm, !pll_active);
tmp = crtc_state->dpll_hw_state.i9xx.dpll;
crtc_state->pixel_multiplier =
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 6/9] drm/i915/dpll: Use intel_display for asserting pll
2025-02-11 10:48 [PATCH 0/9] drm_i915_private to intel_display cleanup Suraj Kandpal
` (4 preceding siblings ...)
2025-02-11 10:48 ` [PATCH 5/9] drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks Suraj Kandpal
@ 2025-02-11 10:48 ` Suraj Kandpal
2025-02-11 13:12 ` Jani Nikula
2025-02-11 10:48 ` [PATCH 7/9] drm/i915/dpll: Use intel_display for update_refclk hook Suraj Kandpal
` (7 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Suraj Kandpal @ 2025-02-11 10:48 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, jani.nikula, Suraj Kandpal
Use intel_display instead of drm_i915_private to assert pll enabled
and disabled and the corresponding changes needed to make that happen.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++----------
.../i915/display/intel_display_power_well.c | 10 ++++-----
drivers/gpu/drm/i915/display/intel_dpll.c | 11 +++++-----
drivers/gpu/drm/i915/display/intel_dpll.h | 5 +++--
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 9 +++-----
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 16 ++++++--------
drivers/gpu/drm/i915/display/intel_fdi.h | 7 +++---
drivers/gpu/drm/i915/display/intel_lvds.c | 7 +++---
.../gpu/drm/i915/display/intel_pch_display.c | 2 +-
drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 12 +++++-----
drivers/gpu/drm/i915/display/vlv_dsi_pll.h | 10 +++++----
12 files changed, 55 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5f4b1d8eed3e..64a139676524 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -518,7 +518,7 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
enum pipe pipe = crtc->pipe;
u32 val;
- drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
+ drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe));
assert_planes_disabled(crtc);
@@ -529,15 +529,15 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
*/
if (HAS_GMCH(dev_priv)) {
if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
- assert_dsi_pll_enabled(dev_priv);
+ assert_dsi_pll_enabled(display);
else
- assert_pll_enabled(dev_priv, pipe);
+ assert_pll_enabled(display, pipe);
} else {
if (new_crtc_state->has_pch_encoder) {
/* if driving the PCH, we need FDI enabled */
- assert_fdi_rx_pll_enabled(dev_priv,
+ assert_fdi_rx_pll_enabled(display,
intel_crtc_pch_transcoder(crtc));
- assert_fdi_tx_pll_enabled(dev_priv,
+ assert_fdi_tx_pll_enabled(display,
(enum pipe) cpu_transcoder);
}
/* FIXME: assert CPU port conditions for SNB+ */
@@ -545,21 +545,21 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
/* Wa_22012358565:adl-p */
if (DISPLAY_VER(dev_priv) == 13)
- intel_de_rmw(dev_priv, PIPE_ARB_CTL(dev_priv, pipe),
+ intel_de_rmw(display, PIPE_ARB_CTL(display, pipe),
0, PIPE_ARB_USE_PROG_SLOTS);
if (DISPLAY_VER(dev_priv) >= 14) {
u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
u32 set = 0;
- if (DISPLAY_VER(dev_priv) == 14)
+ if (DISPLAY_VER(display) == 14)
set |= DP_FEC_BS_JITTER_WA;
intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
clear, set);
}
- val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
+ val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
if (val & TRANSCONF_ENABLE) {
/* we keep both pipes enabled on 830 */
drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
@@ -567,16 +567,16 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
}
/* Wa_1409098942:adlp+ */
- if (DISPLAY_VER(dev_priv) >= 13 &&
+ if (DISPLAY_VER(display) >= 13 &&
new_crtc_state->dsc.compression_enable) {
val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
TRANSCONF_PIXEL_COUNT_SCALING_X4);
}
- intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANSCONF(display, cpu_transcoder),
val | TRANSCONF_ENABLE);
- intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
+ intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
/*
* Until the pipe starts PIPEDSL reads will return a stale value,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index a31d1678dfc0..c2db076fd344 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1313,11 +1313,10 @@ static void vlv_dpio_cmn_power_well_enable(struct intel_display *display,
static void vlv_dpio_cmn_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
enum pipe pipe;
for_each_pipe(display, pipe)
- assert_pll_disabled(dev_priv, pipe);
+ assert_pll_disabled(display, pipe);
/* Assert common reset */
intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0);
@@ -1499,7 +1498,6 @@ static void chv_dpio_cmn_power_well_enable(struct intel_display *display,
static void chv_dpio_cmn_power_well_disable(struct intel_display *display,
struct i915_power_well *power_well)
{
- struct drm_i915_private *dev_priv = to_i915(display->drm);
enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
enum dpio_phy phy;
@@ -1509,11 +1507,11 @@ static void chv_dpio_cmn_power_well_disable(struct intel_display *display,
if (id == VLV_DISP_PW_DPIO_CMN_BC) {
phy = DPIO_PHY0;
- assert_pll_disabled(dev_priv, PIPE_A);
- assert_pll_disabled(dev_priv, PIPE_B);
+ assert_pll_disabled(display, PIPE_A);
+ assert_pll_disabled(display, PIPE_B);
} else {
phy = DPIO_PHY1;
- assert_pll_disabled(dev_priv, PIPE_C);
+ assert_pll_disabled(display, PIPE_C);
}
display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 3256b1293f7f..cc19cd51ab4d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -2329,10 +2329,9 @@ void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
}
/* Only for pre-ILK configs */
-static void assert_pll(struct drm_i915_private *dev_priv,
+static void assert_pll(struct intel_display *display,
enum pipe pipe, bool state)
{
- struct intel_display *display = &dev_priv->display;
bool cur_state;
cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;
@@ -2341,12 +2340,12 @@ static void assert_pll(struct drm_i915_private *dev_priv,
str_on_off(state), str_on_off(cur_state));
}
-void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe)
+void assert_pll_enabled(struct intel_display *display, enum pipe pipe)
{
- assert_pll(i915, pipe, true);
+ assert_pll(display, pipe, true);
}
-void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe)
+void assert_pll_disabled(struct intel_display *display, enum pipe pipe)
{
- assert_pll(i915, pipe, false);
+ assert_pll(display, pipe, false);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
index a86a79408af0..21d06cbd2ce7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll.h
@@ -13,6 +13,7 @@ struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
+struct intel_display;
struct intel_dpll_hw_state;
enum pipe;
@@ -46,7 +47,7 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state);
void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state);
void chv_crtc_clock_get(struct intel_crtc_state *crtc_state);
-void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
-void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
+void assert_pll_enabled(struct intel_display *display, enum pipe pipe);
+void assert_pll_disabled(struct intel_display *display, enum pipe pipe);
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 9976ac6322d1..104054a6df56 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -171,11 +171,10 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
}
/* For ILK+ */
-void assert_shared_dpll(struct drm_i915_private *i915,
+void assert_shared_dpll(struct intel_display *display,
struct intel_shared_dpll *pll,
bool state)
{
- struct intel_display *display = &i915->display;
bool cur_state;
struct intel_dpll_hw_state hw_state;
@@ -256,7 +255,6 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
unsigned int pipe_mask = BIT(crtc->pipe);
unsigned int old_mask;
@@ -280,7 +278,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
if (old_mask) {
drm_WARN_ON(display->drm, !pll->on);
- assert_shared_dpll_enabled(i915, pll);
+ assert_shared_dpll_enabled(display, pll);
goto out;
}
drm_WARN_ON(display->drm, pll->on);
@@ -303,7 +301,6 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
unsigned int pipe_mask = BIT(crtc->pipe);
@@ -325,7 +322,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
pll->info->name, pll->active_mask, pll->on,
crtc->base.base.id, crtc->base.name);
- assert_shared_dpll_enabled(i915, pll);
+ assert_shared_dpll_enabled(display, pll);
drm_WARN_ON(display->drm, !pll->on);
pll->active_mask &= ~pipe_mask;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index ebd0ed79d2b5..b6f2cbce13e4 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -392,7 +392,7 @@ struct intel_shared_dpll {
struct intel_shared_dpll *
intel_get_shared_dpll_by_id(struct intel_display *display,
enum intel_dpll_id id);
-void assert_shared_dpll(struct drm_i915_private *i915,
+void assert_shared_dpll(struct intel_display *display,
struct intel_shared_dpll *pll,
bool state);
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 3e8d6d8af780..9ebe80bfaab6 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -80,14 +80,13 @@ void assert_fdi_rx_disabled(struct drm_i915_private *i915, enum pipe pipe)
assert_fdi_rx(i915, pipe, false);
}
-void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915,
+void assert_fdi_tx_pll_enabled(struct intel_display *display,
enum pipe pipe)
{
- struct intel_display *display = &i915->display;
bool cur_state;
/* ILK FDI PLL is always enabled */
- if (IS_IRONLAKE(i915))
+ if (display->platform.ironlake)
return;
/* On Haswell, DDI ports are responsible for the FDI PLL setup */
@@ -99,10 +98,9 @@ void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915,
"FDI TX PLL assertion failure, should be active but is disabled\n");
}
-static void assert_fdi_rx_pll(struct drm_i915_private *i915,
+static void assert_fdi_rx_pll(struct intel_display *display,
enum pipe pipe, bool state)
{
- struct intel_display *display = &i915->display;
bool cur_state;
cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE;
@@ -111,14 +109,14 @@ static void assert_fdi_rx_pll(struct drm_i915_private *i915,
str_on_off(state), str_on_off(cur_state));
}
-void assert_fdi_rx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe)
+void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe)
{
- assert_fdi_rx_pll(i915, pipe, true);
+ assert_fdi_rx_pll(display, pipe, true);
}
-void assert_fdi_rx_pll_disabled(struct drm_i915_private *i915, enum pipe pipe)
+void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe)
{
- assert_fdi_rx_pll(i915, pipe, false);
+ assert_fdi_rx_pll(display, pipe, false);
}
void intel_fdi_link_train(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h b/drivers/gpu/drm/i915/display/intel_fdi.h
index 477ff0136934..b5be09efb36f 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.h
+++ b/drivers/gpu/drm/i915/display/intel_fdi.h
@@ -13,6 +13,7 @@ struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
+struct intel_display;
struct intel_encoder;
struct intel_link_bw_limits;
@@ -41,8 +42,8 @@ void assert_fdi_tx_enabled(struct drm_i915_private *i915, enum pipe pipe);
void assert_fdi_tx_disabled(struct drm_i915_private *i915, enum pipe pipe);
void assert_fdi_rx_enabled(struct drm_i915_private *i915, enum pipe pipe);
void assert_fdi_rx_disabled(struct drm_i915_private *i915, enum pipe pipe);
-void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
-void assert_fdi_rx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
-void assert_fdi_rx_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
+void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe);
+void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe);
+void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe);
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index e86b3a86db82..6b05db2c10ba 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -240,6 +240,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(state);
struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -248,10 +249,10 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
u32 temp;
if (HAS_PCH_SPLIT(i915)) {
- assert_fdi_rx_pll_disabled(i915, pipe);
- assert_shared_dpll_disabled(i915, crtc_state->shared_dpll);
+ assert_fdi_rx_pll_disabled(display, pipe);
+ assert_shared_dpll_disabled(display, crtc_state->shared_dpll);
} else {
- assert_pll_disabled(i915, pipe);
+ assert_pll_disabled(display, pipe);
}
intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index e874a577b7d1..75ff5592312f 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -256,7 +256,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
u32 val, pipeconf_val;
/* Make sure PCH DPLL is enabled */
- assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
+ assert_shared_dpll_enabled(display, crtc_state->shared_dpll);
/* FDI must be feeding us bits for PCH ports */
assert_fdi_tx_enabled(dev_priv, pipe);
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
index ac69eaece0fd..2ed47e7d1051 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
@@ -590,9 +590,9 @@ void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);
}
-static void assert_dsi_pll(struct drm_i915_private *i915, bool state)
+static void assert_dsi_pll(struct intel_display *display, bool state)
{
- struct intel_display *display = &i915->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
bool cur_state;
vlv_cck_get(i915);
@@ -604,12 +604,12 @@ static void assert_dsi_pll(struct drm_i915_private *i915, bool state)
str_on_off(state), str_on_off(cur_state));
}
-void assert_dsi_pll_enabled(struct drm_i915_private *i915)
+void assert_dsi_pll_enabled(struct intel_display *display)
{
- assert_dsi_pll(i915, true);
+ assert_dsi_pll(display, true);
}
-void assert_dsi_pll_disabled(struct drm_i915_private *i915)
+void assert_dsi_pll_disabled(struct intel_display *display)
{
- assert_dsi_pll(i915, false);
+ assert_dsi_pll(display, false);
}
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.h b/drivers/gpu/drm/i915/display/vlv_dsi_pll.h
index fbe5113dbeb9..a032cc2a2524 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.h
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.h
@@ -11,6 +11,7 @@
enum port;
struct drm_i915_private;
struct intel_crtc_state;
+struct intel_display;
struct intel_encoder;
int vlv_dsi_pll_compute(struct intel_encoder *encoder,
@@ -33,13 +34,14 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
#ifdef I915
-void assert_dsi_pll_enabled(struct drm_i915_private *i915);
-void assert_dsi_pll_disabled(struct drm_i915_private *i915);
+void assert_dsi_pll_enabled(struct intel_display *display);
+void assert_dsi_pll_disabled(struct intel_display *display);
#else
-static inline void assert_dsi_pll_enabled(struct drm_i915_private *i915)
+static inline void assert_dsi_pll_enabled(struct intel_display *display)
{
}
-static inline void assert_dsi_pll_disabled(struct drm_i915_private *i915)
+
+static inline void assert_dsi_pll_disabled(struct intel_display *display)
{
}
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 7/9] drm/i915/dpll: Use intel_display for update_refclk hook
2025-02-11 10:48 [PATCH 0/9] drm_i915_private to intel_display cleanup Suraj Kandpal
` (5 preceding siblings ...)
2025-02-11 10:48 ` [PATCH 6/9] drm/i915/dpll: Use intel_display for asserting pll Suraj Kandpal
@ 2025-02-11 10:48 ` Suraj Kandpal
2025-02-11 13:12 ` Jani Nikula
2025-02-11 10:48 ` [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for shared_dpll_init Suraj Kandpal
` (6 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Suraj Kandpal @ 2025-02-11 10:48 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, jani.nikula, Suraj Kandpal
Use intel_display instead of drm_i915_private for update_refclk hook.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../drm/i915/display/intel_display_driver.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 32 +++++++++----------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +-
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index d448672fdfa4..978f530c810e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -453,7 +453,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
intel_update_czclk(i915);
intel_display_driver_init_hw(display);
- intel_dpll_update_ref_clks(i915);
+ intel_dpll_update_ref_clks(display);
if (display->cdclk.max_cdclk_freq == 0)
intel_update_max_cdclk(display);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 104054a6df56..f94da1ffc8ce 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -109,7 +109,7 @@ struct intel_dpll_mgr {
void (*update_active_dpll)(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
- void (*update_ref_clks)(struct drm_i915_private *i915);
+ void (*update_ref_clks)(struct intel_display *display);
void (*dump_hw_state)(struct drm_printer *p,
const struct intel_dpll_hw_state *dpll_hw_state);
bool (*compare_hw_state)(const struct intel_dpll_hw_state *a,
@@ -1240,14 +1240,14 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
return 0;
}
-static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
+static void hsw_update_dpll_ref_clks(struct intel_display *display)
{
- i915->display.dpll.ref_clks.ssc = 135000;
+ display->dpll.ref_clks.ssc = 135000;
/* Non-SSC is only used on non-ULT HSW. */
- if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
- i915->display.dpll.ref_clks.nssc = 24000;
+ if (intel_de_read(display, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
+ display->dpll.ref_clks.nssc = 24000;
else
- i915->display.dpll.ref_clks.nssc = 135000;
+ display->dpll.ref_clks.nssc = 135000;
}
static void hsw_dump_hw_state(struct drm_printer *p,
@@ -1977,10 +1977,10 @@ static int skl_ddi_pll_get_freq(struct intel_display *display,
return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);
}
-static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
+static void skl_update_dpll_ref_clks(struct intel_display *display)
{
/* No SSC ref */
- i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
+ display->dpll.ref_clks.nssc = display->cdclk.hw.ref;
}
static void skl_dump_hw_state(struct drm_printer *p,
@@ -2446,10 +2446,10 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
return 0;
}
-static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
+static void bxt_update_dpll_ref_clks(struct intel_display *display)
{
- i915->display.dpll.ref_clks.ssc = 100000;
- i915->display.dpll.ref_clks.nssc = 100000;
+ display->dpll.ref_clks.ssc = 100000;
+ display->dpll.ref_clks.nssc = 100000;
/* DSI non-SSC ref 19.2MHz */
}
@@ -4078,10 +4078,10 @@ static void mg_pll_disable(struct intel_display *display,
icl_pll_disable(display, pll, enable_reg);
}
-static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
+static void icl_update_dpll_ref_clks(struct intel_display *display)
{
/* No SSC ref */
- i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
+ display->dpll.ref_clks.nssc = display->cdclk.hw.ref;
}
static void icl_dump_hw_state(struct drm_printer *p,
@@ -4532,10 +4532,10 @@ static void readout_dpll_hw_state(struct intel_display *display,
pll->info->name, pll->state.pipe_mask, pll->on);
}
-void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
+void intel_dpll_update_ref_clks(struct intel_display *display)
{
- if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks)
- i915->display.dpll.mgr->update_ref_clks(i915);
+ if (display->dpll.mgr && display->dpll.mgr->update_ref_clks)
+ display->dpll.mgr->update_ref_clks(display);
}
void intel_dpll_readout_hw_state(struct intel_display *display)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index b6f2cbce13e4..3d988f17f31d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -423,7 +423,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
void intel_shared_dpll_init(struct drm_i915_private *i915);
-void intel_dpll_update_ref_clks(struct drm_i915_private *i915);
+void intel_dpll_update_ref_clks(struct intel_display *display);
void intel_dpll_readout_hw_state(struct intel_display *display);
void intel_dpll_sanitize_state(struct intel_display *display);
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for shared_dpll_init
2025-02-11 10:48 [PATCH 0/9] drm_i915_private to intel_display cleanup Suraj Kandpal
` (6 preceding siblings ...)
2025-02-11 10:48 ` [PATCH 7/9] drm/i915/dpll: Use intel_display for update_refclk hook Suraj Kandpal
@ 2025-02-11 10:48 ` Suraj Kandpal
2025-02-11 13:14 ` Jani Nikula
2025-02-11 10:48 ` [PATCH 9/9] drm/i915/dpll: Replace all other leftover drm_i915_private Suraj Kandpal
` (5 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Suraj Kandpal @ 2025-02-11 10:48 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, jani.nikula, Suraj Kandpal
Use intel_display as an argument for intel_shared_dpll_init() and
replace drm_i915_private in function wherever possible.
While at it prefer using display->platform.xx over IS_PLATFORM.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../drm/i915/display/intel_display_driver.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 49 ++++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 3 +-
3 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 978f530c810e..852f1129a058 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -448,7 +448,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
}
intel_plane_possible_crtcs_init(display);
- intel_shared_dpll_init(i915);
+ intel_shared_dpll_init(display);
intel_fdi_pll_freq_update(i915);
intel_update_czclk(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f94da1ffc8ce..26b6b9372fa3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2042,8 +2042,8 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
{
const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
- enum dpio_phy phy;
- enum dpio_channel ch;
+ enum dpio_phy phy = DPIO_PHY0;
+ enum dpio_channel ch = DPIO_CH0;
u32 temp;
bxt_port_to_phy_channel(display, port, &phy, &ch);
@@ -4302,40 +4302,41 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
/**
* intel_shared_dpll_init - Initialize shared DPLLs
- * @i915: i915 device
+ * @display: intel_display device
*
- * Initialize shared DPLLs for @i915.
+ * Initialize shared DPLLs for @display.
*/
-void intel_shared_dpll_init(struct drm_i915_private *i915)
+void intel_shared_dpll_init(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
const struct intel_dpll_mgr *dpll_mgr = NULL;
const struct dpll_info *dpll_info;
int i;
- mutex_init(&i915->display.dpll.lock);
+ mutex_init(&display->dpll.lock);
- if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915))
+ if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
/* No shared DPLLs on DG2; port PLLs are part of the PHY */
dpll_mgr = NULL;
- else if (IS_ALDERLAKE_P(i915))
+ else if (display->platform.alderlake_p)
dpll_mgr = &adlp_pll_mgr;
- else if (IS_ALDERLAKE_S(i915))
+ else if (display->platform.alderlake_s)
dpll_mgr = &adls_pll_mgr;
- else if (IS_DG1(i915))
+ else if (display->platform.dg1)
dpll_mgr = &dg1_pll_mgr;
- else if (IS_ROCKETLAKE(i915))
+ else if (display->platform.rocketlake)
dpll_mgr = &rkl_pll_mgr;
- else if (DISPLAY_VER(i915) >= 12)
+ else if (DISPLAY_VER(display) >= 12)
dpll_mgr = &tgl_pll_mgr;
- else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915))
+ else if (display->platform.jasperlake || display->platform.elkhartlake)
dpll_mgr = &ehl_pll_mgr;
- else if (DISPLAY_VER(i915) >= 11)
+ else if (DISPLAY_VER(display) >= 11)
dpll_mgr = &icl_pll_mgr;
- else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+ else if (display->platform.geminilake || display->platform.broxton)
dpll_mgr = &bxt_pll_mgr;
- else if (DISPLAY_VER(i915) == 9)
+ else if (DISPLAY_VER(display) == 9)
dpll_mgr = &skl_pll_mgr;
- else if (HAS_DDI(i915))
+ else if (HAS_DDI(display))
dpll_mgr = &hsw_pll_mgr;
else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915))
dpll_mgr = &pch_pll_mgr;
@@ -4346,20 +4347,20 @@ void intel_shared_dpll_init(struct drm_i915_private *i915)
dpll_info = dpll_mgr->dpll_info;
for (i = 0; dpll_info[i].name; i++) {
- if (drm_WARN_ON(&i915->drm,
- i >= ARRAY_SIZE(i915->display.dpll.shared_dplls)))
+ if (drm_WARN_ON(display->drm,
+ i >= ARRAY_SIZE(display->dpll.shared_dplls)))
break;
/* must fit into unsigned long bitmask on 32bit */
- if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32))
+ if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
break;
- i915->display.dpll.shared_dplls[i].info = &dpll_info[i];
- i915->display.dpll.shared_dplls[i].index = i;
+ display->dpll.shared_dplls[i].info = &dpll_info[i];
+ display->dpll.shared_dplls[i].index = i;
}
- i915->display.dpll.mgr = dpll_mgr;
- i915->display.dpll.num_shared_dpll = i;
+ display->dpll.mgr = dpll_mgr;
+ display->dpll.num_shared_dpll = i;
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 3d988f17f31d..caffb084830c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -35,7 +35,6 @@
((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
enum tc_port;
-struct drm_i915_private;
struct drm_printer;
struct intel_atomic_state;
struct intel_crtc;
@@ -422,7 +421,7 @@ bool intel_dpll_get_hw_state(struct intel_display *display,
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
-void intel_shared_dpll_init(struct drm_i915_private *i915);
+void intel_shared_dpll_init(struct intel_display *display);
void intel_dpll_update_ref_clks(struct intel_display *display);
void intel_dpll_readout_hw_state(struct intel_display *display);
void intel_dpll_sanitize_state(struct intel_display *display);
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 9/9] drm/i915/dpll: Replace all other leftover drm_i915_private
2025-02-11 10:48 [PATCH 0/9] drm_i915_private to intel_display cleanup Suraj Kandpal
` (7 preceding siblings ...)
2025-02-11 10:48 ` [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for shared_dpll_init Suraj Kandpal
@ 2025-02-11 10:48 ` Suraj Kandpal
2025-02-11 13:17 ` Jani Nikula
2025-02-11 12:10 ` ✗ Fi.CI.CHECKPATCH: warning for drm_i915_private to intel_display cleanup (rev2) Patchwork
` (4 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Suraj Kandpal @ 2025-02-11 10:48 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, jani.nikula, Suraj Kandpal
Replace all other left over drm_i915_private with intel_display
in dpll_mgr.c.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 99 +++++++++----------
1 file changed, 48 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 26b6b9372fa3..96abb7e295a2 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -117,11 +117,10 @@ struct intel_dpll_mgr {
};
static void
-intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915,
+intel_atomic_duplicate_dpll_state(struct intel_display *display,
struct intel_shared_dpll_state *shared_dpll)
{
struct intel_shared_dpll *pll;
- struct intel_display *display = to_intel_display(&i915->drm);
int i;
/* Copy shared dpll state */
@@ -139,7 +138,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
if (!state->dpll_set) {
state->dpll_set = true;
- intel_atomic_duplicate_dpll_state(to_i915(s->dev),
+ intel_atomic_duplicate_dpll_state(to_intel_display(state),
state->shared_dpll);
}
@@ -420,13 +419,13 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
const struct intel_shared_dpll *pll,
struct intel_shared_dpll_state *shared_dpll_state)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
- drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
+ drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
shared_dpll_state->pipe_mask |= BIT(crtc->pipe);
- drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] reserving %s\n",
+ drm_dbg_kms(display->drm, "[CRTC:%d:%s] reserving %s\n",
crtc->base.base.id, crtc->base.name, pll->info->name);
}
@@ -459,13 +458,13 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
const struct intel_shared_dpll *pll,
struct intel_shared_dpll_state *shared_dpll_state)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
- drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
+ drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe);
- drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] releasing %s\n",
+ drm_dbg_kms(display->drm, "[CRTC:%d:%s] releasing %s\n",
crtc->base.base.id, crtc->base.name, pll->info->name);
}
@@ -545,9 +544,8 @@ static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
return val & DPLL_VCO_ENABLE;
}
-static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915)
+static void ibx_assert_pch_refclk_enabled(struct intel_display *display)
{
- struct intel_display *display = &i915->display;
u32 val;
bool enabled;
@@ -562,12 +560,11 @@ static void ibx_pch_dpll_enable(struct intel_display *display,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
const enum intel_dpll_id id = pll->info->id;
/* PCH refclock must be enabled first */
- ibx_assert_pch_refclk_enabled(i915);
+ ibx_assert_pch_refclk_enabled(display);
intel_de_write(display, PCH_FP0(id), hw_state->fp0);
intel_de_write(display, PCH_FP1(id), hw_state->fp1);
@@ -1074,7 +1071,7 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
static int
hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
int clock = crtc_state->port_clock;
switch (clock / 2) {
@@ -1083,7 +1080,7 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
case 270000:
return 0;
default:
- drm_dbg_kms(&i915->drm, "Invalid clock for DP: %d\n",
+ drm_dbg_kms(display->drm, "Invalid clock for DP: %d\n",
clock);
return -EINVAL;
}
@@ -2255,7 +2252,7 @@ static int
bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
struct dpll *clk_div)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
/* Calculate HDMI div */
/*
@@ -2265,7 +2262,7 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
if (!bxt_find_best_dpll(crtc_state, clk_div))
return -EINVAL;
- drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
+ drm_WARN_ON(display->drm, clk_div->m1 != 2);
return 0;
}
@@ -2273,7 +2270,7 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
struct dpll *clk_div)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
int i;
*clk_div = bxt_dp_clk_val[0];
@@ -2284,16 +2281,16 @@ static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
}
}
- chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div);
+ chv_calc_dpll_params(display->dpll.ref_clks.nssc, clk_div);
- drm_WARN_ON(&i915->drm, clk_div->vco == 0 ||
+ drm_WARN_ON(display->drm, clk_div->vco == 0 ||
clk_div->dot != crtc_state->port_clock);
}
static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
const struct dpll *clk_div)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;
int clock = crtc_state->port_clock;
int vco = clk_div->vco;
@@ -2317,7 +2314,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
gain_ctl = 1;
targ_cnt = 9;
} else {
- drm_err(&i915->drm, "Invalid VCO\n");
+ drm_err(display->drm, "Invalid VCO\n");
return -EINVAL;
}
@@ -2700,9 +2697,9 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
struct skl_wrpll_params *pll_params)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
const struct icl_combo_pll_params *params =
- i915->display.dpll.ref_clks.nssc == 24000 ?
+ display->dpll.ref_clks.nssc == 24000 ?
icl_dp_combo_pll_24MHz_values :
icl_dp_combo_pll_19_2MHz_values;
int clock = crtc_state->port_clock;
@@ -2722,12 +2719,12 @@ static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
struct skl_wrpll_params *pll_params)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
- if (DISPLAY_VER(i915) >= 12) {
- switch (i915->display.dpll.ref_clks.nssc) {
+ if (DISPLAY_VER(display) >= 12) {
+ switch (display->dpll.ref_clks.nssc) {
default:
- MISSING_CASE(i915->display.dpll.ref_clks.nssc);
+ MISSING_CASE(display->dpll.ref_clks.nssc);
fallthrough;
case 19200:
case 38400:
@@ -2738,9 +2735,9 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
break;
}
} else {
- switch (i915->display.dpll.ref_clks.nssc) {
+ switch (display->dpll.ref_clks.nssc) {
default:
- MISSING_CASE(i915->display.dpll.ref_clks.nssc);
+ MISSING_CASE(display->dpll.ref_clks.nssc);
fallthrough;
case 19200:
case 38400:
@@ -2998,9 +2995,9 @@ static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
struct intel_dpll_hw_state *dpll_hw_state)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
- int refclk_khz = i915->display.dpll.ref_clks.nssc;
+ int refclk_khz = display->dpll.ref_clks.nssc;
int clock = crtc_state->port_clock;
u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
u32 iref_ndiv, iref_trim, iref_pulse_w;
@@ -3010,7 +3007,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
u64 tmp;
bool use_ssc = false;
bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
- bool is_dkl = DISPLAY_VER(i915) >= 12;
+ bool is_dkl = DISPLAY_VER(display) >= 12;
int ret;
ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
@@ -3108,8 +3105,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
DKL_PLL_DIV0_PROP_COEFF(prop_coeff) |
DKL_PLL_DIV0_FBPREDIV(m1div) |
DKL_PLL_DIV0_FBDIV_INT(m2div_int);
- if (i915->display.vbt.override_afc_startup) {
- u8 val = i915->display.vbt.override_afc_startup_val;
+ if (display->vbt.override_afc_startup) {
+ u8 val = display->vbt.override_afc_startup_val;
hw_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val);
}
@@ -3347,7 +3344,6 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct icl_port_dpll *port_dpll =
@@ -3355,13 +3351,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
enum port port = encoder->port;
unsigned long dpll_mask;
- if (IS_ALDERLAKE_S(i915)) {
+ if (display->platform.alderlake_s) {
dpll_mask =
BIT(DPLL_ID_DG1_DPLL3) |
BIT(DPLL_ID_DG1_DPLL2) |
BIT(DPLL_ID_ICL_DPLL1) |
BIT(DPLL_ID_ICL_DPLL0);
- } else if (IS_DG1(i915)) {
+ } else if (display->platform.dg1) {
if (port == PORT_D || port == PORT_E) {
dpll_mask =
BIT(DPLL_ID_DG1_DPLL2) |
@@ -3371,12 +3367,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
BIT(DPLL_ID_DG1_DPLL0) |
BIT(DPLL_ID_DG1_DPLL1);
}
- } else if (IS_ROCKETLAKE(i915)) {
+ } else if (display->platform.rocketlake) {
dpll_mask =
BIT(DPLL_ID_EHL_DPLL4) |
BIT(DPLL_ID_ICL_DPLL1) |
BIT(DPLL_ID_ICL_DPLL0);
- } else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
+ } else if ((display->platform.jasperlake ||
+ display->platform.elkhartlake) &&
port != PORT_A) {
dpll_mask =
BIT(DPLL_ID_EHL_DPLL4) |
@@ -4381,10 +4378,10 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
- const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
+ struct intel_display *display = to_intel_display(state);
+ const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
- if (drm_WARN_ON(&i915->drm, !dpll_mgr))
+ if (drm_WARN_ON(display->drm, !dpll_mgr))
return -EINVAL;
return dpll_mgr->compute_dplls(state, crtc, encoder);
@@ -4414,10 +4411,10 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
- const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
+ struct intel_display *display = to_intel_display(state);
+ const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
- if (drm_WARN_ON(&i915->drm, !dpll_mgr))
+ if (drm_WARN_ON(display->drm, !dpll_mgr))
return -EINVAL;
return dpll_mgr->get_dplls(state, crtc, encoder);
@@ -4437,8 +4434,8 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
void intel_release_shared_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
- const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
+ struct intel_display *display = to_intel_display(state);
+ const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
/*
* FIXME: this function is called for every platform having a
@@ -4466,10 +4463,10 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
+ struct intel_display *display = to_intel_display(encoder);
+ const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
- if (drm_WARN_ON(&i915->drm, !dpll_mgr))
+ if (drm_WARN_ON(display->drm, !dpll_mgr))
return;
dpll_mgr->update_active_dpll(state, crtc, encoder);
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm_i915_private to intel_display cleanup (rev2)
2025-02-11 10:48 [PATCH 0/9] drm_i915_private to intel_display cleanup Suraj Kandpal
` (8 preceding siblings ...)
2025-02-11 10:48 ` [PATCH 9/9] drm/i915/dpll: Replace all other leftover drm_i915_private Suraj Kandpal
@ 2025-02-11 12:10 ` Patchwork
2025-02-11 12:10 ` ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2025-02-11 12:10 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-gfx
== Series Details ==
Series: drm_i915_private to intel_display cleanup (rev2)
URL : https://patchwork.freedesktop.org/series/144588/
State : warning
== Summary ==
Error: dim checkpatch failed
37f096e9961c drm/i915/display_debug_fs: Use intel_display wherever possible
-:54: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 63)
#54: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:95:
+ if (DISPLAY_VER(display) >= 9)
/* no global SR status; inspect per-plane WM */;
total: 0 errors, 1 warnings, 0 checks, 507 lines checked
a052eb583c24 drm/i915/display_debug_fs: Prefer using display->platform
56335358a845 drm/i915/dpll: Change param to intel_display in for_each_shared_dpll
-:141: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__display' - possible side-effects?
#141: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.h:33:
+#define for_each_shared_dpll(__display, __pll, __i) \
+ for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
+ ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
-:141: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#141: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.h:33:
+#define for_each_shared_dpll(__display, __pll, __i) \
+ for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
+ ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
total: 0 errors, 0 warnings, 2 checks, 218 lines checked
f35ee0e7dd2c drm/i915/dpll: Use intel_display for dpll dump and compare hw state
b06cd75b3507 drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks
d6e03bdf8b64 drm/i915/dpll: Use intel_display for asserting pll
5082d7956254 drm/i915/dpll: Use intel_display for update_refclk hook
4df213d2a364 drm/i915/dpll: Accept intel_display as argument for shared_dpll_init
547b40419030 drm/i915/dpll: Replace all other leftover drm_i915_private
^ permalink raw reply [flat|nested] 29+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm_i915_private to intel_display cleanup (rev2)
2025-02-11 10:48 [PATCH 0/9] drm_i915_private to intel_display cleanup Suraj Kandpal
` (9 preceding siblings ...)
2025-02-11 12:10 ` ✗ Fi.CI.CHECKPATCH: warning for drm_i915_private to intel_display cleanup (rev2) Patchwork
@ 2025-02-11 12:10 ` Patchwork
2025-02-11 13:45 ` ✓ i915.CI.BAT: success " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2025-02-11 12:10 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-gfx
== Series Details ==
Series: drm_i915_private to intel_display cleanup (rev2)
URL : https://patchwork.freedesktop.org/series/144588/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/9] drm/i915/display_debug_fs: Use intel_display wherever possible
2025-02-11 10:48 ` [PATCH 1/9] drm/i915/display_debug_fs: Use intel_display wherever possible Suraj Kandpal
@ 2025-02-11 12:51 ` Jani Nikula
2025-02-11 12:52 ` Jani Nikula
1 sibling, 0 replies; 29+ messages in thread
From: Jani Nikula @ 2025-02-11 12:51 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Use struct intel_display wherever possible in intel_display_debug_fs.c
> to reduce the use of drm_i915_private.
>
> --v2
> -Rebase
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> .../drm/i915/display/intel_display_debugfs.c | 158 +++++++++---------
> 1 file changed, 81 insertions(+), 77 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 89e5eea90be8..d85924caa26e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -68,17 +68,17 @@ static int intel_display_caps(struct seq_file *m, void *data)
>
> static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
>
> - spin_lock(&dev_priv->display.fb_tracking.lock);
> + spin_lock(&display->fb_tracking.lock);
>
> seq_printf(m, "FB tracking busy bits: 0x%08x\n",
> - dev_priv->display.fb_tracking.busy_bits);
> + display->fb_tracking.busy_bits);
>
> seq_printf(m, "FB tracking flip bits: 0x%08x\n",
> - dev_priv->display.fb_tracking.flip_bits);
> + display->fb_tracking.flip_bits);
>
> - spin_unlock(&dev_priv->display.fb_tracking.lock);
> + spin_unlock(&display->fb_tracking.lock);
>
> return 0;
> }
> @@ -86,25 +86,25 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
> static int i915_sr_status(struct seq_file *m, void *unused)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> - struct intel_display *display = &dev_priv->display;
> + struct intel_display *display = node_to_intel_display(m->private);
> intel_wakeref_t wakeref;
> bool sr_enabled = false;
>
> wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);
>
> - if (DISPLAY_VER(dev_priv) >= 9)
> + if (DISPLAY_VER(display) >= 9)
> /* no global SR status; inspect per-plane WM */;
> else if (HAS_PCH_SPLIT(dev_priv))
> - sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM_LP_ENABLE;
> + sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;
> else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
> IS_I945G(dev_priv) || IS_I945GM(dev_priv))
> - sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
> + sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
> else if (IS_I915GM(dev_priv))
> - sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN;
> + sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;
> else if (IS_PINEVIEW(dev_priv))
> - sr_enabled = intel_de_read(dev_priv, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
> + sr_enabled = intel_de_read(display, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
> + sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>
> intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
>
> @@ -115,12 +115,12 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>
> static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
> struct intel_framebuffer *fbdev_fb = NULL;
> struct drm_framebuffer *drm_fb;
>
> #ifdef CONFIG_DRM_FBDEV_EMULATION
> - fbdev_fb = intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev);
> + fbdev_fb = intel_fbdev_framebuffer(display->fbdev.fbdev);
> if (fbdev_fb) {
> seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
> fbdev_fb->base.width,
> @@ -134,8 +134,8 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
> }
> #endif
>
> - mutex_lock(&dev_priv->drm.mode_config.fb_lock);
> - drm_for_each_fb(drm_fb, &dev_priv->drm) {
> + mutex_lock(&display->drm->mode_config.fb_lock);
> + drm_for_each_fb(drm_fb, display->drm) {
> struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
> if (fb == fbdev_fb)
> continue;
> @@ -150,7 +150,7 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
> intel_bo_describe(m, intel_fb_bo(&fb->base));
> seq_putc(m, '\n');
> }
> - mutex_unlock(&dev_priv->drm.mode_config.fb_lock);
> + mutex_unlock(&display->drm->mode_config.fb_lock);
>
> return 0;
> }
> @@ -179,14 +179,14 @@ static void intel_encoder_info(struct seq_file *m,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
> struct drm_connector_list_iter conn_iter;
> struct drm_connector *connector;
>
> seq_printf(m, "\t[ENCODER:%d:%s]: connectors:\n",
> encoder->base.base.id, encoder->base.name);
>
> - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> + drm_connector_list_iter_begin(display->drm, &conn_iter);
> drm_for_each_connector_iter(connector, &conn_iter) {
> const struct drm_connector_state *conn_state =
> connector->state;
> @@ -391,10 +391,10 @@ static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane)
>
> static void intel_plane_info(struct seq_file *m, struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
> struct intel_plane *plane;
>
> - for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> + for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
> seq_printf(m, "\t[PLANE:%d:%s]: type=%s\n",
> plane->base.base.id, plane->base.name,
> plane_type(plane->base.type));
> @@ -537,7 +537,7 @@ static void crtc_updates_add(struct intel_crtc *crtc)
>
> static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
> struct drm_printer p = drm_seq_file_printer(m);
> const struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
> @@ -571,7 +571,7 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
>
> intel_vdsc_state_dump(&p, 1, crtc_state);
>
> - for_each_intel_encoder_mask(&dev_priv->drm, encoder,
> + for_each_intel_encoder_mask(display->drm, encoder,
> crtc_state->uapi.encoder_mask)
> intel_encoder_info(m, crtc, encoder);
>
> @@ -586,6 +586,7 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
>
> static int i915_display_info(struct seq_file *m, void *unused)
> {
> + struct intel_display *display = node_to_intel_display(m->private);
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> struct intel_crtc *crtc;
> struct drm_connector *connector;
> @@ -594,22 +595,22 @@ static int i915_display_info(struct seq_file *m, void *unused)
>
> wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>
> - drm_modeset_lock_all(&dev_priv->drm);
> + drm_modeset_lock_all(display->drm);
>
> seq_printf(m, "CRTC info\n");
> seq_printf(m, "---------\n");
> - for_each_intel_crtc(&dev_priv->drm, crtc)
> + for_each_intel_crtc(display->drm, crtc)
> intel_crtc_info(m, crtc);
>
> seq_printf(m, "\n");
> seq_printf(m, "Connector info\n");
> seq_printf(m, "--------------\n");
> - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> + drm_connector_list_iter_begin(display->drm, &conn_iter);
> drm_for_each_connector_iter(connector, &conn_iter)
> intel_connector_info(m, connector);
> drm_connector_list_iter_end(&conn_iter);
>
> - drm_modeset_unlock_all(&dev_priv->drm);
> + drm_modeset_unlock_all(display->drm);
>
> intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>
> @@ -618,11 +619,11 @@ static int i915_display_info(struct seq_file *m, void *unused)
>
> static int i915_display_capabilities(struct seq_file *m, void *unused)
> {
> - struct drm_i915_private *i915 = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
> struct drm_printer p = drm_seq_file_printer(m);
>
> - intel_display_device_info_print(DISPLAY_INFO(i915),
> - DISPLAY_RUNTIME_INFO(i915), &p);
> + intel_display_device_info_print(DISPLAY_INFO(display),
> + DISPLAY_RUNTIME_INFO(display), &p);
>
> return 0;
> }
> @@ -630,15 +631,16 @@ static int i915_display_capabilities(struct seq_file *m, void *unused)
> static int i915_shared_dplls_info(struct seq_file *m, void *unused)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
> struct drm_printer p = drm_seq_file_printer(m);
> struct intel_shared_dpll *pll;
> int i;
>
> - drm_modeset_lock_all(&dev_priv->drm);
> + drm_modeset_lock_all(display->drm);
>
> drm_printf(&p, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n",
> - dev_priv->display.dpll.ref_clks.nssc,
> - dev_priv->display.dpll.ref_clks.ssc);
> + display->dpll.ref_clks.nssc,
> + display->dpll.ref_clks.ssc);
>
> for_each_shared_dpll(dev_priv, pll, i) {
> drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,
> @@ -649,25 +651,25 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
> drm_printf(&p, " tracked hardware state:\n");
> intel_dpll_dump_hw_state(dev_priv, &p, &pll->state.hw_state);
> }
> - drm_modeset_unlock_all(&dev_priv->drm);
> + drm_modeset_unlock_all(display->drm);
>
> return 0;
> }
>
> static int i915_ddb_info(struct seq_file *m, void *unused)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
> struct skl_ddb_entry *entry;
> struct intel_crtc *crtc;
>
> - if (DISPLAY_VER(dev_priv) < 9)
> + if (DISPLAY_VER(display) < 9)
> return -ENODEV;
>
> - drm_modeset_lock_all(&dev_priv->drm);
> + drm_modeset_lock_all(display->drm);
>
> seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
>
> - for_each_intel_crtc(&dev_priv->drm, crtc) {
> + for_each_intel_crtc(display->drm, crtc) {
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
> enum pipe pipe = crtc->pipe;
> @@ -687,16 +689,16 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
> entry->end, skl_ddb_entry_size(entry));
> }
>
> - drm_modeset_unlock_all(&dev_priv->drm);
> + drm_modeset_unlock_all(display->drm);
>
> return 0;
> }
>
> static bool
> -intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
> +intel_lpsp_power_well_enabled(struct intel_display *display,
> enum i915_power_well_id power_well_id)
> {
> - struct intel_display *display = &i915->display;
> + struct drm_i915_private *i915 = to_i915(display->drm);
> intel_wakeref_t wakeref;
> bool is_enabled;
>
> @@ -710,15 +712,16 @@ intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
>
> static int i915_lpsp_status(struct seq_file *m, void *unused)
> {
> + struct intel_display *display = node_to_intel_display(m->private);
> struct drm_i915_private *i915 = node_to_i915(m->private);
> bool lpsp_enabled = false;
>
> - if (DISPLAY_VER(i915) >= 13 || IS_DISPLAY_VER(i915, 9, 10)) {
> - lpsp_enabled = !intel_lpsp_power_well_enabled(i915, SKL_DISP_PW_2);
> - } else if (IS_DISPLAY_VER(i915, 11, 12)) {
> - lpsp_enabled = !intel_lpsp_power_well_enabled(i915, ICL_DISP_PW_3);
> + if (DISPLAY_VER(display) >= 13 || IS_DISPLAY_VER(display, 9, 10)) {
> + lpsp_enabled = !intel_lpsp_power_well_enabled(display, SKL_DISP_PW_2);
> + } else if (IS_DISPLAY_VER(display, 11, 12)) {
> + lpsp_enabled = !intel_lpsp_power_well_enabled(display, ICL_DISP_PW_3);
> } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> - lpsp_enabled = !intel_lpsp_power_well_enabled(i915, HSW_DISP_PW_GLOBAL);
> + lpsp_enabled = !intel_lpsp_power_well_enabled(display, HSW_DISP_PW_GLOBAL);
> } else {
> seq_puts(m, "LPSP: not supported\n");
> return 0;
> @@ -731,13 +734,13 @@ static int i915_lpsp_status(struct seq_file *m, void *unused)
>
> static int i915_dp_mst_info(struct seq_file *m, void *unused)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
> struct intel_encoder *intel_encoder;
> struct intel_digital_port *dig_port;
> struct drm_connector *connector;
> struct drm_connector_list_iter conn_iter;
>
> - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> + drm_connector_list_iter_begin(display->drm, &conn_iter);
> drm_for_each_connector_iter(connector, &conn_iter) {
> if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
> continue;
> @@ -765,7 +768,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
> const char __user *ubuf,
> size_t cnt, loff_t *ppos)
> {
> - struct drm_i915_private *dev_priv = filp->private_data;
> + struct intel_display *display = filp->private_data;
> struct intel_crtc *crtc;
> int ret;
> bool reset;
> @@ -777,7 +780,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
> if (!reset)
> return cnt;
>
> - for_each_intel_crtc(&dev_priv->drm, crtc) {
> + for_each_intel_crtc(display->drm, crtc) {
> struct drm_crtc_commit *commit;
> struct intel_crtc_state *crtc_state;
>
> @@ -794,7 +797,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
> }
>
> if (!ret && crtc_state->hw.active) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Re-arming FIFO underruns on pipe %c\n",
> pipe_name(crtc->pipe));
>
> @@ -807,7 +810,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
> return ret;
> }
>
> - intel_fbc_reset_underrun(&dev_priv->display);
> + intel_fbc_reset_underrun(display);
>
> return cnt;
> }
> @@ -839,7 +842,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
> struct drm_minor *minor = i915->drm.primary;
>
> debugfs_create_file("i915_fifo_underrun_reset", 0644, minor->debugfs_root,
> - to_i915(minor->dev), &i915_fifo_underrun_reset_ops);
> + to_intel_display(minor->dev), &i915_fifo_underrun_reset_ops);
Please don't inline to_intel_display(minor->dev), add a separate local
variable instead. Eventually we'll pass display to
intel_display_debugfs_register(), the local variable will get removed,
and this place doesn't need to be changed.
Other than that,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> drm_debugfs_create_files(intel_display_debugfs_list,
> ARRAY_SIZE(intel_display_debugfs_list),
> @@ -860,8 +863,9 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
> static int i915_lpsp_capability_show(struct seq_file *m, void *data)
> {
> struct intel_connector *connector = m->private;
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct intel_encoder *encoder = intel_attached_encoder(connector);
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> int connector_type = connector->base.connector_type;
> bool lpsp_capable = false;
>
> @@ -871,19 +875,19 @@ static int i915_lpsp_capability_show(struct seq_file *m, void *data)
> if (connector->base.status != connector_status_connected)
> return -ENODEV;
>
> - if (DISPLAY_VER(i915) >= 13)
> + if (DISPLAY_VER(display) >= 13)
> lpsp_capable = encoder->port <= PORT_B;
> - else if (DISPLAY_VER(i915) >= 12)
> + else if (DISPLAY_VER(display) >= 12)
> /*
> * Actually TGL can drive LPSP on port till DDI_C
> * but there is no physical connected DDI_C on TGL sku's,
> * even driver is not initializing DDI_C port for gen12.
> */
> lpsp_capable = encoder->port <= PORT_B;
> - else if (DISPLAY_VER(i915) == 11)
> + else if (DISPLAY_VER(display) == 11)
> lpsp_capable = (connector_type == DRM_MODE_CONNECTOR_DSI ||
> connector_type == DRM_MODE_CONNECTOR_eDP);
> - else if (IS_DISPLAY_VER(i915, 9, 10))
> + else if (IS_DISPLAY_VER(display, 9, 10))
> lpsp_capable = (encoder->port == PORT_A &&
> (connector_type == DRM_MODE_CONNECTOR_DSI ||
> connector_type == DRM_MODE_CONNECTOR_eDP ||
> @@ -900,7 +904,7 @@ DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability);
> static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
> {
> struct intel_connector *connector = m->private;
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct drm_crtc *crtc;
> struct intel_dp *intel_dp;
> struct drm_modeset_acquire_ctx ctx;
> @@ -912,7 +916,7 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>
> do {
> try_again = false;
> - ret = drm_modeset_lock(&i915->drm.mode_config.connection_mutex,
> + ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,
> &ctx);
> if (ret) {
> if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) {
> @@ -973,7 +977,7 @@ static ssize_t i915_dsc_fec_support_write(struct file *file,
> {
> struct seq_file *m = file->private_data;
> struct intel_connector *connector = m->private;
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct intel_encoder *encoder = intel_attached_encoder(connector);
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> bool dsc_enable = false;
> @@ -982,14 +986,14 @@ static ssize_t i915_dsc_fec_support_write(struct file *file,
> if (len == 0)
> return 0;
>
> - drm_dbg(&i915->drm,
> + drm_dbg(display->drm,
> "Copied %zu bytes from user to force DSC\n", len);
>
> ret = kstrtobool_from_user(ubuf, len, &dsc_enable);
> if (ret < 0)
> return ret;
>
> - drm_dbg(&i915->drm, "Got %s for DSC Enable\n",
> + drm_dbg(display->drm, "Got %s for DSC Enable\n",
> (dsc_enable) ? "true" : "false");
> intel_dp->force_dsc_en = dsc_enable;
>
> @@ -1016,7 +1020,7 @@ static const struct file_operations i915_dsc_fec_support_fops = {
> static int i915_dsc_bpc_show(struct seq_file *m, void *data)
> {
> struct intel_connector *connector = m->private;
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct intel_encoder *encoder = intel_attached_encoder(connector);
> struct drm_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> @@ -1025,7 +1029,7 @@ static int i915_dsc_bpc_show(struct seq_file *m, void *data)
> if (!encoder)
> return -ENODEV;
>
> - ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
> + ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
> if (ret)
> return ret;
>
> @@ -1038,7 +1042,7 @@ static int i915_dsc_bpc_show(struct seq_file *m, void *data)
> crtc_state = to_intel_crtc_state(crtc->state);
> seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component);
>
> -out: drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
> +out: drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
>
> return ret;
> }
> @@ -1082,7 +1086,7 @@ static const struct file_operations i915_dsc_bpc_fops = {
> static int i915_dsc_output_format_show(struct seq_file *m, void *data)
> {
> struct intel_connector *connector = m->private;
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct intel_encoder *encoder = intel_attached_encoder(connector);
> struct drm_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> @@ -1091,7 +1095,7 @@ static int i915_dsc_output_format_show(struct seq_file *m, void *data)
> if (!encoder)
> return -ENODEV;
>
> - ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
> + ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
> if (ret)
> return ret;
>
> @@ -1105,7 +1109,7 @@ static int i915_dsc_output_format_show(struct seq_file *m, void *data)
> seq_printf(m, "DSC_Output_Format: %s\n",
> intel_output_format_name(crtc_state->output_format));
>
> -out: drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
> +out: drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
>
> return ret;
> }
> @@ -1149,7 +1153,7 @@ static const struct file_operations i915_dsc_output_format_fops = {
> static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
> {
> struct intel_connector *connector = m->private;
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct intel_encoder *encoder = intel_attached_encoder(connector);
> struct drm_crtc *crtc;
> struct intel_dp *intel_dp;
> @@ -1158,7 +1162,7 @@ static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
> if (!encoder)
> return -ENODEV;
>
> - ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
> + ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
> if (ret)
> return ret;
>
> @@ -1173,7 +1177,7 @@ static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
> str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
>
> out:
> - drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
> + drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
>
> return ret;
> }
> @@ -1184,8 +1188,8 @@ static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
> {
> struct seq_file *m = file->private_data;
> struct intel_connector *connector = m->private;
> + struct intel_display *display = to_intel_display(connector);
> struct intel_encoder *encoder = intel_attached_encoder(connector);
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> bool dsc_fractional_bpp_enable = false;
> int ret;
> @@ -1193,14 +1197,14 @@ static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
> if (len == 0)
> return 0;
>
> - drm_dbg(&i915->drm,
> + drm_dbg(display->drm,
> "Copied %zu bytes from user to force fractional bpp for DSC\n", len);
>
> ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
> if (ret < 0)
> return ret;
>
> - drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
> + drm_dbg(display->drm, "Got %s for DSC Fractional BPP Enable\n",
> (dsc_fractional_bpp_enable) ? "true" : "false");
> intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
>
> @@ -1329,7 +1333,7 @@ static const struct file_operations i915_joiner_fops = {
> */
> void intel_connector_debugfs_add(struct intel_connector *connector)
> {
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct dentry *root = connector->base.debugfs_entry;
> int connector_type = connector->base.connector_type;
>
> @@ -1344,7 +1348,7 @@ void intel_connector_debugfs_add(struct intel_connector *connector)
> intel_alpm_lobf_debugfs_add(connector);
> intel_dp_link_training_debugfs_add(connector);
>
> - if (DISPLAY_VER(i915) >= 11 &&
> + if (DISPLAY_VER(display) >= 11 &&
> ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !connector->mst_port) ||
> connector_type == DRM_MODE_CONNECTOR_eDP)) {
> debugfs_create_file("i915_dsc_fec_support", 0644, root,
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/9] drm/i915/display_debug_fs: Use intel_display wherever possible
2025-02-11 10:48 ` [PATCH 1/9] drm/i915/display_debug_fs: Use intel_display wherever possible Suraj Kandpal
2025-02-11 12:51 ` Jani Nikula
@ 2025-02-11 12:52 ` Jani Nikula
1 sibling, 0 replies; 29+ messages in thread
From: Jani Nikula @ 2025-02-11 12:52 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Use struct intel_display wherever possible in intel_display_debug_fs.c
> to reduce the use of drm_i915_private.
PS. "drm/i915/display_debug_fs:" is not a prefix we've ever used.
>
> --v2
> -Rebase
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> .../drm/i915/display/intel_display_debugfs.c | 158 +++++++++---------
> 1 file changed, 81 insertions(+), 77 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 89e5eea90be8..d85924caa26e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -68,17 +68,17 @@ static int intel_display_caps(struct seq_file *m, void *data)
>
> static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
>
> - spin_lock(&dev_priv->display.fb_tracking.lock);
> + spin_lock(&display->fb_tracking.lock);
>
> seq_printf(m, "FB tracking busy bits: 0x%08x\n",
> - dev_priv->display.fb_tracking.busy_bits);
> + display->fb_tracking.busy_bits);
>
> seq_printf(m, "FB tracking flip bits: 0x%08x\n",
> - dev_priv->display.fb_tracking.flip_bits);
> + display->fb_tracking.flip_bits);
>
> - spin_unlock(&dev_priv->display.fb_tracking.lock);
> + spin_unlock(&display->fb_tracking.lock);
>
> return 0;
> }
> @@ -86,25 +86,25 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
> static int i915_sr_status(struct seq_file *m, void *unused)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> - struct intel_display *display = &dev_priv->display;
> + struct intel_display *display = node_to_intel_display(m->private);
> intel_wakeref_t wakeref;
> bool sr_enabled = false;
>
> wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);
>
> - if (DISPLAY_VER(dev_priv) >= 9)
> + if (DISPLAY_VER(display) >= 9)
> /* no global SR status; inspect per-plane WM */;
> else if (HAS_PCH_SPLIT(dev_priv))
> - sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM_LP_ENABLE;
> + sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;
> else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
> IS_I945G(dev_priv) || IS_I945GM(dev_priv))
> - sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
> + sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
> else if (IS_I915GM(dev_priv))
> - sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN;
> + sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;
> else if (IS_PINEVIEW(dev_priv))
> - sr_enabled = intel_de_read(dev_priv, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
> + sr_enabled = intel_de_read(display, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
> + sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>
> intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
>
> @@ -115,12 +115,12 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>
> static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
> struct intel_framebuffer *fbdev_fb = NULL;
> struct drm_framebuffer *drm_fb;
>
> #ifdef CONFIG_DRM_FBDEV_EMULATION
> - fbdev_fb = intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev);
> + fbdev_fb = intel_fbdev_framebuffer(display->fbdev.fbdev);
> if (fbdev_fb) {
> seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
> fbdev_fb->base.width,
> @@ -134,8 +134,8 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
> }
> #endif
>
> - mutex_lock(&dev_priv->drm.mode_config.fb_lock);
> - drm_for_each_fb(drm_fb, &dev_priv->drm) {
> + mutex_lock(&display->drm->mode_config.fb_lock);
> + drm_for_each_fb(drm_fb, display->drm) {
> struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
> if (fb == fbdev_fb)
> continue;
> @@ -150,7 +150,7 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
> intel_bo_describe(m, intel_fb_bo(&fb->base));
> seq_putc(m, '\n');
> }
> - mutex_unlock(&dev_priv->drm.mode_config.fb_lock);
> + mutex_unlock(&display->drm->mode_config.fb_lock);
>
> return 0;
> }
> @@ -179,14 +179,14 @@ static void intel_encoder_info(struct seq_file *m,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
> struct drm_connector_list_iter conn_iter;
> struct drm_connector *connector;
>
> seq_printf(m, "\t[ENCODER:%d:%s]: connectors:\n",
> encoder->base.base.id, encoder->base.name);
>
> - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> + drm_connector_list_iter_begin(display->drm, &conn_iter);
> drm_for_each_connector_iter(connector, &conn_iter) {
> const struct drm_connector_state *conn_state =
> connector->state;
> @@ -391,10 +391,10 @@ static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane)
>
> static void intel_plane_info(struct seq_file *m, struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
> struct intel_plane *plane;
>
> - for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> + for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
> seq_printf(m, "\t[PLANE:%d:%s]: type=%s\n",
> plane->base.base.id, plane->base.name,
> plane_type(plane->base.type));
> @@ -537,7 +537,7 @@ static void crtc_updates_add(struct intel_crtc *crtc)
>
> static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
> struct drm_printer p = drm_seq_file_printer(m);
> const struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
> @@ -571,7 +571,7 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
>
> intel_vdsc_state_dump(&p, 1, crtc_state);
>
> - for_each_intel_encoder_mask(&dev_priv->drm, encoder,
> + for_each_intel_encoder_mask(display->drm, encoder,
> crtc_state->uapi.encoder_mask)
> intel_encoder_info(m, crtc, encoder);
>
> @@ -586,6 +586,7 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
>
> static int i915_display_info(struct seq_file *m, void *unused)
> {
> + struct intel_display *display = node_to_intel_display(m->private);
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> struct intel_crtc *crtc;
> struct drm_connector *connector;
> @@ -594,22 +595,22 @@ static int i915_display_info(struct seq_file *m, void *unused)
>
> wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>
> - drm_modeset_lock_all(&dev_priv->drm);
> + drm_modeset_lock_all(display->drm);
>
> seq_printf(m, "CRTC info\n");
> seq_printf(m, "---------\n");
> - for_each_intel_crtc(&dev_priv->drm, crtc)
> + for_each_intel_crtc(display->drm, crtc)
> intel_crtc_info(m, crtc);
>
> seq_printf(m, "\n");
> seq_printf(m, "Connector info\n");
> seq_printf(m, "--------------\n");
> - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> + drm_connector_list_iter_begin(display->drm, &conn_iter);
> drm_for_each_connector_iter(connector, &conn_iter)
> intel_connector_info(m, connector);
> drm_connector_list_iter_end(&conn_iter);
>
> - drm_modeset_unlock_all(&dev_priv->drm);
> + drm_modeset_unlock_all(display->drm);
>
> intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>
> @@ -618,11 +619,11 @@ static int i915_display_info(struct seq_file *m, void *unused)
>
> static int i915_display_capabilities(struct seq_file *m, void *unused)
> {
> - struct drm_i915_private *i915 = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
> struct drm_printer p = drm_seq_file_printer(m);
>
> - intel_display_device_info_print(DISPLAY_INFO(i915),
> - DISPLAY_RUNTIME_INFO(i915), &p);
> + intel_display_device_info_print(DISPLAY_INFO(display),
> + DISPLAY_RUNTIME_INFO(display), &p);
>
> return 0;
> }
> @@ -630,15 +631,16 @@ static int i915_display_capabilities(struct seq_file *m, void *unused)
> static int i915_shared_dplls_info(struct seq_file *m, void *unused)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
> struct drm_printer p = drm_seq_file_printer(m);
> struct intel_shared_dpll *pll;
> int i;
>
> - drm_modeset_lock_all(&dev_priv->drm);
> + drm_modeset_lock_all(display->drm);
>
> drm_printf(&p, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n",
> - dev_priv->display.dpll.ref_clks.nssc,
> - dev_priv->display.dpll.ref_clks.ssc);
> + display->dpll.ref_clks.nssc,
> + display->dpll.ref_clks.ssc);
>
> for_each_shared_dpll(dev_priv, pll, i) {
> drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,
> @@ -649,25 +651,25 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
> drm_printf(&p, " tracked hardware state:\n");
> intel_dpll_dump_hw_state(dev_priv, &p, &pll->state.hw_state);
> }
> - drm_modeset_unlock_all(&dev_priv->drm);
> + drm_modeset_unlock_all(display->drm);
>
> return 0;
> }
>
> static int i915_ddb_info(struct seq_file *m, void *unused)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
> struct skl_ddb_entry *entry;
> struct intel_crtc *crtc;
>
> - if (DISPLAY_VER(dev_priv) < 9)
> + if (DISPLAY_VER(display) < 9)
> return -ENODEV;
>
> - drm_modeset_lock_all(&dev_priv->drm);
> + drm_modeset_lock_all(display->drm);
>
> seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
>
> - for_each_intel_crtc(&dev_priv->drm, crtc) {
> + for_each_intel_crtc(display->drm, crtc) {
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
> enum pipe pipe = crtc->pipe;
> @@ -687,16 +689,16 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
> entry->end, skl_ddb_entry_size(entry));
> }
>
> - drm_modeset_unlock_all(&dev_priv->drm);
> + drm_modeset_unlock_all(display->drm);
>
> return 0;
> }
>
> static bool
> -intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
> +intel_lpsp_power_well_enabled(struct intel_display *display,
> enum i915_power_well_id power_well_id)
> {
> - struct intel_display *display = &i915->display;
> + struct drm_i915_private *i915 = to_i915(display->drm);
> intel_wakeref_t wakeref;
> bool is_enabled;
>
> @@ -710,15 +712,16 @@ intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
>
> static int i915_lpsp_status(struct seq_file *m, void *unused)
> {
> + struct intel_display *display = node_to_intel_display(m->private);
> struct drm_i915_private *i915 = node_to_i915(m->private);
> bool lpsp_enabled = false;
>
> - if (DISPLAY_VER(i915) >= 13 || IS_DISPLAY_VER(i915, 9, 10)) {
> - lpsp_enabled = !intel_lpsp_power_well_enabled(i915, SKL_DISP_PW_2);
> - } else if (IS_DISPLAY_VER(i915, 11, 12)) {
> - lpsp_enabled = !intel_lpsp_power_well_enabled(i915, ICL_DISP_PW_3);
> + if (DISPLAY_VER(display) >= 13 || IS_DISPLAY_VER(display, 9, 10)) {
> + lpsp_enabled = !intel_lpsp_power_well_enabled(display, SKL_DISP_PW_2);
> + } else if (IS_DISPLAY_VER(display, 11, 12)) {
> + lpsp_enabled = !intel_lpsp_power_well_enabled(display, ICL_DISP_PW_3);
> } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> - lpsp_enabled = !intel_lpsp_power_well_enabled(i915, HSW_DISP_PW_GLOBAL);
> + lpsp_enabled = !intel_lpsp_power_well_enabled(display, HSW_DISP_PW_GLOBAL);
> } else {
> seq_puts(m, "LPSP: not supported\n");
> return 0;
> @@ -731,13 +734,13 @@ static int i915_lpsp_status(struct seq_file *m, void *unused)
>
> static int i915_dp_mst_info(struct seq_file *m, void *unused)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_display *display = node_to_intel_display(m->private);
> struct intel_encoder *intel_encoder;
> struct intel_digital_port *dig_port;
> struct drm_connector *connector;
> struct drm_connector_list_iter conn_iter;
>
> - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> + drm_connector_list_iter_begin(display->drm, &conn_iter);
> drm_for_each_connector_iter(connector, &conn_iter) {
> if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
> continue;
> @@ -765,7 +768,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
> const char __user *ubuf,
> size_t cnt, loff_t *ppos)
> {
> - struct drm_i915_private *dev_priv = filp->private_data;
> + struct intel_display *display = filp->private_data;
> struct intel_crtc *crtc;
> int ret;
> bool reset;
> @@ -777,7 +780,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
> if (!reset)
> return cnt;
>
> - for_each_intel_crtc(&dev_priv->drm, crtc) {
> + for_each_intel_crtc(display->drm, crtc) {
> struct drm_crtc_commit *commit;
> struct intel_crtc_state *crtc_state;
>
> @@ -794,7 +797,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
> }
>
> if (!ret && crtc_state->hw.active) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Re-arming FIFO underruns on pipe %c\n",
> pipe_name(crtc->pipe));
>
> @@ -807,7 +810,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
> return ret;
> }
>
> - intel_fbc_reset_underrun(&dev_priv->display);
> + intel_fbc_reset_underrun(display);
>
> return cnt;
> }
> @@ -839,7 +842,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
> struct drm_minor *minor = i915->drm.primary;
>
> debugfs_create_file("i915_fifo_underrun_reset", 0644, minor->debugfs_root,
> - to_i915(minor->dev), &i915_fifo_underrun_reset_ops);
> + to_intel_display(minor->dev), &i915_fifo_underrun_reset_ops);
>
> drm_debugfs_create_files(intel_display_debugfs_list,
> ARRAY_SIZE(intel_display_debugfs_list),
> @@ -860,8 +863,9 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
> static int i915_lpsp_capability_show(struct seq_file *m, void *data)
> {
> struct intel_connector *connector = m->private;
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct intel_encoder *encoder = intel_attached_encoder(connector);
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> int connector_type = connector->base.connector_type;
> bool lpsp_capable = false;
>
> @@ -871,19 +875,19 @@ static int i915_lpsp_capability_show(struct seq_file *m, void *data)
> if (connector->base.status != connector_status_connected)
> return -ENODEV;
>
> - if (DISPLAY_VER(i915) >= 13)
> + if (DISPLAY_VER(display) >= 13)
> lpsp_capable = encoder->port <= PORT_B;
> - else if (DISPLAY_VER(i915) >= 12)
> + else if (DISPLAY_VER(display) >= 12)
> /*
> * Actually TGL can drive LPSP on port till DDI_C
> * but there is no physical connected DDI_C on TGL sku's,
> * even driver is not initializing DDI_C port for gen12.
> */
> lpsp_capable = encoder->port <= PORT_B;
> - else if (DISPLAY_VER(i915) == 11)
> + else if (DISPLAY_VER(display) == 11)
> lpsp_capable = (connector_type == DRM_MODE_CONNECTOR_DSI ||
> connector_type == DRM_MODE_CONNECTOR_eDP);
> - else if (IS_DISPLAY_VER(i915, 9, 10))
> + else if (IS_DISPLAY_VER(display, 9, 10))
> lpsp_capable = (encoder->port == PORT_A &&
> (connector_type == DRM_MODE_CONNECTOR_DSI ||
> connector_type == DRM_MODE_CONNECTOR_eDP ||
> @@ -900,7 +904,7 @@ DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability);
> static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
> {
> struct intel_connector *connector = m->private;
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct drm_crtc *crtc;
> struct intel_dp *intel_dp;
> struct drm_modeset_acquire_ctx ctx;
> @@ -912,7 +916,7 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>
> do {
> try_again = false;
> - ret = drm_modeset_lock(&i915->drm.mode_config.connection_mutex,
> + ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,
> &ctx);
> if (ret) {
> if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) {
> @@ -973,7 +977,7 @@ static ssize_t i915_dsc_fec_support_write(struct file *file,
> {
> struct seq_file *m = file->private_data;
> struct intel_connector *connector = m->private;
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct intel_encoder *encoder = intel_attached_encoder(connector);
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> bool dsc_enable = false;
> @@ -982,14 +986,14 @@ static ssize_t i915_dsc_fec_support_write(struct file *file,
> if (len == 0)
> return 0;
>
> - drm_dbg(&i915->drm,
> + drm_dbg(display->drm,
> "Copied %zu bytes from user to force DSC\n", len);
>
> ret = kstrtobool_from_user(ubuf, len, &dsc_enable);
> if (ret < 0)
> return ret;
>
> - drm_dbg(&i915->drm, "Got %s for DSC Enable\n",
> + drm_dbg(display->drm, "Got %s for DSC Enable\n",
> (dsc_enable) ? "true" : "false");
> intel_dp->force_dsc_en = dsc_enable;
>
> @@ -1016,7 +1020,7 @@ static const struct file_operations i915_dsc_fec_support_fops = {
> static int i915_dsc_bpc_show(struct seq_file *m, void *data)
> {
> struct intel_connector *connector = m->private;
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct intel_encoder *encoder = intel_attached_encoder(connector);
> struct drm_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> @@ -1025,7 +1029,7 @@ static int i915_dsc_bpc_show(struct seq_file *m, void *data)
> if (!encoder)
> return -ENODEV;
>
> - ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
> + ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
> if (ret)
> return ret;
>
> @@ -1038,7 +1042,7 @@ static int i915_dsc_bpc_show(struct seq_file *m, void *data)
> crtc_state = to_intel_crtc_state(crtc->state);
> seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component);
>
> -out: drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
> +out: drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
>
> return ret;
> }
> @@ -1082,7 +1086,7 @@ static const struct file_operations i915_dsc_bpc_fops = {
> static int i915_dsc_output_format_show(struct seq_file *m, void *data)
> {
> struct intel_connector *connector = m->private;
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct intel_encoder *encoder = intel_attached_encoder(connector);
> struct drm_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> @@ -1091,7 +1095,7 @@ static int i915_dsc_output_format_show(struct seq_file *m, void *data)
> if (!encoder)
> return -ENODEV;
>
> - ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
> + ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
> if (ret)
> return ret;
>
> @@ -1105,7 +1109,7 @@ static int i915_dsc_output_format_show(struct seq_file *m, void *data)
> seq_printf(m, "DSC_Output_Format: %s\n",
> intel_output_format_name(crtc_state->output_format));
>
> -out: drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
> +out: drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
>
> return ret;
> }
> @@ -1149,7 +1153,7 @@ static const struct file_operations i915_dsc_output_format_fops = {
> static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
> {
> struct intel_connector *connector = m->private;
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct intel_encoder *encoder = intel_attached_encoder(connector);
> struct drm_crtc *crtc;
> struct intel_dp *intel_dp;
> @@ -1158,7 +1162,7 @@ static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
> if (!encoder)
> return -ENODEV;
>
> - ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
> + ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
> if (ret)
> return ret;
>
> @@ -1173,7 +1177,7 @@ static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
> str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
>
> out:
> - drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
> + drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
>
> return ret;
> }
> @@ -1184,8 +1188,8 @@ static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
> {
> struct seq_file *m = file->private_data;
> struct intel_connector *connector = m->private;
> + struct intel_display *display = to_intel_display(connector);
> struct intel_encoder *encoder = intel_attached_encoder(connector);
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> bool dsc_fractional_bpp_enable = false;
> int ret;
> @@ -1193,14 +1197,14 @@ static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
> if (len == 0)
> return 0;
>
> - drm_dbg(&i915->drm,
> + drm_dbg(display->drm,
> "Copied %zu bytes from user to force fractional bpp for DSC\n", len);
>
> ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
> if (ret < 0)
> return ret;
>
> - drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
> + drm_dbg(display->drm, "Got %s for DSC Fractional BPP Enable\n",
> (dsc_fractional_bpp_enable) ? "true" : "false");
> intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
>
> @@ -1329,7 +1333,7 @@ static const struct file_operations i915_joiner_fops = {
> */
> void intel_connector_debugfs_add(struct intel_connector *connector)
> {
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct dentry *root = connector->base.debugfs_entry;
> int connector_type = connector->base.connector_type;
>
> @@ -1344,7 +1348,7 @@ void intel_connector_debugfs_add(struct intel_connector *connector)
> intel_alpm_lobf_debugfs_add(connector);
> intel_dp_link_training_debugfs_add(connector);
>
> - if (DISPLAY_VER(i915) >= 11 &&
> + if (DISPLAY_VER(display) >= 11 &&
> ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !connector->mst_port) ||
> connector_type == DRM_MODE_CONNECTOR_eDP)) {
> debugfs_create_file("i915_dsc_fec_support", 0644, root,
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 2/9] drm/i915/display_debug_fs: Prefer using display->platform
2025-02-11 10:48 ` [PATCH 2/9] drm/i915/display_debug_fs: Prefer using display->platform Suraj Kandpal
@ 2025-02-11 12:53 ` Jani Nikula
0 siblings, 0 replies; 29+ messages in thread
From: Jani Nikula @ 2025-02-11 12:53 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Prefer using display->platform.xx instead of IS_PLATFORM() checks
Could've been squashed to the previous patch?
Ditto about the subject prefix as previous patch.
Regardless,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index d85924caa26e..991c1726f522 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -96,14 +96,14 @@ static int i915_sr_status(struct seq_file *m, void *unused)
> /* no global SR status; inspect per-plane WM */;
> else if (HAS_PCH_SPLIT(dev_priv))
> sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;
> - else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
> - IS_I945G(dev_priv) || IS_I945GM(dev_priv))
> + else if (display->platform.i965gm || display->platform.g4x ||
> + display->platform.i945g || display->platform.i945gm)
> sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
> - else if (IS_I915GM(dev_priv))
> + else if (display->platform.i915gm)
> sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;
> - else if (IS_PINEVIEW(dev_priv))
> + else if (display->platform.pineview)
> sr_enabled = intel_de_read(display, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
> - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> + else if (display->platform.valleyview || display->platform.cherryview)
> sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>
> intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/9] drm/i915/dpll: Change param to intel_display in for_each_shared_dpll
2025-02-11 10:48 ` [PATCH 3/9] drm/i915/dpll: Change param to intel_display in for_each_shared_dpll Suraj Kandpal
@ 2025-02-11 12:56 ` Jani Nikula
0 siblings, 0 replies; 29+ messages in thread
From: Jani Nikula @ 2025-02-11 12:56 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Change the argument of for_each_shared_dpll to take intel_display which
> helps move as an ongoing effort to get rid off the dependency on
> drm_i915_private. Some opportunistic changes in intel_pch_refclk done
> too.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> .../drm/i915/display/intel_display_debugfs.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 ++++++++-----
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 6 ++--
> .../gpu/drm/i915/display/intel_pch_refclk.c | 36 +++++++++----------
> 4 files changed, 37 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 991c1726f522..87e6f4000101 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -642,7 +642,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
> display->dpll.ref_clks.nssc,
> display->dpll.ref_clks.ssc);
>
> - for_each_shared_dpll(dev_priv, pll, i) {
> + for_each_shared_dpll(display, pll, i) {
> drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,
> pll->info->name, pll->info->id);
> drm_printf(&p, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index cb2ef317d219..171d16e91c61 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -121,10 +121,11 @@ intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915,
> struct intel_shared_dpll_state *shared_dpll)
> {
> struct intel_shared_dpll *pll;
> + struct intel_display *display = to_intel_display(&i915->drm);
Nitpick, these could just be:
struct intel_display *display = &i915->display;
And they'll go away once the function parameter gets changed to display.
Anyway,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
either way
> int i;
>
> /* Copy shared dpll state */
> - for_each_shared_dpll(i915, pll, i)
> + for_each_shared_dpll(display, pll, i)
> shared_dpll[pll->index] = pll->state;
> }
>
> @@ -157,10 +158,11 @@ struct intel_shared_dpll *
> intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
> enum intel_dpll_id id)
> {
> + struct intel_display *display = to_intel_display(&i915->drm);
> struct intel_shared_dpll *pll;
> int i;
>
> - for_each_shared_dpll(i915, pll, i) {
> + for_each_shared_dpll(display, pll, i) {
> if (pll->info->id == id)
> return pll;
> }
> @@ -344,12 +346,13 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> static unsigned long
> intel_dpll_mask_all(struct drm_i915_private *i915)
> {
> + struct intel_display *display = to_intel_display(&i915->drm);
> struct intel_shared_dpll *pll;
> unsigned long dpll_mask = 0;
> int i;
>
> - for_each_shared_dpll(i915, pll, i) {
> - drm_WARN_ON(&i915->drm, dpll_mask & BIT(pll->info->id));
> + for_each_shared_dpll(display, pll, i) {
> + drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id));
>
> dpll_mask |= BIT(pll->info->id);
> }
> @@ -513,7 +516,7 @@ static void intel_put_dpll(struct intel_atomic_state *state,
> */
> void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
> {
> - struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_display *display = to_intel_display(state);
> struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
> struct intel_shared_dpll *pll;
> int i;
> @@ -521,7 +524,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
> if (!state->dpll_set)
> return;
>
> - for_each_shared_dpll(i915, pll, i)
> + for_each_shared_dpll(display, pll, i)
> swap(pll->state, shared_dpll[pll->index]);
> }
>
> @@ -4551,10 +4554,11 @@ void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
>
> void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
> {
> + struct intel_display *display = to_intel_display(&i915->drm);
> struct intel_shared_dpll *pll;
> int i;
>
> - for_each_shared_dpll(i915, pll, i)
> + for_each_shared_dpll(display, pll, i)
> readout_dpll_hw_state(i915, pll);
> }
>
> @@ -4578,10 +4582,11 @@ static void sanitize_dpll_state(struct drm_i915_private *i915,
>
> void intel_dpll_sanitize_state(struct drm_i915_private *i915)
> {
> + struct intel_display *display = to_intel_display(&i915->drm);
> struct intel_shared_dpll *pll;
> int i;
>
> - for_each_shared_dpll(i915, pll, i)
> + for_each_shared_dpll(display, pll, i)
> sanitize_dpll_state(i915, pll);
> }
>
> @@ -4728,10 +4733,11 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
>
> void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
> {
> + struct intel_display *display = to_intel_display(state);
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> struct intel_shared_dpll *pll;
> int i;
>
> - for_each_shared_dpll(i915, pll, i)
> + for_each_shared_dpll(display, pll, i)
> verify_single_dpll_state(i915, pll, NULL, NULL);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 3eee76874304..382bdf8f0b65 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -30,9 +30,9 @@
> #include "intel_display_power.h"
> #include "intel_wakeref.h"
>
> -#define for_each_shared_dpll(__i915, __pll, __i) \
> - for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \
> - ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++)
> +#define for_each_shared_dpll(__display, __pll, __i) \
> + for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
> + ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
>
> enum tc_port;
> struct drm_i915_private;
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> index 71471c1d7dc9..68e953d2b124 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -492,7 +492,7 @@ static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
>
> static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct intel_display *display = to_intel_display(&dev_priv->drm);
> struct intel_encoder *encoder;
> struct intel_shared_dpll *pll;
> int i;
> @@ -505,7 +505,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
> bool using_ssc_source = false;
>
> /* We need to take the global config into account */
> - for_each_intel_encoder(&dev_priv->drm, encoder) {
> + for_each_intel_encoder(display->drm, encoder) {
> switch (encoder->type) {
> case INTEL_OUTPUT_LVDS:
> has_panel = true;
> @@ -522,7 +522,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
> }
>
> if (HAS_PCH_IBX(dev_priv)) {
> - has_ck505 = dev_priv->display.vbt.display_clock_mode;
> + has_ck505 = display->vbt.display_clock_mode;
> can_ssc = has_ck505;
> } else {
> has_ck505 = false;
> @@ -530,10 +530,10 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
> }
>
> /* Check if any DPLLs are using the SSC source */
> - for_each_shared_dpll(dev_priv, pll, i) {
> + for_each_shared_dpll(display, pll, i) {
> u32 temp;
>
> - temp = intel_de_read(dev_priv, PCH_DPLL(pll->info->id));
> + temp = intel_de_read(display, PCH_DPLL(pll->info->id));
>
> if (!(temp & DPLL_VCO_ENABLE))
> continue;
> @@ -545,7 +545,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
> }
> }
>
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
> has_panel, has_lvds, has_ck505, using_ssc_source);
>
> @@ -554,7 +554,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
> * PCH B stepping, previous chipset stepping should be
> * ignoring this setting.
> */
> - val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
> + val = intel_de_read(display, PCH_DREF_CONTROL);
>
> /* As we must carefully and slowly disable/enable each source in turn,
> * compute the final state we want first and check if we need to
> @@ -614,8 +614,8 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
> }
>
> /* Get SSC going before enabling the outputs */
> - intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
> - intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
> + intel_de_write(display, PCH_DREF_CONTROL, val);
> + intel_de_posting_read(display, PCH_DREF_CONTROL);
> udelay(200);
>
> val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
> @@ -633,23 +633,23 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
> val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
> }
>
> - intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
> - intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
> + intel_de_write(display, PCH_DREF_CONTROL, val);
> + intel_de_posting_read(display, PCH_DREF_CONTROL);
> udelay(200);
> } else {
> - drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
> + drm_dbg_kms(display->drm, "Disabling CPU source output\n");
>
> val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
>
> /* Turn off CPU output */
> val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
>
> - intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
> - intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
> + intel_de_write(display, PCH_DREF_CONTROL, val);
> + intel_de_posting_read(display, PCH_DREF_CONTROL);
> udelay(200);
>
> if (!using_ssc_source) {
> - drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
> + drm_dbg_kms(display->drm, "Disabling SSC source\n");
>
> /* Turn off the SSC source */
> val &= ~DREF_SSC_SOURCE_MASK;
> @@ -658,13 +658,13 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
> /* Turn off SSC1 */
> val &= ~DREF_SSC1_ENABLE;
>
> - intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
> - intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
> + intel_de_write(display, PCH_DREF_CONTROL, val);
> + intel_de_posting_read(display, PCH_DREF_CONTROL);
> udelay(200);
> }
> }
>
> - drm_WARN_ON(&dev_priv->drm, val != final);
> + drm_WARN_ON(display->drm, val != final);
> }
>
> /*
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 4/9] drm/i915/dpll: Use intel_display for dpll dump and compare hw state
2025-02-11 10:48 ` [PATCH 4/9] drm/i915/dpll: Use intel_display for dpll dump and compare hw state Suraj Kandpal
@ 2025-02-11 12:59 ` Jani Nikula
0 siblings, 0 replies; 29+ messages in thread
From: Jani Nikula @ 2025-02-11 12:59 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Lets use intel_display for dpll dump and compare hw state. This also
*Let's
> helps elimanate drm_i915_private dependency from i915_shared_dplls_info
> in display_debug_fs.
There's no display_debug_fs...
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> .../gpu/drm/i915/display/intel_crtc_state_dump.c | 3 ++-
> drivers/gpu/drm/i915/display/intel_display.c | 8 ++++----
> .../gpu/drm/i915/display/intel_display_debugfs.c | 3 +--
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 ++++++++--------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++--
> 5 files changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index ecd0d9853c60..599ddce96371 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -176,6 +176,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state,
> const char *context)
> {
> + struct intel_display *display = to_intel_display(pipe_config);
> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> const struct intel_plane_state *plane_state;
> @@ -340,7 +341,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
> pipe_config->ips_enabled, pipe_config->double_wide,
> pipe_config->has_drrs);
>
> - intel_dpll_dump_hw_state(i915, &p, &pipe_config->dpll_hw_state);
> + intel_dpll_dump_hw_state(display, &p, &pipe_config->dpll_hw_state);
>
> if (IS_CHERRYVIEW(i915))
> drm_printf(&p, "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 9f8a8c94cf4c..5f4b1d8eed3e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5348,14 +5348,14 @@ pipe_config_pll_mismatch(struct drm_printer *p, bool fastset,
> const struct intel_dpll_hw_state *a,
> const struct intel_dpll_hw_state *b)
> {
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc);
>
> pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */
>
> drm_printf(p, "expected:\n");
> - intel_dpll_dump_hw_state(i915, p, a);
> + intel_dpll_dump_hw_state(display, p, a);
> drm_printf(p, "found:\n");
> - intel_dpll_dump_hw_state(i915, p, b);
> + intel_dpll_dump_hw_state(display, p, b);
> }
>
> static void
> @@ -5495,7 +5495,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> } while (0)
>
> #define PIPE_CONF_CHECK_PLL(name) do { \
> - if (!intel_dpll_compare_hw_state(dev_priv, ¤t_config->name, \
> + if (!intel_dpll_compare_hw_state(display, ¤t_config->name, \
> &pipe_config->name)) { \
> pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \
> ¤t_config->name, \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 87e6f4000101..970b8078db8b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -630,7 +630,6 @@ static int i915_display_capabilities(struct seq_file *m, void *unused)
>
> static int i915_shared_dplls_info(struct seq_file *m, void *unused)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> struct intel_display *display = node_to_intel_display(m->private);
> struct drm_printer p = drm_seq_file_printer(m);
> struct intel_shared_dpll *pll;
> @@ -649,7 +648,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
> pll->state.pipe_mask, pll->active_mask,
> str_yes_no(pll->on));
> drm_printf(&p, " tracked hardware state:\n");
> - intel_dpll_dump_hw_state(dev_priv, &p, &pll->state.hw_state);
> + intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state);
> }
> drm_modeset_unlock_all(display->drm);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 171d16e91c61..ee4e263ce999 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4592,18 +4592,18 @@ void intel_dpll_sanitize_state(struct drm_i915_private *i915)
>
> /**
> * intel_dpll_dump_hw_state - dump hw_state
> - * @i915: i915 drm device
> + * @display: intel_display structure
> * @p: where to print the state to
> * @dpll_hw_state: hw state to be dumped
> *
> * Dumo out the relevant values in @dpll_hw_state.
> */
> -void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
> +void intel_dpll_dump_hw_state(struct intel_display *display,
> struct drm_printer *p,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> - if (i915->display.dpll.mgr) {
> - i915->display.dpll.mgr->dump_hw_state(p, dpll_hw_state);
> + if (display->dpll.mgr) {
> + display->dpll.mgr->dump_hw_state(p, dpll_hw_state);
> } else {
> /* fallback for platforms that don't use the shared dpll
> * infrastructure
> @@ -4614,7 +4614,7 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
>
> /**
> * intel_dpll_compare_hw_state - compare the two states
> - * @i915: i915 drm device
> + * @display: intel_display structure
> * @a: first DPLL hw state
> * @b: second DPLL hw state
> *
> @@ -4622,12 +4622,12 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
> *
> * Returns: true if the states are equal, false if the differ
> */
> -bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,
> +bool intel_dpll_compare_hw_state(struct intel_display *display,
> const struct intel_dpll_hw_state *a,
> const struct intel_dpll_hw_state *b)
> {
> - if (i915->display.dpll.mgr) {
> - return i915->display.dpll.mgr->compare_hw_state(a, b);
> + if (display->dpll.mgr) {
> + return display->dpll.mgr->compare_hw_state(a, b);
> } else {
> /* fallback for platforms that don't use the shared dpll
> * infrastructure
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 382bdf8f0b65..42379494f347 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -427,10 +427,10 @@ void intel_dpll_update_ref_clks(struct drm_i915_private *i915);
> void intel_dpll_readout_hw_state(struct drm_i915_private *i915);
> void intel_dpll_sanitize_state(struct drm_i915_private *i915);
>
> -void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
> +void intel_dpll_dump_hw_state(struct intel_display *display,
> struct drm_printer *p,
> const struct intel_dpll_hw_state *dpll_hw_state);
> -bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,
> +bool intel_dpll_compare_hw_state(struct intel_display *display,
> const struct intel_dpll_hw_state *a,
> const struct intel_dpll_hw_state *b);
> enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 5/9] drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks
2025-02-11 10:48 ` [PATCH 5/9] drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks Suraj Kandpal
@ 2025-02-11 13:10 ` Jani Nikula
0 siblings, 0 replies; 29+ messages in thread
From: Jani Nikula @ 2025-02-11 13:10 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> We use intel_display for function hooks of shared_dpll_mgr and
> any function that gets called when we use for_each_shared_dpll.
> This also contains some opportunistic display->platform.xx changes
> all to reductate the use of drm_i915_private.
>
> --v2
> -rebase
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> /*
> * Try to set up the PCH reference clock once all DPLLs
> * that depend on it have been shut down.
> */
> - if (i915->display.dpll.pch_ssc_use & BIT(id))
> - intel_init_pch_refclk(i915);
> + if (display->dpll.pch_ssc_use & BIT(id))
> + intel_init_pch_refclk(to_i915(display->drm));
For future reference:
- Please don't add inline uses of to_i915().
- There's too much going on in one patch.
Regardless, this is supposed to be non-functional, so I'll let it pass.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 6/9] drm/i915/dpll: Use intel_display for asserting pll
2025-02-11 10:48 ` [PATCH 6/9] drm/i915/dpll: Use intel_display for asserting pll Suraj Kandpal
@ 2025-02-11 13:12 ` Jani Nikula
0 siblings, 0 replies; 29+ messages in thread
From: Jani Nikula @ 2025-02-11 13:12 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Use intel_display instead of drm_i915_private to assert pll enabled
> and disabled and the corresponding changes needed to make that happen.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++----------
> .../i915/display/intel_display_power_well.c | 10 ++++-----
> drivers/gpu/drm/i915/display/intel_dpll.c | 11 +++++-----
> drivers/gpu/drm/i915/display/intel_dpll.h | 5 +++--
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 9 +++-----
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +-
> drivers/gpu/drm/i915/display/intel_fdi.c | 16 ++++++--------
> drivers/gpu/drm/i915/display/intel_fdi.h | 7 +++---
> drivers/gpu/drm/i915/display/intel_lvds.c | 7 +++---
> .../gpu/drm/i915/display/intel_pch_display.c | 2 +-
> drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 12 +++++-----
> drivers/gpu/drm/i915/display/vlv_dsi_pll.h | 10 +++++----
> 12 files changed, 55 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 5f4b1d8eed3e..64a139676524 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -518,7 +518,7 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
> enum pipe pipe = crtc->pipe;
> u32 val;
>
> - drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
> + drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe));
>
> assert_planes_disabled(crtc);
>
> @@ -529,15 +529,15 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
> */
> if (HAS_GMCH(dev_priv)) {
> if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
> - assert_dsi_pll_enabled(dev_priv);
> + assert_dsi_pll_enabled(display);
> else
> - assert_pll_enabled(dev_priv, pipe);
> + assert_pll_enabled(display, pipe);
> } else {
> if (new_crtc_state->has_pch_encoder) {
> /* if driving the PCH, we need FDI enabled */
> - assert_fdi_rx_pll_enabled(dev_priv,
> + assert_fdi_rx_pll_enabled(display,
> intel_crtc_pch_transcoder(crtc));
> - assert_fdi_tx_pll_enabled(dev_priv,
> + assert_fdi_tx_pll_enabled(display,
> (enum pipe) cpu_transcoder);
> }
> /* FIXME: assert CPU port conditions for SNB+ */
> @@ -545,21 +545,21 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
>
> /* Wa_22012358565:adl-p */
> if (DISPLAY_VER(dev_priv) == 13)
> - intel_de_rmw(dev_priv, PIPE_ARB_CTL(dev_priv, pipe),
> + intel_de_rmw(display, PIPE_ARB_CTL(display, pipe),
> 0, PIPE_ARB_USE_PROG_SLOTS);
>
> if (DISPLAY_VER(dev_priv) >= 14) {
> u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
> u32 set = 0;
>
> - if (DISPLAY_VER(dev_priv) == 14)
> + if (DISPLAY_VER(display) == 14)
> set |= DP_FEC_BS_JITTER_WA;
>
> intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
> clear, set);
> }
>
> - val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
> + val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
> if (val & TRANSCONF_ENABLE) {
> /* we keep both pipes enabled on 830 */
> drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
> @@ -567,16 +567,16 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
> }
>
> /* Wa_1409098942:adlp+ */
> - if (DISPLAY_VER(dev_priv) >= 13 &&
> + if (DISPLAY_VER(display) >= 13 &&
> new_crtc_state->dsc.compression_enable) {
> val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
> val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
> TRANSCONF_PIXEL_COUNT_SCALING_X4);
> }
>
> - intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANSCONF(display, cpu_transcoder),
> val | TRANSCONF_ENABLE);
> - intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
> + intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
>
> /*
> * Until the pipe starts PIPEDSL reads will return a stale value,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index a31d1678dfc0..c2db076fd344 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1313,11 +1313,10 @@ static void vlv_dpio_cmn_power_well_enable(struct intel_display *display,
> static void vlv_dpio_cmn_power_well_disable(struct intel_display *display,
> struct i915_power_well *power_well)
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> enum pipe pipe;
>
> for_each_pipe(display, pipe)
> - assert_pll_disabled(dev_priv, pipe);
> + assert_pll_disabled(display, pipe);
>
> /* Assert common reset */
> intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0);
> @@ -1499,7 +1498,6 @@ static void chv_dpio_cmn_power_well_enable(struct intel_display *display,
> static void chv_dpio_cmn_power_well_disable(struct intel_display *display,
> struct i915_power_well *power_well)
> {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
> enum dpio_phy phy;
>
> @@ -1509,11 +1507,11 @@ static void chv_dpio_cmn_power_well_disable(struct intel_display *display,
>
> if (id == VLV_DISP_PW_DPIO_CMN_BC) {
> phy = DPIO_PHY0;
> - assert_pll_disabled(dev_priv, PIPE_A);
> - assert_pll_disabled(dev_priv, PIPE_B);
> + assert_pll_disabled(display, PIPE_A);
> + assert_pll_disabled(display, PIPE_B);
> } else {
> phy = DPIO_PHY1;
> - assert_pll_disabled(dev_priv, PIPE_C);
> + assert_pll_disabled(display, PIPE_C);
> }
>
> display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 3256b1293f7f..cc19cd51ab4d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -2329,10 +2329,9 @@ void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
> }
>
> /* Only for pre-ILK configs */
> -static void assert_pll(struct drm_i915_private *dev_priv,
> +static void assert_pll(struct intel_display *display,
> enum pipe pipe, bool state)
> {
> - struct intel_display *display = &dev_priv->display;
> bool cur_state;
>
> cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;
> @@ -2341,12 +2340,12 @@ static void assert_pll(struct drm_i915_private *dev_priv,
> str_on_off(state), str_on_off(cur_state));
> }
>
> -void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe)
> +void assert_pll_enabled(struct intel_display *display, enum pipe pipe)
> {
> - assert_pll(i915, pipe, true);
> + assert_pll(display, pipe, true);
> }
>
> -void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe)
> +void assert_pll_disabled(struct intel_display *display, enum pipe pipe)
> {
> - assert_pll(i915, pipe, false);
> + assert_pll(display, pipe, false);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
> index a86a79408af0..21d06cbd2ce7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.h
> @@ -13,6 +13,7 @@ struct drm_i915_private;
> struct intel_atomic_state;
> struct intel_crtc;
> struct intel_crtc_state;
> +struct intel_display;
> struct intel_dpll_hw_state;
> enum pipe;
>
> @@ -46,7 +47,7 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state);
> void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state);
> void chv_crtc_clock_get(struct intel_crtc_state *crtc_state);
>
> -void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
> -void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
> +void assert_pll_enabled(struct intel_display *display, enum pipe pipe);
> +void assert_pll_disabled(struct intel_display *display, enum pipe pipe);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 9976ac6322d1..104054a6df56 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -171,11 +171,10 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
> }
>
> /* For ILK+ */
> -void assert_shared_dpll(struct drm_i915_private *i915,
> +void assert_shared_dpll(struct intel_display *display,
> struct intel_shared_dpll *pll,
> bool state)
> {
> - struct intel_display *display = &i915->display;
> bool cur_state;
> struct intel_dpll_hw_state hw_state;
>
> @@ -256,7 +255,6 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> unsigned int pipe_mask = BIT(crtc->pipe);
> unsigned int old_mask;
> @@ -280,7 +278,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
>
> if (old_mask) {
> drm_WARN_ON(display->drm, !pll->on);
> - assert_shared_dpll_enabled(i915, pll);
> + assert_shared_dpll_enabled(display, pll);
> goto out;
> }
> drm_WARN_ON(display->drm, pll->on);
> @@ -303,7 +301,6 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> unsigned int pipe_mask = BIT(crtc->pipe);
>
> @@ -325,7 +322,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> pll->info->name, pll->active_mask, pll->on,
> crtc->base.base.id, crtc->base.name);
>
> - assert_shared_dpll_enabled(i915, pll);
> + assert_shared_dpll_enabled(display, pll);
> drm_WARN_ON(display->drm, !pll->on);
>
> pll->active_mask &= ~pipe_mask;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index ebd0ed79d2b5..b6f2cbce13e4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -392,7 +392,7 @@ struct intel_shared_dpll {
> struct intel_shared_dpll *
> intel_get_shared_dpll_by_id(struct intel_display *display,
> enum intel_dpll_id id);
> -void assert_shared_dpll(struct drm_i915_private *i915,
> +void assert_shared_dpll(struct intel_display *display,
> struct intel_shared_dpll *pll,
> bool state);
> #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 3e8d6d8af780..9ebe80bfaab6 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -80,14 +80,13 @@ void assert_fdi_rx_disabled(struct drm_i915_private *i915, enum pipe pipe)
> assert_fdi_rx(i915, pipe, false);
> }
>
> -void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915,
> +void assert_fdi_tx_pll_enabled(struct intel_display *display,
> enum pipe pipe)
> {
> - struct intel_display *display = &i915->display;
> bool cur_state;
>
> /* ILK FDI PLL is always enabled */
> - if (IS_IRONLAKE(i915))
> + if (display->platform.ironlake)
> return;
>
> /* On Haswell, DDI ports are responsible for the FDI PLL setup */
> @@ -99,10 +98,9 @@ void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915,
> "FDI TX PLL assertion failure, should be active but is disabled\n");
> }
>
> -static void assert_fdi_rx_pll(struct drm_i915_private *i915,
> +static void assert_fdi_rx_pll(struct intel_display *display,
> enum pipe pipe, bool state)
> {
> - struct intel_display *display = &i915->display;
> bool cur_state;
>
> cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE;
> @@ -111,14 +109,14 @@ static void assert_fdi_rx_pll(struct drm_i915_private *i915,
> str_on_off(state), str_on_off(cur_state));
> }
>
> -void assert_fdi_rx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe)
> +void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe)
> {
> - assert_fdi_rx_pll(i915, pipe, true);
> + assert_fdi_rx_pll(display, pipe, true);
> }
>
> -void assert_fdi_rx_pll_disabled(struct drm_i915_private *i915, enum pipe pipe)
> +void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe)
> {
> - assert_fdi_rx_pll(i915, pipe, false);
> + assert_fdi_rx_pll(display, pipe, false);
> }
>
> void intel_fdi_link_train(struct intel_crtc *crtc,
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h b/drivers/gpu/drm/i915/display/intel_fdi.h
> index 477ff0136934..b5be09efb36f 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.h
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.h
> @@ -13,6 +13,7 @@ struct drm_i915_private;
> struct intel_atomic_state;
> struct intel_crtc;
> struct intel_crtc_state;
> +struct intel_display;
> struct intel_encoder;
> struct intel_link_bw_limits;
>
> @@ -41,8 +42,8 @@ void assert_fdi_tx_enabled(struct drm_i915_private *i915, enum pipe pipe);
> void assert_fdi_tx_disabled(struct drm_i915_private *i915, enum pipe pipe);
> void assert_fdi_rx_enabled(struct drm_i915_private *i915, enum pipe pipe);
> void assert_fdi_rx_disabled(struct drm_i915_private *i915, enum pipe pipe);
> -void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
> -void assert_fdi_rx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
> -void assert_fdi_rx_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
> +void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe);
> +void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe);
> +void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index e86b3a86db82..6b05db2c10ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -240,6 +240,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> {
> + struct intel_display *display = to_intel_display(state);
> struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -248,10 +249,10 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
> u32 temp;
>
> if (HAS_PCH_SPLIT(i915)) {
> - assert_fdi_rx_pll_disabled(i915, pipe);
> - assert_shared_dpll_disabled(i915, crtc_state->shared_dpll);
> + assert_fdi_rx_pll_disabled(display, pipe);
> + assert_shared_dpll_disabled(display, crtc_state->shared_dpll);
> } else {
> - assert_pll_disabled(i915, pipe);
> + assert_pll_disabled(display, pipe);
> }
>
> intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps);
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index e874a577b7d1..75ff5592312f 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -256,7 +256,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
> u32 val, pipeconf_val;
>
> /* Make sure PCH DPLL is enabled */
> - assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
> + assert_shared_dpll_enabled(display, crtc_state->shared_dpll);
>
> /* FDI must be feeding us bits for PCH ports */
> assert_fdi_tx_enabled(dev_priv, pipe);
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> index ac69eaece0fd..2ed47e7d1051 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> @@ -590,9 +590,9 @@ void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);
> }
>
> -static void assert_dsi_pll(struct drm_i915_private *i915, bool state)
> +static void assert_dsi_pll(struct intel_display *display, bool state)
> {
> - struct intel_display *display = &i915->display;
> + struct drm_i915_private *i915 = to_i915(display->drm);
> bool cur_state;
>
> vlv_cck_get(i915);
> @@ -604,12 +604,12 @@ static void assert_dsi_pll(struct drm_i915_private *i915, bool state)
> str_on_off(state), str_on_off(cur_state));
> }
>
> -void assert_dsi_pll_enabled(struct drm_i915_private *i915)
> +void assert_dsi_pll_enabled(struct intel_display *display)
> {
> - assert_dsi_pll(i915, true);
> + assert_dsi_pll(display, true);
> }
>
> -void assert_dsi_pll_disabled(struct drm_i915_private *i915)
> +void assert_dsi_pll_disabled(struct intel_display *display)
> {
> - assert_dsi_pll(i915, false);
> + assert_dsi_pll(display, false);
> }
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.h b/drivers/gpu/drm/i915/display/vlv_dsi_pll.h
> index fbe5113dbeb9..a032cc2a2524 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.h
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.h
> @@ -11,6 +11,7 @@
> enum port;
> struct drm_i915_private;
> struct intel_crtc_state;
> +struct intel_display;
> struct intel_encoder;
>
> int vlv_dsi_pll_compute(struct intel_encoder *encoder,
> @@ -33,13 +34,14 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
> void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
>
> #ifdef I915
> -void assert_dsi_pll_enabled(struct drm_i915_private *i915);
> -void assert_dsi_pll_disabled(struct drm_i915_private *i915);
> +void assert_dsi_pll_enabled(struct intel_display *display);
> +void assert_dsi_pll_disabled(struct intel_display *display);
> #else
> -static inline void assert_dsi_pll_enabled(struct drm_i915_private *i915)
> +static inline void assert_dsi_pll_enabled(struct intel_display *display)
> {
> }
> -static inline void assert_dsi_pll_disabled(struct drm_i915_private *i915)
> +
> +static inline void assert_dsi_pll_disabled(struct intel_display *display)
> {
> }
> #endif
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 7/9] drm/i915/dpll: Use intel_display for update_refclk hook
2025-02-11 10:48 ` [PATCH 7/9] drm/i915/dpll: Use intel_display for update_refclk hook Suraj Kandpal
@ 2025-02-11 13:12 ` Jani Nikula
0 siblings, 0 replies; 29+ messages in thread
From: Jani Nikula @ 2025-02-11 13:12 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Use intel_display instead of drm_i915_private for update_refclk hook.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../drm/i915/display/intel_display_driver.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 32 +++++++++----------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +-
> 3 files changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index d448672fdfa4..978f530c810e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -453,7 +453,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
>
> intel_update_czclk(i915);
> intel_display_driver_init_hw(display);
> - intel_dpll_update_ref_clks(i915);
> + intel_dpll_update_ref_clks(display);
>
> if (display->cdclk.max_cdclk_freq == 0)
> intel_update_max_cdclk(display);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 104054a6df56..f94da1ffc8ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -109,7 +109,7 @@ struct intel_dpll_mgr {
> void (*update_active_dpll)(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder);
> - void (*update_ref_clks)(struct drm_i915_private *i915);
> + void (*update_ref_clks)(struct intel_display *display);
> void (*dump_hw_state)(struct drm_printer *p,
> const struct intel_dpll_hw_state *dpll_hw_state);
> bool (*compare_hw_state)(const struct intel_dpll_hw_state *a,
> @@ -1240,14 +1240,14 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
> return 0;
> }
>
> -static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
> +static void hsw_update_dpll_ref_clks(struct intel_display *display)
> {
> - i915->display.dpll.ref_clks.ssc = 135000;
> + display->dpll.ref_clks.ssc = 135000;
> /* Non-SSC is only used on non-ULT HSW. */
> - if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
> - i915->display.dpll.ref_clks.nssc = 24000;
> + if (intel_de_read(display, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
> + display->dpll.ref_clks.nssc = 24000;
> else
> - i915->display.dpll.ref_clks.nssc = 135000;
> + display->dpll.ref_clks.nssc = 135000;
> }
>
> static void hsw_dump_hw_state(struct drm_printer *p,
> @@ -1977,10 +1977,10 @@ static int skl_ddi_pll_get_freq(struct intel_display *display,
> return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);
> }
>
> -static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
> +static void skl_update_dpll_ref_clks(struct intel_display *display)
> {
> /* No SSC ref */
> - i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
> + display->dpll.ref_clks.nssc = display->cdclk.hw.ref;
> }
>
> static void skl_dump_hw_state(struct drm_printer *p,
> @@ -2446,10 +2446,10 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
> return 0;
> }
>
> -static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
> +static void bxt_update_dpll_ref_clks(struct intel_display *display)
> {
> - i915->display.dpll.ref_clks.ssc = 100000;
> - i915->display.dpll.ref_clks.nssc = 100000;
> + display->dpll.ref_clks.ssc = 100000;
> + display->dpll.ref_clks.nssc = 100000;
> /* DSI non-SSC ref 19.2MHz */
> }
>
> @@ -4078,10 +4078,10 @@ static void mg_pll_disable(struct intel_display *display,
> icl_pll_disable(display, pll, enable_reg);
> }
>
> -static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
> +static void icl_update_dpll_ref_clks(struct intel_display *display)
> {
> /* No SSC ref */
> - i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
> + display->dpll.ref_clks.nssc = display->cdclk.hw.ref;
> }
>
> static void icl_dump_hw_state(struct drm_printer *p,
> @@ -4532,10 +4532,10 @@ static void readout_dpll_hw_state(struct intel_display *display,
> pll->info->name, pll->state.pipe_mask, pll->on);
> }
>
> -void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
> +void intel_dpll_update_ref_clks(struct intel_display *display)
> {
> - if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks)
> - i915->display.dpll.mgr->update_ref_clks(i915);
> + if (display->dpll.mgr && display->dpll.mgr->update_ref_clks)
> + display->dpll.mgr->update_ref_clks(display);
> }
>
> void intel_dpll_readout_hw_state(struct intel_display *display)
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index b6f2cbce13e4..3d988f17f31d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -423,7 +423,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
> void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
> void intel_shared_dpll_init(struct drm_i915_private *i915);
> -void intel_dpll_update_ref_clks(struct drm_i915_private *i915);
> +void intel_dpll_update_ref_clks(struct intel_display *display);
> void intel_dpll_readout_hw_state(struct intel_display *display);
> void intel_dpll_sanitize_state(struct intel_display *display);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for shared_dpll_init
2025-02-11 10:48 ` [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for shared_dpll_init Suraj Kandpal
@ 2025-02-11 13:14 ` Jani Nikula
2025-02-11 14:23 ` Kandpal, Suraj
0 siblings, 1 reply; 29+ messages in thread
From: Jani Nikula @ 2025-02-11 13:14 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Use intel_display as an argument for intel_shared_dpll_init() and
> replace drm_i915_private in function wherever possible.
> While at it prefer using display->platform.xx over IS_PLATFORM.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> .../drm/i915/display/intel_display_driver.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 49 ++++++++++---------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 3 +-
> 3 files changed, 27 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 978f530c810e..852f1129a058 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -448,7 +448,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
> }
>
> intel_plane_possible_crtcs_init(display);
> - intel_shared_dpll_init(i915);
> + intel_shared_dpll_init(display);
> intel_fdi_pll_freq_update(i915);
>
> intel_update_czclk(i915);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index f94da1ffc8ce..26b6b9372fa3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2042,8 +2042,8 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
> {
> const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
> - enum dpio_phy phy;
> - enum dpio_channel ch;
> + enum dpio_phy phy = DPIO_PHY0;
> + enum dpio_channel ch = DPIO_CH0;
Unrelated change, please drop.
With that fixed,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> u32 temp;
>
> bxt_port_to_phy_channel(display, port, &phy, &ch);
> @@ -4302,40 +4302,41 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
>
> /**
> * intel_shared_dpll_init - Initialize shared DPLLs
> - * @i915: i915 device
> + * @display: intel_display device
> *
> - * Initialize shared DPLLs for @i915.
> + * Initialize shared DPLLs for @display.
> */
> -void intel_shared_dpll_init(struct drm_i915_private *i915)
> +void intel_shared_dpll_init(struct intel_display *display)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> const struct intel_dpll_mgr *dpll_mgr = NULL;
> const struct dpll_info *dpll_info;
> int i;
>
> - mutex_init(&i915->display.dpll.lock);
> + mutex_init(&display->dpll.lock);
>
> - if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915))
> + if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
> /* No shared DPLLs on DG2; port PLLs are part of the PHY */
> dpll_mgr = NULL;
> - else if (IS_ALDERLAKE_P(i915))
> + else if (display->platform.alderlake_p)
> dpll_mgr = &adlp_pll_mgr;
> - else if (IS_ALDERLAKE_S(i915))
> + else if (display->platform.alderlake_s)
> dpll_mgr = &adls_pll_mgr;
> - else if (IS_DG1(i915))
> + else if (display->platform.dg1)
> dpll_mgr = &dg1_pll_mgr;
> - else if (IS_ROCKETLAKE(i915))
> + else if (display->platform.rocketlake)
> dpll_mgr = &rkl_pll_mgr;
> - else if (DISPLAY_VER(i915) >= 12)
> + else if (DISPLAY_VER(display) >= 12)
> dpll_mgr = &tgl_pll_mgr;
> - else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915))
> + else if (display->platform.jasperlake || display->platform.elkhartlake)
> dpll_mgr = &ehl_pll_mgr;
> - else if (DISPLAY_VER(i915) >= 11)
> + else if (DISPLAY_VER(display) >= 11)
> dpll_mgr = &icl_pll_mgr;
> - else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
> + else if (display->platform.geminilake || display->platform.broxton)
> dpll_mgr = &bxt_pll_mgr;
> - else if (DISPLAY_VER(i915) == 9)
> + else if (DISPLAY_VER(display) == 9)
> dpll_mgr = &skl_pll_mgr;
> - else if (HAS_DDI(i915))
> + else if (HAS_DDI(display))
> dpll_mgr = &hsw_pll_mgr;
> else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915))
> dpll_mgr = &pch_pll_mgr;
> @@ -4346,20 +4347,20 @@ void intel_shared_dpll_init(struct drm_i915_private *i915)
> dpll_info = dpll_mgr->dpll_info;
>
> for (i = 0; dpll_info[i].name; i++) {
> - if (drm_WARN_ON(&i915->drm,
> - i >= ARRAY_SIZE(i915->display.dpll.shared_dplls)))
> + if (drm_WARN_ON(display->drm,
> + i >= ARRAY_SIZE(display->dpll.shared_dplls)))
> break;
>
> /* must fit into unsigned long bitmask on 32bit */
> - if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32))
> + if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
> break;
>
> - i915->display.dpll.shared_dplls[i].info = &dpll_info[i];
> - i915->display.dpll.shared_dplls[i].index = i;
> + display->dpll.shared_dplls[i].info = &dpll_info[i];
> + display->dpll.shared_dplls[i].index = i;
> }
>
> - i915->display.dpll.mgr = dpll_mgr;
> - i915->display.dpll.num_shared_dpll = i;
> + display->dpll.mgr = dpll_mgr;
> + display->dpll.num_shared_dpll = i;
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 3d988f17f31d..caffb084830c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -35,7 +35,6 @@
> ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
>
> enum tc_port;
> -struct drm_i915_private;
> struct drm_printer;
> struct intel_atomic_state;
> struct intel_crtc;
> @@ -422,7 +421,7 @@ bool intel_dpll_get_hw_state(struct intel_display *display,
> void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
> void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
> -void intel_shared_dpll_init(struct drm_i915_private *i915);
> +void intel_shared_dpll_init(struct intel_display *display);
> void intel_dpll_update_ref_clks(struct intel_display *display);
> void intel_dpll_readout_hw_state(struct intel_display *display);
> void intel_dpll_sanitize_state(struct intel_display *display);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 9/9] drm/i915/dpll: Replace all other leftover drm_i915_private
2025-02-11 10:48 ` [PATCH 9/9] drm/i915/dpll: Replace all other leftover drm_i915_private Suraj Kandpal
@ 2025-02-11 13:17 ` Jani Nikula
0 siblings, 0 replies; 29+ messages in thread
From: Jani Nikula @ 2025-02-11 13:17 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Replace all other left over drm_i915_private with intel_display
> in dpll_mgr.c.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 99 +++++++++----------
> 1 file changed, 48 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 26b6b9372fa3..96abb7e295a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -117,11 +117,10 @@ struct intel_dpll_mgr {
> };
>
> static void
> -intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915,
> +intel_atomic_duplicate_dpll_state(struct intel_display *display,
> struct intel_shared_dpll_state *shared_dpll)
> {
> struct intel_shared_dpll *pll;
> - struct intel_display *display = to_intel_display(&i915->drm);
> int i;
>
> /* Copy shared dpll state */
> @@ -139,7 +138,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
> if (!state->dpll_set) {
> state->dpll_set = true;
>
> - intel_atomic_duplicate_dpll_state(to_i915(s->dev),
> + intel_atomic_duplicate_dpll_state(to_intel_display(state),
Please do not add inline to_intel_display() usages, ever, anywhere. Add
a local display variable instead.
With that fixed,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> state->shared_dpll);
> }
>
> @@ -420,13 +419,13 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
> const struct intel_shared_dpll *pll,
> struct intel_shared_dpll_state *shared_dpll_state)
> {
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc);
>
> - drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
> + drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
>
> shared_dpll_state->pipe_mask |= BIT(crtc->pipe);
>
> - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] reserving %s\n",
> + drm_dbg_kms(display->drm, "[CRTC:%d:%s] reserving %s\n",
> crtc->base.base.id, crtc->base.name, pll->info->name);
> }
>
> @@ -459,13 +458,13 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> const struct intel_shared_dpll *pll,
> struct intel_shared_dpll_state *shared_dpll_state)
> {
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc);
>
> - drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
> + drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
>
> shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe);
>
> - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] releasing %s\n",
> + drm_dbg_kms(display->drm, "[CRTC:%d:%s] releasing %s\n",
> crtc->base.base.id, crtc->base.name, pll->info->name);
> }
>
> @@ -545,9 +544,8 @@ static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
> return val & DPLL_VCO_ENABLE;
> }
>
> -static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915)
> +static void ibx_assert_pch_refclk_enabled(struct intel_display *display)
> {
> - struct intel_display *display = &i915->display;
> u32 val;
> bool enabled;
>
> @@ -562,12 +560,11 @@ static void ibx_pch_dpll_enable(struct intel_display *display,
> struct intel_shared_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> - struct drm_i915_private *i915 = to_i915(display->drm);
> const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
> const enum intel_dpll_id id = pll->info->id;
>
> /* PCH refclock must be enabled first */
> - ibx_assert_pch_refclk_enabled(i915);
> + ibx_assert_pch_refclk_enabled(display);
>
> intel_de_write(display, PCH_FP0(id), hw_state->fp0);
> intel_de_write(display, PCH_FP1(id), hw_state->fp1);
> @@ -1074,7 +1071,7 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
> static int
> hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> int clock = crtc_state->port_clock;
>
> switch (clock / 2) {
> @@ -1083,7 +1080,7 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
> case 270000:
> return 0;
> default:
> - drm_dbg_kms(&i915->drm, "Invalid clock for DP: %d\n",
> + drm_dbg_kms(display->drm, "Invalid clock for DP: %d\n",
> clock);
> return -EINVAL;
> }
> @@ -2255,7 +2252,7 @@ static int
> bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
> struct dpll *clk_div)
> {
> - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_display *display = to_intel_display(crtc_state);
>
> /* Calculate HDMI div */
> /*
> @@ -2265,7 +2262,7 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
> if (!bxt_find_best_dpll(crtc_state, clk_div))
> return -EINVAL;
>
> - drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
> + drm_WARN_ON(display->drm, clk_div->m1 != 2);
>
> return 0;
> }
> @@ -2273,7 +2270,7 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
> static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
> struct dpll *clk_div)
> {
> - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> int i;
>
> *clk_div = bxt_dp_clk_val[0];
> @@ -2284,16 +2281,16 @@ static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
> }
> }
>
> - chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div);
> + chv_calc_dpll_params(display->dpll.ref_clks.nssc, clk_div);
>
> - drm_WARN_ON(&i915->drm, clk_div->vco == 0 ||
> + drm_WARN_ON(display->drm, clk_div->vco == 0 ||
> clk_div->dot != crtc_state->port_clock);
> }
>
> static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
> const struct dpll *clk_div)
> {
> - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;
> int clock = crtc_state->port_clock;
> int vco = clk_div->vco;
> @@ -2317,7 +2314,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
> gain_ctl = 1;
> targ_cnt = 9;
> } else {
> - drm_err(&i915->drm, "Invalid VCO\n");
> + drm_err(display->drm, "Invalid VCO\n");
> return -EINVAL;
> }
>
> @@ -2700,9 +2697,9 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
> static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
> struct skl_wrpll_params *pll_params)
> {
> - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> const struct icl_combo_pll_params *params =
> - i915->display.dpll.ref_clks.nssc == 24000 ?
> + display->dpll.ref_clks.nssc == 24000 ?
> icl_dp_combo_pll_24MHz_values :
> icl_dp_combo_pll_19_2MHz_values;
> int clock = crtc_state->port_clock;
> @@ -2722,12 +2719,12 @@ static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
> static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> struct skl_wrpll_params *pll_params)
> {
> - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_display *display = to_intel_display(crtc_state);
>
> - if (DISPLAY_VER(i915) >= 12) {
> - switch (i915->display.dpll.ref_clks.nssc) {
> + if (DISPLAY_VER(display) >= 12) {
> + switch (display->dpll.ref_clks.nssc) {
> default:
> - MISSING_CASE(i915->display.dpll.ref_clks.nssc);
> + MISSING_CASE(display->dpll.ref_clks.nssc);
> fallthrough;
> case 19200:
> case 38400:
> @@ -2738,9 +2735,9 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> break;
> }
> } else {
> - switch (i915->display.dpll.ref_clks.nssc) {
> + switch (display->dpll.ref_clks.nssc) {
> default:
> - MISSING_CASE(i915->display.dpll.ref_clks.nssc);
> + MISSING_CASE(display->dpll.ref_clks.nssc);
> fallthrough;
> case 19200:
> case 38400:
> @@ -2998,9 +2995,9 @@ static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
> static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> - int refclk_khz = i915->display.dpll.ref_clks.nssc;
> + int refclk_khz = display->dpll.ref_clks.nssc;
> int clock = crtc_state->port_clock;
> u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
> u32 iref_ndiv, iref_trim, iref_pulse_w;
> @@ -3010,7 +3007,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> u64 tmp;
> bool use_ssc = false;
> bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
> - bool is_dkl = DISPLAY_VER(i915) >= 12;
> + bool is_dkl = DISPLAY_VER(display) >= 12;
> int ret;
>
> ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
> @@ -3108,8 +3105,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> DKL_PLL_DIV0_PROP_COEFF(prop_coeff) |
> DKL_PLL_DIV0_FBPREDIV(m1div) |
> DKL_PLL_DIV0_FBDIV_INT(m2div_int);
> - if (i915->display.vbt.override_afc_startup) {
> - u8 val = i915->display.vbt.override_afc_startup_val;
> + if (display->vbt.override_afc_startup) {
> + u8 val = display->vbt.override_afc_startup_val;
>
> hw_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val);
> }
> @@ -3347,7 +3344,6 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> struct icl_port_dpll *port_dpll =
> @@ -3355,13 +3351,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> enum port port = encoder->port;
> unsigned long dpll_mask;
>
> - if (IS_ALDERLAKE_S(i915)) {
> + if (display->platform.alderlake_s) {
> dpll_mask =
> BIT(DPLL_ID_DG1_DPLL3) |
> BIT(DPLL_ID_DG1_DPLL2) |
> BIT(DPLL_ID_ICL_DPLL1) |
> BIT(DPLL_ID_ICL_DPLL0);
> - } else if (IS_DG1(i915)) {
> + } else if (display->platform.dg1) {
> if (port == PORT_D || port == PORT_E) {
> dpll_mask =
> BIT(DPLL_ID_DG1_DPLL2) |
> @@ -3371,12 +3367,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> BIT(DPLL_ID_DG1_DPLL0) |
> BIT(DPLL_ID_DG1_DPLL1);
> }
> - } else if (IS_ROCKETLAKE(i915)) {
> + } else if (display->platform.rocketlake) {
> dpll_mask =
> BIT(DPLL_ID_EHL_DPLL4) |
> BIT(DPLL_ID_ICL_DPLL1) |
> BIT(DPLL_ID_ICL_DPLL0);
> - } else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
> + } else if ((display->platform.jasperlake ||
> + display->platform.elkhartlake) &&
> port != PORT_A) {
> dpll_mask =
> BIT(DPLL_ID_EHL_DPLL4) |
> @@ -4381,10 +4378,10 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> {
> - struct drm_i915_private *i915 = to_i915(state->base.dev);
> - const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
> + struct intel_display *display = to_intel_display(state);
> + const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
>
> - if (drm_WARN_ON(&i915->drm, !dpll_mgr))
> + if (drm_WARN_ON(display->drm, !dpll_mgr))
> return -EINVAL;
>
> return dpll_mgr->compute_dplls(state, crtc, encoder);
> @@ -4414,10 +4411,10 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> {
> - struct drm_i915_private *i915 = to_i915(state->base.dev);
> - const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
> + struct intel_display *display = to_intel_display(state);
> + const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
>
> - if (drm_WARN_ON(&i915->drm, !dpll_mgr))
> + if (drm_WARN_ON(display->drm, !dpll_mgr))
> return -EINVAL;
>
> return dpll_mgr->get_dplls(state, crtc, encoder);
> @@ -4437,8 +4434,8 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> void intel_release_shared_dplls(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> - struct drm_i915_private *i915 = to_i915(state->base.dev);
> - const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
> + struct intel_display *display = to_intel_display(state);
> + const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
>
> /*
> * FIXME: this function is called for every platform having a
> @@ -4466,10 +4463,10 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> - const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
> + struct intel_display *display = to_intel_display(encoder);
> + const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
>
> - if (drm_WARN_ON(&i915->drm, !dpll_mgr))
> + if (drm_WARN_ON(display->drm, !dpll_mgr))
> return;
>
> dpll_mgr->update_active_dpll(state, crtc, encoder);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* ✓ i915.CI.BAT: success for drm_i915_private to intel_display cleanup (rev2)
2025-02-11 10:48 [PATCH 0/9] drm_i915_private to intel_display cleanup Suraj Kandpal
` (10 preceding siblings ...)
2025-02-11 12:10 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2025-02-11 13:45 ` Patchwork
2025-02-11 16:23 ` ✗ i915.CI.Full: failure " Patchwork
2025-02-12 9:54 ` [PATCH 0/9] drm_i915_private to intel_display cleanup Kandpal, Suraj
13 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2025-02-11 13:45 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3226 bytes --]
== Series Details ==
Series: drm_i915_private to intel_display cleanup (rev2)
URL : https://patchwork.freedesktop.org/series/144588/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16107 -> Patchwork_144588v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/index.html
Participating hosts (44 -> 41)
------------------------------
Missing (3): fi-glk-j4005 fi-snb-2520m fi-pnv-d510
Known issues
------------
Here are the changes found in Patchwork_144588v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- bat-dg1-7: [PASS][1] -> [FAIL][2] ([i915#13633])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/bat-dg1-7/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/bat-dg1-7/igt@i915_pm_rpm@module-reload.html
- bat-rpls-4: [PASS][3] -> [FAIL][4] ([i915#13633])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: [PASS][5] -> [SKIP][6] ([i915#9197]) +3 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
#### Possible fixes ####
* igt@i915_selftest@live@workarounds:
- bat-arls-5: [DMESG-FAIL][7] ([i915#12061]) -> [PASS][8] +1 other test pass
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/bat-arls-5/igt@i915_selftest@live@workarounds.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/bat-arls-5/igt@i915_selftest@live@workarounds.html
#### Warnings ####
* igt@i915_selftest@live:
- bat-arlh-3: [DMESG-FAIL][9] ([i915#12061]) -> [DMESG-FAIL][10] ([i915#12061] / [i915#12435])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/bat-arlh-3/igt@i915_selftest@live.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/bat-arlh-3/igt@i915_selftest@live.html
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12435
[i915#13633]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13633
[i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197
Build changes
-------------
* Linux: CI_DRM_16107 -> Patchwork_144588v2
CI-20190529: 20190529
CI_DRM_16107: 27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8228: 8228
Patchwork_144588v2: 27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/index.html
[-- Attachment #2: Type: text/html, Size: 4127 bytes --]
^ permalink raw reply [flat|nested] 29+ messages in thread
* RE: [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for shared_dpll_init
2025-02-11 13:14 ` Jani Nikula
@ 2025-02-11 14:23 ` Kandpal, Suraj
2025-02-11 16:57 ` Jani Nikula
0 siblings, 1 reply; 29+ messages in thread
From: Kandpal, Suraj @ 2025-02-11 14:23 UTC (permalink / raw)
To: Nikula, Jani, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, February 11, 2025 6:45 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Kandpal, Suraj
> <suraj.kandpal@intel.com>
> Subject: Re: [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for
> shared_dpll_init
>
> On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > Use intel_display as an argument for intel_shared_dpll_init() and
> > replace drm_i915_private in function wherever possible.
> > While at it prefer using display->platform.xx over IS_PLATFORM.
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > .../drm/i915/display/intel_display_driver.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 49
> > ++++++++++--------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h |
> > 3 +-
> > 3 files changed, 27 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > index 978f530c810e..852f1129a058 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > @@ -448,7 +448,7 @@ int intel_display_driver_probe_nogem(struct
> intel_display *display)
> > }
> >
> > intel_plane_possible_crtcs_init(display);
> > - intel_shared_dpll_init(i915);
> > + intel_shared_dpll_init(display);
> > intel_fdi_pll_freq_update(i915);
> >
> > intel_update_czclk(i915);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index f94da1ffc8ce..26b6b9372fa3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -2042,8 +2042,8 @@ static void bxt_ddi_pll_enable(struct
> > intel_display *display, {
> > const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> > enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping
> */
> > - enum dpio_phy phy;
> > - enum dpio_channel ch;
> > + enum dpio_phy phy = DPIO_PHY0;
> > + enum dpio_channel ch = DPIO_CH0;
>
> Unrelated change, please drop.
>
The problem is by dropping these changes I am not able to build the kernel and it throws the following warning because of which I had to add this
drivers/gpu/drm/i915/display/intel_dpll_mgr.c: In function _bxt_ddi_pll_enable_:
./drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg_defs.h:240:56: error: _phy_ is used uninitialized [-Werror=uniniti
alized]
240 | (BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) + \
| ^
drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2047:23: note: _phy_ was declared here
2047 | enum dpio_phy phy;
| ^~~
In file included from ./drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h:6,
from drivers/gpu/drm/i915/display/intel_display_reg_defs.h:9,
from drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h:9,
from drivers/gpu/drm/i915/display/intel_dpll_mgr.c:27:
./drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg_defs.h:213:58: error: _ch_ is used uninitialized [-Werror=uninitia
lized]
213 | #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
| ^
drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2048:27: note: _ch_ was declared here
2048 | enum dpio_channel ch;
Regards,
Suraj Kandpal
> With that fixed,
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
> > u32 temp;
> >
> > bxt_port_to_phy_channel(display, port, &phy, &ch); @@ -4302,40
> > +4302,41 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
> >
> > /**
> > * intel_shared_dpll_init - Initialize shared DPLLs
> > - * @i915: i915 device
> > + * @display: intel_display device
> > *
> > - * Initialize shared DPLLs for @i915.
> > + * Initialize shared DPLLs for @display.
> > */
> > -void intel_shared_dpll_init(struct drm_i915_private *i915)
> > +void intel_shared_dpll_init(struct intel_display *display)
> > {
> > + struct drm_i915_private *i915 = to_i915(display->drm);
> > const struct intel_dpll_mgr *dpll_mgr = NULL;
> > const struct dpll_info *dpll_info;
> > int i;
> >
> > - mutex_init(&i915->display.dpll.lock);
> > + mutex_init(&display->dpll.lock);
> >
> > - if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915))
> > + if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
> > /* No shared DPLLs on DG2; port PLLs are part of the PHY */
> > dpll_mgr = NULL;
> > - else if (IS_ALDERLAKE_P(i915))
> > + else if (display->platform.alderlake_p)
> > dpll_mgr = &adlp_pll_mgr;
> > - else if (IS_ALDERLAKE_S(i915))
> > + else if (display->platform.alderlake_s)
> > dpll_mgr = &adls_pll_mgr;
> > - else if (IS_DG1(i915))
> > + else if (display->platform.dg1)
> > dpll_mgr = &dg1_pll_mgr;
> > - else if (IS_ROCKETLAKE(i915))
> > + else if (display->platform.rocketlake)
> > dpll_mgr = &rkl_pll_mgr;
> > - else if (DISPLAY_VER(i915) >= 12)
> > + else if (DISPLAY_VER(display) >= 12)
> > dpll_mgr = &tgl_pll_mgr;
> > - else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915))
> > + else if (display->platform.jasperlake ||
> > +display->platform.elkhartlake)
> > dpll_mgr = &ehl_pll_mgr;
> > - else if (DISPLAY_VER(i915) >= 11)
> > + else if (DISPLAY_VER(display) >= 11)
> > dpll_mgr = &icl_pll_mgr;
> > - else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
> > + else if (display->platform.geminilake || display->platform.broxton)
> > dpll_mgr = &bxt_pll_mgr;
> > - else if (DISPLAY_VER(i915) == 9)
> > + else if (DISPLAY_VER(display) == 9)
> > dpll_mgr = &skl_pll_mgr;
> > - else if (HAS_DDI(i915))
> > + else if (HAS_DDI(display))
> > dpll_mgr = &hsw_pll_mgr;
> > else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915))
> > dpll_mgr = &pch_pll_mgr;
> > @@ -4346,20 +4347,20 @@ void intel_shared_dpll_init(struct
> drm_i915_private *i915)
> > dpll_info = dpll_mgr->dpll_info;
> >
> > for (i = 0; dpll_info[i].name; i++) {
> > - if (drm_WARN_ON(&i915->drm,
> > - i >= ARRAY_SIZE(i915-
> >display.dpll.shared_dplls)))
> > + if (drm_WARN_ON(display->drm,
> > + i >= ARRAY_SIZE(display->dpll.shared_dplls)))
> > break;
> >
> > /* must fit into unsigned long bitmask on 32bit */
> > - if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32))
> > + if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
> > break;
> >
> > - i915->display.dpll.shared_dplls[i].info = &dpll_info[i];
> > - i915->display.dpll.shared_dplls[i].index = i;
> > + display->dpll.shared_dplls[i].info = &dpll_info[i];
> > + display->dpll.shared_dplls[i].index = i;
> > }
> >
> > - i915->display.dpll.mgr = dpll_mgr;
> > - i915->display.dpll.num_shared_dpll = i;
> > + display->dpll.mgr = dpll_mgr;
> > + display->dpll.num_shared_dpll = i;
> > }
> >
> > /**
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index 3d988f17f31d..caffb084830c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -35,7 +35,6 @@
> > ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
> >
> > enum tc_port;
> > -struct drm_i915_private;
> > struct drm_printer;
> > struct intel_atomic_state;
> > struct intel_crtc;
> > @@ -422,7 +421,7 @@ bool intel_dpll_get_hw_state(struct intel_display
> > *display, void intel_enable_shared_dpll(const struct intel_crtc_state
> > *crtc_state); void intel_disable_shared_dpll(const struct
> > intel_crtc_state *crtc_state); void
> > intel_shared_dpll_swap_state(struct intel_atomic_state *state); -void
> > intel_shared_dpll_init(struct drm_i915_private *i915);
> > +void intel_shared_dpll_init(struct intel_display *display);
> > void intel_dpll_update_ref_clks(struct intel_display *display); void
> > intel_dpll_readout_hw_state(struct intel_display *display); void
> > intel_dpll_sanitize_state(struct intel_display *display);
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* ✗ i915.CI.Full: failure for drm_i915_private to intel_display cleanup (rev2)
2025-02-11 10:48 [PATCH 0/9] drm_i915_private to intel_display cleanup Suraj Kandpal
` (11 preceding siblings ...)
2025-02-11 13:45 ` ✓ i915.CI.BAT: success " Patchwork
@ 2025-02-11 16:23 ` Patchwork
2025-02-12 9:54 ` [PATCH 0/9] drm_i915_private to intel_display cleanup Kandpal, Suraj
13 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2025-02-11 16:23 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 100275 bytes --]
== Series Details ==
Series: drm_i915_private to intel_display cleanup (rev2)
URL : https://patchwork.freedesktop.org/series/144588/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16107_full -> Patchwork_144588v2_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_144588v2_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_144588v2_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_144588v2_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_schedule@pi-ringfull@bcs0:
- shard-glk: [PASS][1] -> [FAIL][2] +2 other tests fail
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk2/igt@gem_exec_schedule@pi-ringfull@bcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk1/igt@gem_exec_schedule@pi-ringfull@bcs0.html
* igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-4:
- shard-dg1: [PASS][3] -> [FAIL][4] +1 other test fail
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg1-18/igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-4.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-14/igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-4.html
* igt@kms_cursor_crc@cursor-random-256x256@pipe-d-edp-1:
- shard-mtlp: [PASS][5] -> [ABORT][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-mtlp-1/igt@kms_cursor_crc@cursor-random-256x256@pipe-d-edp-1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-8/igt@kms_cursor_crc@cursor-random-256x256@pipe-d-edp-1.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1:
- shard-snb: [PASS][7] -> [INCOMPLETE][8] +1 other test incomplete
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-snb4/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-snb1/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html
#### Warnings ####
* igt@kms_cursor_crc@cursor-random-256x256@pipe-a-edp-1:
- shard-mtlp: [ABORT][9] -> [DMESG-WARN][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-mtlp-1/igt@kms_cursor_crc@cursor-random-256x256@pipe-a-edp-1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-8/igt@kms_cursor_crc@cursor-random-256x256@pipe-a-edp-1.html
Known issues
------------
Here are the changes found in Patchwork_144588v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-rkl: NOTRUN -> [SKIP][11] ([i915#8411])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@device_reset@cold-reset-bound:
- shard-dg2-9: NOTRUN -> [SKIP][12] ([i915#11078])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@device_reset@cold-reset-bound.html
* igt@device_reset@unbind-cold-reset-rebind:
- shard-rkl: NOTRUN -> [SKIP][13] ([i915#11078])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@device_reset@unbind-cold-reset-rebind.html
* igt@drm_fdinfo@most-busy-idle-check-all@bcs0:
- shard-dg1: NOTRUN -> [SKIP][14] ([i915#8414]) +6 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@drm_fdinfo@most-busy-idle-check-all@bcs0.html
* igt@drm_fdinfo@virtual-busy-hang:
- shard-dg2: NOTRUN -> [SKIP][15] ([i915#8414])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@drm_fdinfo@virtual-busy-hang.html
- shard-mtlp: NOTRUN -> [SKIP][16] ([i915#8414])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@drm_fdinfo@virtual-busy-hang.html
* igt@drm_fdinfo@virtual-busy-idle:
- shard-dg2-9: NOTRUN -> [SKIP][17] ([i915#8414]) +1 other test skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@drm_fdinfo@virtual-busy-idle.html
* igt@gem_caching@writes:
- shard-mtlp: NOTRUN -> [SKIP][18] ([i915#4873])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-4/igt@gem_caching@writes.html
* igt@gem_close_race@multigpu-basic-process:
- shard-dg1: NOTRUN -> [SKIP][19] ([i915#7697])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-dg2: NOTRUN -> [SKIP][20] ([i915#7697]) +1 other test skip
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@gem_close_race@multigpu-basic-threads.html
- shard-tglu: NOTRUN -> [SKIP][21] ([i915#7697])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@gem_close_race@multigpu-basic-threads.html
- shard-mtlp: NOTRUN -> [SKIP][22] ([i915#7697])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-6/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_create@create-ext-cpu-access-sanity-check:
- shard-rkl: NOTRUN -> [SKIP][23] ([i915#6335])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@gem_create@create-ext-cpu-access-sanity-check.html
* igt@gem_ctx_persistence@heartbeat-close:
- shard-mtlp: NOTRUN -> [SKIP][24] ([i915#8555])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-2/igt@gem_ctx_persistence@heartbeat-close.html
* igt@gem_ctx_persistence@heartbeat-stop:
- shard-dg1: NOTRUN -> [SKIP][25] ([i915#8555])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@gem_ctx_persistence@heartbeat-stop.html
* igt@gem_ctx_persistence@legacy-engines-hang:
- shard-snb: NOTRUN -> [SKIP][26] ([i915#1099])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-snb2/igt@gem_ctx_persistence@legacy-engines-hang.html
* igt@gem_ctx_sseu@mmap-args:
- shard-tglu-1: NOTRUN -> [SKIP][27] ([i915#280])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-mtlp: [PASS][28] -> [ABORT][29] ([i915#13193]) +2 other tests abort
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-mtlp-2/igt@gem_eio@in-flight-contexts-immediate.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-7/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_exec_balancer@bonded-dual:
- shard-dg2-9: NOTRUN -> [SKIP][30] ([i915#4771])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@gem_exec_balancer@bonded-dual.html
* igt@gem_exec_balancer@bonded-pair:
- shard-mtlp: NOTRUN -> [SKIP][31] ([i915#4771])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-4/igt@gem_exec_balancer@bonded-pair.html
* igt@gem_exec_balancer@invalid-bonds:
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#4036])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@gem_exec_balancer@invalid-bonds.html
- shard-mtlp: NOTRUN -> [SKIP][33] ([i915#4036])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-6/igt@gem_exec_balancer@invalid-bonds.html
* igt@gem_exec_balancer@parallel-dmabuf-import-out-fence:
- shard-tglu: NOTRUN -> [SKIP][34] ([i915#4525])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-7/igt@gem_exec_balancer@parallel-dmabuf-import-out-fence.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-rkl: NOTRUN -> [SKIP][35] ([i915#4525])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-tglu-1: NOTRUN -> [SKIP][36] ([i915#4525])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_capture@capture-invisible:
- shard-rkl: NOTRUN -> [SKIP][37] ([i915#6334]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@gem_exec_capture@capture-invisible.html
* igt@gem_exec_capture@capture-recoverable:
- shard-tglu: NOTRUN -> [SKIP][38] ([i915#6344])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@gem_exec_capture@capture-recoverable.html
* igt@gem_exec_fence@submit3:
- shard-dg2-9: NOTRUN -> [SKIP][39] ([i915#4812])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@gem_exec_fence@submit3.html
* igt@gem_exec_fence@submit67:
- shard-dg2: NOTRUN -> [SKIP][40] ([i915#4812])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@gem_exec_fence@submit67.html
* igt@gem_exec_flush@basic-uc-ro-default:
- shard-dg1: NOTRUN -> [SKIP][41] ([i915#3539] / [i915#4852])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-14/igt@gem_exec_flush@basic-uc-ro-default.html
* igt@gem_exec_flush@basic-wb-ro-default:
- shard-dg2-9: NOTRUN -> [SKIP][42] ([i915#3539] / [i915#4852]) +1 other test skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@gem_exec_flush@basic-wb-ro-default.html
* igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
- shard-dg2: NOTRUN -> [SKIP][43] ([i915#3281]) +4 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html
* igt@gem_exec_reloc@basic-cpu-wc-active:
- shard-mtlp: NOTRUN -> [SKIP][44] ([i915#3281]) +6 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-2/igt@gem_exec_reloc@basic-cpu-wc-active.html
* igt@gem_exec_reloc@basic-gtt-cpu-active:
- shard-dg2-9: NOTRUN -> [SKIP][45] ([i915#3281]) +4 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@gem_exec_reloc@basic-gtt-cpu-active.html
* igt@gem_exec_reloc@basic-gtt-read:
- shard-dg1: NOTRUN -> [SKIP][46] ([i915#3281])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@gem_exec_reloc@basic-gtt-read.html
* igt@gem_exec_reloc@basic-write-read-active:
- shard-rkl: NOTRUN -> [SKIP][47] ([i915#3281]) +5 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@gem_exec_reloc@basic-write-read-active.html
* igt@gem_exec_schedule@preempt-queue-contexts:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#4537] / [i915#4812])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@gem_exec_schedule@preempt-queue-contexts.html
* igt@gem_exec_suspend@basic-s0@smem:
- shard-dg2: [PASS][49] -> [INCOMPLETE][50] ([i915#11441] / [i915#13304]) +1 other test incomplete
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg2-1/igt@gem_exec_suspend@basic-s0@smem.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-3/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- shard-tglu-1: NOTRUN -> [ABORT][51] ([i915#7975]) +1 other test abort
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@gem_fence_thrash@bo-copy:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#4860]) +1 other test skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@gem_fence_thrash@bo-copy.html
* igt@gem_fenced_exec_thrash@2-spare-fences:
- shard-dg1: NOTRUN -> [SKIP][53] ([i915#4860])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@gem_fenced_exec_thrash@2-spare-fences.html
* igt@gem_fenced_exec_thrash@no-spare-fences:
- shard-rkl: [PASS][54] -> [DMESG-WARN][55] ([i915#12964]) +4 other tests dmesg-warn
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-rkl-1/igt@gem_fenced_exec_thrash@no-spare-fences.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@gem_fenced_exec_thrash@no-spare-fences.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][56] ([i915#4860])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html
* igt@gem_lmem_swapping@massive:
- shard-glk: NOTRUN -> [SKIP][57] ([i915#4613])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk2/igt@gem_lmem_swapping@massive.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-tglu-1: NOTRUN -> [SKIP][58] ([i915#4613]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@gem_lmem_swapping@parallel-multi.html
- shard-mtlp: NOTRUN -> [SKIP][59] ([i915#4613])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-4/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-rkl: NOTRUN -> [SKIP][60] ([i915#4613]) +1 other test skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-tglu: NOTRUN -> [SKIP][61] ([i915#4613]) +1 other test skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_media_vme:
- shard-rkl: NOTRUN -> [SKIP][62] ([i915#284])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@gem_media_vme.html
* igt@gem_mmap@short-mmap:
- shard-mtlp: NOTRUN -> [SKIP][63] ([i915#4083]) +1 other test skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@gem_mmap@short-mmap.html
- shard-dg2: NOTRUN -> [SKIP][64] ([i915#4083])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@gem_mmap@short-mmap.html
* igt@gem_mmap_gtt@basic-read:
- shard-dg2-9: NOTRUN -> [SKIP][65] ([i915#4077]) +6 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@gem_mmap_gtt@basic-read.html
* igt@gem_mmap_gtt@cpuset-medium-copy:
- shard-mtlp: NOTRUN -> [SKIP][66] ([i915#4077]) +9 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@gem_mmap_gtt@cpuset-medium-copy.html
* igt@gem_mmap_wc@read:
- shard-dg1: NOTRUN -> [SKIP][67] ([i915#4083])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@gem_mmap_wc@read.html
* igt@gem_mmap_wc@write-read-distinct:
- shard-dg2-9: NOTRUN -> [SKIP][68] ([i915#4083]) +1 other test skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@gem_mmap_wc@write-read-distinct.html
* igt@gem_partial_pwrite_pread@reads:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#3282]) +1 other test skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@gem_partial_pwrite_pread@reads.html
- shard-mtlp: NOTRUN -> [SKIP][70] ([i915#3282]) +2 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@gem_partial_pwrite_pread@reads.html
* igt@gem_partial_pwrite_pread@writes-after-reads-display:
- shard-dg1: NOTRUN -> [SKIP][71] ([i915#3282]) +1 other test skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
* igt@gem_pread@snoop:
- shard-rkl: NOTRUN -> [SKIP][72] ([i915#3282]) +3 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@gem_pread@snoop.html
* igt@gem_pwrite@basic-random:
- shard-dg2-9: NOTRUN -> [SKIP][73] ([i915#3282]) +1 other test skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@gem_pwrite@basic-random.html
* igt@gem_pxp@create-regular-buffer:
- shard-rkl: NOTRUN -> [TIMEOUT][74] ([i915#12917] / [i915#12964])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@gem_pxp@create-regular-buffer.html
* igt@gem_pxp@display-protected-crc:
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#4270])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@fail-invalid-protected-context:
- shard-rkl: [PASS][76] -> [TIMEOUT][77] ([i915#12964])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-rkl-8/igt@gem_pxp@fail-invalid-protected-context.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-3/igt@gem_pxp@fail-invalid-protected-context.html
* igt@gem_pxp@hw-rejects-pxp-context:
- shard-tglu-1: NOTRUN -> [SKIP][78] ([i915#13398])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@gem_pxp@hw-rejects-pxp-context.html
- shard-mtlp: NOTRUN -> [SKIP][79] ([i915#13398])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-4/igt@gem_pxp@hw-rejects-pxp-context.html
* igt@gem_pxp@protected-raw-src-copy-not-readible:
- shard-dg2-9: NOTRUN -> [SKIP][80] ([i915#4270]) +1 other test skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@gem_pxp@protected-raw-src-copy-not-readible.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-rkl: [PASS][81] -> [TIMEOUT][82] ([i915#12917] / [i915#12964])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-rkl-8/igt@gem_pxp@reject-modify-context-protection-off-2.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-3/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_render_copy@y-tiled-to-vebox-y-tiled:
- shard-dg2-9: NOTRUN -> [SKIP][83] ([i915#5190] / [i915#8428]) +2 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@gem_render_copy@y-tiled-to-vebox-y-tiled.html
* igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled:
- shard-mtlp: NOTRUN -> [SKIP][84] ([i915#8428]) +1 other test skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html
- shard-dg2: NOTRUN -> [SKIP][85] ([i915#5190] / [i915#8428]) +3 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html
* igt@gem_tiled_partial_pwrite_pread@writes-after-reads:
- shard-dg1: NOTRUN -> [SKIP][86] ([i915#4077]) +5 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@gem_tiled_partial_pwrite_pread@writes-after-reads.html
* igt@gem_tiled_pread_basic:
- shard-dg2: NOTRUN -> [SKIP][87] ([i915#4079])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@gem_tiled_pread_basic.html
* igt@gem_unfence_active_buffers:
- shard-mtlp: NOTRUN -> [SKIP][88] ([i915#4879])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-2/igt@gem_unfence_active_buffers.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-tglu-1: NOTRUN -> [SKIP][89] ([i915#3297]) +1 other test skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-dg2: NOTRUN -> [SKIP][90] ([i915#3297])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@forbidden-operations:
- shard-mtlp: NOTRUN -> [SKIP][91] ([i915#3282] / [i915#3297])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-4/igt@gem_userptr_blits@forbidden-operations.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-dg2-9: NOTRUN -> [SKIP][92] ([i915#3297]) +1 other test skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate:
- shard-dg2-9: NOTRUN -> [SKIP][93] ([i915#3297] / [i915#4880])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@gem_userptr_blits@map-fixed-invalidate.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-mtlp: NOTRUN -> [SKIP][94] ([i915#3297]) +1 other test skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
- shard-dg2: NOTRUN -> [SKIP][95] ([i915#3297] / [i915#4880])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@unsync-unmap:
- shard-rkl: NOTRUN -> [SKIP][96] ([i915#3297]) +1 other test skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@gem_userptr_blits@unsync-unmap.html
* igt@gen7_exec_parse@bitmasks:
- shard-dg2: NOTRUN -> [SKIP][97] +9 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-5/igt@gen7_exec_parse@bitmasks.html
* igt@gen7_exec_parse@chained-batch:
- shard-rkl: NOTRUN -> [SKIP][98] +10 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@gen7_exec_parse@chained-batch.html
* igt@gen9_exec_parse@allowed-single:
- shard-mtlp: NOTRUN -> [SKIP][99] ([i915#2856]) +1 other test skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@gen9_exec_parse@allowed-single.html
- shard-dg2: NOTRUN -> [SKIP][100] ([i915#2856]) +1 other test skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@batch-without-end:
- shard-dg2-9: NOTRUN -> [SKIP][101] ([i915#2856])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@gen9_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@batch-zero-length:
- shard-rkl: NOTRUN -> [SKIP][102] ([i915#2527]) +1 other test skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@gen9_exec_parse@batch-zero-length.html
* igt@gen9_exec_parse@bb-oversize:
- shard-tglu-1: NOTRUN -> [SKIP][103] ([i915#2527] / [i915#2856]) +2 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@gen9_exec_parse@bb-oversize.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-tglu: NOTRUN -> [SKIP][104] ([i915#2527] / [i915#2856]) +1 other test skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-dg1: NOTRUN -> [SKIP][105] ([i915#2527])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@i915_module_load@resize-bar:
- shard-dg1: NOTRUN -> [SKIP][106] ([i915#7178])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-14/igt@i915_module_load@resize-bar.html
* igt@i915_pipe_stress@stress-xrgb8888-ytiled:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#7091])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
- shard-mtlp: NOTRUN -> [SKIP][108] ([i915#8436])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
* igt@i915_pm_freq_api@freq-reset-multiple:
- shard-tglu: NOTRUN -> [SKIP][109] ([i915#8399])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@i915_pm_freq_api@freq-reset-multiple.html
* igt@i915_pm_freq_api@freq-suspend:
- shard-rkl: NOTRUN -> [SKIP][110] ([i915#8399]) +1 other test skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@i915_pm_freq_api@freq-suspend.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglu-1: NOTRUN -> [WARN][111] ([i915#2681]) +1 other test warn
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rps@thresholds-idle:
- shard-mtlp: NOTRUN -> [SKIP][112] ([i915#11681])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-4/igt@i915_pm_rps@thresholds-idle.html
* igt@i915_query@hwconfig_table:
- shard-rkl: NOTRUN -> [SKIP][113] ([i915#6245])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@i915_query@hwconfig_table.html
* igt@i915_selftest@live@workarounds:
- shard-mtlp: [PASS][114] -> [DMESG-FAIL][115] ([i915#12061]) +1 other test dmesg-fail
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-mtlp-3/igt@i915_selftest@live@workarounds.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-1/igt@i915_selftest@live@workarounds.html
* igt@i915_suspend@fence-restore-untiled:
- shard-dg2: NOTRUN -> [SKIP][116] ([i915#4077]) +4 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@i915_suspend@fence-restore-untiled.html
* igt@intel_hwmon@hwmon-read:
- shard-tglu-1: NOTRUN -> [SKIP][117] ([i915#7707])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@intel_hwmon@hwmon-read.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- shard-dg2-9: NOTRUN -> [SKIP][118] ([i915#4212])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
- shard-mtlp: NOTRUN -> [SKIP][119] ([i915#12454] / [i915#12712])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-4/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
- shard-tglu-1: NOTRUN -> [SKIP][120] ([i915#12454] / [i915#12712])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
* igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-hdmi-a-3-y-rc-ccs-cc:
- shard-dg1: NOTRUN -> [SKIP][121] ([i915#8709]) +7 other tests skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-12/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-hdmi-a-3-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-c-hdmi-a-1-4-rc-ccs-cc:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#8709]) +7 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-8/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-c-hdmi-a-1-4-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][123] ([i915#8709]) +1 other test skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-2-4-mc-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][124] ([i915#8709]) +7 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-2-4-mc-ccs.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-tglu-1: NOTRUN -> [SKIP][125] ([i915#9531])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][126] ([i915#4538] / [i915#5286])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][127] ([i915#5286]) +2 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-addfb-size-overflow:
- shard-dg1: NOTRUN -> [SKIP][128] ([i915#5286]) +1 other test skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-14/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-tglu: NOTRUN -> [SKIP][129] ([i915#5286]) +3 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-tglu-1: NOTRUN -> [SKIP][130] ([i915#5286]) +2 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-180:
- shard-mtlp: NOTRUN -> [SKIP][131] +12 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][132] ([i915#3638])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb:
- shard-dg2-9: NOTRUN -> [SKIP][133] ([i915#5190])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_big_fb@y-tiled-addfb.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
- shard-dg2: NOTRUN -> [SKIP][134] ([i915#4538] / [i915#5190]) +3 other tests skip
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-180:
- shard-dg2-9: NOTRUN -> [SKIP][135] ([i915#4538] / [i915#5190]) +4 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-mtlp: NOTRUN -> [SKIP][136] ([i915#6187])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-6/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][137] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][138] ([i915#4423] / [i915#6095]) +5 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-4.html
* igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
- shard-tglu: NOTRUN -> [SKIP][139] ([i915#12313])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
- shard-mtlp: NOTRUN -> [SKIP][140] ([i915#12313]) +1 other test skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-6/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
- shard-dg2: NOTRUN -> [SKIP][141] ([i915#12313]) +1 other test skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc:
- shard-snb: NOTRUN -> [SKIP][142] +48 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-snb2/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@bad-rotation-90-yf-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][143] ([i915#6095]) +24 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@kms_ccs@bad-rotation-90-yf-tiled-ccs.html
* igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs@pipe-b-hdmi-a-2:
- shard-dg2-9: NOTRUN -> [SKIP][144] ([i915#10307] / [i915#6095]) +29 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-dg2: NOTRUN -> [SKIP][145] ([i915#12805])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][146] ([i915#6095]) +69 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][147] ([i915#6095]) +29 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-7/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][148] ([i915#6095]) +19 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-8/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1.html
* igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#10307] / [i915#6095]) +112 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-8/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][150] ([i915#6095]) +44 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
- shard-rkl: NOTRUN -> [SKIP][151] ([i915#12313]) +1 other test skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][152] ([i915#6095]) +167 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-13/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3.html
* igt@kms_cdclk@mode-transition:
- shard-tglu-1: NOTRUN -> [SKIP][153] ([i915#3742])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-rkl: NOTRUN -> [SKIP][154] ([i915#3742])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][155] ([i915#11616] / [i915#7213]) +3 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-8/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html
* igt@kms_chamelium_audio@dp-audio:
- shard-tglu: NOTRUN -> [SKIP][156] ([i915#11151] / [i915#7828]) +2 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@kms_chamelium_audio@dp-audio.html
- shard-dg2: NOTRUN -> [SKIP][157] ([i915#11151] / [i915#7828]) +2 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@kms_chamelium_audio@dp-audio.html
* igt@kms_chamelium_audio@hdmi-audio:
- shard-dg2-9: NOTRUN -> [SKIP][158] ([i915#11151] / [i915#7828]) +4 other tests skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_chamelium_audio@hdmi-audio.html
* igt@kms_chamelium_edid@dp-edid-stress-resolution-4k:
- shard-dg1: NOTRUN -> [SKIP][159] ([i915#11151] / [i915#7828]) +2 other tests skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-14/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html
* igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
- shard-rkl: NOTRUN -> [SKIP][160] ([i915#11151] / [i915#7828]) +2 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium_frames@dp-crc-fast:
- shard-tglu-1: NOTRUN -> [SKIP][161] ([i915#11151] / [i915#7828]) +5 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_chamelium_frames@dp-crc-fast.html
* igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
- shard-mtlp: NOTRUN -> [SKIP][162] ([i915#11151] / [i915#7828]) +5 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-4/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html
* igt@kms_content_protection@atomic:
- shard-tglu: NOTRUN -> [SKIP][163] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@kms_content_protection@atomic.html
- shard-dg2: NOTRUN -> [SKIP][164] ([i915#7118] / [i915#9424])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms:
- shard-mtlp: NOTRUN -> [SKIP][165] ([i915#6944] / [i915#9424]) +1 other test skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@kms_content_protection@atomic-dpms.html
- shard-dg2: NOTRUN -> [FAIL][166] ([i915#7173]) +1 other test fail
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-dg2-9: NOTRUN -> [SKIP][167] ([i915#3299])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-tglu-1: NOTRUN -> [SKIP][168] ([i915#3116] / [i915#3299])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@legacy:
- shard-rkl: NOTRUN -> [SKIP][169] ([i915#7118] / [i915#9424])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@mei-interface:
- shard-rkl: NOTRUN -> [SKIP][170] ([i915#9424])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@uevent:
- shard-dg2-9: NOTRUN -> [SKIP][171] ([i915#7118] / [i915#9424])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-dg1: NOTRUN -> [SKIP][172] ([i915#13049])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-offscreen-max-size:
- shard-mtlp: NOTRUN -> [SKIP][173] ([i915#3555] / [i915#8814])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-4/igt@kms_cursor_crc@cursor-offscreen-max-size.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-rkl: NOTRUN -> [SKIP][174] ([i915#13049])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-128x42:
- shard-mtlp: NOTRUN -> [SKIP][175] ([i915#8814]) +3 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@kms_cursor_crc@cursor-rapid-movement-128x42.html
* igt@kms_cursor_crc@cursor-rapid-movement-max-size:
- shard-rkl: NOTRUN -> [SKIP][176] ([i915#3555]) +2 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-dg1: NOTRUN -> [SKIP][177] ([i915#13049] / [i915#4423])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-tglu: NOTRUN -> [SKIP][178] ([i915#4103]) +1 other test skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
- shard-dg2: NOTRUN -> [SKIP][179] ([i915#4103] / [i915#4213])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-dg2: NOTRUN -> [SKIP][180] ([i915#13046] / [i915#5354]) +1 other test skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
- shard-mtlp: NOTRUN -> [SKIP][181] ([i915#9809])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
- shard-dg2-9: NOTRUN -> [SKIP][182] ([i915#13046] / [i915#5354]) +2 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-tglu-1: NOTRUN -> [SKIP][183] ([i915#9067])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-rkl: NOTRUN -> [SKIP][184] ([i915#4103])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-tglu-1: NOTRUN -> [SKIP][185] ([i915#9723])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
- shard-mtlp: NOTRUN -> [SKIP][186] ([i915#9833])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-2/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-dg2: NOTRUN -> [SKIP][187] ([i915#9833])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][188] ([i915#3804])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html
* igt@kms_dp_aux_dev:
- shard-dg2-9: NOTRUN -> [SKIP][189] ([i915#1257])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_dp_aux_dev.html
* igt@kms_draw_crc@draw-method-blt:
- shard-dg1: NOTRUN -> [DMESG-WARN][190] ([i915#4423]) +3 other tests dmesg-warn
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_draw_crc@draw-method-blt.html
* igt@kms_dsc@dsc-basic:
- shard-rkl: NOTRUN -> [SKIP][191] ([i915#3555] / [i915#3840])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-tglu: NOTRUN -> [SKIP][192] ([i915#3555] / [i915#3840])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-7/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_dsc@dsc-with-formats:
- shard-mtlp: NOTRUN -> [SKIP][193] ([i915#3555] / [i915#3840])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-4/igt@kms_dsc@dsc-with-formats.html
- shard-tglu-1: NOTRUN -> [SKIP][194] ([i915#3555] / [i915#3840])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_dsc@dsc-with-formats.html
* igt@kms_feature_discovery@display-2x:
- shard-tglu-1: NOTRUN -> [SKIP][195] ([i915#1839])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_feature_discovery@display-2x.html
* igt@kms_feature_discovery@display-4x:
- shard-rkl: NOTRUN -> [SKIP][196] ([i915#1839]) +1 other test skip
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@kms_feature_discovery@display-4x.html
* igt@kms_fence_pin_leak:
- shard-dg1: NOTRUN -> [SKIP][197] ([i915#4881])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-tglu: NOTRUN -> [SKIP][198] ([i915#3637]) +3 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-7/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-dg2-9: NOTRUN -> [SKIP][199] ([i915#9934]) +1 other test skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-dg1: NOTRUN -> [SKIP][200] ([i915#9934]) +2 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-dg2: NOTRUN -> [SKIP][201] ([i915#8381])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-flip-vs-fences-interruptible:
- shard-dg2-9: NOTRUN -> [SKIP][202] ([i915#8381])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_flip@2x-flip-vs-fences-interruptible.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-mtlp: NOTRUN -> [SKIP][203] ([i915#3637]) +2 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-6/igt@kms_flip@2x-flip-vs-rmfb.html
- shard-dg2: NOTRUN -> [SKIP][204] ([i915#9934])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-tglu-1: NOTRUN -> [SKIP][205] ([i915#3637]) +3 other tests skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
- shard-rkl: NOTRUN -> [SKIP][206] ([i915#9934]) +4 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a2:
- shard-rkl: NOTRUN -> [FAIL][207] ([i915#11989])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a2.html
* igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a1:
- shard-tglu: NOTRUN -> [FAIL][208] ([i915#11989]) +1 other test fail
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a1.html
* igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a3:
- shard-dg2: NOTRUN -> [FAIL][209] ([i915#11989]) +2 other tests fail
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a3.html
* igt@kms_flip@flip-vs-fences-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][210] ([i915#8381])
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-2/igt@kms_flip@flip-vs-fences-interruptible.html
* igt@kms_flip@flip-vs-modeset-vs-hang@b-hdmi-a1:
- shard-rkl: NOTRUN -> [DMESG-WARN][211] ([i915#12964]) +9 other tests dmesg-warn
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-4/igt@kms_flip@flip-vs-modeset-vs-hang@b-hdmi-a1.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@a-vga1:
- shard-snb: [PASS][212] -> [FAIL][213] ([i915#11989]) +5 other tests fail
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-snb7/igt@kms_flip@wf_vblank-ts-check-interruptible@a-vga1.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-snb5/igt@kms_flip@wf_vblank-ts-check-interruptible@a-vga1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][214] ([i915#2672] / [i915#3555]) +2 other tests skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][215] ([i915#2672] / [i915#8813]) +1 other test skip
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][216] ([i915#2672]) +2 other tests skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode:
- shard-dg2-9: NOTRUN -> [SKIP][217] ([i915#2672]) +1 other test skip
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][218] ([i915#2672] / [i915#3555] / [i915#8813]) +3 other tests skip
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-tglu-1: NOTRUN -> [SKIP][219] ([i915#2587] / [i915#2672]) +2 other tests skip
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
- shard-rkl: NOTRUN -> [SKIP][220] ([i915#2672] / [i915#3555]) +1 other test skip
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][221] ([i915#2672]) +1 other test skip
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
- shard-tglu-1: NOTRUN -> [SKIP][222] ([i915#2672] / [i915#3555]) +2 other tests skip
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-tglu: NOTRUN -> [SKIP][223] ([i915#2672] / [i915#3555])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][224] ([i915#2587] / [i915#2672])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
- shard-dg2-9: NOTRUN -> [SKIP][225] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
- shard-dg1: NOTRUN -> [SKIP][226] ([i915#4423])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
- shard-tglu-1: NOTRUN -> [SKIP][227] +49 other tests skip
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite:
- shard-tglu: NOTRUN -> [SKIP][228] +36 other tests skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary:
- shard-dg2: [PASS][229] -> [FAIL][230] ([i915#6880]) +3 other tests fail
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-dg1: NOTRUN -> [SKIP][231] ([i915#5439])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-dg2: NOTRUN -> [SKIP][232] ([i915#3458]) +6 other tests skip
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][233] ([i915#8708]) +2 other tests skip
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-14/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-dg1: NOTRUN -> [SKIP][234] ([i915#3458] / [i915#4423])
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-dg2-9: NOTRUN -> [SKIP][235] ([i915#8708]) +7 other tests skip
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
- shard-dg1: NOTRUN -> [SKIP][236] +8 other tests skip
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-mtlp: NOTRUN -> [SKIP][237] ([i915#1825]) +16 other tests skip
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite:
- shard-rkl: NOTRUN -> [SKIP][238] ([i915#1825]) +16 other tests skip
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-move:
- shard-dg2: NOTRUN -> [SKIP][239] ([i915#5354]) +12 other tests skip
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite:
- shard-dg2-9: NOTRUN -> [SKIP][240] ([i915#3458]) +9 other tests skip
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2-9: NOTRUN -> [SKIP][241] ([i915#5354]) +10 other tests skip
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][242] ([i915#8708]) +8 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-modesetfrombusy:
- shard-rkl: NOTRUN -> [SKIP][243] ([i915#3023]) +9 other tests skip
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][244] ([i915#8708]) +5 other tests skip
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-4/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite:
- shard-dg1: NOTRUN -> [SKIP][245] ([i915#3458]) +4 other tests skip
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html
* igt@kms_hdmi_inject@inject-audio:
- shard-tglu-1: NOTRUN -> [SKIP][246] ([i915#13030])
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_hdr@brightness-with-hdr:
- shard-rkl: NOTRUN -> [SKIP][247] ([i915#12713])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_hdr@invalid-hdr:
- shard-rkl: NOTRUN -> [SKIP][248] ([i915#3555] / [i915#8228])
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@static-toggle-dpms:
- shard-dg2: [PASS][249] -> [SKIP][250] ([i915#3555] / [i915#8228])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg2-11/igt@kms_hdr@static-toggle-dpms.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-4/igt@kms_hdr@static-toggle-dpms.html
- shard-tglu: NOTRUN -> [SKIP][251] ([i915#3555] / [i915#8228])
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-7/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-tglu: NOTRUN -> [SKIP][252] ([i915#12388])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-7/igt@kms_joiner@basic-force-big-joiner.html
- shard-dg2: [PASS][253] -> [SKIP][254] ([i915#12388])
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg2-11/igt@kms_joiner@basic-force-big-joiner.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-4/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_joiner@basic-ultra-joiner:
- shard-tglu-1: NOTRUN -> [SKIP][255] ([i915#12339])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_joiner@basic-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-rkl: NOTRUN -> [SKIP][256] ([i915#12388])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-tglu: NOTRUN -> [SKIP][257] ([i915#12339])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@kms_joiner@invalid-modeset-ultra-joiner.html
- shard-dg2: NOTRUN -> [SKIP][258] ([i915#12339])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
- shard-dg2-9: NOTRUN -> [SKIP][259] ([i915#13522])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1:
- shard-glk: [PASS][260] -> [INCOMPLETE][261] ([i915#12756])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk6/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk7/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html
* igt@kms_plane_multiple@tiling-yf:
- shard-dg2-9: NOTRUN -> [SKIP][262] ([i915#3555] / [i915#8806])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a:
- shard-dg1: NOTRUN -> [SKIP][263] ([i915#12247]) +4 other tests skip
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation:
- shard-rkl: NOTRUN -> [SKIP][264] ([i915#12247]) +2 other tests skip
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5:
- shard-mtlp: NOTRUN -> [SKIP][265] ([i915#12247] / [i915#6953])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@kms_plane_scaling@planes-downscale-factor-0-5.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
- shard-tglu-1: NOTRUN -> [SKIP][266] ([i915#12247] / [i915#3555])
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
- shard-mtlp: NOTRUN -> [SKIP][267] ([i915#12247] / [i915#3555])
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a:
- shard-tglu-1: NOTRUN -> [SKIP][268] ([i915#12247]) +3 other tests skip
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c:
- shard-mtlp: NOTRUN -> [SKIP][269] ([i915#12247]) +7 other tests skip
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c.html
* igt@kms_pm_backlight@basic-brightness:
- shard-rkl: NOTRUN -> [SKIP][270] ([i915#5354])
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-tglu-1: NOTRUN -> [SKIP][271] ([i915#12343])
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_dc@dc5-retention-flops:
- shard-dg1: NOTRUN -> [SKIP][272] ([i915#3828])
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-14/igt@kms_pm_dc@dc5-retention-flops.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-tglu-1: NOTRUN -> [SKIP][273] ([i915#3828])
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-dg2: NOTRUN -> [SKIP][274] ([i915#8430])
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-mtlp: NOTRUN -> [SKIP][275] ([i915#9519])
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-dg2-9: NOTRUN -> [SKIP][276] ([i915#9519])
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-dg2: NOTRUN -> [SKIP][277] ([i915#9519])
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-tglu-1: NOTRUN -> [SKIP][278] ([i915#9519])
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-dg2: [PASS][279] -> [SKIP][280] ([i915#9519])
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg2-11/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-4/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
- shard-rkl: [PASS][281] -> [SKIP][282] ([i915#9519])
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-rkl-1/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
- shard-tglu: NOTRUN -> [SKIP][283] ([i915#9519])
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-7/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_pm_rpm@pc8-residency:
- shard-dg2-9: NOTRUN -> [SKIP][284]
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_pm_rpm@pc8-residency.html
* igt@kms_prime@basic-crc-hybrid:
- shard-dg2: NOTRUN -> [SKIP][285] ([i915#6524] / [i915#6805]) +1 other test skip
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@kms_prime@basic-crc-hybrid.html
- shard-tglu: NOTRUN -> [SKIP][286] ([i915#6524])
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_prime@basic-crc-vgem:
- shard-dg2-9: NOTRUN -> [SKIP][287] ([i915#6524] / [i915#6805])
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_prime@basic-crc-vgem.html
* igt@kms_prime@d3hot:
- shard-mtlp: NOTRUN -> [SKIP][288] ([i915#6524]) +1 other test skip
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
- shard-dg1: NOTRUN -> [SKIP][289] ([i915#11520]) +1 other test skip
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
- shard-dg2-9: NOTRUN -> [SKIP][290] ([i915#11520]) +2 other tests skip
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][291] ([i915#9808])
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area@pipe-a-edp-1.html
* igt@kms_psr2_sf@pr-cursor-plane-update-sf:
- shard-tglu: NOTRUN -> [SKIP][292] ([i915#11520]) +3 other tests skip
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@kms_psr2_sf@pr-cursor-plane-update-sf.html
* igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf:
- shard-glk: NOTRUN -> [SKIP][293] ([i915#11520])
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk2/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
- shard-rkl: NOTRUN -> [SKIP][294] ([i915#11520]) +4 other tests skip
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
- shard-mtlp: NOTRUN -> [SKIP][295] ([i915#12316]) +4 other tests skip
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-2/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area:
- shard-snb: NOTRUN -> [SKIP][296] ([i915#11520])
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-snb2/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
- shard-dg2: NOTRUN -> [SKIP][297] ([i915#11520]) +2 other tests skip
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area:
- shard-tglu-1: NOTRUN -> [SKIP][298] ([i915#11520]) +5 other tests skip
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-dg2: NOTRUN -> [SKIP][299] ([i915#9683])
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@kms_psr2_su@frontbuffer-xrgb8888.html
- shard-tglu: NOTRUN -> [SKIP][300] ([i915#9683])
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-dg1: NOTRUN -> [SKIP][301] ([i915#9683])
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-sprite-render:
- shard-dg1: NOTRUN -> [SKIP][302] ([i915#1072] / [i915#9732]) +6 other tests skip
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_psr@fbc-pr-sprite-render.html
* igt@kms_psr@fbc-psr-dpms:
- shard-mtlp: NOTRUN -> [SKIP][303] ([i915#9688]) +6 other tests skip
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-4/igt@kms_psr@fbc-psr-dpms.html
* igt@kms_psr@fbc-psr-primary-render:
- shard-tglu-1: NOTRUN -> [SKIP][304] ([i915#9732]) +12 other tests skip
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_psr@fbc-psr-primary-render.html
* igt@kms_psr@fbc-psr2-sprite-mmap-cpu:
- shard-dg2-9: NOTRUN -> [SKIP][305] ([i915#1072] / [i915#9732]) +10 other tests skip
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_psr@fbc-psr2-sprite-mmap-cpu.html
* igt@kms_psr@psr-no-drrs:
- shard-glk: NOTRUN -> [SKIP][306] +58 other tests skip
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk2/igt@kms_psr@psr-no-drrs.html
* igt@kms_psr@psr2-cursor-plane-move:
- shard-dg2: NOTRUN -> [SKIP][307] ([i915#1072] / [i915#9732]) +8 other tests skip
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@kms_psr@psr2-cursor-plane-move.html
* igt@kms_psr@psr2-cursor-render:
- shard-tglu: NOTRUN -> [SKIP][308] ([i915#9732]) +6 other tests skip
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-7/igt@kms_psr@psr2-cursor-render.html
* igt@kms_psr@psr2-sprite-mmap-cpu:
- shard-rkl: NOTRUN -> [SKIP][309] ([i915#1072] / [i915#9732]) +9 other tests skip
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@kms_psr@psr2-sprite-mmap-cpu.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-tglu: NOTRUN -> [SKIP][310] ([i915#9685])
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-tglu-1: NOTRUN -> [SKIP][311] ([i915#5289])
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
- shard-rkl: NOTRUN -> [SKIP][312] ([i915#5289])
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
- shard-dg2: NOTRUN -> [SKIP][313] ([i915#5190]) +1 other test skip
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
- shard-mtlp: NOTRUN -> [SKIP][314] ([i915#5289])
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
* igt@kms_scaling_modes@scaling-mode-center:
- shard-tglu-1: NOTRUN -> [SKIP][315] ([i915#3555]) +2 other tests skip
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-1/igt@kms_scaling_modes@scaling-mode-center.html
* igt@kms_scaling_modes@scaling-mode-full:
- shard-tglu: NOTRUN -> [SKIP][316] ([i915#3555]) +1 other test skip
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-7/igt@kms_scaling_modes@scaling-mode-full.html
* igt@kms_scaling_modes@scaling-mode-full-aspect:
- shard-dg1: NOTRUN -> [SKIP][317] ([i915#3555] / [i915#4423])
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_scaling_modes@scaling-mode-full-aspect.html
* igt@kms_selftest@drm_framebuffer:
- shard-tglu: NOTRUN -> [ABORT][318] ([i915#13179]) +1 other test abort
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-2/igt@kms_selftest@drm_framebuffer.html
- shard-mtlp: NOTRUN -> [ABORT][319] ([i915#13179]) +1 other test abort
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-6/igt@kms_selftest@drm_framebuffer.html
* igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free:
- shard-dg2: NOTRUN -> [ABORT][320] ([i915#13179]) +1 other test abort
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free.html
* igt@kms_sysfs_edid_timing:
- shard-dg2-9: NOTRUN -> [FAIL][321] ([IGT#160])
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_sysfs_edid_timing.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-rkl: NOTRUN -> [SKIP][322] ([i915#8623])
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_vrr@flip-basic-fastset:
- shard-dg1: NOTRUN -> [SKIP][323] ([i915#9906])
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@flip-dpms:
- shard-dg2-9: NOTRUN -> [SKIP][324] ([i915#3555]) +3 other tests skip
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@kms_vrr@flip-dpms.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-dg2: NOTRUN -> [SKIP][325] ([i915#9906])
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_writeback@writeback-check-output:
- shard-rkl: NOTRUN -> [SKIP][326] ([i915#2437])
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-rkl: NOTRUN -> [SKIP][327] ([i915#2437] / [i915#9412])
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-glk: NOTRUN -> [SKIP][328] ([i915#2437])
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk2/igt@kms_writeback@writeback-invalid-parameters.html
* igt@prime_vgem@basic-fence-flip:
- shard-dg2: NOTRUN -> [SKIP][329] ([i915#3708])
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-read:
- shard-dg1: NOTRUN -> [SKIP][330] ([i915#3708])
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-read:
- shard-rkl: NOTRUN -> [SKIP][331] ([i915#3291] / [i915#3708])
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@prime_vgem@basic-read.html
* igt@prime_vgem@coherency-gtt:
- shard-dg2-9: NOTRUN -> [SKIP][332] ([i915#3708] / [i915#4077])
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@prime_vgem@coherency-gtt.html
* igt@prime_vgem@fence-flip-hang:
- shard-rkl: NOTRUN -> [SKIP][333] ([i915#3708])
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-2/igt@prime_vgem@fence-flip-hang.html
* igt@prime_vgem@fence-write-hang:
- shard-dg2-9: NOTRUN -> [SKIP][334] ([i915#3708])
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@prime_vgem@fence-write-hang.html
* igt@sriov_basic@bind-unbind-vf@vf-4:
- shard-tglu: NOTRUN -> [FAIL][335] ([i915#12910]) +9 other tests fail
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-7/igt@sriov_basic@bind-unbind-vf@vf-4.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-dg2-9: NOTRUN -> [SKIP][336] ([i915#9917])
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-9/igt@sriov_basic@enable-vfs-autoprobe-on.html
#### Possible fixes ####
* igt@gem_eio@in-flight-internal-1us:
- shard-mtlp: [ABORT][337] ([i915#13193]) -> [PASS][338] +3 other tests pass
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-mtlp-7/igt@gem_eio@in-flight-internal-1us.html
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-3/igt@gem_eio@in-flight-internal-1us.html
* igt@gem_pxp@create-valid-protected-context:
- shard-rkl: [TIMEOUT][339] ([i915#12964]) -> [PASS][340]
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-rkl-5/igt@gem_pxp@create-valid-protected-context.html
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-8/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_pxp@reject-modify-context-protection-on:
- shard-rkl: [TIMEOUT][341] ([i915#12917] / [i915#12964]) -> [PASS][342] +1 other test pass
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-rkl-5/igt@gem_pxp@reject-modify-context-protection-on.html
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-8/igt@gem_pxp@reject-modify-context-protection-on.html
* igt@i915_module_load@load:
- shard-glk: ([PASS][343], [PASS][344], [PASS][345], [PASS][346], [PASS][347], [PASS][348], [PASS][349], [PASS][350], [PASS][351], [PASS][352], [PASS][353], [PASS][354], [PASS][355], [PASS][356], [PASS][357], [DMESG-WARN][358], [PASS][359], [PASS][360], [PASS][361], [PASS][362], [PASS][363], [PASS][364]) ([i915#118]) -> ([PASS][365], [PASS][366], [PASS][367], [PASS][368], [PASS][369], [PASS][370], [PASS][371], [PASS][372], [PASS][373], [PASS][374], [PASS][375], [PASS][376], [PASS][377], [PASS][378], [PASS][379], [PASS][380], [PASS][381], [PASS][382], [PASS][383], [PASS][384], [PASS][385], [PASS][386])
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk6/igt@i915_module_load@load.html
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk7/igt@i915_module_load@load.html
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk2/igt@i915_module_load@load.html
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk9/igt@i915_module_load@load.html
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk2/igt@i915_module_load@load.html
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk8/igt@i915_module_load@load.html
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk1/igt@i915_module_load@load.html
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk4/igt@i915_module_load@load.html
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk9/igt@i915_module_load@load.html
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk3/igt@i915_module_load@load.html
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk1/igt@i915_module_load@load.html
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk8/igt@i915_module_load@load.html
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk1/igt@i915_module_load@load.html
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk6/igt@i915_module_load@load.html
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk2/igt@i915_module_load@load.html
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk7/igt@i915_module_load@load.html
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk7/igt@i915_module_load@load.html
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk9/igt@i915_module_load@load.html
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk9/igt@i915_module_load@load.html
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk3/igt@i915_module_load@load.html
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk7/igt@i915_module_load@load.html
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk4/igt@i915_module_load@load.html
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk7/igt@i915_module_load@load.html
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk8/igt@i915_module_load@load.html
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk3/igt@i915_module_load@load.html
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk9/igt@i915_module_load@load.html
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk8/igt@i915_module_load@load.html
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk8/igt@i915_module_load@load.html
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk4/igt@i915_module_load@load.html
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk2/igt@i915_module_load@load.html
[373]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk1/igt@i915_module_load@load.html
[374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk6/igt@i915_module_load@load.html
[375]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk9/igt@i915_module_load@load.html
[376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk9/igt@i915_module_load@load.html
[377]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk2/igt@i915_module_load@load.html
[378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk9/igt@i915_module_load@load.html
[379]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk6/igt@i915_module_load@load.html
[380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk1/igt@i915_module_load@load.html
[381]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk7/igt@i915_module_load@load.html
[382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk4/igt@i915_module_load@load.html
[383]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk3/igt@i915_module_load@load.html
[384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk3/igt@i915_module_load@load.html
[385]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk6/igt@i915_module_load@load.html
[386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk2/igt@i915_module_load@load.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg1: [ABORT][387] ([i915#9820]) -> [PASS][388]
[387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg1-17/igt@i915_module_load@reload-with-fault-injection.html
[388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-dg2: [FAIL][389] ([i915#12942]) -> [PASS][390] +1 other test pass
[389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg2-6/igt@i915_pm_rc6_residency@rc6-accuracy.html
[390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-6/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][391] -> [PASS][392]
[391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-snb2/igt@i915_pm_rps@reset.html
[392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-snb2/igt@i915_pm_rps@reset.html
* igt@kms_atomic_interruptible@universal-setplane-cursor:
- shard-dg1: [DMESG-WARN][393] ([i915#4423]) -> [PASS][394] +4 other tests pass
[393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg1-18/igt@kms_atomic_interruptible@universal-setplane-cursor.html
[394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-14/igt@kms_atomic_interruptible@universal-setplane-cursor.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-dg2: [FAIL][395] ([i915#5956]) -> [PASS][396]
[395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg2-10/igt@kms_atomic_transition@plane-all-modeset-transition.html
[396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-2/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_color@deep-color:
- shard-dg2: [SKIP][397] ([i915#3555]) -> [PASS][398]
[397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg2-8/igt@kms_color@deep-color.html
[398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-10/igt@kms_color@deep-color.html
* igt@kms_cursor_crc@cursor-onscreen-128x42:
- shard-rkl: [FAIL][399] ([i915#13566]) -> [PASS][400]
[399]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-rkl-7/igt@kms_cursor_crc@cursor-onscreen-128x42.html
[400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-5/igt@kms_cursor_crc@cursor-onscreen-128x42.html
* igt@kms_cursor_crc@cursor-onscreen-256x85:
- shard-tglu: [FAIL][401] ([i915#13566]) -> [PASS][402] +3 other tests pass
[401]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-tglu-3/igt@kms_cursor_crc@cursor-onscreen-256x85.html
[402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-tglu-5/igt@kms_cursor_crc@cursor-onscreen-256x85.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-dg1: [FAIL][403] ([i915#13027]) -> [PASS][404]
[403]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg1-14/igt@kms_flip@flip-vs-expired-vblank.html
[404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-13/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
- shard-snb: [SKIP][405] -> [PASS][406]
[405]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-snb1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html
[406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-snb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_plane_scaling@plane-upscale-20x20-with-pixel-format@pipe-a:
- shard-rkl: [DMESG-WARN][407] ([i915#12964]) -> [PASS][408] +11 other tests pass
[407]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-rkl-5/igt@kms_plane_scaling@plane-upscale-20x20-with-pixel-format@pipe-a.html
[408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-8/igt@kms_plane_scaling@plane-upscale-20x20-with-pixel-format@pipe-a.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-rkl: [SKIP][409] ([i915#9519]) -> [PASS][410] +1 other test pass
[409]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-rkl-5/igt@kms_pm_rpm@dpms-lpsp.html
[410]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-rkl-4/igt@kms_pm_rpm@dpms-lpsp.html
* igt@perf_pmu@busy-double-start@ccs0:
- shard-mtlp: [FAIL][411] ([i915#4349]) -> [PASS][412]
[411]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-mtlp-2/igt@perf_pmu@busy-double-start@ccs0.html
[412]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-mtlp-6/igt@perf_pmu@busy-double-start@ccs0.html
#### Warnings ####
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg2: [ABORT][413] ([i915#9820]) -> [ABORT][414] ([i915#10887] / [i915#9820])
[413]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html
[414]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-3/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_selftest@mock:
- shard-glk: [DMESG-WARN][415] ([i915#1982] / [i915#9311]) -> [DMESG-WARN][416] ([i915#9311])
[415]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk1/igt@i915_selftest@mock.html
[416]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk9/igt@i915_selftest@mock.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-glk: [INCOMPLETE][417] ([i915#4817]) -> [INCOMPLETE][418] ([i915#1982] / [i915#4817])
[417]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-glk3/igt@i915_suspend@basic-s3-without-i915.html
[418]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-glk2/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-dg1: [SKIP][419] ([i915#4423] / [i915#4538] / [i915#5286]) -> [SKIP][420] ([i915#4538] / [i915#5286])
[419]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg1-13/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
[420]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-18/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_content_protection@srm:
- shard-dg2: [FAIL][421] ([i915#7173]) -> [SKIP][422] ([i915#7118])
[421]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg2-10/igt@kms_content_protection@srm.html
[422]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-2/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@cursor-random-32x10:
- shard-dg1: [SKIP][423] ([i915#3555] / [i915#4423]) -> [SKIP][424] ([i915#3555])
[423]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg1-13/igt@kms_cursor_crc@cursor-random-32x10.html
[424]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-18/igt@kms_cursor_crc@cursor-random-32x10.html
* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt:
- shard-dg1: [SKIP][425] ([i915#4423] / [i915#8708]) -> [SKIP][426] ([i915#8708]) +1 other test skip
[425]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg1-14/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt.html
[426]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-12/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu:
- shard-dg2: [SKIP][427] ([i915#10433] / [i915#3458]) -> [SKIP][428] ([i915#3458]) +2 other tests skip
[427]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu.html
[428]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-dg1: [SKIP][429] ([i915#4423]) -> [SKIP][430] +1 other test skip
[429]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
[430]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- shard-dg2: [SKIP][431] ([i915#3458]) -> [SKIP][432] ([i915#10433] / [i915#3458]) +2 other tests skip
[431]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
[432]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt:
- shard-dg1: [SKIP][433] ([i915#3458] / [i915#4423]) -> [SKIP][434] ([i915#3458])
[433]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16107/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html
[434]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html
[IGT#160]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/160
[i915#10307
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144588v2/index.html
[-- Attachment #2: Type: text/html, Size: 111301 bytes --]
^ permalink raw reply [flat|nested] 29+ messages in thread
* RE: [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for shared_dpll_init
2025-02-11 14:23 ` Kandpal, Suraj
@ 2025-02-11 16:57 ` Jani Nikula
2025-02-12 7:35 ` Kandpal, Suraj
0 siblings, 1 reply; 29+ messages in thread
From: Jani Nikula @ 2025-02-11 16:57 UTC (permalink / raw)
To: Kandpal, Suraj, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K
On Tue, 11 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Tuesday, February 11, 2025 6:45 PM
>> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
>> xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
>> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Kandpal, Suraj
>> <suraj.kandpal@intel.com>
>> Subject: Re: [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for
>> shared_dpll_init
>>
>> On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>> > Use intel_display as an argument for intel_shared_dpll_init() and
>> > replace drm_i915_private in function wherever possible.
>> > While at it prefer using display->platform.xx over IS_PLATFORM.
>> >
>> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> > ---
>> > .../drm/i915/display/intel_display_driver.c | 2 +-
>> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 49
>> > ++++++++++--------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h |
>> > 3 +-
>> > 3 files changed, 27 insertions(+), 27 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
>> > b/drivers/gpu/drm/i915/display/intel_display_driver.c
>> > index 978f530c810e..852f1129a058 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
>> > @@ -448,7 +448,7 @@ int intel_display_driver_probe_nogem(struct
>> intel_display *display)
>> > }
>> >
>> > intel_plane_possible_crtcs_init(display);
>> > - intel_shared_dpll_init(i915);
>> > + intel_shared_dpll_init(display);
>> > intel_fdi_pll_freq_update(i915);
>> >
>> > intel_update_czclk(i915);
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> > index f94da1ffc8ce..26b6b9372fa3 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> > @@ -2042,8 +2042,8 @@ static void bxt_ddi_pll_enable(struct
>> > intel_display *display, {
>> > const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
>> > enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping
>> */
>> > - enum dpio_phy phy;
>> > - enum dpio_channel ch;
>> > + enum dpio_phy phy = DPIO_PHY0;
>> > + enum dpio_channel ch = DPIO_CH0;
>>
>> Unrelated change, please drop.
>>
>
> The problem is by dropping these changes I am not able to build the kernel and it throws the following warning because of which I had to add this
>
>
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c: In function _bxt_ddi_pll_enable_:
> ./drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg_defs.h:240:56: error: _phy_ is used uninitialized [-Werror=uniniti
> alized]
> 240 | (BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) + \
> | ^
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2047:23: note: _phy_ was declared here
> 2047 | enum dpio_phy phy;
> | ^~~
> In file included from ./drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h:6,
> from drivers/gpu/drm/i915/display/intel_display_reg_defs.h:9,
> from drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h:9,
> from drivers/gpu/drm/i915/display/intel_dpll_mgr.c:27:
> ./drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg_defs.h:213:58: error: _ch_ is used uninitialized [-Werror=uninitia
> lized]
> 213 | #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
> | ^
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2048:27: note: _ch_ was declared here
> 2048 | enum dpio_channel ch;
Did you think to look into why this happens? I encourage you to always
do that instead of just silencing the warning. You'll learn about C and
the compiler.
It's quite interesting and subtle and deserves to be mentioned in the
commit message.
For i915.ko, bxt_port_to_phy_channel() is a regular function, and the
compiler will likely assume it'll initialize the parameters. And it
does.
For xe.ko, bxt_port_to_phy_channel() is a static inline stub, and the
compiler can be absolutely certain the parameters aren't initialized.
So, why does this cause an error now? The above didn't change now!
With IS_GEMINILAKE() || IS_BROXTON() the compiler can be sure it's false
for xe.ko. The whole chain bxt_pll_mgr -> bxt_plls -> bxt_ddi_pll_funcs
-> bxt_ddi_pll_enable can be optimized away. It's unreachable.
Not so with display->platform.geminilake ||
display->platform.broxton. The compiler sees use of uninitialized
variables.
BR,
Jani.
>
> Regards,
> Suraj Kandpal
>
>> With that fixed,
>>
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>>
>>
>> > u32 temp;
>> >
>> > bxt_port_to_phy_channel(display, port, &phy, &ch); @@ -4302,40
>> > +4302,41 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
>> >
>> > /**
>> > * intel_shared_dpll_init - Initialize shared DPLLs
>> > - * @i915: i915 device
>> > + * @display: intel_display device
>> > *
>> > - * Initialize shared DPLLs for @i915.
>> > + * Initialize shared DPLLs for @display.
>> > */
>> > -void intel_shared_dpll_init(struct drm_i915_private *i915)
>> > +void intel_shared_dpll_init(struct intel_display *display)
>> > {
>> > + struct drm_i915_private *i915 = to_i915(display->drm);
>> > const struct intel_dpll_mgr *dpll_mgr = NULL;
>> > const struct dpll_info *dpll_info;
>> > int i;
>> >
>> > - mutex_init(&i915->display.dpll.lock);
>> > + mutex_init(&display->dpll.lock);
>> >
>> > - if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915))
>> > + if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
>> > /* No shared DPLLs on DG2; port PLLs are part of the PHY */
>> > dpll_mgr = NULL;
>> > - else if (IS_ALDERLAKE_P(i915))
>> > + else if (display->platform.alderlake_p)
>> > dpll_mgr = &adlp_pll_mgr;
>> > - else if (IS_ALDERLAKE_S(i915))
>> > + else if (display->platform.alderlake_s)
>> > dpll_mgr = &adls_pll_mgr;
>> > - else if (IS_DG1(i915))
>> > + else if (display->platform.dg1)
>> > dpll_mgr = &dg1_pll_mgr;
>> > - else if (IS_ROCKETLAKE(i915))
>> > + else if (display->platform.rocketlake)
>> > dpll_mgr = &rkl_pll_mgr;
>> > - else if (DISPLAY_VER(i915) >= 12)
>> > + else if (DISPLAY_VER(display) >= 12)
>> > dpll_mgr = &tgl_pll_mgr;
>> > - else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915))
>> > + else if (display->platform.jasperlake ||
>> > +display->platform.elkhartlake)
>> > dpll_mgr = &ehl_pll_mgr;
>> > - else if (DISPLAY_VER(i915) >= 11)
>> > + else if (DISPLAY_VER(display) >= 11)
>> > dpll_mgr = &icl_pll_mgr;
>> > - else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
>> > + else if (display->platform.geminilake || display->platform.broxton)
>> > dpll_mgr = &bxt_pll_mgr;
>> > - else if (DISPLAY_VER(i915) == 9)
>> > + else if (DISPLAY_VER(display) == 9)
>> > dpll_mgr = &skl_pll_mgr;
>> > - else if (HAS_DDI(i915))
>> > + else if (HAS_DDI(display))
>> > dpll_mgr = &hsw_pll_mgr;
>> > else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915))
>> > dpll_mgr = &pch_pll_mgr;
>> > @@ -4346,20 +4347,20 @@ void intel_shared_dpll_init(struct
>> drm_i915_private *i915)
>> > dpll_info = dpll_mgr->dpll_info;
>> >
>> > for (i = 0; dpll_info[i].name; i++) {
>> > - if (drm_WARN_ON(&i915->drm,
>> > - i >= ARRAY_SIZE(i915-
>> >display.dpll.shared_dplls)))
>> > + if (drm_WARN_ON(display->drm,
>> > + i >= ARRAY_SIZE(display->dpll.shared_dplls)))
>> > break;
>> >
>> > /* must fit into unsigned long bitmask on 32bit */
>> > - if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32))
>> > + if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
>> > break;
>> >
>> > - i915->display.dpll.shared_dplls[i].info = &dpll_info[i];
>> > - i915->display.dpll.shared_dplls[i].index = i;
>> > + display->dpll.shared_dplls[i].info = &dpll_info[i];
>> > + display->dpll.shared_dplls[i].index = i;
>> > }
>> >
>> > - i915->display.dpll.mgr = dpll_mgr;
>> > - i915->display.dpll.num_shared_dpll = i;
>> > + display->dpll.mgr = dpll_mgr;
>> > + display->dpll.num_shared_dpll = i;
>> > }
>> >
>> > /**
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> > index 3d988f17f31d..caffb084830c 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> > @@ -35,7 +35,6 @@
>> > ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
>> >
>> > enum tc_port;
>> > -struct drm_i915_private;
>> > struct drm_printer;
>> > struct intel_atomic_state;
>> > struct intel_crtc;
>> > @@ -422,7 +421,7 @@ bool intel_dpll_get_hw_state(struct intel_display
>> > *display, void intel_enable_shared_dpll(const struct intel_crtc_state
>> > *crtc_state); void intel_disable_shared_dpll(const struct
>> > intel_crtc_state *crtc_state); void
>> > intel_shared_dpll_swap_state(struct intel_atomic_state *state); -void
>> > intel_shared_dpll_init(struct drm_i915_private *i915);
>> > +void intel_shared_dpll_init(struct intel_display *display);
>> > void intel_dpll_update_ref_clks(struct intel_display *display); void
>> > intel_dpll_readout_hw_state(struct intel_display *display); void
>> > intel_dpll_sanitize_state(struct intel_display *display);
>>
>> --
>> Jani Nikula, Intel
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* RE: [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for shared_dpll_init
2025-02-11 16:57 ` Jani Nikula
@ 2025-02-12 7:35 ` Kandpal, Suraj
0 siblings, 0 replies; 29+ messages in thread
From: Kandpal, Suraj @ 2025-02-12 7:35 UTC (permalink / raw)
To: Nikula, Jani, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, February 11, 2025 10:27 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Subject: RE: [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for
> shared_dpll_init
>
> On Tue, 11 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
> >> -----Original Message-----
> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> Sent: Tuesday, February 11, 2025 6:45 PM
> >> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> >> xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> >> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Kandpal, Suraj
> >> <suraj.kandpal@intel.com>
> >> Subject: Re: [PATCH 8/9] drm/i915/dpll: Accept intel_display as
> >> argument for shared_dpll_init
> >>
> >> On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> >> > Use intel_display as an argument for intel_shared_dpll_init() and
> >> > replace drm_i915_private in function wherever possible.
> >> > While at it prefer using display->platform.xx over IS_PLATFORM.
> >> >
> >> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> >> > ---
> >> > .../drm/i915/display/intel_display_driver.c | 2 +-
> >> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 49
> >> > ++++++++++--------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >> > ++++++++++|
> >> > 3 +-
> >> > 3 files changed, 27 insertions(+), 27 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> >> > b/drivers/gpu/drm/i915/display/intel_display_driver.c
> >> > index 978f530c810e..852f1129a058 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> >> > @@ -448,7 +448,7 @@ int intel_display_driver_probe_nogem(struct
> >> intel_display *display)
> >> > }
> >> >
> >> > intel_plane_possible_crtcs_init(display);
> >> > - intel_shared_dpll_init(i915);
> >> > + intel_shared_dpll_init(display);
> >> > intel_fdi_pll_freq_update(i915);
> >> >
> >> > intel_update_czclk(i915);
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> > index f94da1ffc8ce..26b6b9372fa3 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> > @@ -2042,8 +2042,8 @@ static void bxt_ddi_pll_enable(struct
> >> > intel_display *display, {
> >> > const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> >> > enum port port = (enum port)pll->info->id; /* 1:1 port->PLL
> >> > mapping
> >> */
> >> > - enum dpio_phy phy;
> >> > - enum dpio_channel ch;
> >> > + enum dpio_phy phy = DPIO_PHY0;
> >> > + enum dpio_channel ch = DPIO_CH0;
> >>
> >> Unrelated change, please drop.
> >>
> >
> > The problem is by dropping these changes I am not able to build the
> > kernel and it throws the following warning because of which I had to
> > add this
> >
> >
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c: In function
> _bxt_ddi_pll_enable_:
> > ./drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg_defs.h:24
> > 0:56: error: _phy_ is used uninitialized [-Werror=uniniti alized]
> > 240 | (BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +
> \
> > | ^
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2047:23: note: _phy_ was
> declared here
> > 2047 | enum dpio_phy phy;
> > | ^~~
> > In file included from ./drivers/gpu/drm/xe/compat-i915-
> headers/i915_reg_defs.h:6,
> > from drivers/gpu/drm/i915/display/intel_display_reg_defs.h:9,
> > from drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h:9,
> > from drivers/gpu/drm/i915/display/intel_dpll_mgr.c:27:
> > ./drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg_defs.h:21
> > 3:58: error: _ch_ is used uninitialized [-Werror=uninitia lized]
> > 213 | #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) -
> (__a)))
> > | ^
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2048:27: note: _ch_ was
> declared here
> > 2048 | enum dpio_channel ch;
>
> Did you think to look into why this happens? I encourage you to always do
> that instead of just silencing the warning. You'll learn about C and the
> compiler.
>
> It's quite interesting and subtle and deserves to be mentioned in the
> commit message.
>
> For i915.ko, bxt_port_to_phy_channel() is a regular function, and the
> compiler will likely assume it'll initialize the parameters. And it does.
>
> For xe.ko, bxt_port_to_phy_channel() is a static inline stub, and the
> compiler can be absolutely certain the parameters aren't initialized.
>
> So, why does this cause an error now? The above didn't change now!
>
> With IS_GEMINILAKE() || IS_BROXTON() the compiler can be sure it's false
> for xe.ko. The whole chain bxt_pll_mgr -> bxt_plls -> bxt_ddi_pll_funcs
> -> bxt_ddi_pll_enable can be optimized away. It's unreachable.
>
> Not so with display->platform.geminilake ||
> display->platform.broxton. The compiler sees use of uninitialized
> variables.
Ahh ohkay, I understand it now thanks for explaining it.
Will amend the commit message
Will explore these things and add them to commit message in future too.
Regards,
Suraj Kandpal
>
> BR,
> Jani.
>
>
>
> >
> > Regards,
> > Suraj Kandpal
> >
> >> With that fixed,
> >>
> >> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> >>
> >>
> >> > u32 temp;
> >> >
> >> > bxt_port_to_phy_channel(display, port, &phy, &ch); @@ -4302,40
> >> > +4302,41 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
> >> >
> >> > /**
> >> > * intel_shared_dpll_init - Initialize shared DPLLs
> >> > - * @i915: i915 device
> >> > + * @display: intel_display device
> >> > *
> >> > - * Initialize shared DPLLs for @i915.
> >> > + * Initialize shared DPLLs for @display.
> >> > */
> >> > -void intel_shared_dpll_init(struct drm_i915_private *i915)
> >> > +void intel_shared_dpll_init(struct intel_display *display)
> >> > {
> >> > + struct drm_i915_private *i915 = to_i915(display->drm);
> >> > const struct intel_dpll_mgr *dpll_mgr = NULL;
> >> > const struct dpll_info *dpll_info;
> >> > int i;
> >> >
> >> > - mutex_init(&i915->display.dpll.lock);
> >> > + mutex_init(&display->dpll.lock);
> >> >
> >> > - if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915))
> >> > + if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
> >> > /* No shared DPLLs on DG2; port PLLs are part of the PHY */
> >> > dpll_mgr = NULL;
> >> > - else if (IS_ALDERLAKE_P(i915))
> >> > + else if (display->platform.alderlake_p)
> >> > dpll_mgr = &adlp_pll_mgr;
> >> > - else if (IS_ALDERLAKE_S(i915))
> >> > + else if (display->platform.alderlake_s)
> >> > dpll_mgr = &adls_pll_mgr;
> >> > - else if (IS_DG1(i915))
> >> > + else if (display->platform.dg1)
> >> > dpll_mgr = &dg1_pll_mgr;
> >> > - else if (IS_ROCKETLAKE(i915))
> >> > + else if (display->platform.rocketlake)
> >> > dpll_mgr = &rkl_pll_mgr;
> >> > - else if (DISPLAY_VER(i915) >= 12)
> >> > + else if (DISPLAY_VER(display) >= 12)
> >> > dpll_mgr = &tgl_pll_mgr;
> >> > - else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915))
> >> > + else if (display->platform.jasperlake ||
> >> > +display->platform.elkhartlake)
> >> > dpll_mgr = &ehl_pll_mgr;
> >> > - else if (DISPLAY_VER(i915) >= 11)
> >> > + else if (DISPLAY_VER(display) >= 11)
> >> > dpll_mgr = &icl_pll_mgr;
> >> > - else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
> >> > + else if (display->platform.geminilake ||
> >> > + display->platform.broxton)
> >> > dpll_mgr = &bxt_pll_mgr;
> >> > - else if (DISPLAY_VER(i915) == 9)
> >> > + else if (DISPLAY_VER(display) == 9)
> >> > dpll_mgr = &skl_pll_mgr;
> >> > - else if (HAS_DDI(i915))
> >> > + else if (HAS_DDI(display))
> >> > dpll_mgr = &hsw_pll_mgr;
> >> > else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915))
> >> > dpll_mgr = &pch_pll_mgr; @@ -4346,20 +4347,20 @@ void
> >> > intel_shared_dpll_init(struct
> >> drm_i915_private *i915)
> >> > dpll_info = dpll_mgr->dpll_info;
> >> >
> >> > for (i = 0; dpll_info[i].name; i++) {
> >> > - if (drm_WARN_ON(&i915->drm,
> >> > - i >= ARRAY_SIZE(i915-
> >> >display.dpll.shared_dplls)))
> >> > + if (drm_WARN_ON(display->drm,
> >> > + i >=
> >> > + ARRAY_SIZE(display->dpll.shared_dplls)))
> >> > break;
> >> >
> >> > /* must fit into unsigned long bitmask on 32bit */
> >> > - if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32))
> >> > + if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
> >> > break;
> >> >
> >> > - i915->display.dpll.shared_dplls[i].info = &dpll_info[i];
> >> > - i915->display.dpll.shared_dplls[i].index = i;
> >> > + display->dpll.shared_dplls[i].info = &dpll_info[i];
> >> > + display->dpll.shared_dplls[i].index = i;
> >> > }
> >> >
> >> > - i915->display.dpll.mgr = dpll_mgr;
> >> > - i915->display.dpll.num_shared_dpll = i;
> >> > + display->dpll.mgr = dpll_mgr;
> >> > + display->dpll.num_shared_dpll = i;
> >> > }
> >> >
> >> > /**
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >> > index 3d988f17f31d..caffb084830c 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >> > @@ -35,7 +35,6 @@
> >> > ((__pll) = &(__display)->dpll.shared_dplls[(__i)])
> >> > ; (__i)++)
> >> >
> >> > enum tc_port;
> >> > -struct drm_i915_private;
> >> > struct drm_printer;
> >> > struct intel_atomic_state;
> >> > struct intel_crtc;
> >> > @@ -422,7 +421,7 @@ bool intel_dpll_get_hw_state(struct
> >> > intel_display *display, void intel_enable_shared_dpll(const struct
> >> > intel_crtc_state *crtc_state); void
> >> > intel_disable_shared_dpll(const struct intel_crtc_state
> >> > *crtc_state); void intel_shared_dpll_swap_state(struct
> >> > intel_atomic_state *state); -void intel_shared_dpll_init(struct
> >> > drm_i915_private *i915);
> >> > +void intel_shared_dpll_init(struct intel_display *display);
> >> > void intel_dpll_update_ref_clks(struct intel_display *display);
> >> > void intel_dpll_readout_hw_state(struct intel_display *display);
> >> > void intel_dpll_sanitize_state(struct intel_display *display);
> >>
> >> --
> >> Jani Nikula, Intel
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* RE: [PATCH 0/9] drm_i915_private to intel_display cleanup
2025-02-11 10:48 [PATCH 0/9] drm_i915_private to intel_display cleanup Suraj Kandpal
` (12 preceding siblings ...)
2025-02-11 16:23 ` ✗ i915.CI.Full: failure " Patchwork
@ 2025-02-12 9:54 ` Kandpal, Suraj
13 siblings, 0 replies; 29+ messages in thread
From: Kandpal, Suraj @ 2025-02-12 9:54 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K, Nikula, Jani
> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Tuesday, February 11, 2025 4:19 PM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH 0/9] drm_i915_private to intel_display cleanup
>
> This series started as a cleanup to convert as many drm_i915_private to
> intel_display in intel_display_debug_fs but overflowed and ended up
> cleaning intel_dpll_mgr.c part of the code too and some other places calling
> these functions. This series also replaces IS_PLATFORM() with display-
> >platform.xx to reduce drm_i915_private usage.
> Some stuff that kept me from removing i915_private altogether were PCH
> checks.
>
> --v2
> -Rebase
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Thanks for the reviews pushed to din
Regards,
Suraj Kandpal
>
> Suraj Kandpal (9):
> drm/i915/display_debug_fs: Use intel_display wherever possible
> drm/i915/display_debug_fs: Prefer using display->platform
> drm/i915/dpll: Change param to intel_display in for_each_shared_dpll
> drm/i915/dpll: Use intel_display for dpll dump and compare hw state
> drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks
> drm/i915/dpll: Use intel_display for asserting pll
> drm/i915/dpll: Use intel_display for update_refclk hook
> drm/i915/dpll: Accept intel_display as argument for shared_dpll_init
> drm/i915/dpll: Replace all other leftover drm_i915_private
>
> .../drm/i915/display/intel_crtc_state_dump.c | 3 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 130 +--
> drivers/gpu/drm/i915/display/intel_display.c | 30 +-
> .../drm/i915/display/intel_display_debugfs.c | 173 +--
> .../drm/i915/display/intel_display_driver.c | 4 +-
> .../i915/display/intel_display_power_well.c | 13 +-
> drivers/gpu/drm/i915/display/intel_dkl_phy.c | 54 +-
> drivers/gpu/drm/i915/display/intel_dkl_phy.h | 9 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 11 +-
> drivers/gpu/drm/i915/display/intel_dpll.h | 5 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1011 ++++++++---------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 27 +-
> drivers/gpu/drm/i915/display/intel_fdi.c | 16 +-
> drivers/gpu/drm/i915/display/intel_fdi.h | 7 +-
> drivers/gpu/drm/i915/display/intel_lvds.c | 7 +-
> .../drm/i915/display/intel_modeset_setup.c | 4 +-
> .../gpu/drm/i915/display/intel_pch_display.c | 45 +-
> .../gpu/drm/i915/display/intel_pch_refclk.c | 36 +-
> drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 12 +-
> drivers/gpu/drm/i915/display/vlv_dsi_pll.h | 10 +-
> 20 files changed, 799 insertions(+), 808 deletions(-)
>
> --
> 2.34.1
^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2025-02-12 9:54 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-02-11 10:48 [PATCH 0/9] drm_i915_private to intel_display cleanup Suraj Kandpal
2025-02-11 10:48 ` [PATCH 1/9] drm/i915/display_debug_fs: Use intel_display wherever possible Suraj Kandpal
2025-02-11 12:51 ` Jani Nikula
2025-02-11 12:52 ` Jani Nikula
2025-02-11 10:48 ` [PATCH 2/9] drm/i915/display_debug_fs: Prefer using display->platform Suraj Kandpal
2025-02-11 12:53 ` Jani Nikula
2025-02-11 10:48 ` [PATCH 3/9] drm/i915/dpll: Change param to intel_display in for_each_shared_dpll Suraj Kandpal
2025-02-11 12:56 ` Jani Nikula
2025-02-11 10:48 ` [PATCH 4/9] drm/i915/dpll: Use intel_display for dpll dump and compare hw state Suraj Kandpal
2025-02-11 12:59 ` Jani Nikula
2025-02-11 10:48 ` [PATCH 5/9] drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks Suraj Kandpal
2025-02-11 13:10 ` Jani Nikula
2025-02-11 10:48 ` [PATCH 6/9] drm/i915/dpll: Use intel_display for asserting pll Suraj Kandpal
2025-02-11 13:12 ` Jani Nikula
2025-02-11 10:48 ` [PATCH 7/9] drm/i915/dpll: Use intel_display for update_refclk hook Suraj Kandpal
2025-02-11 13:12 ` Jani Nikula
2025-02-11 10:48 ` [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for shared_dpll_init Suraj Kandpal
2025-02-11 13:14 ` Jani Nikula
2025-02-11 14:23 ` Kandpal, Suraj
2025-02-11 16:57 ` Jani Nikula
2025-02-12 7:35 ` Kandpal, Suraj
2025-02-11 10:48 ` [PATCH 9/9] drm/i915/dpll: Replace all other leftover drm_i915_private Suraj Kandpal
2025-02-11 13:17 ` Jani Nikula
2025-02-11 12:10 ` ✗ Fi.CI.CHECKPATCH: warning for drm_i915_private to intel_display cleanup (rev2) Patchwork
2025-02-11 12:10 ` ✗ Fi.CI.SPARSE: " Patchwork
2025-02-11 13:45 ` ✓ i915.CI.BAT: success " Patchwork
2025-02-11 16:23 ` ✗ i915.CI.Full: failure " Patchwork
2025-02-12 9:54 ` [PATCH 0/9] drm_i915_private to intel_display cleanup Kandpal, Suraj
-- strict thread matches above, loose matches on Subject: below --
2025-02-10 12:39 Suraj Kandpal
2025-02-10 12:39 ` [PATCH 5/9] drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks Suraj Kandpal
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