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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 0/4] drm/i915: Start cleaning up the DPLL ID mess
Date: Tue, 04 Oct 2022 12:37:53 +0300	[thread overview]
Message-ID: <87tu4kszda.fsf@intel.com> (raw)
In-Reply-To: <20220926191341.5495-1-ville.syrjala@linux.intel.com>

On Mon, 26 Sep 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Start to clean up the mess around DPLL IDs a bit by removing
> the nasty assumption that the index of the DPLL in the
> arrays matches its ID. Fortunately we did have a WARN
> i nthere to cathc mistakes, but better to not has such
> silly assumptions i nthe first place.
>
> There's still a lot of mess left since the DPLL IDs in
> the hardware are a mess as well. Eg. the index of the
> register instance often differs from the index used
> to select the DPLL in clock routing thing. So we could
> probably clean up more of that, perhaps by declaring
> separate IDs for each PLL for each use case...

A couple of comments inline, but the series is

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

I think the debugfs DPLL number is benign enough that can be fixed
afterwards too.



>
> v2:
> - the trivial patches were already merged
> - introduce pll->index
> - add another patch for for_each_shared_dpll()
> - add another patch s/dev_priv/i915/
>
> Ville Syrjälä (4):
>   drm/i915: Stop requiring PLL index == PLL ID
>   drm/i915: Decouple I915_NUM_PLLS from PLL IDs
>   drm/i915: Introduce for_each_shared_dpll()
>   drm/i915: s/dev_priv/i915/ in the shared_dpll code
>
>  .../drm/i915/display/intel_display_debugfs.c  |    5 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1011 +++++++++--------
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   26 +-
>  .../gpu/drm/i915/display/intel_pch_refclk.c   |    7 +-
>  4 files changed, 543 insertions(+), 506 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center

      parent reply	other threads:[~2022-10-04  9:38 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-26 19:13 [Intel-gfx] [PATCH v2 0/4] drm/i915: Start cleaning up the DPLL ID mess Ville Syrjala
2022-09-26 19:13 ` [Intel-gfx] [PATCH v2 1/4] drm/i915: Stop requiring PLL index == PLL ID Ville Syrjala
2022-09-26 19:13 ` [Intel-gfx] [PATCH v2 2/4] drm/i915: Decouple I915_NUM_PLLS from PLL IDs Ville Syrjala
2022-09-26 19:13 ` [Intel-gfx] [PATCH v2 3/4] drm/i915: Introduce for_each_shared_dpll() Ville Syrjala
2022-10-04  9:34   ` Jani Nikula
2022-10-04  9:36   ` Jani Nikula
2022-09-26 19:13 ` [Intel-gfx] [PATCH v2 4/4] drm/i915: s/dev_priv/i915/ in the shared_dpll code Ville Syrjala
2022-09-27  0:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start cleaning up the DPLL ID mess (rev2) Patchwork
2022-09-27  0:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-09-27  1:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-27 12:26 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-10-04  9:37 ` Jani Nikula [this message]

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