* [Intel-gfx] [PATCH] drm/i915/execlists: Explicitly reset both reg and context runtime
@ 2020-03-26 18:05 Chris Wilson
0 siblings, 0 replies; 5+ messages in thread
From: Chris Wilson @ 2020-03-26 18:05 UTC (permalink / raw)
To: intel-gfx
Upon a GPU reset, we copy the default context image over top of the
guilty image. This will rollback the CTX_TIMESTAMP register to before
our value of ce->runtime.last. Reset both back to 0 so that we do not
encounter an underflow on the next schedule out after resume.
This should not be a huge issue in practice, as hangs should be rare in
correct code.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..b458f8e17cf5 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1154,6 +1154,7 @@ static void restore_default_state(struct intel_context *ce,
engine->context_size - PAGE_SIZE);
execlists_init_reg_state(regs, ce, engine, ce->ring, false);
+ ce->runtime.last = intel_context_get_runtime(ce);
}
static void reset_active(struct i915_request *rq,
@@ -4581,6 +4582,7 @@ static void init_common_reg_state(u32 * const regs,
regs[CTX_CONTEXT_CONTROL] = ctl;
regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
+ regs[CTX_TIMESTAMP] = 0;
}
static void init_wa_bb_reg_state(u32 * const regs,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/execlists: Explicitly reset both reg and context runtime
@ 2020-03-30 12:58 Chris Wilson
2020-03-30 18:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Explicitly reset both reg and context runtime (rev2) Patchwork
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Chris Wilson @ 2020-03-30 12:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Upon a GPU reset, we copy the default context image over top of the
guilty image. This will rollback the CTX_TIMESTAMP register to before
our value of ce->runtime.last. Reset both back to 0 so that we do not
encounter an underflow on the next schedule out after resume.
This should not be a huge issue in practice, as hangs should be rare in
correct code.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 24 +++++++++++++-----------
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 9104796673dc..d53078b345be 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -238,6 +238,17 @@ __execlists_update_reg_state(const struct intel_context *ce,
const struct intel_engine_cs *engine,
u32 head);
+static u32 intel_context_get_runtime(const struct intel_context *ce)
+{
+ /*
+ * We can use either ppHWSP[16] which is recorded before the context
+ * switch (and so excludes the cost of context switches) or use the
+ * value from the context image itself, which is saved/restored earlier
+ * and so includes the cost of the save.
+ */
+ return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
+}
+
static void mark_eio(struct i915_request *rq)
{
if (i915_request_completed(rq))
@@ -1154,6 +1165,7 @@ static void restore_default_state(struct intel_context *ce,
engine->context_size - PAGE_SIZE);
execlists_init_reg_state(regs, ce, engine, ce->ring, false);
+ ce->runtime.last = intel_context_get_runtime(ce);
}
static void reset_active(struct i915_request *rq,
@@ -1195,17 +1207,6 @@ static void reset_active(struct i915_request *rq,
ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
}
-static u32 intel_context_get_runtime(const struct intel_context *ce)
-{
- /*
- * We can use either ppHWSP[16] which is recorded before the context
- * switch (and so excludes the cost of context switches) or use the
- * value from the context image itself, which is saved/restored earlier
- * and so includes the cost of the save.
- */
- return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
-}
-
static void st_update_runtime_underflow(struct intel_context *ce, s32 dt)
{
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
@@ -4601,6 +4602,7 @@ static void init_common_reg_state(u32 * const regs,
regs[CTX_CONTEXT_CONTROL] = ctl;
regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
+ regs[CTX_TIMESTAMP] = 0;
}
static void init_wa_bb_reg_state(u32 * const regs,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Explicitly reset both reg and context runtime (rev2)
2020-03-30 12:58 [Intel-gfx] [PATCH] drm/i915/execlists: Explicitly reset both reg and context runtime Chris Wilson
@ 2020-03-30 18:38 ` Patchwork
2020-03-30 19:56 ` [Intel-gfx] [PATCH] drm/i915/execlists: Explicitly reset both reg and context runtime Mika Kuoppala
2020-03-31 6:35 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Explicitly reset both reg and context runtime (rev2) Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-03-30 18:38 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/execlists: Explicitly reset both reg and context runtime (rev2)
URL : https://patchwork.freedesktop.org/series/75127/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8216 -> Patchwork_17132
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/index.html
Changes
-------
No changes found
Participating hosts (45 -> 36)
------------------------------
Additional (4): fi-bdw-5557u fi-ivb-3770 fi-snb-2520m fi-elk-e7500
Missing (13): fi-hsw-4770r fi-ilk-m540 fi-bsw-n3050 fi-hsw-4200u fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-ctg-p8600 fi-bdw-samus fi-tgl-y fi-bsw-nick fi-skl-6600u
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8216 -> Patchwork_17132
CI-20190529: 20190529
CI_DRM_8216: 4ccea545b3b32da9999542abd56251e4e13bdf04 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5545: 9e5bfd10d56f81b98e0229c6bb14670221fd0b54 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17132: 56c1f7f67f817ca22e115c8713e1638353b6d6c2 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
56c1f7f67f81 drm/i915/execlists: Explicitly reset both reg and context runtime
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/execlists: Explicitly reset both reg and context runtime
2020-03-30 12:58 [Intel-gfx] [PATCH] drm/i915/execlists: Explicitly reset both reg and context runtime Chris Wilson
2020-03-30 18:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Explicitly reset both reg and context runtime (rev2) Patchwork
@ 2020-03-30 19:56 ` Mika Kuoppala
2020-03-31 6:35 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Explicitly reset both reg and context runtime (rev2) Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Mika Kuoppala @ 2020-03-30 19:56 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Upon a GPU reset, we copy the default context image over top of the
> guilty image. This will rollback the CTX_TIMESTAMP register to before
> our value of ce->runtime.last. Reset both back to 0 so that we do not
> encounter an underflow on the next schedule out after resume.
>
> This should not be a huge issue in practice, as hangs should be rare in
> correct code.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 24 +++++++++++++-----------
> 1 file changed, 13 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 9104796673dc..d53078b345be 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -238,6 +238,17 @@ __execlists_update_reg_state(const struct intel_context *ce,
> const struct intel_engine_cs *engine,
> u32 head);
>
> +static u32 intel_context_get_runtime(const struct intel_context *ce)
> +{
> + /*
> + * We can use either ppHWSP[16] which is recorded before the context
> + * switch (and so excludes the cost of context switches) or use the
> + * value from the context image itself, which is saved/restored earlier
> + * and so includes the cost of the save.
> + */
> + return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
> +}
> +
> static void mark_eio(struct i915_request *rq)
> {
> if (i915_request_completed(rq))
> @@ -1154,6 +1165,7 @@ static void restore_default_state(struct intel_context *ce,
> engine->context_size - PAGE_SIZE);
>
> execlists_init_reg_state(regs, ce, engine, ce->ring, false);
> + ce->runtime.last = intel_context_get_runtime(ce);
> }
>
> static void reset_active(struct i915_request *rq,
> @@ -1195,17 +1207,6 @@ static void reset_active(struct i915_request *rq,
> ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
> }
>
> -static u32 intel_context_get_runtime(const struct intel_context *ce)
> -{
> - /*
> - * We can use either ppHWSP[16] which is recorded before the context
> - * switch (and so excludes the cost of context switches) or use the
> - * value from the context image itself, which is saved/restored earlier
> - * and so includes the cost of the save.
> - */
> - return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
> -}
> -
> static void st_update_runtime_underflow(struct intel_context *ce, s32 dt)
> {
> #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> @@ -4601,6 +4602,7 @@ static void init_common_reg_state(u32 * const regs,
> regs[CTX_CONTEXT_CONTROL] = ctl;
>
> regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
> + regs[CTX_TIMESTAMP] = 0;
> }
>
> static void init_wa_bb_reg_state(u32 * const regs,
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Explicitly reset both reg and context runtime (rev2)
2020-03-30 12:58 [Intel-gfx] [PATCH] drm/i915/execlists: Explicitly reset both reg and context runtime Chris Wilson
2020-03-30 18:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Explicitly reset both reg and context runtime (rev2) Patchwork
2020-03-30 19:56 ` [Intel-gfx] [PATCH] drm/i915/execlists: Explicitly reset both reg and context runtime Mika Kuoppala
@ 2020-03-31 6:35 ` Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-03-31 6:35 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/execlists: Explicitly reset both reg and context runtime (rev2)
URL : https://patchwork.freedesktop.org/series/75127/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8216_full -> Patchwork_17132_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17132_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112146]) +5 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-iclb7/igt@gem_exec_async@concurrent-writes-bsd.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html
* igt@gem_exec_balancer@hang:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#1277])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-tglb8/igt@gem_exec_balancer@hang.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-tglb1/igt@gem_exec_balancer@hang.html
* igt@gem_exec_schedule@fifo-bsd1:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +14 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-iclb4/igt@gem_exec_schedule@fifo-bsd1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-iclb7/igt@gem_exec_schedule@fifo-bsd1.html
* igt@gem_exec_schedule@implicit-both-bsd2:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [i915#677])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-iclb1/igt@gem_exec_schedule@implicit-both-bsd2.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-iclb8/igt@gem_exec_schedule@implicit-both-bsd2.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-iclb3/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-iclb1/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-snb: [PASS][11] -> [TIMEOUT][12] ([i915#1526])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-snb2/igt@i915_pm_rc6_residency@rc6-idle.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-snb2/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_selftest@live@execlists:
- shard-apl: [PASS][13] -> [INCOMPLETE][14] ([i915#656])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-apl1/igt@i915_selftest@live@execlists.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-apl2/igt@i915_selftest@live@execlists.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +5 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#79])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-skl6/igt@kms_flip@flip-vs-expired-vblank.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-glk: [PASS][25] -> [FAIL][26] ([i915#899])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-glk8/igt@kms_plane_lowres@pipe-a-tiling-x.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-glk9/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-iclb8/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][29] -> [FAIL][30] ([i915#31])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-apl1/igt@kms_setmode@basic.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-apl6/igt@kms_setmode@basic.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#112080]) +8 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-iclb2/igt@perf_pmu@busy-no-semaphores-vcs1.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-iclb3/igt@perf_pmu@busy-no-semaphores-vcs1.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][33] ([fdo#112080]) -> [PASS][34] +9 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-iclb8/igt@gem_busy@busy-vcs1.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-iclb2/igt@gem_busy@busy-vcs1.html
* igt@gem_exec_schedule@implicit-read-write-bsd2:
- shard-iclb: [SKIP][35] ([fdo#109276] / [i915#677]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-iclb6/igt@gem_exec_schedule@implicit-read-write-bsd2.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-iclb2/igt@gem_exec_schedule@implicit-read-write-bsd2.html
* igt@gem_exec_schedule@pi-userfault-bsd:
- shard-iclb: [SKIP][37] ([i915#677]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-iclb2/igt@gem_exec_schedule@pi-userfault-bsd.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-iclb8/igt@gem_exec_schedule@pi-userfault-bsd.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [SKIP][39] ([fdo#112146]) -> [PASS][40] +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-iclb4/igt@gem_exec_schedule@wide-bsd.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-iclb7/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][41] ([i915#180]) -> [PASS][42] +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][43] ([i915#454]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
* igt@i915_selftest@live@requests:
- shard-iclb: [INCOMPLETE][45] -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-iclb8/igt@i915_selftest@live@requests.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-iclb5/igt@i915_selftest@live@requests.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48] +2 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [FAIL][49] ([i915#72]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][51] ([i915#79]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][53] ([fdo#109642] / [fdo#111068]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-iclb8/igt@kms_psr2_su@frontbuffer.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-iclb8/igt@kms_psr@psr2_primary_mmap_gtt.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][57] ([fdo#109276]) -> [PASS][58] +20 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-iclb3/igt@prime_busy@hang-bsd2.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-iclb1/igt@prime_busy@hang-bsd2.html
* {igt@sysfs_heartbeat_interval@mixed@vcs0}:
- shard-skl: [FAIL][59] ([i915#1459]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-skl4/igt@sysfs_heartbeat_interval@mixed@vcs0.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-skl10/igt@sysfs_heartbeat_interval@mixed@vcs0.html
#### Warnings ####
* igt@kms_content_protection@atomic:
- shard-kbl: [FAIL][61] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][62] ([i915#1319])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-kbl1/igt@kms_content_protection@atomic.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-kbl7/igt@kms_content_protection@atomic.html
* igt@runner@aborted:
- shard-apl: [FAIL][63] ([i915#1423]) -> ([FAIL][64], [FAIL][65]) ([i915#1423] / [i915#529])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8216/shard-apl2/igt@runner@aborted.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-apl2/igt@runner@aborted.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/shard-apl7/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#1277]: https://gitlab.freedesktop.org/drm/intel/issues/1277
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1423]: https://gitlab.freedesktop.org/drm/intel/issues/1423
[i915#1459]: https://gitlab.freedesktop.org/drm/intel/issues/1459
[i915#1526]: https://gitlab.freedesktop.org/drm/intel/issues/1526
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#529]: https://gitlab.freedesktop.org/drm/intel/issues/529
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8216 -> Patchwork_17132
CI-20190529: 20190529
CI_DRM_8216: 4ccea545b3b32da9999542abd56251e4e13bdf04 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5545: 9e5bfd10d56f81b98e0229c6bb14670221fd0b54 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17132: 56c1f7f67f817ca22e115c8713e1638353b6d6c2 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17132/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-03-31 6:35 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-03-30 12:58 [Intel-gfx] [PATCH] drm/i915/execlists: Explicitly reset both reg and context runtime Chris Wilson
2020-03-30 18:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Explicitly reset both reg and context runtime (rev2) Patchwork
2020-03-30 19:56 ` [Intel-gfx] [PATCH] drm/i915/execlists: Explicitly reset both reg and context runtime Mika Kuoppala
2020-03-31 6:35 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Explicitly reset both reg and context runtime (rev2) Patchwork
-- strict thread matches above, loose matches on Subject: below --
2020-03-26 18:05 [Intel-gfx] [PATCH] drm/i915/execlists: Explicitly reset both reg and context runtime Chris Wilson
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox