* Re: [Intel-gfx] [PATCH] drm/i915/display/dp: 128/132b LT requirement
2023-04-17 10:00 [Intel-gfx] [PATCH] drm/i915/display/dp: 128/132b LT requirement Arun R Murthy
@ 2023-04-17 10:20 ` Jani Nikula
2023-04-17 10:24 ` Jani Nikula
2023-04-17 10:51 ` [Intel-gfx] [PATCHv2] " Arun R Murthy
` (8 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2023-04-17 10:20 UTC (permalink / raw)
To: Arun R Murthy, intel-gfx
On Mon, 17 Apr 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> For 128b/132b LT prior to LT DPTX should set power state, DP channel
> coding and then link rate.
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> .../drm/i915/display/intel_dp_link_training.c | 52 +++++++++++++------
> 1 file changed, 35 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 6aa4ae5e7ebe..83ea9ece0157 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -686,23 +686,41 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
> drm_dbg_kms(&i915->drm,
> "[ENCODER:%d:%s] Using LINK_RATE_SET value %02x\n",
> encoder->base.base.id, encoder->base.name, rate_select);
> -
> - /* Write the link configuration data */
> - link_config[0] = link_bw;
> - link_config[1] = crtc_state->lane_count;
> - if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
> -
> - /* eDP 1.4 rate select method. */
> - if (!link_bw)
> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> - &rate_select, 1);
> -
> - link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> - link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> - DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> - drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
> + if (intel_dp_is_uhbr(crtc_state)) {
> + /*
> + * Spec DP2.1 Section 3.5.2.16
> + * Prior to LT DPTX should set 128/132 DP Channel coding and then set link rate
> + */
> + link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> + link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> + DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> + drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
> + /* Write the link configuration data */
> + link_config[0] = link_bw;
> + link_config[1] = crtc_state->lane_count;
> + if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> + link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
> + /* eDP 1.4 rate select method. */
> + if (!link_bw)
> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> + &rate_select, 1);
> + } else {
> + /* Write the link configuration data */
> + link_config[0] = link_bw;
> + link_config[1] = crtc_state->lane_count;
> + if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> + link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
> + /* eDP 1.4 rate select method. */
> + if (!link_bw)
> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> + &rate_select, 1);
> + link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> + link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> + DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> + drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
> + }
I'd rather we change the order for 8b10b too.
If we can't do that, you need to add two functions that do each step,
and then call them in different order for different channel coding. We
don't want all of the above duplicated.
Also, in what looks like a rebase fail, you change vrr.flipline to
vrr.enable.
BR,
Jani.
>
> return true;
> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915/display/dp: 128/132b LT requirement
2023-04-17 10:20 ` Jani Nikula
@ 2023-04-17 10:24 ` Jani Nikula
0 siblings, 0 replies; 18+ messages in thread
From: Jani Nikula @ 2023-04-17 10:24 UTC (permalink / raw)
To: Arun R Murthy, intel-gfx
On Mon, 17 Apr 2023, Jani Nikula <jani.nikula@intel.com> wrote:
> On Mon, 17 Apr 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
>> For 128b/132b LT prior to LT DPTX should set power state, DP channel
>> coding and then link rate.
>>
>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> ---
>> .../drm/i915/display/intel_dp_link_training.c | 52 +++++++++++++------
>> 1 file changed, 35 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index 6aa4ae5e7ebe..83ea9ece0157 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -686,23 +686,41 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
>> drm_dbg_kms(&i915->drm,
>> "[ENCODER:%d:%s] Using LINK_RATE_SET value %02x\n",
>> encoder->base.base.id, encoder->base.name, rate_select);
>> -
>> - /* Write the link configuration data */
>> - link_config[0] = link_bw;
>> - link_config[1] = crtc_state->lane_count;
>> - if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
>> - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
>> -
>> - /* eDP 1.4 rate select method. */
>> - if (!link_bw)
>> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
>> - &rate_select, 1);
>> -
>> - link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
>> - link_config[1] = intel_dp_is_uhbr(crtc_state) ?
>> - DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
>> - drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
>> + if (intel_dp_is_uhbr(crtc_state)) {
>> + /*
>> + * Spec DP2.1 Section 3.5.2.16
>> + * Prior to LT DPTX should set 128/132 DP Channel coding and then set link rate
PS. I've taken great care to use "128b/132b" in comments
everywhere. There isn't a single instance of "128/132".
It'll be helpful when you git grep 128b/132b.
BR,
Jani.
>> + */
>> + link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
>> + link_config[1] = intel_dp_is_uhbr(crtc_state) ?
>> + DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
>> + drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
>> + /* Write the link configuration data */
>> + link_config[0] = link_bw;
>> + link_config[1] = crtc_state->lane_count;
>> + if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
>> + link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
>> + /* eDP 1.4 rate select method. */
>> + if (!link_bw)
>> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
>> + &rate_select, 1);
>> + } else {
>> + /* Write the link configuration data */
>> + link_config[0] = link_bw;
>> + link_config[1] = crtc_state->lane_count;
>> + if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
>> + link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
>> + /* eDP 1.4 rate select method. */
>> + if (!link_bw)
>> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
>> + &rate_select, 1);
>> + link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
>> + link_config[1] = intel_dp_is_uhbr(crtc_state) ?
>> + DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
>> + drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
>> + }
>
> I'd rather we change the order for 8b10b too.
>
> If we can't do that, you need to add two functions that do each step,
> and then call them in different order for different channel coding. We
> don't want all of the above duplicated.
>
> Also, in what looks like a rebase fail, you change vrr.flipline to
> vrr.enable.
>
>
> BR,
> Jani.
>
>
>>
>> return true;
>> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCHv2] drm/i915/display/dp: 128/132b LT requirement
2023-04-17 10:00 [Intel-gfx] [PATCH] drm/i915/display/dp: 128/132b LT requirement Arun R Murthy
2023-04-17 10:20 ` Jani Nikula
@ 2023-04-17 10:51 ` Arun R Murthy
2023-04-17 15:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/dp: 128/132b LT requirement (rev2) Patchwork
` (7 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Arun R Murthy @ 2023-04-17 10:51 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
For 128b/132b LT prior to LT DPTX should set power state, DP channel
coding and then link rate.
v2: added separate function to avoid code duplication(Jani N)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
.../drm/i915/display/intel_dp_link_training.c | 62 +++++++++++++------
1 file changed, 44 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 6aa4ae5e7ebe..3418cf43e555 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -637,6 +637,37 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
return true;
}
+static void
+intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ u8 link_config[2];
+
+ link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
+ link_config[1] = intel_dp_is_uhbr(crtc_state) ?
+ DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
+ drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
+}
+
+static void
+intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ u8 link_bw, u8 rate_select)
+{
+ u8 link_config[2];
+
+ /* Write the link configuration data */
+ link_config[0] = link_bw;
+ link_config[1] = crtc_state->lane_count;
+ if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
+ link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
+ /* eDP 1.4 rate select method. */
+ if (!link_bw)
+ drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
+ &rate_select, 1);
+}
+
/*
* Prepare link training by configuring the link parameters. On DDI platforms
* also enable the port here.
@@ -647,7 +678,6 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- u8 link_config[2];
u8 link_bw, rate_select;
if (intel_dp->prepare_link_retrain)
@@ -686,23 +716,19 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s] Using LINK_RATE_SET value %02x\n",
encoder->base.base.id, encoder->base.name, rate_select);
-
- /* Write the link configuration data */
- link_config[0] = link_bw;
- link_config[1] = crtc_state->lane_count;
- if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
- link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
- drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
-
- /* eDP 1.4 rate select method. */
- if (!link_bw)
- drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
- &rate_select, 1);
-
- link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
- link_config[1] = intel_dp_is_uhbr(crtc_state) ?
- DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
- drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
+ if (intel_dp_is_uhbr(crtc_state)) {
+ /*
+ * Spec DP2.1 Section 3.5.2.16
+ * Prior to LT DPTX should set 128/132 DP Channel coding and then set link rate
+ */
+ intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
+ intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
+ rate_select);
+ } else {
+ intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
+ rate_select);
+ intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
+ }
return true;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/dp: 128/132b LT requirement (rev2)
2023-04-17 10:00 [Intel-gfx] [PATCH] drm/i915/display/dp: 128/132b LT requirement Arun R Murthy
2023-04-17 10:20 ` Jani Nikula
2023-04-17 10:51 ` [Intel-gfx] [PATCHv2] " Arun R Murthy
@ 2023-04-17 15:00 ` Patchwork
2023-04-17 22:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (6 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2023-04-17 15:00 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 11558 bytes --]
== Series Details ==
Series: drm/i915/display/dp: 128/132b LT requirement (rev2)
URL : https://patchwork.freedesktop.org/series/116562/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13020 -> Patchwork_116562v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/index.html
Participating hosts (35 -> 37)
------------------------------
Additional (3): fi-kbl-soraka fi-tgl-1115g4 bat-adls-5
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_116562v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-adls-5: NOTRUN -> [SKIP][1] ([i915#7456])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-adls-5/igt@debugfs_test@basic-hwmon.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([i915#7456])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/fi-tgl-1115g4/igt@debugfs_test@basic-hwmon.html
* igt@gem_exec_suspend@basic-s0@smem:
- bat-rpls-2: NOTRUN -> [ABORT][3] ([i915#6687])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-rpls-2/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_exec_suspend@basic-s3@smem:
- bat-rpls-1: NOTRUN -> [ABORT][4] ([i915#6687] / [i915#7978])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/fi-tgl-1115g4/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- bat-adls-5: NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-adls-5/igt@gem_lmem_swapping@random-engines.html
* igt@gem_tiled_pread_basic:
- bat-adls-5: NOTRUN -> [SKIP][10] ([i915#3282])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-adls-5/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([i915#7561])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-cfl-8109u: [PASS][12] -> [DMESG-FAIL][13] ([i915#5334])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13020/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][14] ([i915#1886])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- bat-adls-5: NOTRUN -> [DMESG-WARN][15] ([i915#5591])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-adls-5/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@mman:
- bat-rpls-1: [PASS][16] -> [TIMEOUT][17] ([i915#6794])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13020/bat-rpls-1/igt@i915_selftest@live@mman.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-rpls-1/igt@i915_selftest@live@mman.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-FAIL][18] ([i915#6367] / [i915#7913] / [i915#7996])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-rpls-2/igt@i915_selftest@live@slpc.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][19] ([i915#7443])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/fi-tgl-1115g4/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium_edid@dp-edid-read:
- fi-tgl-1115g4: NOTRUN -> [SKIP][20] ([i915#7828]) +7 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/fi-tgl-1115g4/igt@kms_chamelium_edid@dp-edid-read.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][21] ([fdo#109271]) +16 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/fi-kbl-soraka/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][22] ([i915#7828])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-dg2-11/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- bat-adls-5: NOTRUN -> [SKIP][23] ([i915#7828]) +8 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-adls-5/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][24] ([i915#4103]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-adls-5: NOTRUN -> [SKIP][25] ([i915#4103]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-adls-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][26] ([fdo#109285])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
- bat-adls-5: NOTRUN -> [SKIP][27] ([fdo#109285])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-adls-5/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][28] ([i915#3546]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-adlp-9/igt@kms_pipe_crc_basic@read-crc.html
* igt@kms_psr@cursor_plane_move:
- fi-tgl-1115g4: NOTRUN -> [SKIP][29] ([fdo#110189]) +3 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/fi-tgl-1115g4/igt@kms_psr@cursor_plane_move.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-adls-5: NOTRUN -> [SKIP][30] ([i915#3555] / [i915#4579])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-adls-5/igt@kms_setmode@basic-clone-single-crtc.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][31] ([i915#3555] / [i915#4579])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/fi-tgl-1115g4/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-read:
- bat-adls-5: NOTRUN -> [SKIP][32] ([fdo#109295] / [i915#3291]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-adls-5/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4: NOTRUN -> [SKIP][33] ([fdo#109295] / [i915#3301])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html
- bat-adls-5: NOTRUN -> [SKIP][34] ([fdo#109295] / [i915#3301])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-adls-5/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- bat-dg2-11: [ABORT][35] ([i915#7913] / [i915#7979]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13020/bat-dg2-11/igt@i915_selftest@live@hangcheck.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-dg2-11/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][37] ([i915#4983] / [i915#7913]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13020/bat-rpls-2/igt@i915_selftest@live@reset.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/bat-rpls-2/igt@i915_selftest@live@reset.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7979]: https://gitlab.freedesktop.org/drm/intel/issues/7979
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
Build changes
-------------
* Linux: CI_DRM_13020 -> Patchwork_116562v2
CI-20190529: 20190529
CI_DRM_13020: 3e4aefa137a3ae4ee40a89e5b7274cc4d3c02e6f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7258: ad2eb276eda849b7a7985229009a816c7608186c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116562v2: 3e4aefa137a3ae4ee40a89e5b7274cc4d3c02e6f @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
55b19e1ba958 drm/i915/display/dp: 128/132b LT requirement
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/index.html
[-- Attachment #2: Type: text/html, Size: 14192 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/dp: 128/132b LT requirement (rev2)
2023-04-17 10:00 [Intel-gfx] [PATCH] drm/i915/display/dp: 128/132b LT requirement Arun R Murthy
` (2 preceding siblings ...)
2023-04-17 15:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/dp: 128/132b LT requirement (rev2) Patchwork
@ 2023-04-17 22:33 ` Patchwork
2023-04-19 2:25 ` [Intel-gfx] [RESEND PATCHv2] drm/i915/display/dp: 128/132b LT requirement Arun R Murthy
` (5 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2023-04-17 22:33 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10930 bytes --]
== Series Details ==
Series: drm/i915/display/dp: 128/132b LT requirement (rev2)
URL : https://patchwork.freedesktop.org/series/116562/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13020_full -> Patchwork_116562v2_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (8 -> 7)
------------------------------
Missing (1): shard-rkl0
Known issues
------------
Here are the changes found in Patchwork_116562v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2846])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13020/shard-glk9/igt@gem_exec_fair@basic-deadline.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/shard-glk9/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13020/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13020/shard-apl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/shard-apl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][7] -> [ABORT][8] ([i915#5566])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13020/shard-apl3/igt@gen9_exec_parse@allowed-all.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/shard-apl3/igt@gen9_exec_parse@allowed-all.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-apl: [PASS][9] -> [FAIL][10] ([i915#2346])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13020/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s4-devices@smem:
- {shard-tglu}: [ABORT][11] ([i915#7975]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13020/shard-tglu-10/igt@gem_exec_suspend@basic-s4-devices@smem.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/shard-tglu-7/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@i915_pm_rpm@dpms-lpsp:
- {shard-rkl}: [SKIP][13] ([i915#1397]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13020/shard-rkl-4/igt@i915_pm_rpm@dpms-lpsp.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/shard-rkl-7/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- {shard-dg1}: [SKIP][15] ([i915#1397]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13020/shard-dg1-14/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/shard-dg1-17/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_cursor_legacy@forked-bo@pipe-b:
- {shard-rkl}: [INCOMPLETE][17] ([i915#8011]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13020/shard-rkl-7/igt@kms_cursor_legacy@forked-bo@pipe-b.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/shard-rkl-6/igt@kms_cursor_legacy@forked-bo@pipe-b.html
* igt@kms_cursor_legacy@single-move@pipe-b:
- {shard-dg1}: [INCOMPLETE][19] ([i915#8011] / [i915#8347]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13020/shard-dg1-14/igt@kms_cursor_legacy@single-move@pipe-b.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/shard-dg1-17/igt@kms_cursor_legacy@single-move@pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8150]: https://gitlab.freedesktop.org/drm/intel/issues/8150
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8308]: https://gitlab.freedesktop.org/drm/intel/issues/8308
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
Build changes
-------------
* Linux: CI_DRM_13020 -> Patchwork_116562v2
CI-20190529: 20190529
CI_DRM_13020: 3e4aefa137a3ae4ee40a89e5b7274cc4d3c02e6f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7258: ad2eb276eda849b7a7985229009a816c7608186c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116562v2: 3e4aefa137a3ae4ee40a89e5b7274cc4d3c02e6f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v2/index.html
[-- Attachment #2: Type: text/html, Size: 6545 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread* [Intel-gfx] [RESEND PATCHv2] drm/i915/display/dp: 128/132b LT requirement
2023-04-17 10:00 [Intel-gfx] [PATCH] drm/i915/display/dp: 128/132b LT requirement Arun R Murthy
` (3 preceding siblings ...)
2023-04-17 22:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-04-19 2:25 ` Arun R Murthy
2023-04-19 7:18 ` Jani Nikula
2023-04-19 3:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/dp: 128/132b LT requirement (rev3) Patchwork
` (4 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Arun R Murthy @ 2023-04-19 2:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
For 128b/132b LT prior to LT DPTX should set power state, DP channel
coding and then link rate.
v2: added separate function to avoid code duplication(Jani N)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
.../drm/i915/display/intel_dp_link_training.c | 62 +++++++++++++------
1 file changed, 44 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 6aa4ae5e7ebe..e5809cf7d0c4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -637,6 +637,37 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
return true;
}
+static void
+intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ u8 link_config[2];
+
+ link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
+ link_config[1] = intel_dp_is_uhbr(crtc_state) ?
+ DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
+ drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
+}
+
+static void
+intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ u8 link_bw, u8 rate_select)
+{
+ u8 link_config[2];
+
+ /* Write the link configuration data */
+ link_config[0] = link_bw;
+ link_config[1] = crtc_state->lane_count;
+ if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
+ link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
+ /* eDP 1.4 rate select method. */
+ if (!link_bw)
+ drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
+ &rate_select, 1);
+}
+
/*
* Prepare link training by configuring the link parameters. On DDI platforms
* also enable the port here.
@@ -647,7 +678,6 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- u8 link_config[2];
u8 link_bw, rate_select;
if (intel_dp->prepare_link_retrain)
@@ -686,23 +716,19 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s] Using LINK_RATE_SET value %02x\n",
encoder->base.base.id, encoder->base.name, rate_select);
-
- /* Write the link configuration data */
- link_config[0] = link_bw;
- link_config[1] = crtc_state->lane_count;
- if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
- link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
- drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
-
- /* eDP 1.4 rate select method. */
- if (!link_bw)
- drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
- &rate_select, 1);
-
- link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
- link_config[1] = intel_dp_is_uhbr(crtc_state) ?
- DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
- drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
+ if (intel_dp_is_uhbr(crtc_state)) {
+ /*
+ * Spec DP2.1 Section 3.5.2.16
+ * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate
+ */
+ intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
+ intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
+ rate_select);
+ } else {
+ intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
+ rate_select);
+ intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
+ }
return true;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [RESEND PATCHv2] drm/i915/display/dp: 128/132b LT requirement
2023-04-19 2:25 ` [Intel-gfx] [RESEND PATCHv2] drm/i915/display/dp: 128/132b LT requirement Arun R Murthy
@ 2023-04-19 7:18 ` Jani Nikula
2023-04-19 8:03 ` Murthy, Arun R
0 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2023-04-19 7:18 UTC (permalink / raw)
To: Arun R Murthy, intel-gfx
On Wed, 19 Apr 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> For 128b/132b LT prior to LT DPTX should set power state, DP channel
> coding and then link rate.
>
> v2: added separate function to avoid code duplication(Jani N)
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
RESEND for what reason?
Two v2 and neither fixes
https://lore.kernel.org/r/87o7nmergw.fsf@intel.com
BR,
Jani.
> ---
> .../drm/i915/display/intel_dp_link_training.c | 62 +++++++++++++------
> 1 file changed, 44 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 6aa4ae5e7ebe..e5809cf7d0c4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -637,6 +637,37 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
> return true;
> }
>
> +static void
> +intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state)
> +{
> + u8 link_config[2];
> +
> + link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> + link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> + DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> + drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
> +}
> +
> +static void
> +intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state,
> + u8 link_bw, u8 rate_select)
> +{
> + u8 link_config[2];
> +
> + /* Write the link configuration data */
> + link_config[0] = link_bw;
> + link_config[1] = crtc_state->lane_count;
> + if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> + link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
> + /* eDP 1.4 rate select method. */
> + if (!link_bw)
> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> + &rate_select, 1);
> +}
> +
> /*
> * Prepare link training by configuring the link parameters. On DDI platforms
> * also enable the port here.
> @@ -647,7 +678,6 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> - u8 link_config[2];
> u8 link_bw, rate_select;
>
> if (intel_dp->prepare_link_retrain)
> @@ -686,23 +716,19 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
> drm_dbg_kms(&i915->drm,
> "[ENCODER:%d:%s] Using LINK_RATE_SET value %02x\n",
> encoder->base.base.id, encoder->base.name, rate_select);
> -
> - /* Write the link configuration data */
> - link_config[0] = link_bw;
> - link_config[1] = crtc_state->lane_count;
> - if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
> -
> - /* eDP 1.4 rate select method. */
> - if (!link_bw)
> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> - &rate_select, 1);
> -
> - link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> - link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> - DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> - drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
> + if (intel_dp_is_uhbr(crtc_state)) {
> + /*
> + * Spec DP2.1 Section 3.5.2.16
> + * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate
> + */
> + intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
> + intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
> + rate_select);
> + } else {
> + intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
> + rate_select);
> + intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
> + }
>
> return true;
> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [RESEND PATCHv2] drm/i915/display/dp: 128/132b LT requirement
2023-04-19 7:18 ` Jani Nikula
@ 2023-04-19 8:03 ` Murthy, Arun R
2023-04-19 9:55 ` Jani Nikula
0 siblings, 1 reply; 18+ messages in thread
From: Murthy, Arun R @ 2023-04-19 8:03 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Wednesday, April 19, 2023 12:48 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> Subject: Re: [RESEND PATCHv2] drm/i915/display/dp: 128/132b LT
> requirement
>
> On Wed, 19 Apr 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > For 128b/132b LT prior to LT DPTX should set power state, DP channel
> > coding and then link rate.
> >
> > v2: added separate function to avoid code duplication(Jani N)
> >
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>
> RESEND for what reason?
Typo is sending V2 patch hence corrected and sent it again.
>
> Two v2 and neither fixes
> https://lore.kernel.org/r/87o7nmergw.fsf@intel.com
This is pointing to the v1 patch.
V2 patch addressing review comments can be located @ https://lore.kernel.org/all/20230419022522.3457924-1-arun.r.murthy@intel.com/
Thanks and Regards,
Arun R Murthy
--------------------
>
> BR,
> Jani.
>
>
> > ---
> > .../drm/i915/display/intel_dp_link_training.c | 62
> > +++++++++++++------
> > 1 file changed, 44 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index 6aa4ae5e7ebe..e5809cf7d0c4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -637,6 +637,37 @@ static bool
> intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
> > return true;
> > }
> >
> > +static void
> > +intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state *crtc_state) {
> > + u8 link_config[2];
> > +
> > + link_config[0] = crtc_state->vrr.flipline ?
> DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> > + link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> > + DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> > + drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
> link_config,
> > +2); }
> > +
> > +static void
> > +intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state *crtc_state,
> > + u8 link_bw, u8 rate_select)
> > +{
> > + u8 link_config[2];
> > +
> > + /* Write the link configuration data */
> > + link_config[0] = link_bw;
> > + link_config[1] = crtc_state->lane_count;
> > + if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> > + link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> > + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,
> 2);
> > + /* eDP 1.4 rate select method. */
> > + if (!link_bw)
> > + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> > + &rate_select, 1);
> > +}
> > +
> > /*
> > * Prepare link training by configuring the link parameters. On DDI
> platforms
> > * also enable the port here.
> > @@ -647,7 +678,6 @@ intel_dp_prepare_link_train(struct intel_dp
> > *intel_dp, {
> > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > - u8 link_config[2];
> > u8 link_bw, rate_select;
> >
> > if (intel_dp->prepare_link_retrain)
> > @@ -686,23 +716,19 @@ intel_dp_prepare_link_train(struct intel_dp
> *intel_dp,
> > drm_dbg_kms(&i915->drm,
> > "[ENCODER:%d:%s] Using LINK_RATE_SET value
> %02x\n",
> > encoder->base.base.id, encoder->base.name,
> rate_select);
> > -
> > - /* Write the link configuration data */
> > - link_config[0] = link_bw;
> > - link_config[1] = crtc_state->lane_count;
> > - if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> > - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> > - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,
> 2);
> > -
> > - /* eDP 1.4 rate select method. */
> > - if (!link_bw)
> > - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> > - &rate_select, 1);
> > -
> > - link_config[0] = crtc_state->vrr.flipline ?
> DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> > - link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> > - DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> > - drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
> link_config, 2);
> > + if (intel_dp_is_uhbr(crtc_state)) {
> > + /*
> > + * Spec DP2.1 Section 3.5.2.16
> > + * Prior to LT DPTX should set 128b/132b DP Channel coding
> and then set link rate
> > + */
> > + intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
> > + intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
> > + rate_select);
> > + } else {
> > + intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
> > + rate_select);
> > + intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
> > + }
> >
> > return true;
> > }
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [RESEND PATCHv2] drm/i915/display/dp: 128/132b LT requirement
2023-04-19 8:03 ` Murthy, Arun R
@ 2023-04-19 9:55 ` Jani Nikula
2023-04-19 10:07 ` Murthy, Arun R
0 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2023-04-19 9:55 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx@lists.freedesktop.org
On Wed, 19 Apr 2023, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Wednesday, April 19, 2023 12:48 PM
>> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
>> Subject: Re: [RESEND PATCHv2] drm/i915/display/dp: 128/132b LT
>> requirement
>>
>> On Wed, 19 Apr 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
>> > For 128b/132b LT prior to LT DPTX should set power state, DP channel
>> > coding and then link rate.
>> >
>> > v2: added separate function to avoid code duplication(Jani N)
>> >
>> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>>
>> RESEND for what reason?
> Typo is sending V2 patch hence corrected and sent it again.
>
>>
>> Two v2 and neither fixes
>> https://lore.kernel.org/r/87o7nmergw.fsf@intel.com
> This is pointing to the v1 patch.
> V2 patch addressing review comments can be located @ https://lore.kernel.org/all/20230419022522.3457924-1-arun.r.murthy@intel.com/
Argh.
RESEND means you're sending the exact same patch again. Hence
*re-send*. That's what I thought. That's what everyone would think.
It's even documented in submitting-patches.rst [1].
---
There's still the question of whether we could just change the order for
8b/10b too [2]. On IRC, Ville thinks we could, "i don't think there is
any order specified. just use the same alwas imo".
BR,
Jani.
[1] https://docs.kernel.org/process/submitting-patches.html#don-t-get-discouraged-or-impatient
[2] https://lore.kernel.org/r/87r0siernf.fsf@intel.com
>
> Thanks and Regards,
> Arun R Murthy
> --------------------
>>
>> BR,
>> Jani.
>>
>>
>> > ---
>> > .../drm/i915/display/intel_dp_link_training.c | 62
>> > +++++++++++++------
>> > 1 file changed, 44 insertions(+), 18 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> > index 6aa4ae5e7ebe..e5809cf7d0c4 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> > @@ -637,6 +637,37 @@ static bool
>> intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
>> > return true;
>> > }
>> >
>> > +static void
>> > +intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
>> > + const struct intel_crtc_state *crtc_state) {
>> > + u8 link_config[2];
>> > +
>> > + link_config[0] = crtc_state->vrr.flipline ?
>> DP_MSA_TIMING_PAR_IGNORE_EN : 0;
>> > + link_config[1] = intel_dp_is_uhbr(crtc_state) ?
>> > + DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
>> > + drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
>> link_config,
>> > +2); }
>> > +
>> > +static void
>> > +intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
>> > + const struct intel_crtc_state *crtc_state,
>> > + u8 link_bw, u8 rate_select)
>> > +{
>> > + u8 link_config[2];
>> > +
>> > + /* Write the link configuration data */
>> > + link_config[0] = link_bw;
>> > + link_config[1] = crtc_state->lane_count;
>> > + if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
>> > + link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>> > + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,
>> 2);
>> > + /* eDP 1.4 rate select method. */
>> > + if (!link_bw)
>> > + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
>> > + &rate_select, 1);
>> > +}
>> > +
>> > /*
>> > * Prepare link training by configuring the link parameters. On DDI
>> platforms
>> > * also enable the port here.
>> > @@ -647,7 +678,6 @@ intel_dp_prepare_link_train(struct intel_dp
>> > *intel_dp, {
>> > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>> > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> > - u8 link_config[2];
>> > u8 link_bw, rate_select;
>> >
>> > if (intel_dp->prepare_link_retrain)
>> > @@ -686,23 +716,19 @@ intel_dp_prepare_link_train(struct intel_dp
>> *intel_dp,
>> > drm_dbg_kms(&i915->drm,
>> > "[ENCODER:%d:%s] Using LINK_RATE_SET value
>> %02x\n",
>> > encoder->base.base.id, encoder->base.name,
>> rate_select);
>> > -
>> > - /* Write the link configuration data */
>> > - link_config[0] = link_bw;
>> > - link_config[1] = crtc_state->lane_count;
>> > - if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
>> > - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>> > - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,
>> 2);
>> > -
>> > - /* eDP 1.4 rate select method. */
>> > - if (!link_bw)
>> > - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
>> > - &rate_select, 1);
>> > -
>> > - link_config[0] = crtc_state->vrr.flipline ?
>> DP_MSA_TIMING_PAR_IGNORE_EN : 0;
>> > - link_config[1] = intel_dp_is_uhbr(crtc_state) ?
>> > - DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
>> > - drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
>> link_config, 2);
>> > + if (intel_dp_is_uhbr(crtc_state)) {
>> > + /*
>> > + * Spec DP2.1 Section 3.5.2.16
>> > + * Prior to LT DPTX should set 128b/132b DP Channel coding
>> and then set link rate
>> > + */
>> > + intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
>> > + intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
>> > + rate_select);
>> > + } else {
>> > + intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
>> > + rate_select);
>> > + intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
>> > + }
>> >
>> > return true;
>> > }
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [RESEND PATCHv2] drm/i915/display/dp: 128/132b LT requirement
2023-04-19 9:55 ` Jani Nikula
@ 2023-04-19 10:07 ` Murthy, Arun R
2023-04-24 15:27 ` Ville Syrjälä
0 siblings, 1 reply; 18+ messages in thread
From: Murthy, Arun R @ 2023-04-19 10:07 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Wednesday, April 19, 2023 3:26 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com
> Subject: RE: [RESEND PATCHv2] drm/i915/display/dp: 128/132b LT
> requirement
>
> On Wed, 19 Apr 2023, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> -----Original Message-----
> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> Sent: Wednesday, April 19, 2023 12:48 PM
> >> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> >> gfx@lists.freedesktop.org
> >> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> >> Subject: Re: [RESEND PATCHv2] drm/i915/display/dp: 128/132b LT
> >> requirement
> >>
> >> On Wed, 19 Apr 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> >> > For 128b/132b LT prior to LT DPTX should set power state, DP
> >> > channel coding and then link rate.
> >> >
> >> > v2: added separate function to avoid code duplication(Jani N)
> >> >
> >> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> >>
> >> RESEND for what reason?
> > Typo is sending V2 patch hence corrected and sent it again.
> >
> >>
> >> Two v2 and neither fixes
> >> https://lore.kernel.org/r/87o7nmergw.fsf@intel.com
> > This is pointing to the v1 patch.
> > V2 patch addressing review comments can be located @
> > https://lore.kernel.org/all/20230419022522.3457924-1-arun.r.murthy@int
> > el.com/
>
> Argh.
>
> RESEND means you're sending the exact same patch again. Hence *re-send*.
> That's what I thought. That's what everyone would think.
>
> It's even documented in submitting-patches.rst [1].
>
> ---
>
> There's still the question of whether we could just change the order for
> 8b/10b too [2]. On IRC, Ville thinks we could, "i don't think there is any order
> specified. just use the same alwas imo".
>
Spec DP2.1 section 3.5.1.2 (for 8b/10b LT)
write the following Link Configuration parameters:
* LINK_BW_SET register (DPCD 00100h)
* LANE_COUNT_SET field in the LANE_COUNT_SET register (DPCD 00101h[4:0])
* DOWNSPREAD_CTRL register (DPCD 00107h)
* MAIN_LINK_CHANNEL_CODING_SET register (DPCD 00108h)
Whereas for 128b/132b section 3.5.2.16 says
Prior to link training, a DPTX should perform the following:
1 Verify that the SET_POWER_STATE field in the
SET_POWER_AND_SET_DP_PWR_VOLTAGE register is programmed to D0 normal
operation (DPCD 00600h[2:0] = 001b).
2 Write DPCD 00108h = 02h to select 128b/132b DP channel coding.
3 Program the target link rate and lane count by way of an AUX write transaction to
DPCD 00100h and 00101h, respectively
Thanks and Regards,
Arun R Murthy
-------------------
>
> BR,
> Jani.
>
>
> [1] https://docs.kernel.org/process/submitting-patches.html#don-t-get-
> discouraged-or-impatient
> [2] https://lore.kernel.org/r/87r0siernf.fsf@intel.com
>
>
>
>
>
>
> >
> > Thanks and Regards,
> > Arun R Murthy
> > --------------------
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >> > ---
> >> > .../drm/i915/display/intel_dp_link_training.c | 62
> >> > +++++++++++++------
> >> > 1 file changed, 44 insertions(+), 18 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> > index 6aa4ae5e7ebe..e5809cf7d0c4 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> > @@ -637,6 +637,37 @@ static bool
> >> intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
> >> > return true;
> >> > }
> >> >
> >> > +static void
> >> > +intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
> >> > + const struct intel_crtc_state *crtc_state) {
> >> > + u8 link_config[2];
> >> > +
> >> > + link_config[0] = crtc_state->vrr.flipline ?
> >> DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> >> > + link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> >> > + DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> >> > + drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
> >> link_config,
> >> > +2); }
> >> > +
> >> > +static void
> >> > +intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
> >> > + const struct intel_crtc_state *crtc_state,
> >> > + u8 link_bw, u8 rate_select) {
> >> > + u8 link_config[2];
> >> > +
> >> > + /* Write the link configuration data */
> >> > + link_config[0] = link_bw;
> >> > + link_config[1] = crtc_state->lane_count;
> >> > + if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> >> > + link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> >> > + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,
> >> 2);
> >> > + /* eDP 1.4 rate select method. */
> >> > + if (!link_bw)
> >> > + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> >> > + &rate_select, 1); }
> >> > +
> >> > /*
> >> > * Prepare link training by configuring the link parameters. On
> >> > DDI
> >> platforms
> >> > * also enable the port here.
> >> > @@ -647,7 +678,6 @@ intel_dp_prepare_link_train(struct intel_dp
> >> > *intel_dp, {
> >> > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> >> > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> >> > - u8 link_config[2];
> >> > u8 link_bw, rate_select;
> >> >
> >> > if (intel_dp->prepare_link_retrain) @@ -686,23 +716,19 @@
> >> > intel_dp_prepare_link_train(struct intel_dp
> >> *intel_dp,
> >> > drm_dbg_kms(&i915->drm,
> >> > "[ENCODER:%d:%s] Using LINK_RATE_SET value
> >> %02x\n",
> >> > encoder->base.base.id, encoder->base.name,
> >> rate_select);
> >> > -
> >> > - /* Write the link configuration data */
> >> > - link_config[0] = link_bw;
> >> > - link_config[1] = crtc_state->lane_count;
> >> > - if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> >> > - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> >> > - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,
> >> 2);
> >> > -
> >> > - /* eDP 1.4 rate select method. */
> >> > - if (!link_bw)
> >> > - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> >> > - &rate_select, 1);
> >> > -
> >> > - link_config[0] = crtc_state->vrr.flipline ?
> >> DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> >> > - link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> >> > - DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> >> > - drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
> >> link_config, 2);
> >> > + if (intel_dp_is_uhbr(crtc_state)) {
> >> > + /*
> >> > + * Spec DP2.1 Section 3.5.2.16
> >> > + * Prior to LT DPTX should set 128b/132b DP Channel
> >> > + coding
> >> and then set link rate
> >> > + */
> >> > + intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
> >> > + intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
> >> > + rate_select);
> >> > + } else {
> >> > + intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
> >> > + rate_select);
> >> > + intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
> >> > + }
> >> >
> >> > return true;
> >> > }
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [RESEND PATCHv2] drm/i915/display/dp: 128/132b LT requirement
2023-04-19 10:07 ` Murthy, Arun R
@ 2023-04-24 15:27 ` Ville Syrjälä
0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2023-04-24 15:27 UTC (permalink / raw)
To: Murthy, Arun R; +Cc: Nikula, Jani, intel-gfx@lists.freedesktop.org
On Wed, Apr 19, 2023 at 10:07:46AM +0000, Murthy, Arun R wrote:
> > -----Original Message-----
> > From: Nikula, Jani <jani.nikula@intel.com>
> > Sent: Wednesday, April 19, 2023 3:26 PM
> > To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Cc: ville.syrjala@linux.intel.com
> > Subject: RE: [RESEND PATCHv2] drm/i915/display/dp: 128/132b LT
> > requirement
> >
> > On Wed, 19 Apr 2023, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> > >> -----Original Message-----
> > >> From: Nikula, Jani <jani.nikula@intel.com>
> > >> Sent: Wednesday, April 19, 2023 12:48 PM
> > >> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> > >> gfx@lists.freedesktop.org
> > >> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> > >> Subject: Re: [RESEND PATCHv2] drm/i915/display/dp: 128/132b LT
> > >> requirement
> > >>
> > >> On Wed, 19 Apr 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > >> > For 128b/132b LT prior to LT DPTX should set power state, DP
> > >> > channel coding and then link rate.
> > >> >
> > >> > v2: added separate function to avoid code duplication(Jani N)
> > >> >
> > >> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > >>
> > >> RESEND for what reason?
> > > Typo is sending V2 patch hence corrected and sent it again.
> > >
> > >>
> > >> Two v2 and neither fixes
> > >> https://lore.kernel.org/r/87o7nmergw.fsf@intel.com
> > > This is pointing to the v1 patch.
> > > V2 patch addressing review comments can be located @
> > > https://lore.kernel.org/all/20230419022522.3457924-1-arun.r.murthy@int
> > > el.com/
> >
> > Argh.
> >
> > RESEND means you're sending the exact same patch again. Hence *re-send*.
> > That's what I thought. That's what everyone would think.
> >
> > It's even documented in submitting-patches.rst [1].
> >
> > ---
> >
> > There's still the question of whether we could just change the order for
> > 8b/10b too [2]. On IRC, Ville thinks we could, "i don't think there is any order
> > specified. just use the same alwas imo".
> >
> Spec DP2.1 section 3.5.1.2 (for 8b/10b LT)
> write the following Link Configuration parameters:
> * LINK_BW_SET register (DPCD 00100h)
> * LANE_COUNT_SET field in the LANE_COUNT_SET register (DPCD 00101h[4:0])
> * DOWNSPREAD_CTRL register (DPCD 00107h)
> * MAIN_LINK_CHANNEL_CODING_SET register (DPCD 00108h)
Looks like an unordered list to me
>
> Whereas for 128b/132b section 3.5.2.16 says
> Prior to link training, a DPTX should perform the following:
> 1 Verify that the SET_POWER_STATE field in the
> SET_POWER_AND_SET_DP_PWR_VOLTAGE register is programmed to D0 normal
> operation (DPCD 00600h[2:0] = 001b).
> 2 Write DPCD 00108h = 02h to select 128b/132b DP channel coding.
> 3 Program the target link rate and lane count by way of an AUX write transaction to
> DPCD 00100h and 00101h, respectively
whereas this is an ordered list.
>
>
> Thanks and Regards,
> Arun R Murthy
> -------------------
> >
> > BR,
> > Jani.
> >
> >
> > [1] https://docs.kernel.org/process/submitting-patches.html#don-t-get-
> > discouraged-or-impatient
> > [2] https://lore.kernel.org/r/87r0siernf.fsf@intel.com
> >
> >
> >
> >
> >
> >
> > >
> > > Thanks and Regards,
> > > Arun R Murthy
> > > --------------------
> > >>
> > >> BR,
> > >> Jani.
> > >>
> > >>
> > >> > ---
> > >> > .../drm/i915/display/intel_dp_link_training.c | 62
> > >> > +++++++++++++------
> > >> > 1 file changed, 44 insertions(+), 18 deletions(-)
> > >> >
> > >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > >> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > >> > index 6aa4ae5e7ebe..e5809cf7d0c4 100644
> > >> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > >> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > >> > @@ -637,6 +637,37 @@ static bool
> > >> intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
> > >> > return true;
> > >> > }
> > >> >
> > >> > +static void
> > >> > +intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
> > >> > + const struct intel_crtc_state *crtc_state) {
> > >> > + u8 link_config[2];
> > >> > +
> > >> > + link_config[0] = crtc_state->vrr.flipline ?
> > >> DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> > >> > + link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> > >> > + DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> > >> > + drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
> > >> link_config,
> > >> > +2); }
> > >> > +
> > >> > +static void
> > >> > +intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
> > >> > + const struct intel_crtc_state *crtc_state,
> > >> > + u8 link_bw, u8 rate_select) {
> > >> > + u8 link_config[2];
> > >> > +
> > >> > + /* Write the link configuration data */
> > >> > + link_config[0] = link_bw;
> > >> > + link_config[1] = crtc_state->lane_count;
> > >> > + if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> > >> > + link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> > >> > + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,
> > >> 2);
> > >> > + /* eDP 1.4 rate select method. */
> > >> > + if (!link_bw)
> > >> > + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> > >> > + &rate_select, 1); }
> > >> > +
> > >> > /*
> > >> > * Prepare link training by configuring the link parameters. On
> > >> > DDI
> > >> platforms
> > >> > * also enable the port here.
> > >> > @@ -647,7 +678,6 @@ intel_dp_prepare_link_train(struct intel_dp
> > >> > *intel_dp, {
> > >> > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> > >> > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > >> > - u8 link_config[2];
> > >> > u8 link_bw, rate_select;
> > >> >
> > >> > if (intel_dp->prepare_link_retrain) @@ -686,23 +716,19 @@
> > >> > intel_dp_prepare_link_train(struct intel_dp
> > >> *intel_dp,
> > >> > drm_dbg_kms(&i915->drm,
> > >> > "[ENCODER:%d:%s] Using LINK_RATE_SET value
> > >> %02x\n",
> > >> > encoder->base.base.id, encoder->base.name,
> > >> rate_select);
> > >> > -
> > >> > - /* Write the link configuration data */
> > >> > - link_config[0] = link_bw;
> > >> > - link_config[1] = crtc_state->lane_count;
> > >> > - if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> > >> > - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> > >> > - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,
> > >> 2);
> > >> > -
> > >> > - /* eDP 1.4 rate select method. */
> > >> > - if (!link_bw)
> > >> > - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> > >> > - &rate_select, 1);
> > >> > -
> > >> > - link_config[0] = crtc_state->vrr.flipline ?
> > >> DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> > >> > - link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> > >> > - DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> > >> > - drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
> > >> link_config, 2);
> > >> > + if (intel_dp_is_uhbr(crtc_state)) {
> > >> > + /*
> > >> > + * Spec DP2.1 Section 3.5.2.16
> > >> > + * Prior to LT DPTX should set 128b/132b DP Channel
> > >> > + coding
> > >> and then set link rate
> > >> > + */
> > >> > + intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
> > >> > + intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
> > >> > + rate_select);
> > >> > + } else {
> > >> > + intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
> > >> > + rate_select);
> > >> > + intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
> > >> > + }
> > >> >
> > >> > return true;
> > >> > }
> > >>
> > >> --
> > >> Jani Nikula, Intel Open Source Graphics Center
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/dp: 128/132b LT requirement (rev3)
2023-04-17 10:00 [Intel-gfx] [PATCH] drm/i915/display/dp: 128/132b LT requirement Arun R Murthy
` (4 preceding siblings ...)
2023-04-19 2:25 ` [Intel-gfx] [RESEND PATCHv2] drm/i915/display/dp: 128/132b LT requirement Arun R Murthy
@ 2023-04-19 3:10 ` Patchwork
2023-04-19 5:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (3 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2023-04-19 3:10 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4998 bytes --]
== Series Details ==
Series: drm/i915/display/dp: 128/132b LT requirement (rev3)
URL : https://patchwork.freedesktop.org/series/116562/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13027 -> Patchwork_116562v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/index.html
Participating hosts (37 -> 36)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_116562v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3@smem:
- bat-rpls-1: NOTRUN -> [ABORT][1] ([i915#6687] / [i915#7978])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-5: [PASS][2] -> [FAIL][3] ([i915#8308])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/bat-dg1-5/igt@i915_pm_rps@basic-api.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/bat-dg1-5/igt@i915_pm_rps@basic-api.html
- bat-dg2-11: [PASS][4] -> [FAIL][5] ([i915#8308])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/bat-dg2-11/igt@i915_pm_rps@basic-api.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/bat-dg2-11/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@hangcheck:
- fi-skl-guc: [PASS][6] -> [DMESG-WARN][7] ([i915#8073])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/fi-skl-guc/igt@i915_selftest@live@hangcheck.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/fi-skl-guc/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- fi-glk-j4005: NOTRUN -> [SKIP][8] ([fdo#109271])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/fi-glk-j4005/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][9] ([i915#3546]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/bat-adlp-9/igt@kms_pipe_crc_basic@read-crc.html
#### Possible fixes ####
* igt@dmabuf@all-tests@dma_fence:
- fi-glk-j4005: [ABORT][10] -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/fi-glk-j4005/igt@dmabuf@all-tests@dma_fence.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/fi-glk-j4005/igt@dmabuf@all-tests@dma_fence.html
* igt@dmabuf@all-tests@dma_fence_chain:
- fi-glk-j4005: [DMESG-FAIL][12] -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/fi-glk-j4005/igt@dmabuf@all-tests@dma_fence_chain.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/fi-glk-j4005/igt@dmabuf@all-tests@dma_fence_chain.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [ABORT][14] ([i915#7911] / [i915#7982]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/bat-rpls-1/igt@i915_selftest@live@requests.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/bat-rpls-1/igt@i915_selftest@live@requests.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [FAIL][16] ([i915#7932]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
[i915#8073]: https://gitlab.freedesktop.org/drm/intel/issues/8073
[i915#8308]: https://gitlab.freedesktop.org/drm/intel/issues/8308
Build changes
-------------
* Linux: CI_DRM_13027 -> Patchwork_116562v3
CI-20190529: 20190529
CI_DRM_13027: 9e1eb302fc69b5d8dc662f1ce7ed8684e87c5751 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7259: 3d3a7f1c041d3f8d84d7457abf96adef0ea071cb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116562v3: 9e1eb302fc69b5d8dc662f1ce7ed8684e87c5751 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
f20472c99629 drm/i915/display/dp: 128/132b LT requirement
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/index.html
[-- Attachment #2: Type: text/html, Size: 5911 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/dp: 128/132b LT requirement (rev3)
2023-04-17 10:00 [Intel-gfx] [PATCH] drm/i915/display/dp: 128/132b LT requirement Arun R Murthy
` (5 preceding siblings ...)
2023-04-19 3:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/dp: 128/132b LT requirement (rev3) Patchwork
@ 2023-04-19 5:08 ` Patchwork
2023-04-25 2:59 ` [Intel-gfx] [PATCHv3] drm/i915/display/dp: 128/132b LT requirement Arun R Murthy
` (2 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2023-04-19 5:08 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 14110 bytes --]
== Series Details ==
Series: drm/i915/display/dp: 128/132b LT requirement (rev3)
URL : https://patchwork.freedesktop.org/series/116562/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13027_full -> Patchwork_116562v3_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (8 -> 7)
------------------------------
Missing (1): shard-rkl0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_116562v3_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
- {shard-rkl}: NOTRUN -> [ABORT][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-rkl-4/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
* igt@kms_vblank@pipe-h-ts-continuation-dpms-suspend:
- {shard-dg1}: NOTRUN -> [SKIP][2] +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-dg1-14/igt@kms_vblank@pipe-h-ts-continuation-dpms-suspend.html
* {igt@vmwgfx/vmw_ref_count@surface_prime_transfer_single_surface_multiple_handle}:
- {shard-rkl}: NOTRUN -> [SKIP][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-rkl-4/igt@vmwgfx/vmw_ref_count@surface_prime_transfer_single_surface_multiple_handle.html
Known issues
------------
Here are the changes found in Patchwork_116562v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_barrier_race@remote-request@rcs0:
- shard-apl: [PASS][4] -> [ABORT][5] ([i915#8211] / [i915#8234])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-apl6/igt@gem_barrier_race@remote-request@rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-apl3/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][10] -> [FAIL][11] ([i915#2346])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][12] -> [FAIL][13] ([i915#79])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271]) +29 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-snb6/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1.html
* igt@kms_vblank@pipe-h-query-forked:
- shard-glk: NOTRUN -> [SKIP][15] ([fdo#109271]) +10 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-glk8/igt@kms_vblank@pipe-h-query-forked.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [FAIL][16] ([i915#2842]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-glk6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-glk8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- {shard-rkl}: [FAIL][18] ([i915#2842]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-rkl-7/igt@gem_exec_fair@basic-pace@vecs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-rkl-2/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [ABORT][20] ([i915#5566]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-glk5/igt@gen9_exec_parse@allowed-single.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-glk7/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_rc6_residency@rc6-idle@vecs0:
- {shard-dg1}: [FAIL][22] ([i915#3591]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- {shard-rkl}: [SKIP][24] ([i915#1397]) -> [PASS][25] +4 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-rkl-2/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- {shard-dg1}: [SKIP][26] ([i915#1397]) -> [PASS][27] +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-dg1-14/igt@i915_pm_rpm@dpms-non-lpsp.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-dg1-16/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@kms_cursor_legacy@forked-bo@pipe-b:
- {shard-dg1}: [INCOMPLETE][28] ([i915#8011] / [i915#8347]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-dg1-14/igt@kms_cursor_legacy@forked-bo@pipe-b.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-dg1-16/igt@kms_cursor_legacy@forked-bo@pipe-b.html
* igt@kms_cursor_legacy@single-bo@pipe-b:
- {shard-rkl}: [INCOMPLETE][30] ([i915#8011]) -> [PASS][31] +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-rkl-7/igt@kms_cursor_legacy@single-bo@pipe-b.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/shard-rkl-1/igt@kms_cursor_legacy@single-bo@pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
Build changes
-------------
* Linux: CI_DRM_13027 -> Patchwork_116562v3
CI-20190529: 20190529
CI_DRM_13027: 9e1eb302fc69b5d8dc662f1ce7ed8684e87c5751 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7259: 3d3a7f1c041d3f8d84d7457abf96adef0ea071cb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116562v3: 9e1eb302fc69b5d8dc662f1ce7ed8684e87c5751 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v3/index.html
[-- Attachment #2: Type: text/html, Size: 10078 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread* [Intel-gfx] [PATCHv3] drm/i915/display/dp: 128/132b LT requirement
2023-04-17 10:00 [Intel-gfx] [PATCH] drm/i915/display/dp: 128/132b LT requirement Arun R Murthy
` (6 preceding siblings ...)
2023-04-19 5:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-04-25 2:59 ` Arun R Murthy
2023-05-02 13:18 ` Jani Nikula
2023-04-25 3:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/dp: 128/132b LT requirement (rev4) Patchwork
2023-04-25 10:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
9 siblings, 1 reply; 18+ messages in thread
From: Arun R Murthy @ 2023-04-25 2:59 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
For 128b/132b LT prior to LT DPTX should set power state, DP channel
coding and then link rate.
v2: added separate function to avoid code duplication(Jani N)
v3: DP2.1 section 3.5.2.16 is ordered, 3.5.1.2 is unordered and hence
discarding <Ville>
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
.../drm/i915/display/intel_dp_link_training.c | 56 +++++++++++++------
1 file changed, 38 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 6aa4ae5e7ebe..27eb41499d7e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -637,6 +637,37 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
return true;
}
+static void
+intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ u8 link_config[2];
+
+ link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
+ link_config[1] = intel_dp_is_uhbr(crtc_state) ?
+ DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
+ drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
+}
+
+static void
+intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ u8 link_bw, u8 rate_select)
+{
+ u8 link_config[2];
+
+ /* Write the link configuration data */
+ link_config[0] = link_bw;
+ link_config[1] = crtc_state->lane_count;
+ if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
+ link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
+ /* eDP 1.4 rate select method. */
+ if (!link_bw)
+ drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
+ &rate_select, 1);
+}
+
/*
* Prepare link training by configuring the link parameters. On DDI platforms
* also enable the port here.
@@ -647,7 +678,6 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- u8 link_config[2];
u8 link_bw, rate_select;
if (intel_dp->prepare_link_retrain)
@@ -686,23 +716,13 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s] Using LINK_RATE_SET value %02x\n",
encoder->base.base.id, encoder->base.name, rate_select);
-
- /* Write the link configuration data */
- link_config[0] = link_bw;
- link_config[1] = crtc_state->lane_count;
- if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
- link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
- drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
-
- /* eDP 1.4 rate select method. */
- if (!link_bw)
- drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
- &rate_select, 1);
-
- link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
- link_config[1] = intel_dp_is_uhbr(crtc_state) ?
- DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
- drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
+ /*
+ * Spec DP2.1 Section 3.5.2.16
+ * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate
+ */
+ intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
+ intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
+ rate_select);
return true;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCHv3] drm/i915/display/dp: 128/132b LT requirement
2023-04-25 2:59 ` [Intel-gfx] [PATCHv3] drm/i915/display/dp: 128/132b LT requirement Arun R Murthy
@ 2023-05-02 13:18 ` Jani Nikula
0 siblings, 0 replies; 18+ messages in thread
From: Jani Nikula @ 2023-05-02 13:18 UTC (permalink / raw)
To: Arun R Murthy, intel-gfx
On Tue, 25 Apr 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> For 128b/132b LT prior to LT DPTX should set power state, DP channel
> coding and then link rate.
>
> v2: added separate function to avoid code duplication(Jani N)
> v3: DP2.1 section 3.5.2.16 is ordered, 3.5.1.2 is unordered and hence
> discarding <Ville>
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks for the patch, pushed to drm-intel-next.
BR,
Jani.
> ---
> .../drm/i915/display/intel_dp_link_training.c | 56 +++++++++++++------
> 1 file changed, 38 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 6aa4ae5e7ebe..27eb41499d7e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -637,6 +637,37 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
> return true;
> }
>
> +static void
> +intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state)
> +{
> + u8 link_config[2];
> +
> + link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> + link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> + DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> + drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
> +}
> +
> +static void
> +intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state,
> + u8 link_bw, u8 rate_select)
> +{
> + u8 link_config[2];
> +
> + /* Write the link configuration data */
> + link_config[0] = link_bw;
> + link_config[1] = crtc_state->lane_count;
> + if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> + link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
> + /* eDP 1.4 rate select method. */
> + if (!link_bw)
> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> + &rate_select, 1);
> +}
> +
> /*
> * Prepare link training by configuring the link parameters. On DDI platforms
> * also enable the port here.
> @@ -647,7 +678,6 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> - u8 link_config[2];
> u8 link_bw, rate_select;
>
> if (intel_dp->prepare_link_retrain)
> @@ -686,23 +716,13 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
> drm_dbg_kms(&i915->drm,
> "[ENCODER:%d:%s] Using LINK_RATE_SET value %02x\n",
> encoder->base.base.id, encoder->base.name, rate_select);
> -
> - /* Write the link configuration data */
> - link_config[0] = link_bw;
> - link_config[1] = crtc_state->lane_count;
> - if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
> -
> - /* eDP 1.4 rate select method. */
> - if (!link_bw)
> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> - &rate_select, 1);
> -
> - link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> - link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> - DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> - drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
> + /*
> + * Spec DP2.1 Section 3.5.2.16
> + * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate
> + */
> + intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
> + intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
> + rate_select);
>
> return true;
> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/dp: 128/132b LT requirement (rev4)
2023-04-17 10:00 [Intel-gfx] [PATCH] drm/i915/display/dp: 128/132b LT requirement Arun R Murthy
` (7 preceding siblings ...)
2023-04-25 2:59 ` [Intel-gfx] [PATCHv3] drm/i915/display/dp: 128/132b LT requirement Arun R Murthy
@ 2023-04-25 3:40 ` Patchwork
2023-04-25 10:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
9 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2023-04-25 3:40 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4084 bytes --]
== Series Details ==
Series: drm/i915/display/dp: 128/132b LT requirement (rev4)
URL : https://patchwork.freedesktop.org/series/116562/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13056 -> Patchwork_116562v4
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/index.html
Participating hosts (39 -> 37)
------------------------------
Missing (2): fi-kbl-soraka fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_116562v4 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3@smem:
- bat-rpls-1: NOTRUN -> [ABORT][1] ([i915#6687] / [i915#7978])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@slpc:
- bat-rpls-1: NOTRUN -> [DMESG-FAIL][2] ([i915#6367] / [i915#7996])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/bat-rpls-1/igt@i915_selftest@live@slpc.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1:
- bat-dg2-8: [PASS][3] -> [FAIL][4] ([i915#7932])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_heartbeat:
- fi-glk-j4005: [DMESG-FAIL][5] ([i915#5334]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@migrate:
- bat-atsm-1: [DMESG-FAIL][7] ([i915#7699]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/bat-atsm-1/igt@i915_selftest@live@migrate.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/bat-atsm-1/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: [ABORT][9] ([i915#4983] / [i915#8384]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/bat-rpls-1/igt@i915_selftest@live@reset.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/bat-rpls-1/igt@i915_selftest@live@reset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
[i915#8176]: https://gitlab.freedesktop.org/drm/intel/issues/8176
[i915#8361]: https://gitlab.freedesktop.org/drm/intel/issues/8361
[i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384
Build changes
-------------
* Linux: CI_DRM_13056 -> Patchwork_116562v4
CI-20190529: 20190529
CI_DRM_13056: 308c0163d9e46238948942260e6d2abcad3d8bff @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7267: a267f0236e06fc282e3dc3b8c7d76f9ed6088d9b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116562v4: 308c0163d9e46238948942260e6d2abcad3d8bff @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
30ae6e72ee71 drm/i915/display/dp: 128/132b LT requirement
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/index.html
[-- Attachment #2: Type: text/html, Size: 4700 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/dp: 128/132b LT requirement (rev4)
2023-04-17 10:00 [Intel-gfx] [PATCH] drm/i915/display/dp: 128/132b LT requirement Arun R Murthy
` (8 preceding siblings ...)
2023-04-25 3:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/dp: 128/132b LT requirement (rev4) Patchwork
@ 2023-04-25 10:41 ` Patchwork
9 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2023-04-25 10:41 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 20178 bytes --]
== Series Details ==
Series: drm/i915/display/dp: 128/132b LT requirement (rev4)
URL : https://patchwork.freedesktop.org/series/116562/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13056_full -> Patchwork_116562v4_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_116562v4_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
- {shard-dg1}: NOTRUN -> [SKIP][1] +70 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-dg1-12/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite:
- {shard-dg1}: [PASS][2] -> [SKIP][3] +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-dg1-12/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
- {shard-dg1}: [SKIP][4] ([i915#4833]) -> [SKIP][5] +4 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-dg1-12/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- {shard-dg1}: [SKIP][6] ([i915#5439]) -> [SKIP][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-dg1-12/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
- {shard-dg1}: [SKIP][8] ([i915#3458]) -> [SKIP][9] +9 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
- {shard-dg1}: [SKIP][10] ([fdo#111825]) -> [SKIP][11] +16 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-dg1-15/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_plane@pixel-format@pipe-a-planes:
- {shard-rkl}: [PASS][12] -> [ABORT][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-rkl-2/igt@kms_plane@pixel-format@pipe-a-planes.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-rkl-2/igt@kms_plane@pixel-format@pipe-a-planes.html
Known issues
------------
Here are the changes found in Patchwork_116562v4_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][14] -> [FAIL][15] ([i915#2842]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
- shard-apl: [PASS][16] -> [DMESG-WARN][17] ([i915#62] / [i915#7634])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-apl7/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-apl1/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-dp-1:
- shard-apl: [PASS][18] -> [DMESG-WARN][19] ([i915#180] / [i915#62]) +16 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-apl7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-dp-1.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-apl1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-dp-1.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-180:
- shard-apl: [PASS][20] -> [DMESG-WARN][21] ([i915#1982] / [i915#62])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-apl7/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-apl1/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html
* igt@kms_cursor_edge_walk@64x64-right-edge@pipe-a-dp-1:
- shard-apl: [PASS][22] -> [DMESG-WARN][23] ([i915#62]) +113 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-apl4/igt@kms_cursor_edge_walk@64x64-right-edge@pipe-a-dp-1.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-apl1/igt@kms_cursor_edge_walk@64x64-right-edge@pipe-a-dp-1.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][24] ([fdo#109271])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-glk1/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2:
- shard-glk: [PASS][25] -> [FAIL][26] ([i915#79])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-vga-1:
- shard-snb: NOTRUN -> [SKIP][27] ([fdo#109271]) +38 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-snb6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-vga-1.html
#### Possible fixes ####
* igt@drm_fdinfo@virtual-idle:
- {shard-rkl}: [FAIL][28] ([i915#7742]) -> [PASS][29] +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-rkl-3/igt@drm_fdinfo@virtual-idle.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-rkl-1/igt@drm_fdinfo@virtual-idle.html
* igt@gem_exec_fair@basic-deadline:
- {shard-rkl}: [FAIL][30] ([i915#2846]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-rkl-6/igt@gem_exec_fair@basic-deadline.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-rkl-7/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-rkl}: [FAIL][32] ([i915#2842]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-rkl-1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-rkl-6/igt@gem_exec_fair@basic-pace-share@rcs0.html
- {shard-tglu}: [FAIL][34] ([i915#2842]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-tglu-3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-tglu-5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-snb: [FAIL][36] ([i915#8295]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-snb1/igt@gem_ppgtt@blt-vs-render-ctxn.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-snb5/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- {shard-dg1}: [SKIP][38] ([i915#1937]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-dg1-15/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-dg1-14/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-rkl}: [SKIP][40] ([i915#1397]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-rkl-2/igt@i915_pm_rpm@modeset-lpsp-stress.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-dg1}: [SKIP][42] ([i915#1397]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-dg1-15/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-dg1-14/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-apl: [FAIL][44] ([i915#2346]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@forked-move@pipe-b:
- {shard-dg1}: [INCOMPLETE][46] ([i915#8011] / [i915#8347]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-dg1-14/igt@kms_cursor_legacy@forked-move@pipe-b.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-dg1-18/igt@kms_cursor_legacy@forked-move@pipe-b.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][48] ([i915#79]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
- shard-apl: [FAIL][50] ([i915#79]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13056/shard-apl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/shard-apl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7634]: https://gitlab.freedesktop.org/drm/intel/issues/7634
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7733]: https://gitlab.freedesktop.org/drm/intel/issues/7733
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8153]: https://gitlab.freedesktop.org/drm/intel/issues/8153
[i915#8154]: https://gitlab.freedesktop.org/drm/intel/issues/8154
[i915#8295]: https://gitlab.freedesktop.org/drm/intel/issues/8295
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
Build changes
-------------
* Linux: CI_DRM_13056 -> Patchwork_116562v4
CI-20190529: 20190529
CI_DRM_13056: 308c0163d9e46238948942260e6d2abcad3d8bff @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7267: a267f0236e06fc282e3dc3b8c7d76f9ed6088d9b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116562v4: 308c0163d9e46238948942260e6d2abcad3d8bff @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116562v4/index.html
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