[PATCH 00/16] Add support for 3 VDSC engines 12 slices

[PATCH 00/16] Add support for 3 VDSC engines 12 slices

[Ankit Nautiyal]

For BMG 3 VDSC engines are supported and each pipe can then support
3 slices. For Ultra joiner cases for modes like 8k@120 Hz we require
ultrajoiner and 3 x 4= 12 slices.
Add support for 3 VDSC engines and 12 DSC slices. Along with this
Pixel replication and Odd pixel considerartions are also required.

Rev2: Rebase
Rev3:
-Add patch to account for pixel replication in pipe_src.
-Fix kernel test bot warning.
-Minor refactoring.
Rev4:
-Address review comments from last version.
-Add BW consideration with pixel replication
-Split Odd pixel handling in separate patches.

Ankit Nautiyal (16):
  drm/i915/dp: Update Comment for Valid DSC Slices per Line
  drm/i915/display: Prepare for dsc 3 stream splitter
  drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine
  drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2
  drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine
  drm/i915/dp: Ensure hactive is divisible by slice count
  drm/i915/dp: Enable 3 DSC engines for 12 slices
  drm/i915/display: Add macro HAS_PIXEL_REPLICATION
  drm/i915/display: Add support for DSC pixel replication
  drm/i915/dp_mst: Account for pixel replication for MST overhead with
    DSC
  drm/i915/dp: Account for pixel replication for BW computation with DSC
  drm/i915/display: Account for pixel replication in pipe_src
  drm/i915/dp: Enable DSC pixel replication
  drm/i915/dsc: Introduce odd pixel removal
  drm/i915/display: Adjust Pipe SRC Width for Odd Pixels
  drm/i915/dp: Add Check for Odd Pixel Requirement

 drivers/gpu/drm/i915/display/icl_dsi.c        |   2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  36 +++++-
 .../drm/i915/display/intel_display_device.h   |   3 +
 .../drm/i915/display/intel_display_types.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |  87 ++++++++++++--
 drivers/gpu/drm/i915/display/intel_dp.h       |   2 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  19 ++-
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 113 ++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_vdsc.h     |   9 ++
 .../gpu/drm/i915/display/intel_vdsc_regs.h    |  22 +++-
 10 files changed, 270 insertions(+), 27 deletions(-)

-- 
2.45.2

[PATCH 01/16] drm/i915/dp: Update Comment for Valid DSC Slices per Line

[Ankit Nautiyal]

For some platforms, the maximum slices per DSC engine is 4, while for
others it is 2. Update the comment to reflect this and clarify that
the 'valid_dsc_slicecount' list represents the valid number of slices
per pipe.

Currently, we are working with 1, and 2 slices per DSC engine,
which works for all platforms. With this the number of slices per pipe
can be 1,2 or 4 with different slice & DSC engine configuration.

Add a #TODO for adding support for 4 slices per DSC engine where
supported.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7e04913bc2ff..286b272aa98c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -108,8 +108,14 @@
 /* Constants for DP DSC configurations */
 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 
-/* With Single pipe configuration, HW is capable of supporting maximum
- * of 4 slices per line.
+/*
+ * With Single pipe configuration, HW is capable of supporting maximum of:
+ * 2 slices per line for ICL, BMG
+ * 4 slices per line for other platforms.
+ * For now consider a max of 2 slices per line, which works for all platforms.
+ * With this we can have max of 4 DSC Slices per pipe.
+ *
+ * #TODO Split this better to use 4 slices/dsc engine where supported.
  */
 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 
-- 
2.45.2

[PATCH 02/16] drm/i915/display: Prepare for dsc 3 stream splitter

[Ankit Nautiyal]

At the moment dsc_split represents that dsc splitter is used or not.
With 3 DSC engines, the splitter can split into two streams or three
streams. Make the member dsc_split as int and set that to 2 when dsc
splitter splits to 2 stream.

v2: Avoid new enum for dsc split. (Suraj)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
 .../drm/i915/display/intel_display_types.h    |  2 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 20 ++++++++++++++-----
 5 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 87a27d91d15d..553e75cf118c 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1595,7 +1595,7 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
 
 	/* FIXME: split only when necessary */
 	if (crtc_state->dsc.slice_count > 1)
-		crtc_state->dsc.dsc_split = true;
+		crtc_state->dsc.dsc_split = 2;
 
 	/* FIXME: initialize from VBT */
 	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ef1436146325..9e2f0fd0558f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5741,7 +5741,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
 
 	PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
-	PIPE_CONF_CHECK_BOOL(dsc.dsc_split);
+	PIPE_CONF_CHECK_I(dsc.dsc_split);
 	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
 
 	PIPE_CONF_CHECK_BOOL(splitter.enable);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 2bb1fa64da2f..58f510909f4d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1235,7 +1235,7 @@ struct intel_crtc_state {
 	/* Display Stream compression state */
 	struct {
 		bool compression_enable;
-		bool dsc_split;
+		int dsc_split;
 		/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
 		u16 compressed_bpp_x16;
 		u8 slice_count;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 286b272aa98c..c1867c883b73 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2409,7 +2409,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	 * then we need to use 2 VDSC instances.
 	 */
 	if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
-		pipe_config->dsc.dsc_split = true;
+		pipe_config->dsc.dsc_split = 2;
 
 	ret = intel_dp_dsc_compute_params(connector, pipe_config);
 	if (ret < 0) {
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 40525f5c4c42..3bce13c21756 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -379,7 +379,14 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 
 static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
 {
-	return crtc_state->dsc.dsc_split ? 2 : 1;
+	switch (crtc_state->dsc.dsc_split) {
+	case 2:
+		return 2;
+	case 0:
+	default:
+		break;
+	}
+	return 1;
 }
 
 int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
@@ -976,8 +983,11 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	if (!crtc_state->dsc.compression_enable)
 		goto out;
 
-	crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
-		(dss_ctl1 & JOINER_ENABLE);
+	if ((dss_ctl1 & JOINER_ENABLE) &&
+	    (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE))
+		crtc_state->dsc.dsc_split = 2;
+	else
+		crtc_state->dsc.dsc_split = 0;
 
 	intel_dsc_get_pps_config(crtc_state);
 out:
@@ -988,10 +998,10 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent,
 				  const struct intel_crtc_state *crtc_state)
 {
 	drm_printf_indent(p, indent,
-			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n",
+			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %d\n",
 			  FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
 			  crtc_state->dsc.slice_count,
-			  str_yes_no(crtc_state->dsc.dsc_split));
+			  crtc_state->dsc.dsc_split);
 }
 
 void intel_vdsc_state_dump(struct drm_printer *p, int indent,
-- 
2.45.2

[PATCH 03/16] drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine

[Ankit Nautiyal]

Drop use of LEFT/RIGHT VDSC engine and use VDSC0/VDSC1 instead.
While at it, use REG_BIT macro for the bits.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c      | 8 ++++----
 drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 3bce13c21756..198446738662 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -777,9 +777,9 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
 
 	intel_dsc_pps_configure(crtc_state);
 
-	dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
+	dss_ctl2_val |= VDSC0_ENABLE;
 	if (vdsc_instances_per_pipe > 1) {
-		dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
+		dss_ctl2_val |= VDSC1_ENABLE;
 		dss_ctl1_val |= JOINER_ENABLE;
 	}
 	if (crtc_state->joiner_pipes) {
@@ -979,12 +979,12 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));
 	dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));
 
-	crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
+	crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE;
 	if (!crtc_state->dsc.compression_enable)
 		goto out;
 
 	if ((dss_ctl1 & JOINER_ENABLE) &&
-	    (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE))
+	    (dss_ctl2 & VDSC1_ENABLE))
 		crtc_state->dsc.dsc_split = 2;
 	else
 		crtc_state->dsc.dsc_split = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index bf32a3b46fb1..d7a72b95ee7e 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -21,8 +21,8 @@
 #define  MAX_DL_BUFFER_TARGET_DEPTH		0x5a0
 
 #define DSS_CTL2				_MMIO(0x67404)
-#define  LEFT_BRANCH_VDSC_ENABLE		(1 << 31)
-#define  RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
+#define  VDSC0_ENABLE				REG_BIT(31)
+#define  VDSC1_ENABLE				REG_BIT(15)
 #define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
 #define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
 
-- 
2.45.2

[PATCH 04/16] drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2

[Ankit Nautiyal]

Introduce the register bits to enable the 3rd DSC engine VDSC2.
Add support to read/write these bits.

v2: Only introduce bits that are used and update the subject and commit
message. (Suraj)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 20 +++++++++++++++----
 .../gpu/drm/i915/display/intel_vdsc_regs.h    |  2 ++
 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 198446738662..70b75de921de 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -380,6 +380,8 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
 {
 	switch (crtc_state->dsc.dsc_split) {
+	case 3:
+		return 3;
 	case 2:
 		return 2;
 	case 0:
@@ -782,6 +784,12 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
 		dss_ctl2_val |= VDSC1_ENABLE;
 		dss_ctl1_val |= JOINER_ENABLE;
 	}
+
+	if (vdsc_instances_per_pipe > 2) {
+		dss_ctl2_val |= VDSC2_ENABLE;
+		dss_ctl2_val |= SMALL_JOINER_CONFIG_3_ENGINES;
+	}
+
 	if (crtc_state->joiner_pipes) {
 		if (intel_crtc_ultrajoiner_enable_needed(crtc_state))
 			dss_ctl1_val |= ULTRA_JOINER_ENABLE;
@@ -983,11 +991,15 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	if (!crtc_state->dsc.compression_enable)
 		goto out;
 
-	if ((dss_ctl1 & JOINER_ENABLE) &&
-	    (dss_ctl2 & VDSC1_ENABLE))
-		crtc_state->dsc.dsc_split = 2;
-	else
+	if (dss_ctl1 & JOINER_ENABLE) {
+		if (dss_ctl2 & (VDSC2_ENABLE | SMALL_JOINER_CONFIG_3_ENGINES))
+			crtc_state->dsc.dsc_split = 3;
+
+		else if (dss_ctl2 & VDSC1_ENABLE)
+			crtc_state->dsc.dsc_split = 2;
+	} else {
 		crtc_state->dsc.dsc_split = 0;
+	}
 
 	intel_dsc_get_pps_config(crtc_state);
 out:
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index d7a72b95ee7e..474a7f9f3881 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -22,6 +22,8 @@
 
 #define DSS_CTL2				_MMIO(0x67404)
 #define  VDSC0_ENABLE				REG_BIT(31)
+#define  VDSC2_ENABLE				REG_BIT(30)
+#define  SMALL_JOINER_CONFIG_3_ENGINES		REG_BIT(23)
 #define  VDSC1_ENABLE				REG_BIT(15)
 #define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
 #define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
-- 
2.45.2

[PATCH 05/16] drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine

[Ankit Nautiyal]

With BMG each pipe has 3 DSC engines, so add bits to read/write the PPS
registers for the 3rd DSC engine

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c      | 8 +++++---
 drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 6 ++++++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 70b75de921de..777a287210f9 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -411,8 +411,10 @@ static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int
 
 	pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
 
-	if (dsc_reg_num >= 3)
+	if (dsc_reg_num >= 4)
 		MISSING_CASE(dsc_reg_num);
+	if (dsc_reg_num >= 3)
+		dsc_reg[2] = BMG_DSC2_PPS(pipe, pps);
 	if (dsc_reg_num >= 2)
 		dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) : DSCC_PPS(pps);
 	if (dsc_reg_num >= 1)
@@ -424,7 +426,7 @@ static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state,
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	i915_reg_t dsc_reg[2];
+	i915_reg_t dsc_reg[3];
 	int i, vdsc_per_pipe, dsc_reg_num;
 
 	vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
@@ -824,7 +826,7 @@ static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	i915_reg_t dsc_reg[2];
+	i915_reg_t dsc_reg[3];
 	int i, vdsc_per_pipe, dsc_reg_num;
 	u32 val;
 
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index 474a7f9f3881..2d478a84b07c 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -59,8 +59,10 @@
 #define DSCC_PPS(pps)				_MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4)
 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB	0x78270
 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB	0x78370
+#define _BMG_DSC2_PICTURE_PARAMETER_SET_0_PB	0x78970
 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC	0x78470
 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC	0x78570
+#define _BMG_DSC2_PICTURE_PARAMETER_SET_0_PC	0x78A70
 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
 							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
@@ -73,8 +75,12 @@
 #define _ICL_DSC1_PPS_0(pipe)			_PICK_EVEN((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
+#define _BMG_DSC2_PPS_0(pipe)			_PICK_EVEN((pipe) - PIPE_B, \
+							   _BMG_DSC2_PICTURE_PARAMETER_SET_0_PB, \
+							   _BMG_DSC2_PICTURE_PARAMETER_SET_0_PC)
 #define  ICL_DSC0_PPS(pipe, pps)		_MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4))
 #define  ICL_DSC1_PPS(pipe, pps)		_MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
+#define  BMG_DSC2_PPS(pipe, pps)		_MMIO(_BMG_DSC2_PPS_0(pipe) + ((pps) * 4))
 
 /* PPS 0 */
 #define   DSC_PPS0_NATIVE_422_ENABLE		REG_BIT(23)
-- 
2.45.2

[PATCH 06/16] drm/i915/dp: Ensure hactive is divisible by slice count

[Ankit Nautiyal]

According to the DSC spec, the slice width should be chosen such that
the picture width (hactive) is evenly divisible by the slice width.
If not, extra pixels (padding) must be added to the last slice to
ensure all slices have the same width.

Currently, we do not support handling these extra pixels.
Therefore, select a slice count that evenly divides the hactive
(slice_width = hactive / slice_count).

This check is already implemented for DSI, where the slice count is
selected from the BIOS.

For DP, currently with 1, 2, 4 slices per pipe it is unlikely to have
slice count not being able to divide hactive, but with 3 DSC engines
and 3 slices, we can have such cases. Adding this check prepares for
future scenarios where such configurations might be used.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c1867c883b73..0607ea4ee321 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1037,6 +1037,9 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
 		if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2)
 			continue;
 
+		if (mode_hdisplay % test_slice_count)
+			continue;
+
 		if (min_slice_count <= test_slice_count)
 			return test_slice_count;
 	}
-- 
2.45.2

[PATCH 07/16] drm/i915/dp: Enable 3 DSC engines for 12 slices

[Ankit Nautiyal]

Certain resolutions require 12 DSC slices support along with ultrajoiner.
For such cases, the third DSC Engine per Pipe is enabled. Each DSC
Engine processes 1 Slice, resulting in a total of 12 VDSC slices
(4 Pipes * 3 DSC Instances per Pipe).
Add support for 12 DSC slices and 3 DSC engines for such modes.

v2: Add missing check for 3 slices support only with 4 joined pipes.
(Suraj)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0607ea4ee321..53a437caacac 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -115,9 +115,12 @@ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
  * For now consider a max of 2 slices per line, which works for all platforms.
  * With this we can have max of 4 DSC Slices per pipe.
  *
+ * For higher resolutions where 12 slice support is required with
+ * ultrajoiner, only then each pipe can support 3 slices.
+ *
  * #TODO Split this better to use 4 slices/dsc engine where supported.
  */
-static const u8 valid_dsc_slicecount[] = {1, 2, 4};
+static const u8 valid_dsc_slicecount[] = {1, 2, 3, 4};
 
 /**
  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
@@ -1025,6 +1028,13 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
 	for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 		u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes;
 
+		/*
+		 * 3 DSC Slices per pipe need 3 DSC engines,
+		 * which is supported only with Ultrajoiner.
+		 */
+		if (valid_dsc_slicecount[i] == 3 && num_joined_pipes != 4)
+			continue;
+
 		if (test_slice_count >
 		    drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))
 			break;
@@ -2410,8 +2420,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
 	 * is greater than the maximum Cdclock and if slice count is even
 	 * then we need to use 2 VDSC instances.
+	 * In case of Ultrajoiner along with 12 slices we need to use 3
+	 * VDSC instances.
 	 */
-	if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
+	if (pipe_config->joiner_pipes && num_joined_pipes == 4 &&
+	    pipe_config->dsc.slice_count == 12)
+		pipe_config->dsc.dsc_split = 3;
+	else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
 		pipe_config->dsc.dsc_split = 2;
 
 	ret = intel_dp_dsc_compute_params(connector, pipe_config);
-- 
2.45.2

[PATCH 08/16] drm/i915/display: Add macro HAS_PIXEL_REPLICATION

[Ankit Nautiyal]

Add macro for Pixel replication support with DSC.
Bspec: 49259, 68912.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 071a36b51f79..a21b910879df 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -149,6 +149,9 @@ enum intel_display_subplatform {
 #define HAS_MBUS_JOINING(i915)		(IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
 #define HAS_MSO(i915)			(DISPLAY_VER(i915) >= 12)
 #define HAS_OVERLAY(i915)		(DISPLAY_INFO(i915)->has_overlay)
+#define HAS_PIXEL_REPLICATION(i915)	(HAS_DSC(i915) && \
+					 (DISPLAY_VER(i915) >= 20 || \
+					  DISPLAY_VER_FULL(i915) == IP_VER(14, 1)))
 #define HAS_PSR(i915)			(DISPLAY_INFO(i915)->has_psr)
 #define HAS_PSR_HW_TRACKING(i915)	(DISPLAY_INFO(i915)->has_psr_hw_tracking)
 #define HAS_PSR2_SEL_FETCH(i915)	(DISPLAY_VER(i915) >= 12)
-- 
2.45.2

[PATCH 09/16] drm/i915/display: Add support for DSC pixel replication

[Ankit Nautiyal]

With 3 VDSC engines and Ultrajoiner, we may encounter a situation where
hactive is not a multiple of slice count. In this case we need to add
extra pixels to the last slice to distribute pixels evenly across
slices.

Add member to store DSC pixel replication when hactive is not divisible
by slice count. Fill DSS_CTL3 register with the replicated pixel count.
Also add this in dsc state dump.

v2: Use macro REG_FIELD_PREP and HAS_PIXEL_REPLICATION. (Suraj)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  1 +
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 25 +++++++++++++++++--
 .../gpu/drm/i915/display/intel_vdsc_regs.h    |  8 ++++++
 4 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9e2f0fd0558f..1b772f58998e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5743,6 +5743,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
 	PIPE_CONF_CHECK_I(dsc.dsc_split);
 	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
+	PIPE_CONF_CHECK_I(dsc.replicated_pixels);
 
 	PIPE_CONF_CHECK_BOOL(splitter.enable);
 	PIPE_CONF_CHECK_I(splitter.link_count);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 58f510909f4d..17554f52611c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1239,6 +1239,7 @@ struct intel_crtc_state {
 		/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
 		u16 compressed_bpp_x16;
 		u8 slice_count;
+		int replicated_pixels;
 		struct drm_dsc_config config;
 	} dsc;
 
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 777a287210f9..14cc1ef3641e 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -774,6 +774,7 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 dss_ctl1_val = 0;
 	u32 dss_ctl2_val = 0;
+	u32 dss_ctl3_val = 0;
 	int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
 
 	if (!crtc_state->dsc.compression_enable)
@@ -804,8 +805,16 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
 		if (intel_crtc_is_bigjoiner_primary(crtc_state))
 			dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
 	}
+
+	if (crtc_state->dsc.replicated_pixels)
+		dss_ctl3_val = DSC_PIXEL_REPLICATION(crtc_state->dsc.replicated_pixels);
+
 	intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
 	intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
+
+	if (HAS_PIXEL_REPLICATION(dev_priv) && dss_ctl3_val)
+		intel_de_write(dev_priv,
+			       BMG_PIPE_DSS_CTL3(crtc_state->cpu_transcoder), dss_ctl3_val);
 }
 
 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
@@ -818,6 +827,10 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
 	    old_crtc_state->joiner_pipes) {
 		intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
 		intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
+
+		if (HAS_PIXEL_REPLICATION(dev_priv))
+			intel_de_write(dev_priv,
+				       BMG_PIPE_DSS_CTL3(old_crtc_state->cpu_transcoder), 0);
 	}
 }
 
@@ -975,7 +988,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	enum intel_display_power_domain power_domain;
 	intel_wakeref_t wakeref;
-	u32 dss_ctl1, dss_ctl2;
+	u32 dss_ctl1, dss_ctl2, dss_ctl3 = 0;
 
 	if (!intel_dsc_source_support(crtc_state))
 		return;
@@ -989,6 +1002,9 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));
 	dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));
 
+	if (HAS_PIXEL_REPLICATION(dev_priv))
+		dss_ctl3 = intel_de_read(dev_priv, BMG_PIPE_DSS_CTL3(crtc_state->cpu_transcoder));
+
 	crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE;
 	if (!crtc_state->dsc.compression_enable)
 		goto out;
@@ -1003,6 +1019,10 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 		crtc_state->dsc.dsc_split = 0;
 	}
 
+	if (dss_ctl3 & DSC_PIXEL_REPLICATION_MASK)
+		crtc_state->dsc.replicated_pixels =
+			dss_ctl3 & DSC_PIXEL_REPLICATION_MASK;
+
 	intel_dsc_get_pps_config(crtc_state);
 out:
 	intel_display_power_put(dev_priv, power_domain, wakeref);
@@ -1012,9 +1032,10 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent,
 				  const struct intel_crtc_state *crtc_state)
 {
 	drm_printf_indent(p, indent,
-			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %d\n",
+			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, replicated pixels: %d split: %d\n",
 			  FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
 			  crtc_state->dsc.slice_count,
+			  crtc_state->dsc.replicated_pixels,
 			  crtc_state->dsc.dsc_split);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index 2d478a84b07c..f07fad6239bc 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -50,6 +50,14 @@
 							   _ICL_PIPE_DSS_CTL2_PB, \
 							   _ICL_PIPE_DSS_CTL2_PC)
 
+#define _BMG_PIPE_DSS_CTL3_PB			0x782f0
+#define _BMG_PIPE_DSS_CTL3_PC			0x784f0
+#define BMG_PIPE_DSS_CTL3(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
+							   _BMG_PIPE_DSS_CTL3_PB, \
+							   _BMG_PIPE_DSS_CTL3_PC)
+#define  DSC_PIXEL_REPLICATION_MASK		REG_GENMASK(15, 0)
+#define  DSC_PIXEL_REPLICATION(count)		(REG_FIELD_PREP(DSC_PIXEL_REPLICATION_MASK, (count)))
+
 /* Icelake Display Stream Compression Registers */
 #define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
 #define DSCC_PICTURE_PARAMETER_SET_0		_MMIO(0x6BA00)
-- 
2.45.2

[PATCH 10/16] drm/i915/dp_mst: Account for pixel replication for MST overhead with DSC

[Ankit Nautiyal]

Add the extra pixels to the hactive while computing overhead with DSC.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.h     |  1 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +++++++++++++--
 drivers/gpu/drm/i915/display/intel_vdsc.c   | 23 +++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vdsc.h   |  6 ++++++
 4 files changed, 45 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 60baf4072dc9..e90a9dc1a8f5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -20,6 +20,7 @@ struct intel_atomic_state;
 struct intel_connector;
 struct intel_crtc_state;
 struct intel_digital_port;
+struct intel_display;
 struct intel_dp;
 struct intel_encoder;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 1a2ff3e1cb68..72130c7748dd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -92,20 +92,33 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
 				    const struct intel_connector *connector,
 				    bool ssc, int dsc_slice_count, int bpp_x16)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
 	unsigned long flags = DRM_DP_BW_OVERHEAD_MST;
 	int overhead;
+	int replicated_pixels = 0;
 
 	flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
 	flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
 	flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
 
-	if (dsc_slice_count)
+	if (dsc_slice_count) {
 		flags |= DRM_DP_BW_OVERHEAD_DSC;
+		/*
+		 * When hdisplay is not divisible by dsc_slice_count, extra pixels
+		 * are added to last slice. Need to account for the extra overhead due
+		 * to these extra pixels.
+		 */
+		replicated_pixels =
+			intel_dsc_get_replicated_pixels(display,
+							adjusted_mode->hdisplay,
+							dsc_slice_count,
+							crtc_state->output_format);
+	}
 
 	overhead = drm_dp_bw_overhead(crtc_state->lane_count,
-				      adjusted_mode->hdisplay,
+				      adjusted_mode->hdisplay + replicated_pixels,
 				      dsc_slice_count,
 				      bpp_x16,
 				      flags);
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 14cc1ef3641e..c3c6a4a4dafd 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -1048,3 +1048,26 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent,
 	intel_vdsc_dump_state(p, indent, crtc_state);
 	drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);
 }
+
+int intel_dsc_get_replicated_pixels(struct intel_display *display,
+				    int mode_hdisplay,
+				    int slice_count,
+				    enum intel_output_format output_format)
+{
+	int replicated_pixels;
+	int slice_width = DIV_ROUND_UP(mode_hdisplay, slice_count);
+
+	if (!HAS_PIXEL_REPLICATION(display))
+		return 0;
+
+	if (mode_hdisplay % slice_count == 0)
+		return 0;
+
+	/* Odd slice width is not supported by YCbCr420 format */
+	if (slice_width % 2 && output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		return 0;
+
+	replicated_pixels = (slice_width * slice_count) - mode_hdisplay;
+
+	return replicated_pixels;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 290b2e9b3482..41b8b5c5866e 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -10,9 +10,11 @@
 
 struct drm_printer;
 
+enum intel_output_format;
 enum transcoder;
 struct intel_crtc;
 struct intel_crtc_state;
+struct intel_display;
 struct intel_encoder;
 
 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
@@ -31,5 +33,9 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
 			    const struct intel_crtc_state *crtc_state);
 void intel_vdsc_state_dump(struct drm_printer *p, int indent,
 			   const struct intel_crtc_state *crtc_state);
+int intel_dsc_get_replicated_pixels(struct intel_display *display,
+				    int mode_hdisplay,
+				    int slice_count,
+				    enum intel_output_format output_format);
 
 #endif /* __INTEL_VDSC_H__ */
-- 
2.45.2

[PATCH 11/16] drm/i915/dp: Account for pixel replication for BW computation with DSC

[Ankit Nautiyal]

Include the extra pixels added while computing bandwidth with DSC.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 53a437caacac..f35d6fc376c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1940,6 +1940,23 @@ static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_cloc
 	return available_bw > required_bw;
 }
 
+static
+u32 adjust_clock_for_extra_pixels(const struct drm_display_mode *adjusted_mode,
+				  int extra_pixels)
+{
+	u32 clock = adjusted_mode->clock;
+	u16 htotal = adjusted_mode->htotal;
+
+	if (!extra_pixels)
+		return clock;
+	/*
+	 * clock = (htotal) * (vtotal) * refresh_rate
+	 * adjusted_clock = (htotal + extra_pixels) * (vtotal) * refresh_rate
+	 * = clock + (clock * extra_pixels / htotal)
+	 */
+	return clock + extra_pixels * (clock / htotal);
+}
+
 static int dsc_compute_link_config(struct intel_dp *intel_dp,
 				   struct intel_crtc_state *pipe_config,
 				   struct link_config_limits *limits,
@@ -1948,8 +1965,12 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
 {
 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	int link_rate, lane_count;
+	u32 adjusted_clock;
 	int i;
 
+	adjusted_clock = adjust_clock_for_extra_pixels(adjusted_mode,
+						       pipe_config->dsc.replicated_pixels);
+
 	for (i = 0; i < intel_dp->num_common_rates; i++) {
 		link_rate = intel_dp_common_rate(intel_dp, i);
 		if (link_rate < limits->min_rate || link_rate > limits->max_rate)
@@ -1959,7 +1980,7 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
 		     lane_count <= limits->max_lane_count;
 		     lane_count <<= 1) {
 			if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,
-							     lane_count, adjusted_mode->clock,
+							     lane_count, adjusted_clock,
 							     pipe_config->output_format,
 							     timeslots))
 				continue;
-- 
2.45.2

[PATCH 12/16] drm/i915/display: Account for pixel replication in pipe_src

[Ankit Nautiyal]

With DSC pixel replication, extra pixels are added in the last slice
of the last pipe. Due to this the total hactive gets increased by few
pixels. Adjust the computation for pipe source width to account for
pixel replication.

These extra pixels will be take care by the Splitter logic in
hardware.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1b772f58998e..de682fec45cd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2514,6 +2514,22 @@ void intel_encoder_get_config(struct intel_encoder *encoder,
 	intel_crtc_readout_derived_state(crtc_state);
 }
 
+static int intel_splitter_adjust_pipe_width(int width, int replicated_pixels)
+{
+	/* Account for Pixel replication:
+	 * Pixel replication is required due to the rounding of slice_width (Hactive / slice_count).
+	 *
+	 * Splitter HW takes care of these by removing replicated pixels from the last pipe.
+	 */
+
+	if (!replicated_pixels)
+		return width;
+
+	width += replicated_pixels;
+
+	return width;
+}
+
 static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
 {
 	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
@@ -2522,7 +2538,9 @@ static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
 	if (num_pipes == 1)
 		return;
 
-	width = drm_rect_width(&crtc_state->pipe_src);
+	width = intel_splitter_adjust_pipe_width(drm_rect_width(&crtc_state->pipe_src),
+						 crtc_state->dsc.replicated_pixels);
+
 	height = drm_rect_height(&crtc_state->pipe_src);
 
 	drm_rect_init(&crtc_state->pipe_src, 0, 0,
-- 
2.45.2

[PATCH 13/16] drm/i915/dp: Enable DSC pixel replication

[Ankit Nautiyal]

Allow DSC slice count that do not divide the hactive evenly by adding
extra pixels (replicated pixels).
Check if the pixel replication is supported and store the no. of
replicated pixel count in crtc_state.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 20 +++++++++++++--
 drivers/gpu/drm/i915/display/intel_dp.h     |  1 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 ++
 drivers/gpu/drm/i915/display/intel_vdsc.c   | 28 +++++++++++++++------
 drivers/gpu/drm/i915/display/intel_vdsc.h   |  3 +++
 5 files changed, 44 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f35d6fc376c8..433a629c2bae 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -992,9 +992,11 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
 
 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
 				int mode_clock, int mode_hdisplay,
+				enum intel_output_format output_format,
 				int num_joined_pipes)
 {
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+	struct intel_display *display = to_intel_display(connector);
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	u8 min_slice_count, i;
 	int max_slice_width;
 
@@ -1047,7 +1049,11 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
 		if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2)
 			continue;
 
-		if (mode_hdisplay % test_slice_count)
+		if (mode_hdisplay % test_slice_count &&
+		    !intel_dsc_can_use_pixel_replication(display,
+							 mode_hdisplay,
+							 test_slice_count,
+							 output_format))
 			continue;
 
 		if (min_slice_count <= test_slice_count)
@@ -1474,6 +1480,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 				intel_dp_dsc_get_slice_count(connector,
 							     target_clock,
 							     mode->hdisplay,
+							     output_format,
 							     num_joined_pipes);
 		}
 
@@ -2366,6 +2373,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 				int timeslots,
 				bool compute_pipe_bpp)
 {
+	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	const struct intel_connector *connector =
@@ -2428,6 +2436,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 			intel_dp_dsc_get_slice_count(connector,
 						     adjusted_mode->crtc_clock,
 						     adjusted_mode->crtc_hdisplay,
+						     pipe_config->output_format,
 						     num_joined_pipes);
 		if (!dsc_dp_slice_count) {
 			drm_dbg_kms(&dev_priv->drm,
@@ -2437,6 +2446,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 
 		pipe_config->dsc.slice_count = dsc_dp_slice_count;
 	}
+
+	pipe_config->dsc.replicated_pixels =
+		intel_dsc_get_replicated_pixels(display,
+						adjusted_mode->crtc_hdisplay,
+						pipe_config->dsc.slice_count,
+						pipe_config->output_format);
+
 	/*
 	 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
 	 * is greater than the maximum Cdclock and if slice count is even
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index e90a9dc1a8f5..7460675c16f6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -150,6 +150,7 @@ int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector
 					 int bpc);
 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
 				int mode_clock, int mode_hdisplay,
+				enum intel_output_format output_format,
 				int num_joined_pipes);
 int intel_dp_num_joined_pipes(struct intel_dp *intel_dp,
 			      struct intel_connector *connector,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 72130c7748dd..b5c72628d445 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -171,6 +171,7 @@ static int intel_dp_mst_dsc_get_slice_count(const struct intel_connector *connec
 	return intel_dp_dsc_get_slice_count(connector,
 					    adjusted_mode->clock,
 					    adjusted_mode->hdisplay,
+					    crtc_state->output_format,
 					    num_joined_pipes);
 }
 
@@ -1537,6 +1538,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
 				intel_dp_dsc_get_slice_count(intel_connector,
 							     target_clock,
 							     mode->hdisplay,
+							     INTEL_OUTPUT_FORMAT_RGB,
 							     num_joined_pipes);
 		}
 
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index c3c6a4a4dafd..c279f59fdda8 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -1049,6 +1049,22 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent,
 	drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);
 }
 
+bool intel_dsc_can_use_pixel_replication(struct intel_display *display,
+					 int mode_hdisplay, u8 slice_count,
+					 enum intel_output_format output_format)
+{
+	int slice_width = DIV_ROUND_UP(mode_hdisplay, slice_count);
+
+	if (!HAS_PIXEL_REPLICATION(display))
+		return false;
+
+	/* Odd slice width is not supported by YCbCr420 format */
+	if (slice_width % 2 && output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		return false;
+
+	return true;
+}
+
 int intel_dsc_get_replicated_pixels(struct intel_display *display,
 				    int mode_hdisplay,
 				    int slice_count,
@@ -1057,14 +1073,10 @@ int intel_dsc_get_replicated_pixels(struct intel_display *display,
 	int replicated_pixels;
 	int slice_width = DIV_ROUND_UP(mode_hdisplay, slice_count);
 
-	if (!HAS_PIXEL_REPLICATION(display))
-		return 0;
-
-	if (mode_hdisplay % slice_count == 0)
-		return 0;
-
-	/* Odd slice width is not supported by YCbCr420 format */
-	if (slice_width % 2 && output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+	if (!intel_dsc_can_use_pixel_replication(display,
+						 mode_hdisplay,
+						 slice_count,
+						 output_format))
 		return 0;
 
 	replicated_pixels = (slice_width * slice_count) - mode_hdisplay;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 41b8b5c5866e..3611fc53840d 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -33,6 +33,9 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
 			    const struct intel_crtc_state *crtc_state);
 void intel_vdsc_state_dump(struct drm_printer *p, int indent,
 			   const struct intel_crtc_state *crtc_state);
+bool intel_dsc_can_use_pixel_replication(struct intel_display *display,
+					 int mode_hdisplay, u8 slice_count,
+					 enum intel_output_format output_format);
 int intel_dsc_get_replicated_pixels(struct intel_display *display,
 				    int mode_hdisplay,
 				    int slice_count,
-- 
2.45.2

[PATCH 14/16] drm/i915/dsc: Introduce odd pixel removal

[Ankit Nautiyal]

With 3 DSC engines we can support 12 slices. With ultra joiner
usecase while dividing the width into 12 slices, we might
end up having odd number of pixels per pipe.

As per Bspec, pipe src size should be even, so an extra pixel is added
in each pipe. For Pipe A and C the odd pixel is added at the end of
pipe and for Pipe B and D it is added at the beginning of the pipe.
This extra pixel needs to be dropped in Splitter hardware.

Introduce bits to account for odd pixel removal while programming DSS CTL.
Add a new member in crtc state to track if we need to account for the
odd pixel.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c       | 1 +
 drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
 drivers/gpu/drm/i915/display/intel_vdsc.c          | 9 +++++++++
 drivers/gpu/drm/i915/display/intel_vdsc_regs.h     | 2 ++
 4 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index de682fec45cd..ac4a5809efd6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5762,6 +5762,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_I(dsc.dsc_split);
 	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
 	PIPE_CONF_CHECK_I(dsc.replicated_pixels);
+	PIPE_CONF_CHECK_BOOL(dsc.has_odd_pixel);
 
 	PIPE_CONF_CHECK_BOOL(splitter.enable);
 	PIPE_CONF_CHECK_I(splitter.link_count);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 17554f52611c..92c362b9f63c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1235,6 +1235,7 @@ struct intel_crtc_state {
 	/* Display Stream compression state */
 	struct {
 		bool compression_enable;
+		bool has_odd_pixel;
 		int dsc_split;
 		/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
 		u16 compressed_bpp_x16;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index c279f59fdda8..d3d36cb9859c 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -806,6 +806,12 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
 			dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
 	}
 
+	if (crtc_state->dsc.has_odd_pixel) {
+		dss_ctl2_val |= ODD_PIXEL_REMOVAL;
+		if (crtc->pipe == PIPE_A || crtc->pipe == PIPE_C)
+			dss_ctl2_val |= ODD_PIXEL_REMOVAL_CONFIG_EOL;
+	}
+
 	if (crtc_state->dsc.replicated_pixels)
 		dss_ctl3_val = DSC_PIXEL_REPLICATION(crtc_state->dsc.replicated_pixels);
 
@@ -1019,6 +1025,9 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 		crtc_state->dsc.dsc_split = 0;
 	}
 
+	if (dss_ctl2 & ODD_PIXEL_REMOVAL)
+		crtc_state->dsc.has_odd_pixel = true;
+
 	if (dss_ctl3 & DSC_PIXEL_REPLICATION_MASK)
 		crtc_state->dsc.replicated_pixels =
 			dss_ctl3 & DSC_PIXEL_REPLICATION_MASK;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index f07fad6239bc..9c4cf80c2064 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -24,6 +24,8 @@
 #define  VDSC0_ENABLE				REG_BIT(31)
 #define  VDSC2_ENABLE				REG_BIT(30)
 #define  SMALL_JOINER_CONFIG_3_ENGINES		REG_BIT(23)
+#define  ODD_PIXEL_REMOVAL			REG_BIT(18)
+#define  ODD_PIXEL_REMOVAL_CONFIG_EOL		REG_BIT(17)
 #define  VDSC1_ENABLE				REG_BIT(15)
 #define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
 #define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
-- 
2.45.2

[PATCH 15/16] drm/i915/display: Adjust Pipe SRC Width for Odd Pixels

[Ankit Nautiyal]

Enhance the `intel_splitter_adjust_pipe_width` helper to account for
both pixel replication and odd pixels. When the display width is
divided among multiple pipes, extra pixels can make the pipe source
width odd. Since hardware expects an even width, an extra pixel is
added to each pipe to ensure even width.

The splitter hardware will remove these extra pixels.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ac4a5809efd6..5fe96c53d525 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2514,12 +2514,18 @@ void intel_encoder_get_config(struct intel_encoder *encoder,
 	intel_crtc_readout_derived_state(crtc_state);
 }
 
-static int intel_splitter_adjust_pipe_width(int width, int replicated_pixels)
+static int intel_splitter_adjust_pipe_width(int width, int replicated_pixels,
+					    bool has_odd_pixel, int num_pipes)
 {
-	/* Account for Pixel replication:
+	/* Account for Pixel replication + Odd pixel:
 	 * Pixel replication is required due to the rounding of slice_width (Hactive / slice_count).
 	 *
-	 * Splitter HW takes care of these by removing replicated pixels from the last pipe.
+	 * These extra pixels when added to the pipe source width, can make the pipe source width
+	 * odd. Since HW expects the pipe source width to be even, therefore one extra pixel needs
+	 * to be added to the pipe source width to make it even.
+	 *
+	 * Splitter HW takes care of these by removing odd pixel from each pipe and
+	 * replicated pixels from the last pipe.
 	 */
 
 	if (!replicated_pixels)
@@ -2527,7 +2533,11 @@ static int intel_splitter_adjust_pipe_width(int width, int replicated_pixels)
 
 	width += replicated_pixels;
 
-	return width;
+	if (!has_odd_pixel)
+		return width;
+
+	/* Account for one extra pixel for each pipe */
+	return width + num_pipes;
 }
 
 static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
@@ -2539,7 +2549,9 @@ static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
 		return;
 
 	width = intel_splitter_adjust_pipe_width(drm_rect_width(&crtc_state->pipe_src),
-						 crtc_state->dsc.replicated_pixels);
+						 crtc_state->dsc.replicated_pixels,
+						 crtc_state->dsc.has_odd_pixel,
+						 num_pipes);
 
 	height = drm_rect_height(&crtc_state->pipe_src);
 
-- 
2.45.2

[PATCH 16/16] drm/i915/dp: Add Check for Odd Pixel Requirement

[Ankit Nautiyal]

Check if Odd pixel is required during DSC compute config and update
the crtc_state to track the presence of odd pixels.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 433a629c2bae..44e7069c4d27 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2366,6 +2366,14 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 	return 0;
 }
 
+static bool intel_dp_dsc_needs_odd_pixel(int hdisplay, int replicated_pixels, int num_pipes)
+{
+	if (!replicated_pixels || num_pipes == 1)
+		return false;
+
+	return ((hdisplay + replicated_pixels) / num_pipes) % 2;
+}
+
 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 				struct intel_crtc_state *pipe_config,
 				struct drm_connector_state *conn_state,
@@ -2452,6 +2460,10 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 						adjusted_mode->crtc_hdisplay,
 						pipe_config->dsc.slice_count,
 						pipe_config->output_format);
+	pipe_config->dsc.has_odd_pixel =
+		intel_dp_dsc_needs_odd_pixel(adjusted_mode->crtc_hdisplay,
+					     pipe_config->dsc.replicated_pixels,
+					     num_joined_pipes);
 
 	/*
 	 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
-- 
2.45.2

Re: [PATCH 02/16] drm/i915/display: Prepare for dsc 3 stream splitter

[Jani Nikula]

On Mon, 21 Oct 2024, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> At the moment dsc_split represents that dsc splitter is used or not.
> With 3 DSC engines, the splitter can split into two streams or three
> streams. Make the member dsc_split as int and set that to 2 when dsc
> splitter splits to 2 stream.

Maybe also name it accordingly? "dsc split" sounds like a boolean, not
like an int.

Moreover, when you change the meaning of a member, it's often good code
hygiene to rename the member to catch any incorrect uses and to ensure
you changed them all.

>
> v2: Avoid new enum for dsc split. (Suraj)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c        |  2 +-
>  drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
>  .../drm/i915/display/intel_display_types.h    |  2 +-
>  drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
>  drivers/gpu/drm/i915/display/intel_vdsc.c     | 20 ++++++++++++++-----
>  5 files changed, 19 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 87a27d91d15d..553e75cf118c 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1595,7 +1595,7 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
>  
>  	/* FIXME: split only when necessary */
>  	if (crtc_state->dsc.slice_count > 1)
> -		crtc_state->dsc.dsc_split = true;
> +		crtc_state->dsc.dsc_split = 2;
>  
>  	/* FIXME: initialize from VBT */
>  	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ef1436146325..9e2f0fd0558f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5741,7 +5741,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
>  
>  	PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
> -	PIPE_CONF_CHECK_BOOL(dsc.dsc_split);
> +	PIPE_CONF_CHECK_I(dsc.dsc_split);
>  	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
>  
>  	PIPE_CONF_CHECK_BOOL(splitter.enable);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 2bb1fa64da2f..58f510909f4d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1235,7 +1235,7 @@ struct intel_crtc_state {
>  	/* Display Stream compression state */
>  	struct {
>  		bool compression_enable;
> -		bool dsc_split;
> +		int dsc_split;
>  		/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
>  		u16 compressed_bpp_x16;
>  		u8 slice_count;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 286b272aa98c..c1867c883b73 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2409,7 +2409,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  	 * then we need to use 2 VDSC instances.
>  	 */
>  	if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
> -		pipe_config->dsc.dsc_split = true;
> +		pipe_config->dsc.dsc_split = 2;
>  
>  	ret = intel_dp_dsc_compute_params(connector, pipe_config);
>  	if (ret < 0) {
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 40525f5c4c42..3bce13c21756 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -379,7 +379,14 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
>  
>  static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
>  {
> -	return crtc_state->dsc.dsc_split ? 2 : 1;
> +	switch (crtc_state->dsc.dsc_split) {
> +	case 2:
> +		return 2;
> +	case 0:
> +	default:
> +		break;
> +	}
> +	return 1;

Seems overly complicated.

>  }
>  
>  int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
> @@ -976,8 +983,11 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>  	if (!crtc_state->dsc.compression_enable)
>  		goto out;
>  
> -	crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
> -		(dss_ctl1 & JOINER_ENABLE);
> +	if ((dss_ctl1 & JOINER_ENABLE) &&
> +	    (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE))

The extra parens are unnecessary.

> +		crtc_state->dsc.dsc_split = 2;
> +	else
> +		crtc_state->dsc.dsc_split = 0;
>  
>  	intel_dsc_get_pps_config(crtc_state);
>  out:
> @@ -988,10 +998,10 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent,
>  				  const struct intel_crtc_state *crtc_state)
>  {
>  	drm_printf_indent(p, indent,
> -			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n",
> +			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %d\n",

So what does the reader think when they see "split: 1" in the logs?
Split enabled?

>  			  FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
>  			  crtc_state->dsc.slice_count,
> -			  str_yes_no(crtc_state->dsc.dsc_split));
> +			  crtc_state->dsc.dsc_split);
>  }
>  
>  void intel_vdsc_state_dump(struct drm_printer *p, int indent,

-- 
Jani Nikula, Intel

Re: [PATCH 08/16] drm/i915/display: Add macro HAS_PIXEL_REPLICATION

[Jani Nikula]

On Mon, 21 Oct 2024, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> Add macro for Pixel replication support with DSC.

Add blank line here.

> Bspec: 49259, 68912.
>

Remove blank line here.

> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_device.h | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 071a36b51f79..a21b910879df 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -149,6 +149,9 @@ enum intel_display_subplatform {
>  #define HAS_MBUS_JOINING(i915)		(IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
>  #define HAS_MSO(i915)			(DISPLAY_VER(i915) >= 12)
>  #define HAS_OVERLAY(i915)		(DISPLAY_INFO(i915)->has_overlay)
> +#define HAS_PIXEL_REPLICATION(i915)	(HAS_DSC(i915) && \
> +					 (DISPLAY_VER(i915) >= 20 || \
> +					  DISPLAY_VER_FULL(i915) == IP_VER(14, 1)))
>  #define HAS_PSR(i915)			(DISPLAY_INFO(i915)->has_psr)
>  #define HAS_PSR_HW_TRACKING(i915)	(DISPLAY_INFO(i915)->has_psr_hw_tracking)
>  #define HAS_PSR2_SEL_FETCH(i915)	(DISPLAY_VER(i915) >= 12)

-- 
Jani Nikula, Intel

✗ Fi.CI.CHECKPATCH: warning for Add support for 3 VDSC engines 12 slices (rev4)

[Patchwork]

== Series Details ==

Series: Add support for 3 VDSC engines 12 slices (rev4)
URL   : https://patchwork.freedesktop.org/series/139934/
State : warning

== Summary ==

Error: dim checkpatch failed
321ae3da8cc9 drm/i915/dp: Update Comment for Valid DSC Slices per Line
ad2c11146440 drm/i915/display: Prepare for dsc 3 stream splitter
6a9db221e828 drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine
37eb62f9de0d drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2
0a32f374ba17 drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine
42113ffedb7f drm/i915/dp: Ensure hactive is divisible by slice count
2e438d2aa0d6 drm/i915/dp: Enable 3 DSC engines for 12 slices
c74837cd7e1b drm/i915/display: Add macro HAS_PIXEL_REPLICATION
-:19: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#19: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:152:
+#define HAS_PIXEL_REPLICATION(i915)	(HAS_DSC(i915) && \
+					 (DISPLAY_VER(i915) >= 20 || \
+					  DISPLAY_VER_FULL(i915) == IP_VER(14, 1)))

total: 0 errors, 0 warnings, 1 checks, 9 lines checked
eeff3b7f25a7 drm/i915/display: Add support for DSC pixel replication
-:139: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#139: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:59:
+#define  DSC_PIXEL_REPLICATION(count)		(REG_FIELD_PREP(DSC_PIXEL_REPLICATION_MASK, (count)))

total: 0 errors, 1 warnings, 0 checks, 99 lines checked
e3fe2ce6ff54 drm/i915/dp_mst: Account for pixel replication for MST overhead with DSC
70305f1dd965 drm/i915/dp: Account for pixel replication for BW computation with DSC
ce3f7ebc2c7a drm/i915/display: Account for pixel replication in pipe_src
90f48fd82de0 drm/i915/dp: Enable DSC pixel replication
c77b8b4f56c6 drm/i915/dsc: Introduce odd pixel removal
3f3cfc7e0812 drm/i915/display: Adjust Pipe SRC Width for Odd Pixels
e580a07626f6 drm/i915/dp: Add Check for Odd Pixel Requirement

✗ Fi.CI.SPARSE: warning for Add support for 3 VDSC engines 12 slices (rev4)

[Patchwork]

== Series Details ==

Series: Add support for 3 VDSC engines 12 slices (rev4)
URL   : https://patchwork.freedesktop.org/series/139934/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✓ Fi.CI.BAT: success for Add support for 3 VDSC engines 12 slices (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 7620 bytes --]

== Series Details ==

Series: Add support for 3 VDSC engines 12 slices (rev4)
URL   : https://patchwork.freedesktop.org/series/139934/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_15571 -> Patchwork_139934v4
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/index.html

Participating hosts (45 -> 42)
------------------------------

  Missing    (3): bat-kbl-2 fi-snb-2520m fi-tgl-1115g4 

Known issues
------------

  Here are the changes found in Patchwork_139934v4 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@load:
    - bat-dg2-9:          [PASS][1] -> [DMESG-WARN][2] ([i915#11548])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/bat-dg2-9/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/bat-dg2-9/igt@i915_module_load@load.html

  * igt@i915_selftest@live:
    - bat-arlh-2:         [PASS][3] -> [DMESG-FAIL][4] ([i915#10341] / [i915#9500])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/bat-arlh-2/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/bat-arlh-2/igt@i915_selftest@live.html

  * igt@i915_selftest@live@gt_mocs:
    - bat-arlh-2:         [PASS][5] -> [DMESG-FAIL][6] ([i915#9500])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/bat-arlh-2/igt@i915_selftest@live@gt_mocs.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/bat-arlh-2/igt@i915_selftest@live@gt_mocs.html

  
#### Possible fixes ####

  * igt@i915_selftest@live:
    - bat-dg2-11:         [ABORT][7] ([i915#12133]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/bat-dg2-11/igt@i915_selftest@live.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/bat-dg2-11/igt@i915_selftest@live.html

  * igt@i915_selftest@live@uncore:
    - bat-dg2-11:         [ABORT][9] ([i915#12305]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/bat-dg2-11/igt@i915_selftest@live@uncore.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/bat-dg2-11/igt@i915_selftest@live@uncore.html

  
#### Warnings ####

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-dg2-9:          [SKIP][11] ([i915#5190]) -> [SKIP][12] ([i915#4212] / [i915#5190])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
    - bat-mtlp-6:         [SKIP][13] ([i915#5190] / [i915#9792]) -> [SKIP][14] ([i915#4212] / [i915#5190] / [i915#9792])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
    - bat-dg2-11:         [SKIP][15] ([i915#5190]) -> [SKIP][16] ([i915#4212] / [i915#5190])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/bat-dg2-11/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/bat-dg2-11/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
    - bat-dg2-14:         [SKIP][17] ([i915#5190]) -> [SKIP][18] ([i915#4212] / [i915#5190])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/bat-dg2-14/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/bat-dg2-14/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
    - bat-mtlp-8:         [SKIP][19] ([i915#5190]) -> [SKIP][20] ([i915#4212] / [i915#5190])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
    - bat-dg2-8:          [SKIP][21] ([i915#5190]) -> [SKIP][22] ([i915#4212] / [i915#5190])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-dg2-8:          [SKIP][23] ([i915#4215] / [i915#5190]) -> [SKIP][24] ([i915#4212] / [i915#4215] / [i915#5190])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
    - bat-dg1-7:          [SKIP][25] ([i915#4215]) -> [SKIP][26] ([i915#4212] / [i915#4215])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/bat-dg1-7/igt@kms_addfb_basic@basic-y-tiled-legacy.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/bat-dg1-7/igt@kms_addfb_basic@basic-y-tiled-legacy.html
    - bat-dg2-9:          [SKIP][27] ([i915#4215] / [i915#5190]) -> [SKIP][28] ([i915#4212] / [i915#4215] / [i915#5190])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html
    - bat-dg2-11:         [SKIP][29] ([i915#4215] / [i915#5190]) -> [SKIP][30] ([i915#4212] / [i915#4215] / [i915#5190])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/bat-dg2-11/igt@kms_addfb_basic@basic-y-tiled-legacy.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/bat-dg2-11/igt@kms_addfb_basic@basic-y-tiled-legacy.html
    - bat-dg2-14:         [SKIP][31] ([i915#4215] / [i915#5190]) -> [SKIP][32] ([i915#4212] / [i915#4215] / [i915#5190])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/bat-dg2-14/igt@kms_addfb_basic@basic-y-tiled-legacy.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/bat-dg2-14/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  
  [i915#10341]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10341
  [i915#11548]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11548
  [i915#12133]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12133
  [i915#12305]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12305
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4215]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4215
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#9500]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9500
  [i915#9792]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9792


Build changes
-------------

  * Linux: CI_DRM_15571 -> Patchwork_139934v4

  CI-20190529: 20190529
  CI_DRM_15571: 784111a40e40a37100e61736dd137c72cedbdb39 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8080: 20fcbc59241a16c84d12f4f6ba390fb46fd65a36 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_139934v4: 784111a40e40a37100e61736dd137c72cedbdb39 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/index.html

[-- Attachment #2: Type: text/html, Size: 11337 bytes --]

✗ Fi.CI.IGT: failure for Add support for 3 VDSC engines 12 slices (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 61674 bytes --]

== Series Details ==

Series: Add support for 3 VDSC engines 12 slices (rev4)
URL   : https://patchwork.freedesktop.org/series/139934/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_15571_full -> Patchwork_139934v4_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_139934v4_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_139934v4_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/index.html

Participating hosts (7 -> 8)
------------------------------

  Additional (1): shard-dg2-set2 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_139934v4_full:

### IGT changes ###

#### Possible regressions ####

  * igt@perf_pmu@multi-client:
    - shard-mtlp:         [PASS][1] -> [FAIL][2] +1 other test fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-mtlp-8/igt@perf_pmu@multi-client.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-mtlp-6/igt@perf_pmu@multi-client.html

  
Known issues
------------

  Here are the changes found in Patchwork_139934v4_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@drm_read@empty-block:
    - shard-dg1:          [PASS][3] -> [DMESG-WARN][4] ([i915#4423])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg1-12/igt@drm_read@empty-block.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-18/igt@drm_read@empty-block.html

  * igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-lmem0-lmem0:
    - shard-dg2:          NOTRUN -> [INCOMPLETE][5] ([i915#12392] / [i915#7297])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-5/igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-lmem0-lmem0.html

  * igt@gem_exec_balancer@nop:
    - shard-mtlp:         [PASS][6] -> [DMESG-WARN][7] ([i915#12412])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-mtlp-1/igt@gem_exec_balancer@nop.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-mtlp-4/igt@gem_exec_balancer@nop.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-rkl:          [PASS][8] -> [FAIL][9] ([i915#2846])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-rkl-4/igt@gem_exec_fair@basic-deadline.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-rkl-1/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share:
    - shard-rkl:          [PASS][10] -> [FAIL][11] ([i915#2842]) +1 other test fail
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-rkl-2/igt@gem_exec_fair@basic-none-share.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-rkl-5/igt@gem_exec_fair@basic-none-share.html

  * igt@gem_exec_reloc@basic-wc-read:
    - shard-dg2:          NOTRUN -> [SKIP][12] ([i915#3281])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-10/igt@gem_exec_reloc@basic-wc-read.html

  * igt@gem_fenced_exec_thrash@no-spare-fences:
    - shard-dg2:          NOTRUN -> [SKIP][13] ([i915#4860])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-10/igt@gem_fenced_exec_thrash@no-spare-fences.html

  * igt@gem_madvise@dontneed-before-exec:
    - shard-dg2:          NOTRUN -> [SKIP][14] ([i915#3282])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@gem_madvise@dontneed-before-exec.html

  * igt@gem_mmap_gtt@basic-small-copy-odd:
    - shard-dg2:          NOTRUN -> [SKIP][15] ([i915#4077])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@gem_mmap_gtt@basic-small-copy-odd.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][16] ([i915#5190] / [i915#8428])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-5/igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs.html

  * igt@gen9_exec_parse@bb-large:
    - shard-dg2:          NOTRUN -> [SKIP][17] ([i915#2856])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@gen9_exec_parse@bb-large.html

  * igt@gen9_exec_parse@secure-batches:
    - shard-mtlp:         NOTRUN -> [SKIP][18] ([i915#2856])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-mtlp-2/igt@gen9_exec_parse@secure-batches.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-rkl:          [PASS][19] -> [ABORT][20] ([i915#9820])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-rkl-1/igt@i915_module_load@reload-with-fault-injection.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-rkl-3/igt@i915_module_load@reload-with-fault-injection.html
    - shard-mtlp:         [PASS][21] -> [ABORT][22] ([i915#10131] / [i915#9820])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-mtlp-3/igt@i915_module_load@reload-with-fault-injection.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-mtlp-1/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
    - shard-dg1:          [PASS][23] -> [FAIL][24] ([i915#3591])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html

  * igt@i915_pm_rps@min-max-config-loaded:
    - shard-dg1:          NOTRUN -> [SKIP][25] ([i915#11681] / [i915#6621])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-15/igt@i915_pm_rps@min-max-config-loaded.html

  * igt@i915_pm_rps@reset:
    - shard-dg2:          NOTRUN -> [FAIL][26] ([i915#12459])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@i915_pm_rps@reset.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-rkl:          [PASS][27] -> [INCOMPLETE][28] ([i915#4817])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-rkl-5/igt@i915_suspend@basic-s3-without-i915.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-rkl-3/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][29] ([i915#8709]) +7 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-13/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc:
    - shard-rkl:          NOTRUN -> [SKIP][30] ([i915#8709]) +3 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-rkl-5/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc.html

  * igt@kms_atomic_transition@plane-all-transition:
    - shard-dg2:          NOTRUN -> [SKIP][31] ([i915#9197]) +5 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_atomic_transition@plane-all-transition.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-dg1:          NOTRUN -> [SKIP][32] ([i915#4538] / [i915#5286])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-14/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-dg1:          NOTRUN -> [SKIP][33] ([i915#3638])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-15/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-dg2:          NOTRUN -> [SKIP][34] ([i915#4538] / [i915#5190])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
    - shard-snb:          NOTRUN -> [SKIP][35] +7 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-snb7/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html
    - shard-tglu:         NOTRUN -> [SKIP][36] +2 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-tglu-10/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-dg2:          NOTRUN -> [SKIP][37] ([i915#5190] / [i915#9197]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_busy@extended-modeset-hang-oldfb:
    - shard-dg2:          [PASS][38] -> [SKIP][39] ([i915#9197]) +9 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-6/igt@kms_busy@extended-modeset-hang-oldfb.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_busy@extended-modeset-hang-oldfb.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][40] ([i915#6095]) +43 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-rkl-2/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][41] ([i915#6095]) +135 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-16/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4.html

  * igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][42] ([i915#6095]) +9 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-mtlp-2/igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][43] ([i915#10307] / [i915#6095]) +160 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][44] ([i915#6095]) +4 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-tglu-10/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][45] ([i915#10307] / [i915#10434] / [i915#6095]) +2 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [SKIP][46] +48 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-glk1/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][47] ([i915#4087]) +3 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-1/igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3.html

  * igt@kms_chamelium_hpd@hdmi-hpd-fast:
    - shard-dg1:          NOTRUN -> [SKIP][48] ([i915#7828])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-14/igt@kms_chamelium_hpd@hdmi-hpd-fast.html

  * igt@kms_cursor_crc@cursor-offscreen-32x10:
    - shard-mtlp:         NOTRUN -> [SKIP][49] ([i915#3555] / [i915#8814])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-mtlp-8/igt@kms_cursor_crc@cursor-offscreen-32x10.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-dg1:          NOTRUN -> [SKIP][50] ([i915#11453] / [i915#3359])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-14/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          [PASS][51] -> [FAIL][52] ([i915#2346])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
    - shard-snb:          [PASS][53] -> [FAIL][54] ([i915#2346])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-snb2/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-snb1/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html

  * igt@kms_feature_discovery@display-4x:
    - shard-mtlp:         NOTRUN -> [SKIP][55] ([i915#1839])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-mtlp-2/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-glk:          [PASS][56] -> [FAIL][57] ([i915#2122]) +1 other test fail
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-glk4/igt@kms_flip@2x-plain-flip-fb-recreate.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-glk2/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@flip-vs-rmfb-interruptible:
    - shard-dg2:          [PASS][58] -> [SKIP][59] ([i915#5354]) +3 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-6/igt@kms_flip@flip-vs-rmfb-interruptible.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_flip@flip-vs-rmfb-interruptible.html

  * igt@kms_flip@flip-vs-wf_vblank-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][60] ([i915#5354]) +13 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_flip@flip-vs-wf_vblank-interruptible.html

  * igt@kms_flip@plain-flip-ts-check-interruptible:
    - shard-tglu:         NOTRUN -> [FAIL][61] ([i915#2122]) +4 other tests fail
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-tglu-10/igt@kms_flip@plain-flip-ts-check-interruptible.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
    - shard-mtlp:         NOTRUN -> [FAIL][62] ([i915#2122])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-mtlp-8/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling:
    - shard-dg2:          [PASS][63] -> [SKIP][64] ([i915#3555]) +1 other test skip
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-6/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-dg2:          NOTRUN -> [SKIP][65] ([i915#2672] / [i915#3555] / [i915#5190])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][66] ([i915#2672]) +1 other test skip
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling:
    - shard-dg2:          NOTRUN -> [SKIP][67] ([i915#3555])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-dg1:          NOTRUN -> [INCOMPLETE][68] ([i915#2295])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-13/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite:
    - shard-dg1:          NOTRUN -> [SKIP][69] +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][70] ([i915#8708])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][71] ([i915#8708]) +2 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-15/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-dg1:          NOTRUN -> [SKIP][72] ([i915#3458])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-dg2:          [PASS][73] -> [SKIP][74] ([i915#3555] / [i915#8228])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-10/igt@kms_hdr@static-toggle-dpms.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-6/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_plane_alpha_blend@alpha-basic:
    - shard-dg2:          [PASS][75] -> [SKIP][76] ([i915#7294])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-6/igt@kms_plane_alpha_blend@alpha-basic.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_plane_alpha_blend@alpha-basic.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [FAIL][77] ([i915#8292])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-12/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers:
    - shard-dg2:          NOTRUN -> [SKIP][78] ([i915#12247] / [i915#8152] / [i915#9423])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b:
    - shard-dg2:          NOTRUN -> [SKIP][79] ([i915#12247]) +2 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-d:
    - shard-dg2:          NOTRUN -> [SKIP][80] ([i915#12247] / [i915#8152])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-d.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats:
    - shard-dg2:          [PASS][81] -> [SKIP][82] ([i915#3555] / [i915#8152] / [i915#9423])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-10/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-d:
    - shard-dg2:          [PASS][83] -> [SKIP][84] ([i915#8152])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-10/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-d.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-d.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5:
    - shard-dg2:          [PASS][85] -> [SKIP][86] ([i915#12247] / [i915#6953] / [i915#8152] / [i915#9423])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a:
    - shard-dg2:          [PASS][87] -> [SKIP][88] ([i915#12247]) +5 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-d:
    - shard-dg2:          [PASS][89] -> [SKIP][90] ([i915#12247] / [i915#8152])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-d.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-d.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-dg2:          NOTRUN -> [SKIP][91] ([i915#9685])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-10/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-dg2:          [PASS][92] -> [SKIP][93] ([i915#9519])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-3/igt@kms_pm_rpm@dpms-non-lpsp.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-4/igt@kms_pm_rpm@dpms-non-lpsp.html
    - shard-rkl:          [PASS][94] -> [SKIP][95] ([i915#9519]) +1 other test skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-rkl-3/igt@kms_pm_rpm@dpms-non-lpsp.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-rkl-7/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_properties@plane-properties-legacy:
    - shard-dg2:          NOTRUN -> [SKIP][96] ([i915#11521])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_properties@plane-properties-legacy.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-dg1:          NOTRUN -> [SKIP][97] ([i915#11520])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-15/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
    - shard-dg2:          NOTRUN -> [SKIP][98] ([i915#11520])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][99] ([i915#11520])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-glk1/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-dg2:          NOTRUN -> [SKIP][100] ([i915#9683]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-pr-cursor-render:
    - shard-mtlp:         NOTRUN -> [SKIP][101] ([i915#9688])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-mtlp-2/igt@kms_psr@fbc-pr-cursor-render.html

  * igt@kms_psr@pr-no-drrs:
    - shard-dg1:          NOTRUN -> [SKIP][102] ([i915#1072] / [i915#9732])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-15/igt@kms_psr@pr-no-drrs.html

  * igt@kms_psr@psr2-primary-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][103] ([i915#1072] / [i915#9732]) +3 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_psr@psr2-primary-mmap-gtt.html

  * igt@prime_vgem@basic-fence-read:
    - shard-dg2:          NOTRUN -> [SKIP][104] ([i915#3291] / [i915#3708])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@prime_vgem@basic-fence-read.html

  * igt@syncobj_wait@invalid-wait-zero-handles:
    - shard-glk:          NOTRUN -> [FAIL][105] ([i915#9781])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-glk1/igt@syncobj_wait@invalid-wait-zero-handles.html

  
#### Possible fixes ####

  * igt@gem_barrier_race@remote-request:
    - shard-glk:          [ABORT][106] -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-glk1/igt@gem_barrier_race@remote-request.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-glk1/igt@gem_barrier_race@remote-request.html

  * igt@gem_barrier_race@remote-request@rcs0:
    - shard-glk:          [ABORT][108] ([i915#8190]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-glk1/igt@gem_barrier_race@remote-request@rcs0.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-glk1/igt@gem_barrier_race@remote-request@rcs0.html

  * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0:
    - shard-dg2:          [INCOMPLETE][110] ([i915#12392] / [i915#7297]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-7/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-5/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-rkl:          [FAIL][112] ([i915#2842]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-rkl-5/igt@gem_exec_fair@basic-pace@rcs0.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-rkl-2/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
    - shard-dg1:          [FAIL][114] ([i915#3591]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html

  * igt@i915_pm_rps@engine-order:
    - shard-glk:          [FAIL][116] ([i915#12308]) -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-glk5/igt@i915_pm_rps@engine-order.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-glk8/igt@i915_pm_rps@engine-order.html

  * igt@i915_power@sanity:
    - shard-mtlp:         [SKIP][118] ([i915#7984]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-mtlp-5/igt@i915_power@sanity.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-mtlp-3/igt@i915_power@sanity.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking:
    - shard-glk:          [FAIL][120] ([i915#12177]) -> [PASS][121]
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-glk2/igt@kms_atomic_transition@modeset-transition-nonblocking.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs:
    - shard-glk:          [FAIL][122] ([i915#11859]) -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-glk2/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-4:
    - shard-dg1:          [FAIL][124] ([i915#5956]) -> [PASS][125] +1 other test pass
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg1-14/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-4.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-19/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-4.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-180:
    - shard-dg2:          [SKIP][126] ([i915#9197]) -> [PASS][127] +24 other tests pass
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-3/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html

  * igt@kms_cursor_crc@cursor-suspend:
    - shard-mtlp:         [INCOMPLETE][128] ([i915#12358]) -> [PASS][129] +1 other test pass
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-mtlp-4/igt@kms_cursor_crc@cursor-suspend.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-mtlp-8/igt@kms_cursor_crc@cursor-suspend.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][130] ([i915#2122]) -> [PASS][131] +4 other tests pass
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-glk6/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-glk3/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@blocking-wf_vblank:
    - shard-rkl:          [FAIL][132] ([i915#11961] / [i915#2122]) -> [PASS][133]
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-rkl-4/igt@kms_flip@blocking-wf_vblank.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-rkl-7/igt@kms_flip@blocking-wf_vblank.html

  * igt@kms_flip@blocking-wf_vblank@b-hdmi-a1:
    - shard-rkl:          [FAIL][134] ([i915#2122]) -> [PASS][135] +1 other test pass
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-rkl-4/igt@kms_flip@blocking-wf_vblank@b-hdmi-a1.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-rkl-7/igt@kms_flip@blocking-wf_vblank@b-hdmi-a1.html

  * igt@kms_flip@blocking-wf_vblank@c-hdmi-a1:
    - shard-tglu:         [FAIL][136] ([i915#2122]) -> [PASS][137] +1 other test pass
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-tglu-2/igt@kms_flip@blocking-wf_vblank@c-hdmi-a1.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-tglu-4/igt@kms_flip@blocking-wf_vblank@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-dg1:          [DMESG-WARN][138] ([i915#4423]) -> [PASS][139] +2 other tests pass
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg1-15/igt@kms_flip@flip-vs-suspend.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-12/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a1:
    - shard-snb:          [INCOMPLETE][140] -> [PASS][141]
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-snb5/igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a1.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-snb7/igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@b-vga1:
    - shard-snb:          [FAIL][142] ([i915#2122]) -> [PASS][143]
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-snb5/igt@kms_flip@plain-flip-ts-check-interruptible@b-vga1.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-snb7/igt@kms_flip@plain-flip-ts-check-interruptible@b-vga1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
    - shard-dg2:          [SKIP][144] ([i915#3555]) -> [PASS][145] +1 other test pass
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
    - shard-dg2:          [SKIP][146] ([i915#5354]) -> [PASS][147] +8 other tests pass
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-dg2:          [SKIP][148] ([i915#3555] / [i915#8228]) -> [PASS][149]
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-5/igt@kms_hdr@static-toggle-suspend.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-10/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_plane_scaling@invalid-parameters:
    - shard-dg2:          [SKIP][150] ([i915#8152] / [i915#9423]) -> [PASS][151]
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_plane_scaling@invalid-parameters.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_plane_scaling@invalid-parameters.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5:
    - shard-dg2:          [SKIP][152] ([i915#12247] / [i915#3555] / [i915#6953] / [i915#8152] / [i915#9423]) -> [PASS][153]
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a:
    - shard-dg2:          [SKIP][154] ([i915#12247]) -> [PASS][155] +2 other tests pass
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-d:
    - shard-dg2:          [SKIP][156] ([i915#12247] / [i915#8152]) -> [PASS][157]
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-d.html
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-d.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu:         [SKIP][158] ([i915#4281]) -> [PASS][159]
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-tglu-8/igt@kms_pm_dc@dc9-dpms.html
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-tglu-2/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          [SKIP][160] ([i915#9519]) -> [PASS][161] +1 other test pass
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-rkl-2/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_sysfs_edid_timing:
    - shard-dg2:          [FAIL][162] ([IGT#2]) -> [PASS][163]
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-1/igt@kms_sysfs_edid_timing.html
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-10/igt@kms_sysfs_edid_timing.html

  * igt@kms_universal_plane@cursor-fb-leak:
    - shard-mtlp:         [FAIL][164] ([i915#9196]) -> [PASS][165] +1 other test pass
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-mtlp-7/igt@kms_universal_plane@cursor-fb-leak.html
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-mtlp-2/igt@kms_universal_plane@cursor-fb-leak.html

  
#### Warnings ####

  * igt@gem_ctx_engines@invalid-engines:
    - shard-rkl:          [FAIL][166] ([i915#12027] / [i915#12031]) -> [FAIL][167] ([i915#12031] / [i915#12065])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-rkl-5/igt@gem_ctx_engines@invalid-engines.html
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-rkl-1/igt@gem_ctx_engines@invalid-engines.html

  * igt@i915_selftest@mock:
    - shard-glk:          [DMESG-WARN][168] ([i915#9311]) -> [DMESG-WARN][169] ([i915#1982] / [i915#9311])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-glk5/igt@i915_selftest@mock.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-glk8/igt@i915_selftest@mock.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-dg2:          [SKIP][170] ([i915#9197]) -> [SKIP][171] ([i915#9531])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-3/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-dg2:          [SKIP][172] -> [SKIP][173] ([i915#9197]) +1 other test skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-6/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-dg2:          [SKIP][174] ([i915#9197]) -> [SKIP][175] +1 other test skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_big_fb@linear-16bpp-rotate-90.html
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-90:
    - shard-dg2:          [SKIP][176] ([i915#4538] / [i915#5190]) -> [SKIP][177] ([i915#5190] / [i915#9197]) +1 other test skip
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-6/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-dg2:          [SKIP][178] ([i915#5190] / [i915#9197]) -> [SKIP][179] ([i915#4538] / [i915#5190]) +6 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs:
    - shard-dg2:          [SKIP][180] ([i915#9197]) -> [SKIP][181] ([i915#10307] / [i915#6095]) +4 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs.html
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-3/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc:
    - shard-dg2:          [SKIP][182] ([i915#10307] / [i915#6095]) -> [SKIP][183] ([i915#9197]) +2 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-6/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc.html
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_content_protection@atomic:
    - shard-dg2:          [SKIP][184] ([i915#9197]) -> [SKIP][185] ([i915#7118] / [i915#9424])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_content_protection@atomic.html
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_content_protection@atomic.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-dg2:          [SKIP][186] ([i915#11453] / [i915#3359]) -> [SKIP][187] ([i915#9197])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-6/igt@kms_cursor_crc@cursor-offscreen-512x170.html
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-dg2:          [SKIP][188] ([i915#9197]) -> [SKIP][189] ([i915#11453] / [i915#3359])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_cursor_crc@cursor-random-512x512.html
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-3/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
    - shard-dg2:          [SKIP][190] ([i915#9197]) -> [SKIP][191] ([i915#3555]) +1 other test skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_cursor_crc@cursor-sliding-32x10.html
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_cursor_crc@cursor-sliding-32x10.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-dg2:          [SKIP][192] ([i915#9197]) -> [SKIP][193] ([i915#5354]) +1 other test skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
    - shard-dg2:          [SKIP][194] ([i915#9197]) -> [SKIP][195] ([i915#9067])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-dg2:          [SKIP][196] ([i915#9197]) -> [SKIP][197] ([i915#4103] / [i915#4213])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-dg2:          [SKIP][198] ([i915#9197]) -> [SKIP][199] ([i915#3555] / [i915#3840])
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_dsc@dsc-with-bpc-formats.html
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_flip@2x-flip-vs-wf_vblank:
    - shard-dg1:          [SKIP][200] ([i915#9934]) -> [SKIP][201] ([i915#4423] / [i915#9934])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg1-12/igt@kms_flip@2x-flip-vs-wf_vblank.html
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-18/igt@kms_flip@2x-flip-vs-wf_vblank.html

  * igt@kms_flip@plain-flip-ts-check-interruptible:
    - shard-snb:          [INCOMPLETE][202] -> [FAIL][203] ([i915#2122])
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-snb5/igt@kms_flip@plain-flip-ts-check-interruptible.html
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-snb7/igt@kms_flip@plain-flip-ts-check-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
    - shard-dg2:          [SKIP][204] ([i915#3555]) -> [SKIP][205] ([i915#2672] / [i915#3555])
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
    - shard-dg2:          [SKIP][206] ([i915#10433] / [i915#3458]) -> [SKIP][207] ([i915#3458]) +1 other test skip
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
    - shard-dg2:          [SKIP][208] ([i915#3458]) -> [SKIP][209] ([i915#5354]) +1 other test skip
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
    - shard-dg1:          [SKIP][210] ([i915#4423]) -> [SKIP][211]
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-12/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt:
    - shard-dg2:          [SKIP][212] ([i915#5354]) -> [SKIP][213] ([i915#8708]) +6 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
    - shard-dg2:          [SKIP][214] ([i915#3458]) -> [SKIP][215] ([i915#10433] / [i915#3458]) +1 other test skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
    - shard-dg2:          [SKIP][216] ([i915#5354]) -> [SKIP][217] ([i915#3458]) +8 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt:
    - shard-dg2:          [SKIP][218] ([i915#8708]) -> [SKIP][219] ([i915#5354]) +3 other tests skip
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt.html
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt:
    - shard-dg1:          [SKIP][220] ([i915#3458]) -> [SKIP][221] ([i915#3458] / [i915#4423])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt.html
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-19/igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-dg2:          [SKIP][222] ([i915#9197]) -> [SKIP][223] ([i915#3555] / [i915#8228])
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_hdr@bpc-switch-dpms.html
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@static-toggle:
    - shard-dg1:          [SKIP][224] ([i915#3555] / [i915#8228]) -> [SKIP][225] ([i915#3555] / [i915#4423] / [i915#8228])
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg1-13/igt@kms_hdr@static-toggle.html
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-16/igt@kms_hdr@static-toggle.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-dg2:          [SKIP][226] ([i915#9197]) -> [SKIP][227] ([i915#6301])
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_panel_fitting@atomic-fastset.html
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-3/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-dg2:          [SKIP][228] ([i915#9197]) -> [SKIP][229] ([i915#3555] / [i915#8821])
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_plane_lowres@tiling-yf.html
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-3/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
    - shard-dg2:          [SKIP][230] ([i915#12247] / [i915#6953] / [i915#8152] / [i915#9423]) -> [SKIP][231] ([i915#12247] / [i915#6953] / [i915#9423])
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-3/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d:
    - shard-dg2:          [SKIP][232] ([i915#12247] / [i915#8152]) -> [SKIP][233] ([i915#12247])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d.html
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-3/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf:
    - shard-dg1:          [SKIP][234] ([i915#11520]) -> [SKIP][235] ([i915#11520] / [i915#4423])
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg1-17/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf.html
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-19/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@pr-basic:
    - shard-dg1:          [SKIP][236] ([i915#1072] / [i915#9732]) -> [SKIP][237] ([i915#1072] / [i915#4423] / [i915#9732])
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg1-12/igt@kms_psr@pr-basic.html
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg1-18/igt@kms_psr@pr-basic.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-dg2:          [SKIP][238] ([i915#9197]) -> [SKIP][239] ([i915#11131] / [i915#4235])
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_rotation_crc@bad-pixel-format.html
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-3/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-dg2:          [SKIP][240] ([i915#5190] / [i915#9197]) -> [SKIP][241] ([i915#11131] / [i915#4235] / [i915#5190])
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-dg2-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-dg2-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-glk:          [FAIL][242] ([i915#10959]) -> [SKIP][243]
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15571/shard-glk5/igt@kms_tiled_display@basic-test-pattern.html
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/shard-glk8/igt@kms_tiled_display@basic-test-pattern.html

  
  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#10959]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10959
  [i915#11131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11131
  [i915#11453]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11453
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11521]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11521
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#11859]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11859
  [i915#11961]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11961
  [i915#12027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12027
  [i915#12031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12031
  [i915#12065]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12065
  [i915#12177]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12177
  [i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
  [i915#12308]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12308
  [i915#12358]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12358
  [i915#12392]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12392
  [i915#12412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12412
  [i915#12459]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12459
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
  [i915#2295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2295
  [i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2846
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
  [i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7294]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7294
  [i915#7297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7297
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8152
  [i915#8190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8190
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
  [i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
  [i915#8821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8821
  [i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
  [i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
  [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197
  [i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
  [i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9781
  [i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_15571 -> Patchwork_139934v4
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_15571: 784111a40e40a37100e61736dd137c72cedbdb39 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8080: 20fcbc59241a16c84d12f4f6ba390fb46fd65a36 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_139934v4: 784111a40e40a37100e61736dd137c72cedbdb39 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139934v4/index.html

[-- Attachment #2: Type: text/html, Size: 77680 bytes --]

Re: [PATCH 02/16] drm/i915/display: Prepare for dsc 3 stream splitter

[Nautiyal, Ankit K]

On 10/21/2024 6:16 PM, Jani Nikula wrote:
> On Mon, 21 Oct 2024, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> At the moment dsc_split represents that dsc splitter is used or not.
>> With 3 DSC engines, the splitter can split into two streams or three
>> streams. Make the member dsc_split as int and set that to 2 when dsc
>> splitter splits to 2 stream.
> Maybe also name it accordingly? "dsc split" sounds like a boolean, not
> like an int.
>
> Moreover, when you change the meaning of a member, it's often good code
> hygiene to rename the member to catch any incorrect uses and to ensure
> you changed them all.

Noted. Will change the name accordingly.

>
>> v2: Avoid new enum for dsc split. (Suraj)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/icl_dsi.c        |  2 +-
>>   drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
>>   .../drm/i915/display/intel_display_types.h    |  2 +-
>>   drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
>>   drivers/gpu/drm/i915/display/intel_vdsc.c     | 20 ++++++++++++++-----
>>   5 files changed, 19 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
>> index 87a27d91d15d..553e75cf118c 100644
>> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> @@ -1595,7 +1595,7 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
>>   
>>   	/* FIXME: split only when necessary */
>>   	if (crtc_state->dsc.slice_count > 1)
>> -		crtc_state->dsc.dsc_split = true;
>> +		crtc_state->dsc.dsc_split = 2;
>>   
>>   	/* FIXME: initialize from VBT */
>>   	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index ef1436146325..9e2f0fd0558f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -5741,7 +5741,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>>   	PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
>>   
>>   	PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
>> -	PIPE_CONF_CHECK_BOOL(dsc.dsc_split);
>> +	PIPE_CONF_CHECK_I(dsc.dsc_split);
>>   	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
>>   
>>   	PIPE_CONF_CHECK_BOOL(splitter.enable);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 2bb1fa64da2f..58f510909f4d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1235,7 +1235,7 @@ struct intel_crtc_state {
>>   	/* Display Stream compression state */
>>   	struct {
>>   		bool compression_enable;
>> -		bool dsc_split;
>> +		int dsc_split;
>>   		/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
>>   		u16 compressed_bpp_x16;
>>   		u8 slice_count;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 286b272aa98c..c1867c883b73 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -2409,7 +2409,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>>   	 * then we need to use 2 VDSC instances.
>>   	 */
>>   	if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
>> -		pipe_config->dsc.dsc_split = true;
>> +		pipe_config->dsc.dsc_split = 2;
>>   
>>   	ret = intel_dp_dsc_compute_params(connector, pipe_config);
>>   	if (ret < 0) {
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index 40525f5c4c42..3bce13c21756 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -379,7 +379,14 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
>>   
>>   static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
>>   {
>> -	return crtc_state->dsc.dsc_split ? 2 : 1;
>> +	switch (crtc_state->dsc.dsc_split) {
>> +	case 2:
>> +		return 2;
>> +	case 0:
>> +	default:
>> +		break;
>> +	}
>> +	return 1;
> Seems overly complicated.
>
>>   }
>>   
>>   int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
>> @@ -976,8 +983,11 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>>   	if (!crtc_state->dsc.compression_enable)
>>   		goto out;
>>   
>> -	crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
>> -		(dss_ctl1 & JOINER_ENABLE);
>> +	if ((dss_ctl1 & JOINER_ENABLE) &&
>> +	    (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE))
> The extra parens are unnecessary.
>
>> +		crtc_state->dsc.dsc_split = 2;
>> +	else
>> +		crtc_state->dsc.dsc_split = 0;
>>   
>>   	intel_dsc_get_pps_config(crtc_state);
>>   out:
>> @@ -988,10 +998,10 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent,
>>   				  const struct intel_crtc_state *crtc_state)
>>   {
>>   	drm_printf_indent(p, indent,
>> -			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n",
>> +			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %d\n",
> So what does the reader think when they see "split: 1" in the logs?
> Split enabled?

I was meaning to capture the DSC split state as originally intended, and 
extend it to have splitting to 3, 2, or None.

With that we can never have split: 1, but can have either 3, 2, or 0.

I realize, split:0 is a bit ambiguous, so I am thinking about:

-change the dsc_split to dsc_streams: to capture number of DSC streams 
per pipe, instead of DSC splitter operation.

-dsc_streams can be 1, 2 and extended to 3.

-Splitter state will then be implicit, 1 DSC Stream => No Splitter, 2 
DSC Streams => Splitter used to split 2 DSC streams and so on.

With that, deriving number of DSC engine will also be straight forward 
(avoiding the switch case above).


Thanks & Regards,

Ankit



>
>>   			  FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
>>   			  crtc_state->dsc.slice_count,
>> -			  str_yes_no(crtc_state->dsc.dsc_split));
>> +			  crtc_state->dsc.dsc_split);
>>   }
>>   
>>   void intel_vdsc_state_dump(struct drm_printer *p, int indent,

Re: [PATCH 08/16] drm/i915/display: Add macro HAS_PIXEL_REPLICATION

[Nautiyal, Ankit K]

On 10/21/2024 6:19 PM, Jani Nikula wrote:
> On Mon, 21 Oct 2024, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> Add macro for Pixel replication support with DSC.
> Add blank line here.
>
>> Bspec: 49259, 68912.
>>
> Remove blank line here.

Noted will have Bspec as first line of the trailer.

Regards,

Ankit

>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display_device.h | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
>> index 071a36b51f79..a21b910879df 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
>> @@ -149,6 +149,9 @@ enum intel_display_subplatform {
>>   #define HAS_MBUS_JOINING(i915)		(IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
>>   #define HAS_MSO(i915)			(DISPLAY_VER(i915) >= 12)
>>   #define HAS_OVERLAY(i915)		(DISPLAY_INFO(i915)->has_overlay)
>> +#define HAS_PIXEL_REPLICATION(i915)	(HAS_DSC(i915) && \
>> +					 (DISPLAY_VER(i915) >= 20 || \
>> +					  DISPLAY_VER_FULL(i915) == IP_VER(14, 1)))
>>   #define HAS_PSR(i915)			(DISPLAY_INFO(i915)->has_psr)
>>   #define HAS_PSR_HW_TRACKING(i915)	(DISPLAY_INFO(i915)->has_psr_hw_tracking)
>>   #define HAS_PSR2_SEL_FETCH(i915)	(DISPLAY_VER(i915) >= 12)

RE: [PATCH 01/16] drm/i915/dp: Update Comment for Valid DSC Slices per Line

[Kandpal, Suraj]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Monday, October 21, 2024 6:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Kandpal, Suraj
> <suraj.kandpal@intel.com>
> Subject: [PATCH 01/16] drm/i915/dp: Update Comment for Valid DSC Slices
> per Line
> 
> For some platforms, the maximum slices per DSC engine is 4, while for
> others it is 2. Update the comment to reflect this and clarify that the
> 'valid_dsc_slicecount' list represents the valid number of slices per pipe.
> 
> Currently, we are working with 1, and 2 slices per DSC engine, which works
> for all platforms. With this the number of slices per pipe can be 1,2 or 4
> with different slice & DSC engine configuration.
> 
> Add a #TODO for adding support for 4 slices per DSC engine where
> supported.

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7e04913bc2ff..286b272aa98c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -108,8 +108,14 @@
>  /* Constants for DP DSC configurations */  static const u8 valid_dsc_bpp[] =
> {6, 8, 10, 12, 15};
> 
> -/* With Single pipe configuration, HW is capable of supporting maximum
> - * of 4 slices per line.
> +/*
> + * With Single pipe configuration, HW is capable of supporting maximum
> of:
> + * 2 slices per line for ICL, BMG
> + * 4 slices per line for other platforms.
> + * For now consider a max of 2 slices per line, which works for all
> platforms.
> + * With this we can have max of 4 DSC Slices per pipe.
> + *
> + * #TODO Split this better to use 4 slices/dsc engine where supported.
>   */
>  static const u8 valid_dsc_slicecount[] = {1, 2, 4};
> 
> --
> 2.45.2

Re: [PATCH 02/16] drm/i915/display: Prepare for dsc 3 stream splitter

[Nautiyal, Ankit K]

On 10/22/2024 9:23 AM, Nautiyal, Ankit K wrote:
>
> On 10/21/2024 6:16 PM, Jani Nikula wrote:
>> On Mon, 21 Oct 2024, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>>> At the moment dsc_split represents that dsc splitter is used or not.
>>> With 3 DSC engines, the splitter can split into two streams or three
>>> streams. Make the member dsc_split as int and set that to 2 when dsc
>>> splitter splits to 2 stream.
>> Maybe also name it accordingly? "dsc split" sounds like a boolean, not
>> like an int.
>>
>> Moreover, when you change the meaning of a member, it's often good code
>> hygiene to rename the member to catch any incorrect uses and to ensure
>> you changed them all.
>
> Noted. Will change the name accordingly.
>
>>
>>> v2: Avoid new enum for dsc split. (Suraj)
>>>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/display/icl_dsi.c        |  2 +-
>>>   drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
>>>   .../drm/i915/display/intel_display_types.h    |  2 +-
>>>   drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
>>>   drivers/gpu/drm/i915/display/intel_vdsc.c     | 20 
>>> ++++++++++++++-----
>>>   5 files changed, 19 insertions(+), 9 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
>>> b/drivers/gpu/drm/i915/display/icl_dsi.c
>>> index 87a27d91d15d..553e75cf118c 100644
>>> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>>> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>>> @@ -1595,7 +1595,7 @@ static int gen11_dsi_dsc_compute_config(struct 
>>> intel_encoder *encoder,
>>>         /* FIXME: split only when necessary */
>>>       if (crtc_state->dsc.slice_count > 1)
>>> -        crtc_state->dsc.dsc_split = true;
>>> +        crtc_state->dsc.dsc_split = 2;
>>>         /* FIXME: initialize from VBT */
>>>       vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
>>> b/drivers/gpu/drm/i915/display/intel_display.c
>>> index ef1436146325..9e2f0fd0558f 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>> @@ -5741,7 +5741,7 @@ intel_pipe_config_compare(const struct 
>>> intel_crtc_state *current_config,
>>>       PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
>>>         PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
>>> -    PIPE_CONF_CHECK_BOOL(dsc.dsc_split);
>>> +    PIPE_CONF_CHECK_I(dsc.dsc_split);
>>>       PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
>>>         PIPE_CONF_CHECK_BOOL(splitter.enable);
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
>>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> index 2bb1fa64da2f..58f510909f4d 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> @@ -1235,7 +1235,7 @@ struct intel_crtc_state {
>>>       /* Display Stream compression state */
>>>       struct {
>>>           bool compression_enable;
>>> -        bool dsc_split;
>>> +        int dsc_split;
>>>           /* Compressed Bpp in U6.4 format (first 4 bits for 
>>> fractional part) */
>>>           u16 compressed_bpp_x16;
>>>           u8 slice_count;
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
>>> b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index 286b272aa98c..c1867c883b73 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -2409,7 +2409,7 @@ int intel_dp_dsc_compute_config(struct 
>>> intel_dp *intel_dp,
>>>        * then we need to use 2 VDSC instances.
>>>        */
>>>       if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count 
>>> > 1)
>>> -        pipe_config->dsc.dsc_split = true;
>>> +        pipe_config->dsc.dsc_split = 2;
>>>         ret = intel_dp_dsc_compute_params(connector, pipe_config);
>>>       if (ret < 0) {
>>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c 
>>> b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>> index 40525f5c4c42..3bce13c21756 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>> @@ -379,7 +379,14 @@ intel_dsc_power_domain(struct intel_crtc *crtc, 
>>> enum transcoder cpu_transcoder)
>>>     static int intel_dsc_get_vdsc_per_pipe(const struct 
>>> intel_crtc_state *crtc_state)
>>>   {
>>> -    return crtc_state->dsc.dsc_split ? 2 : 1;
>>> +    switch (crtc_state->dsc.dsc_split) {
>>> +    case 2:
>>> +        return 2;
>>> +    case 0:
>>> +    default:
>>> +        break;
>>> +    }
>>> +    return 1;
>> Seems overly complicated.
>>
>>>   }
>>>     int intel_dsc_get_num_vdsc_instances(const struct 
>>> intel_crtc_state *crtc_state)
>>> @@ -976,8 +983,11 @@ void intel_dsc_get_config(struct 
>>> intel_crtc_state *crtc_state)
>>>       if (!crtc_state->dsc.compression_enable)
>>>           goto out;
>>>   -    crtc_state->dsc.dsc_split = (dss_ctl2 & 
>>> RIGHT_BRANCH_VDSC_ENABLE) &&
>>> -        (dss_ctl1 & JOINER_ENABLE);
>>> +    if ((dss_ctl1 & JOINER_ENABLE) &&
>>> +        (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE))
>> The extra parens are unnecessary.
>>
>>> +        crtc_state->dsc.dsc_split = 2;
>>> +    else
>>> +        crtc_state->dsc.dsc_split = 0;
>>>         intel_dsc_get_pps_config(crtc_state);
>>>   out:
>>> @@ -988,10 +998,10 @@ static void intel_vdsc_dump_state(struct 
>>> drm_printer *p, int indent,
>>>                     const struct intel_crtc_state *crtc_state)
>>>   {
>>>       drm_printf_indent(p, indent,
>>> -              "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: 
>>> %d, split: %s\n",
>>> +              "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: 
>>> %d, split: %d\n",
>> So what does the reader think when they see "split: 1" in the logs?
>> Split enabled?
>
> I was meaning to capture the DSC split state as originally intended, 
> and extend it to have splitting to 3, 2, or None.
>
> With that we can never have split: 1, but can have either 3, 2, or 0.
>
> I realize, split:0 is a bit ambiguous, so I am thinking about:
>
> -change the dsc_split to dsc_streams: to capture number of DSC streams 
> per pipe, instead of DSC splitter operation.
>
> -dsc_streams can be 1, 2 and extended to 3.
>
> -Splitter state will then be implicit, 1 DSC Stream => No Splitter, 2 
> DSC Streams => Splitter used to split 2 DSC streams and so on.
>
> With that, deriving number of DSC engine will also be straight forward 
> (avoiding the switch case above).

Suraj,

You were actually pointing to the same thing in last version, sorry to 
misunderstand you. I did remove the complicated enum but some how missed 
this.

Will change this as you had originally suggested.

Thanks & Regards,

Ankit

>
>
> Thanks & Regards,
>
> Ankit
>
>
>
>>
>>> FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
>>>                 crtc_state->dsc.slice_count,
>>> -              str_yes_no(crtc_state->dsc.dsc_split));
>>> +              crtc_state->dsc.dsc_split);
>>>   }
>>>     void intel_vdsc_state_dump(struct drm_printer *p, int indent,

Re: [PATCH 02/16] drm/i915/display: Prepare for dsc 3 stream splitter

[Jani Nikula]

On Tue, 22 Oct 2024, "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com> wrote:
> On 10/21/2024 6:16 PM, Jani Nikula wrote:
>> On Mon, 21 Oct 2024, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>>> At the moment dsc_split represents that dsc splitter is used or not.
>>> With 3 DSC engines, the splitter can split into two streams or three
>>> streams. Make the member dsc_split as int and set that to 2 when dsc
>>> splitter splits to 2 stream.
>> Maybe also name it accordingly? "dsc split" sounds like a boolean, not
>> like an int.
>>
>> Moreover, when you change the meaning of a member, it's often good code
>> hygiene to rename the member to catch any incorrect uses and to ensure
>> you changed them all.
>
> Noted. Will change the name accordingly.
>
>>
>>> v2: Avoid new enum for dsc split. (Suraj)
>>>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/display/icl_dsi.c        |  2 +-
>>>   drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
>>>   .../drm/i915/display/intel_display_types.h    |  2 +-
>>>   drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
>>>   drivers/gpu/drm/i915/display/intel_vdsc.c     | 20 ++++++++++++++-----
>>>   5 files changed, 19 insertions(+), 9 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
>>> index 87a27d91d15d..553e75cf118c 100644
>>> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>>> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>>> @@ -1595,7 +1595,7 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
>>>   
>>>   	/* FIXME: split only when necessary */
>>>   	if (crtc_state->dsc.slice_count > 1)
>>> -		crtc_state->dsc.dsc_split = true;
>>> +		crtc_state->dsc.dsc_split = 2;
>>>   
>>>   	/* FIXME: initialize from VBT */
>>>   	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>> index ef1436146325..9e2f0fd0558f 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>> @@ -5741,7 +5741,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>>>   	PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
>>>   
>>>   	PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
>>> -	PIPE_CONF_CHECK_BOOL(dsc.dsc_split);
>>> +	PIPE_CONF_CHECK_I(dsc.dsc_split);
>>>   	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
>>>   
>>>   	PIPE_CONF_CHECK_BOOL(splitter.enable);
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> index 2bb1fa64da2f..58f510909f4d 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> @@ -1235,7 +1235,7 @@ struct intel_crtc_state {
>>>   	/* Display Stream compression state */
>>>   	struct {
>>>   		bool compression_enable;
>>> -		bool dsc_split;
>>> +		int dsc_split;
>>>   		/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
>>>   		u16 compressed_bpp_x16;
>>>   		u8 slice_count;
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index 286b272aa98c..c1867c883b73 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -2409,7 +2409,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>>>   	 * then we need to use 2 VDSC instances.
>>>   	 */
>>>   	if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
>>> -		pipe_config->dsc.dsc_split = true;
>>> +		pipe_config->dsc.dsc_split = 2;
>>>   
>>>   	ret = intel_dp_dsc_compute_params(connector, pipe_config);
>>>   	if (ret < 0) {
>>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>> index 40525f5c4c42..3bce13c21756 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>> @@ -379,7 +379,14 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
>>>   
>>>   static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
>>>   {
>>> -	return crtc_state->dsc.dsc_split ? 2 : 1;
>>> +	switch (crtc_state->dsc.dsc_split) {
>>> +	case 2:
>>> +		return 2;
>>> +	case 0:
>>> +	default:
>>> +		break;
>>> +	}
>>> +	return 1;
>> Seems overly complicated.
>>
>>>   }
>>>   
>>>   int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
>>> @@ -976,8 +983,11 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>>>   	if (!crtc_state->dsc.compression_enable)
>>>   		goto out;
>>>   
>>> -	crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
>>> -		(dss_ctl1 & JOINER_ENABLE);
>>> +	if ((dss_ctl1 & JOINER_ENABLE) &&
>>> +	    (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE))
>> The extra parens are unnecessary.
>>
>>> +		crtc_state->dsc.dsc_split = 2;
>>> +	else
>>> +		crtc_state->dsc.dsc_split = 0;
>>>   
>>>   	intel_dsc_get_pps_config(crtc_state);
>>>   out:
>>> @@ -988,10 +998,10 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent,
>>>   				  const struct intel_crtc_state *crtc_state)
>>>   {
>>>   	drm_printf_indent(p, indent,
>>> -			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n",
>>> +			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %d\n",
>> So what does the reader think when they see "split: 1" in the logs?
>> Split enabled?
>
> I was meaning to capture the DSC split state as originally intended, and 
> extend it to have splitting to 3, 2, or None.
>
> With that we can never have split: 1, but can have either 3, 2, or 0.
>
> I realize, split:0 is a bit ambiguous, so I am thinking about:
>
> -change the dsc_split to dsc_streams: to capture number of DSC streams 
> per pipe, instead of DSC splitter operation.
>
> -dsc_streams can be 1, 2 and extended to 3.
>
> -Splitter state will then be implicit, 1 DSC Stream => No Splitter, 2 
> DSC Streams => Splitter used to split 2 DSC streams and so on.
>
> With that, deriving number of DSC engine will also be straight forward 
> (avoiding the switch case above).

Maybe be even more explicit, and call it num_streams or stream_count or
something like that.

Also, the crtc_state->dsc.dsc_something is a tautology, the dsc_ prefix
is unnecessary when it's already in a dsc substruct.

BR,
Jani.

>
>
> Thanks & Regards,
>
> Ankit
>
>
>
>>
>>>   			  FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
>>>   			  crtc_state->dsc.slice_count,
>>> -			  str_yes_no(crtc_state->dsc.dsc_split));
>>> +			  crtc_state->dsc.dsc_split);
>>>   }
>>>   
>>>   void intel_vdsc_state_dump(struct drm_printer *p, int indent,

-- 
Jani Nikula, Intel

Re: [PATCH 02/16] drm/i915/display: Prepare for dsc 3 stream splitter

[Nautiyal, Ankit K]

On 10/22/2024 1:21 PM, Jani Nikula wrote:
> On Tue, 22 Oct 2024, "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com> wrote:
>> On 10/21/2024 6:16 PM, Jani Nikula wrote:
>>> On Mon, 21 Oct 2024, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>>>> At the moment dsc_split represents that dsc splitter is used or not.
>>>> With 3 DSC engines, the splitter can split into two streams or three
>>>> streams. Make the member dsc_split as int and set that to 2 when dsc
>>>> splitter splits to 2 stream.
>>> Maybe also name it accordingly? "dsc split" sounds like a boolean, not
>>> like an int.
>>>
>>> Moreover, when you change the meaning of a member, it's often good code
>>> hygiene to rename the member to catch any incorrect uses and to ensure
>>> you changed them all.
>> Noted. Will change the name accordingly.
>>
>>>> v2: Avoid new enum for dsc split. (Suraj)
>>>>
>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/display/icl_dsi.c        |  2 +-
>>>>    drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
>>>>    .../drm/i915/display/intel_display_types.h    |  2 +-
>>>>    drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
>>>>    drivers/gpu/drm/i915/display/intel_vdsc.c     | 20 ++++++++++++++-----
>>>>    5 files changed, 19 insertions(+), 9 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
>>>> index 87a27d91d15d..553e75cf118c 100644
>>>> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>>>> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>>>> @@ -1595,7 +1595,7 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
>>>>    
>>>>    	/* FIXME: split only when necessary */
>>>>    	if (crtc_state->dsc.slice_count > 1)
>>>> -		crtc_state->dsc.dsc_split = true;
>>>> +		crtc_state->dsc.dsc_split = 2;
>>>>    
>>>>    	/* FIXME: initialize from VBT */
>>>>    	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>>> index ef1436146325..9e2f0fd0558f 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>>> @@ -5741,7 +5741,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>>>>    	PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
>>>>    
>>>>    	PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
>>>> -	PIPE_CONF_CHECK_BOOL(dsc.dsc_split);
>>>> +	PIPE_CONF_CHECK_I(dsc.dsc_split);
>>>>    	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
>>>>    
>>>>    	PIPE_CONF_CHECK_BOOL(splitter.enable);
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> index 2bb1fa64da2f..58f510909f4d 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> @@ -1235,7 +1235,7 @@ struct intel_crtc_state {
>>>>    	/* Display Stream compression state */
>>>>    	struct {
>>>>    		bool compression_enable;
>>>> -		bool dsc_split;
>>>> +		int dsc_split;
>>>>    		/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
>>>>    		u16 compressed_bpp_x16;
>>>>    		u8 slice_count;
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> index 286b272aa98c..c1867c883b73 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> @@ -2409,7 +2409,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>>>>    	 * then we need to use 2 VDSC instances.
>>>>    	 */
>>>>    	if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
>>>> -		pipe_config->dsc.dsc_split = true;
>>>> +		pipe_config->dsc.dsc_split = 2;
>>>>    
>>>>    	ret = intel_dp_dsc_compute_params(connector, pipe_config);
>>>>    	if (ret < 0) {
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> index 40525f5c4c42..3bce13c21756 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> @@ -379,7 +379,14 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
>>>>    
>>>>    static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
>>>>    {
>>>> -	return crtc_state->dsc.dsc_split ? 2 : 1;
>>>> +	switch (crtc_state->dsc.dsc_split) {
>>>> +	case 2:
>>>> +		return 2;
>>>> +	case 0:
>>>> +	default:
>>>> +		break;
>>>> +	}
>>>> +	return 1;
>>> Seems overly complicated.
>>>
>>>>    }
>>>>    
>>>>    int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
>>>> @@ -976,8 +983,11 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>>>>    	if (!crtc_state->dsc.compression_enable)
>>>>    		goto out;
>>>>    
>>>> -	crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
>>>> -		(dss_ctl1 & JOINER_ENABLE);
>>>> +	if ((dss_ctl1 & JOINER_ENABLE) &&
>>>> +	    (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE))
>>> The extra parens are unnecessary.
>>>
>>>> +		crtc_state->dsc.dsc_split = 2;
>>>> +	else
>>>> +		crtc_state->dsc.dsc_split = 0;
>>>>    
>>>>    	intel_dsc_get_pps_config(crtc_state);
>>>>    out:
>>>> @@ -988,10 +998,10 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent,
>>>>    				  const struct intel_crtc_state *crtc_state)
>>>>    {
>>>>    	drm_printf_indent(p, indent,
>>>> -			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n",
>>>> +			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %d\n",
>>> So what does the reader think when they see "split: 1" in the logs?
>>> Split enabled?
>> I was meaning to capture the DSC split state as originally intended, and
>> extend it to have splitting to 3, 2, or None.
>>
>> With that we can never have split: 1, but can have either 3, 2, or 0.
>>
>> I realize, split:0 is a bit ambiguous, so I am thinking about:
>>
>> -change the dsc_split to dsc_streams: to capture number of DSC streams
>> per pipe, instead of DSC splitter operation.
>>
>> -dsc_streams can be 1, 2 and extended to 3.
>>
>> -Splitter state will then be implicit, 1 DSC Stream => No Splitter, 2
>> DSC Streams => Splitter used to split 2 DSC streams and so on.
>>
>> With that, deriving number of DSC engine will also be straight forward
>> (avoiding the switch case above).
> Maybe be even more explicit, and call it num_streams or stream_count or
> something like that.
>
> Also, the crtc_state->dsc.dsc_something is a tautology, the dsc_ prefix
> is unnecessary when it's already in a dsc substruct.

I agree, I am working with dsc.num_streams, something like : 
https://patchwork.freedesktop.org/patch/620816/?series=134992&rev=6

Regards,

Ankit


>
> BR,
> Jani.
>
>>
>> Thanks & Regards,
>>
>> Ankit
>>
>>
>>
>>>>    			  FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
>>>>    			  crtc_state->dsc.slice_count,
>>>> -			  str_yes_no(crtc_state->dsc.dsc_split));
>>>> +			  crtc_state->dsc.dsc_split);
>>>>    }
>>>>    
>>>>    void intel_vdsc_state_dump(struct drm_printer *p, int indent,

[PATCH 02/16] drm/i915/display: Prepare for dsc 3 stream splitter

[Ankit Nautiyal]

At the moment dsc_split represents whether the dsc splitter is used
or not. With 3 DSC engines, the splitter can split into two streams
or three streams.

Instead of representing the splitter's state, it is more effective to
represent the number of DSC streams per pipe.

Replace the `dsc.dsc_split` member with `dsc.num_streams` to indicate the
number of DSC streams used per pipe. This change will implicitly
convey the splitter's operation mode.

v2: Avoid new enum for dsc split. (Suraj)
v3:
-Replace dsc_split with num_stream. (Suraj)
-Avoid extra parentheses. (Jani)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c           |  4 +++-
 drivers/gpu/drm/i915/display/intel_display.c     |  2 +-
 .../gpu/drm/i915/display/intel_display_types.h   |  2 +-
 drivers/gpu/drm/i915/display/intel_dp.c          |  4 +++-
 drivers/gpu/drm/i915/display/intel_vdsc.c        | 16 +++++++++++-----
 5 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 87a27d91d15d..7d5571c39b7e 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1595,7 +1595,9 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
 
 	/* FIXME: split only when necessary */
 	if (crtc_state->dsc.slice_count > 1)
-		crtc_state->dsc.dsc_split = true;
+		crtc_state->dsc.num_streams = 2;
+	else
+		crtc_state->dsc.num_streams = 1;
 
 	/* FIXME: initialize from VBT */
 	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ef1436146325..3dfff0a8c386 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5741,7 +5741,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
 
 	PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
-	PIPE_CONF_CHECK_BOOL(dsc.dsc_split);
+	PIPE_CONF_CHECK_I(dsc.num_streams);
 	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
 
 	PIPE_CONF_CHECK_BOOL(splitter.enable);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 2bb1fa64da2f..5611a4dd6a6f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1235,7 +1235,7 @@ struct intel_crtc_state {
 	/* Display Stream compression state */
 	struct {
 		bool compression_enable;
-		bool dsc_split;
+		int num_streams;
 		/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
 		u16 compressed_bpp_x16;
 		u8 slice_count;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 286b272aa98c..77487a55280c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2409,7 +2409,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	 * then we need to use 2 VDSC instances.
 	 */
 	if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
-		pipe_config->dsc.dsc_split = true;
+		pipe_config->dsc.num_streams = 2;
+	else
+		pipe_config->dsc.num_streams = 1;
 
 	ret = intel_dp_dsc_compute_params(connector, pipe_config);
 	if (ret < 0) {
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 40525f5c4c42..afc40d180dec 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -379,7 +379,7 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 
 static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
 {
-	return crtc_state->dsc.dsc_split ? 2 : 1;
+	return crtc_state->dsc.num_streams;
 }
 
 int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
@@ -976,8 +976,14 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	if (!crtc_state->dsc.compression_enable)
 		goto out;
 
-	crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
-		(dss_ctl1 & JOINER_ENABLE);
+	if (dss_ctl1 & JOINER_ENABLE) {
+		if (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE)
+			crtc_state->dsc.num_streams = 2;
+		else
+			crtc_state->dsc.num_streams = 1;
+	} else {
+		crtc_state->dsc.num_streams = 0;
+	}
 
 	intel_dsc_get_pps_config(crtc_state);
 out:
@@ -988,10 +994,10 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent,
 				  const struct intel_crtc_state *crtc_state)
 {
 	drm_printf_indent(p, indent,
-			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n",
+			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, num_streams: %d\n",
 			  FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
 			  crtc_state->dsc.slice_count,
-			  str_yes_no(crtc_state->dsc.dsc_split));
+			  crtc_state->dsc.num_streams);
 }
 
 void intel_vdsc_state_dump(struct drm_printer *p, int indent,
-- 
2.45.2

RE: [PATCH 02/16] drm/i915/display: Prepare for dsc 3 stream splitter

[Kandpal, Suraj]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Wednesday, October 23, 2024 12:23 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH 02/16] drm/i915/display: Prepare for dsc 3 stream splitter
> 
> At the moment dsc_split represents whether the dsc splitter is used or not.
> With 3 DSC engines, the splitter can split into two streams or three streams.
> 
> Instead of representing the splitter's state, it is more effective to represent the
> number of DSC streams per pipe.
> 
> Replace the `dsc.dsc_split` member with `dsc.num_streams` to indicate the
> number of DSC streams used per pipe. This change will implicitly convey the
> splitter's operation mode.
> 
> v2: Avoid new enum for dsc split. (Suraj)
> v3:
> -Replace dsc_split with num_stream. (Suraj) -Avoid extra parentheses. (Jani)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c           |  4 +++-
>  drivers/gpu/drm/i915/display/intel_display.c     |  2 +-
>  .../gpu/drm/i915/display/intel_display_types.h   |  2 +-
>  drivers/gpu/drm/i915/display/intel_dp.c          |  4 +++-
>  drivers/gpu/drm/i915/display/intel_vdsc.c        | 16 +++++++++++-----
>  5 files changed, 19 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 87a27d91d15d..7d5571c39b7e 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1595,7 +1595,9 @@ static int gen11_dsi_dsc_compute_config(struct
> intel_encoder *encoder,
> 
>  	/* FIXME: split only when necessary */
>  	if (crtc_state->dsc.slice_count > 1)
> -		crtc_state->dsc.dsc_split = true;
> +		crtc_state->dsc.num_streams = 2;
> +	else
> +		crtc_state->dsc.num_streams = 1;
> 
>  	/* FIXME: initialize from VBT */
>  	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; diff --git
> a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index ef1436146325..3dfff0a8c386 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5741,7 +5741,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>  	PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
> 
>  	PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
> -	PIPE_CONF_CHECK_BOOL(dsc.dsc_split);
> +	PIPE_CONF_CHECK_I(dsc.num_streams);
>  	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
> 
>  	PIPE_CONF_CHECK_BOOL(splitter.enable);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 2bb1fa64da2f..5611a4dd6a6f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1235,7 +1235,7 @@ struct intel_crtc_state {
>  	/* Display Stream compression state */
>  	struct {
>  		bool compression_enable;
> -		bool dsc_split;
> +		int num_streams;
>  		/* Compressed Bpp in U6.4 format (first 4 bits for fractional
> part) */
>  		u16 compressed_bpp_x16;
>  		u8 slice_count;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 286b272aa98c..77487a55280c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2409,7 +2409,9 @@ int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
>  	 * then we need to use 2 VDSC instances.
>  	 */
>  	if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
> -		pipe_config->dsc.dsc_split = true;
> +		pipe_config->dsc.num_streams = 2;
> +	else
> +		pipe_config->dsc.num_streams = 1;
> 
>  	ret = intel_dp_dsc_compute_params(connector, pipe_config);
>  	if (ret < 0) {
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 40525f5c4c42..afc40d180dec 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -379,7 +379,7 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum
> transcoder cpu_transcoder)
> 
>  static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state
> *crtc_state)  {
> -	return crtc_state->dsc.dsc_split ? 2 : 1;
> +	return crtc_state->dsc.num_streams;
>  }
> 
>  int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state
> *crtc_state) @@ -976,8 +976,14 @@ void intel_dsc_get_config(struct
> intel_crtc_state *crtc_state)
>  	if (!crtc_state->dsc.compression_enable)
>  		goto out;
> 
> -	crtc_state->dsc.dsc_split = (dss_ctl2 &
> RIGHT_BRANCH_VDSC_ENABLE) &&
> -		(dss_ctl1 & JOINER_ENABLE);
> +	if (dss_ctl1 & JOINER_ENABLE) {
> +		if (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE)
> +			crtc_state->dsc.num_streams = 2;
> +		else
> +			crtc_state->dsc.num_streams = 1;
> +	} else {
> +		crtc_state->dsc.num_streams = 0;
> +	}
> 
>  	intel_dsc_get_pps_config(crtc_state);
>  out:
> @@ -988,10 +994,10 @@ static void intel_vdsc_dump_state(struct
> drm_printer *p, int indent,
>  				  const struct intel_crtc_state *crtc_state)  {
>  	drm_printf_indent(p, indent,
> -			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-
> count: %d, split: %s\n",
> +			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-
> count: %d,
> +num_streams: %d\n",
>  			  FXP_Q4_ARGS(crtc_state-
> >dsc.compressed_bpp_x16),
>  			  crtc_state->dsc.slice_count,
> -			  str_yes_no(crtc_state->dsc.dsc_split));
> +			  crtc_state->dsc.num_streams);
>  }
> 
>  void intel_vdsc_state_dump(struct drm_printer *p, int indent,
> --
> 2.45.2